Chip structure and manufacturing method thereof
By surrounding the active surface of the chip to form a semi-ring groove and forming a shielding space after separation of the chip, the problem of metal residue accumulation during the formation of the heat dissipation layer is solved, and the quality and yield of the chip are improved.
Patent Information
- Application Number
- CN202410158168.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-01-22
- Filing Date
- 2024-02-04
- Publication Date
- 2025-07-22
AI Technical Summary
When a heat dissipation layer is formed on the back of the chip, metal residues are prone to accumulate in the gap between the active surface and the carrier, affecting the quality and yield of the chip.
The active surface of the chip is surrounded by a semi-ring groove, and after the chip is separated, it is attached to the carrier to form a shielding space to prevent splashing target atoms from accumulating in the gap.
It effectively avoids contamination of metal residues and improves the quality and yield of the chip.
Smart Images
Figure CN120356868A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a chip structure and a manufacturing method thereof, in particular to a chip structure and a manufacturing method thereof for forming a heat dissipation layer on the back surface of a chip. Background Art
[0002] Please refer to Figure 9 , the active surfaces 11a of a plurality of chips 11 of the separated wafer 10 are attached to the surface 21 of the tape 20. There are grooves 30 between adjacent ones of the plurality of chips 11, and the grooves 30 expose the surface 21. Then, a heat dissipation layer 12 is formed on the back surfaces 11b of the plurality of chips 11 by a process such as sputtering.
[0003] Please refer to Figure 9 , when the heat dissipation layer 12 is formed on the back surface 11b by a sputtering process, due to the physical properties of the plurality of chips 11 and the tape 20 and / or the process environment (such as temperature, etc.), a gap 40 will be generated between the active surface 11a and the tape 20. Atoms of the sputtered target material will accumulate in the tape 20 and the gap 40 to form a plurality of metal residues 50. The plurality of metal residues 50 will adhere to the active surface 11a, thereby affecting the quality and yield of the chip 11. Summary of the Invention
[0004] The main object of the present invention is to provide a chip structure and a manufacturing method thereof, which can avoid the accumulation of metal residues in the gap between the active surface and the carrier when forming a heat dissipation layer on the back surface of the chip, so as to avoid affecting the quality and yield of the chip.
[0005] A chip structure of the present invention includes a chip and a heat dissipation layer. The chip has a back surface, an active surface, side surfaces, and a semi-circular groove. The semi-circular groove surrounds the active surface and is located between the active surface and the side surfaces. The semi-circular groove has a first edge adjacent to the active surface and a second edge adjacent to the side surfaces. The heat dissipation layer covers the back surface.
[0006] Preferably, a first axis extends along the side surface, and the first axis passes through the second edge. A second axis extends along the active surface, and the second axis passes through the first edge. There is a first distance between the first edge and the first axis, and the first distance is not less than 3 μm and not more than 10 μm. There is a second distance between the second edge and the second axis, and the second distance is not less than 5 μm and not more than 120 μm. The ratio of the second distance to the first distance is not less than 0.5 and not more than 40.
[0007] Preferably, the semi-circular groove has a groove side surface and a groove bottom surface. The groove side surface includes the first edge, and the groove bottom surface includes the second edge. The groove side surface faces the first axis, and the groove bottom surface faces the second axis. The groove side surface is connected to the groove bottom surface, and there is an included angle between the groove side surface and the groove bottom surface, and the included angle is not less than 90 degrees.
[0008] Preferably, the included angle is greater than 90 degrees.
[0009] Preferably, the semi-circular groove has a groove side surface, and the groove side surface includes the first edge and the second edge, and the groove side surface faces the intersection of the first axis and the second axis.
[0010] Preferably, the semi-circular groove has a groove side surface and a groove bottom surface. The groove bottom surface includes the second edge. The groove side surface is an arc surface. The groove side surface is connected to the groove bottom surface, and the groove side surface is located between the groove bottom surface and the active surface.
[0011] Preferably, the groove side surface is connected to the active surface, and the groove side surface includes the first edge.
[0012] A manufacturing method of a chip structure of the present invention includes attaching at least one chip to a second carrier. The chip has a back surface, an active surface, a side surface, and a semi-circular groove. The semi-circular groove surrounds the active surface and is located between the active surface and the side surface. The semi-circular groove has a first edge adjacent to the active surface and a second edge adjacent to the side surface. The chip is attached to the second carrier with the active surface, so that the semi-circular groove forms a shielding space between the chip and the second carrier; and forming a heat dissipation layer on the back surface to form a plurality of chip structures.
[0013] Preferably, before attaching the chip to the second carrier, it further includes providing a wafer having a plurality of the chips not separated. Then, attaching the wafer to a first carrier. The wafer is attached to the first carrier with the back surfaces of the plurality of chips and exposes the active surface. Then, forming a ring groove on the active surface. The ring groove surrounds the active surface. The ring groove has a bottom surface and two opposite first edges. Then, cutting the wafer along the bottom surface of the ring groove to separate the plurality of chips, so that the ring groove is formed into two semi-circular grooves, and the chip has the side surface, the first edge, the second edge, and the semi-circular groove. Then, attaching the active surfaces of the plurality of chips to the second carrier and removing the first carrier to expose the back surface.
[0014] Preferably, there is a spacing between the side surfaces of two adjacent chips attached to the second carrier, and the spacing is not less than 20 μm and not more than 1 mm.
[0015] Preferably, a first axis extends along the side surface, the first axis passes through the second edge, a second axis extends along the active surface, the second axis passes through the first edge, a first distance is between the first edge and the first axis, the first distance is not less than 3 μm and not more than 10 μm, a second distance is between the second edge and the second axis, the second distance is not less than 5 μm and not more than 120 μm, and a ratio of the second distance to the first distance is not less than 0.5 and not more than 40.
[0016] Preferably, in the step of forming the annular groove, the annular groove has two opposite groove side surfaces, the groove side surface includes the first edge, the groove side surface is connected to the bottom surface, an included angle is between the groove side surface and the bottom surface, the included angle is not less than 90 degrees, in the step of separating the plurality of chips, the bottom surface is formed into two groove bottom surfaces, the groove side surface is connected to the groove bottom surface, the groove bottom surface includes the second edge, and the included angle is between the groove side surface and the groove bottom surface.
[0017] Preferably, the included angle is greater than 90 degrees.
[0018] Preferably, in the step of forming the annular groove, the annular groove has two opposite groove side surfaces, the groove side surface includes the first edge, the groove side surface is connected to the bottom surface, an included angle is between the groove side surface and the bottom surface, the included angle is greater than 90 degrees, in the step of separating the plurality of chips, the bottom surface is removed, the groove side surface is retained in the semi-annular groove, and the groove side surface includes the second edge.
[0019] Preferably, in the step of forming the annular groove, the annular groove has two opposite groove side surfaces, the groove side surfaces are arc-shaped, the groove side surfaces are connected to the bottom surface, in the step of separating the plurality of chips, the bottom surface is formed into two groove bottom surfaces, the groove bottom surface includes the second edge, the groove side surfaces are connected to the groove bottom surface, and the groove side surfaces are located between the groove bottom surface and the active surface.
[0020] Preferably, the groove side surface is connected to the active surface, and the groove side surface includes the first edge.
[0021] The present invention forms the semi-annular groove around the active surface, and makes the semi-annular groove form the shielding space between the chip and the second carrier, so as to avoid the atomic splash of the splashing target material from accumulating in the gap between the second carrier and the active surface during the formation of the heat dissipation layer, and form metal residues that contaminate the chip or cause damage to the chip. Description of the Drawings
[0022] Figures 1 to 7D : Schematic diagram of the manufacturing method of the chip structure of the present invention.
[0023] Figures 8A to 8D : Cross-sectional view of the chip structure of the present invention.
[0024] Figure 9 : Cross-sectional view of a conventional chip structure.
[0025]
Description of Main Component Symbols
[0026] 10: Wafer 11: Chip
[0027] 11a: Active surface 11b: Back surface
[0028] 12: Heat dissipation layer 20: Tape
[0029] 21: Surface 30: Groove
[0030] 40: Gap 50: Metal residue
[0031] 100: Chip 100A: Chip structure
[0032] 110: Back surface 120: Active surface
[0033] 121: Bonding pad 130: Side surface
[0034] 140: Ring groove 140a: Semi-ring groove
[0035] 141: First edge 142: Second edge
[0036] 143: Bottom surface 143a: Bottom surface of the groove
[0037] 144: Groove side surface 150: Heat dissipation layer
[0038] 200: Wafer A: Included angle
[0039] B: Shielding space C: Sawing lane
[0040] G: Spacing K1: First tool
[0041] K2: Second tool O: Intersection point
[0042] S1: First distance S2: Second distance
[0043] T1: First carrier T2: Second carrier
[0044] X: Second axis Y: First axis Detailed implementation manner
[0045] Please refer to Figures 1 to 7D For a manufacturing method of a chip structure according to the present invention, first, please refer to Figure 1 and Figure 2, a wafer 200 is provided. The wafer 200 has a plurality of unseparated chips 100. The plurality of chips 100 have a back surface 110 and an active surface 120. In this embodiment, the active surface 120 includes a plurality of bonding pads 121. In different embodiments, a redistribution layer (RDL, not shown in the figure) is electrically connected to the plurality of bonding pads 121. Then, the wafer 200 is attached to a first carrier T1. The wafer 200 is attached to the first carrier T1 with the back surface 110 of the plurality of chips 100, and the active surface 120 of the chip 110 is exposed. The first carrier T1 can be selected from adhesive tapes, glass substrates, silicon substrates, etc.
[0046] Please refer to Figures 3 to 4D , then, an annular groove 140 is formed on the active surface 120. The annular groove 140 surrounds the active surface 120. Please refer to Figures 4A to 4D , in this embodiment, the wafer 200 is cut along a scribe line C with a first cutting tool K1 to form the annular groove 140 surrounding the active surface 120. The annular groove 140 has a bottom surface 143 and two opposite first edges 141. The first edge 141 is adjacent to the active surface 120. Please refer to Figures 4A to 4D , in different embodiments, the shape of the annular groove 140 is different due to the difference in the shape of the first cutting tool K1.
[0047] Please refer to Figure 4A 、 Figure 4B and Figure 4C , in the step of forming the annular groove 140, the annular groove 140 has two opposite groove side surfaces 144. The groove side surface 144 includes the first edge 141. The groove side surface 144 is connected to the bottom surface 143. There is an included angle A between the groove side surface 144 and the bottom surface 143. The included angle A is not less than 90 degrees. Please refer to Figure 4A , the groove side surface 144 is perpendicular to the bottom surface 143, and the included angle A is approximately 90 degrees. Please refer to Figure 4B and Figure 4C , the included angle A is greater than 90 degrees, or, please refer to Figure 4D , which is different from Figure 4A 、 Figure 4B and Figure 4C in that the groove side surface 144 is an arc surface.
[0048] Please refer to Figures 5A to 5D, after the step of forming the annular groove 140, a second tool K2 cuts the wafer 200 along the bottom surface 143 of the annular groove 140 and the cutting path C to separate the plurality of chips 100, and to make the chip 110 have a side surface 130 and to form the annular groove 140 into two semi-annular grooves 140a. The semi-annular groove 140a surrounds the active surface 120 and is located between the active surface 120 and the side surface 130. The semi-annular groove 140a has a first edge 141 adjacent to the active surface 120 and a second edge 142 adjacent to the side surface 130.
[0049] Please refer to Figures 5A to 5D , extend a first axis Y along the side surface 130. The first axis Y passes through the second edge 142. Extend a second axis X along the active surface 120. The second axis X passes through the first edge 141. There is a first distance S1 between the first edge 141 and the first axis Y. The first distance S1 is not less than 3 μm and not more than 10 μm. There is a second distance S2 between the second edge 142 and the second axis X. The second distance S2 is not less than 5 μm and not more than 120 μm. The ratio (S2 / S1) of the second distance S2 to the first distance S1 is not less than 0.5 and not more than 40.
[0050] Please refer to Figure 4A , Figure 5A , Figure 4B and Figure 5B , in the step of separating the plurality of chips 100, the second tool K2 cuts the wafer 200 along the bottom surface 143 of the annular groove 140 to make the bottom surface 143 into two groove bottom surfaces 143a. The groove side surface 144 connects the groove bottom surfaces 143a. In this embodiment, the groove bottom surface 143a includes the second edge 142. The groove side surface 144 faces the first axis Y. The groove bottom surface 143a faces the second axis X. There is an angle A between the groove side surface 144 and the groove bottom surface 143a. Or, please refer to Figure 4D and Figure 5D , the groove side surface 144 is an arc surface and connects the groove bottom surfaces 143a.
[0051] Or, please refer to Figure 4C and Figure 5C , in the step of separating the plurality of chips 100, the second tool K2 cuts the wafer 200 along the bottom surface 143 of the annular groove 140 and removes the bottom surface 143. The groove side surface 144 is retained in the semi-annular groove 140a. The groove side surface 144 includes the second edge 142. The groove side surface 144 faces the intersection point O of the first axis Y and the second axis X.
[0052] Please refer to Figures 6A to 6D, then, attach the active surface 120 of the multiple chips 100 to the second carrier T2, such that the semi-circular groove 140a forms a shielding space B between the chip 100 and the second carrier T2. There is a spacing G between the side surfaces 130 of two adjacent chips 110, and the spacing G is not less than 20 μm and not more than 1 mm. The shielding space B is located between the chip 100 and the second carrier T2. Then, remove the first carrier T1 to expose the back surface 110. The second carrier T2 can be selected from adhesive tapes, glass substrates, silicon substrates, etc.
[0053] Please refer to Figures 5A to 5D and Figures 7A to 7D , then, form a heat dissipation layer 150 on the back surface 110 to form multiple chip structures 100A. In this embodiment, the heat dissipation layer 150 covers the back surface 110 and the side surface 130 to form a heat dissipation cover. The method of forming the heat dissipation layer 150 is selected from sputtering and other methods. During the process of forming the heat dissipation layer 150, due to the shielding space B between the chip 100 and the second carrier T2, preferably, further due to the spacing G between the side surfaces 130 of two adjacent chips 110 being not less than 20 μm and not more than 1 mm, the first distance S1 being not less than 3 μm and not more than 10 μm, the second distance S2 being not less than 5 μm and not more than 120 μm, and the ratio (S2 / S1) of the second distance S2 to the first distance S1 being not less than 0.5 and not more than 40, the atoms of the sputtered target material (not shown in the figure) will not splash and accumulate in the gap (not shown in the figure) between the second carrier T2 and the active surface 120, so as not to form metal residues (not shown in the figure) that contaminate the chip 100 or cause damage to the chip 100.
[0054] Please refer to Figures 8A to 8D , then, perform a pick-and-place process with a pick-and-place device (not shown in the figure) to separate the multiple chip structures 100A from the second carrier T2.
[0055] Please refer to Figures 8A to 8D , the differences between the multiple chip structures 100A lie in the shape of the semi-circular groove 140a. The chip structure 100A manufactured by the manufacturing method of the chip structure includes the chip 100 and the heat dissipation layer 150. The semi-circular groove 140a surrounds the active surface 120, the semi-circular groove 140a is located between the active surface 120 and the side surface 130, the semi-circular groove 140a has a first edge 141 adjacent to the active surface 120 and a second edge 142 adjacent to the side surface 130. The heat dissipation layer 150 covers the back surface 110, and preferably, the heat dissipation layer 150 further covers the side surface 130.
[0056] Please refer toFigures 8A to 8D The first distance S1 between the first axis Y extending along the side surface 130 and the first edge 141 is not less than 3 μm and not greater than 10 μm, and the second distance S2 between the second axis X extending along the active surface 120 and the second edge 142 is not less than 5 μm and not greater than 120 μm. The ratio (S2 / S1) of the second distance S2 to the first distance S1 is not less than 0.5 and not greater than 40.
[0057] Please refer to Figure 8A and Figure 8B The semi-circular groove 140a has a groove side surface 144 and a groove bottom surface 143a. The groove side surface 144 includes the first edge 141, and the groove bottom surface 143a includes the second edge 142. The groove side surface 144 faces the first axis Y, and the groove bottom surface 143a faces the second axis X. The groove side surface 144 connects the groove bottom surface 143a, and there is an angle A between the groove side surface 144 and the groove bottom surface 143a. The angle A is not less than 90 degrees. Please refer to Figure 8A The groove side surface 144 is perpendicular to the bottom surface 143, and the angle A is approximately 90 degrees. Please refer to Figure 8B The angle A is greater than 90 degrees. Please refer to Figure 8D The groove side surface 144 is an arc surface and connects the groove bottom surface 143a.
[0058] Please refer to Figure 8C The semi-circular groove 140a has a groove side surface 144. The groove side surface 144 includes the first edge 141 and the second edge 142, and the groove side surface 144 faces the intersection point O of the first axis Y and the second axis X.
[0059] Before the step of separating the multiple chips 100, the ring groove 140 surrounding the active surface 120 is pre-formed on the active surface 120 in the present invention. After the step of separating the multiple chips 100, the ring groove 140 is formed into the semi-circular groove 140a surrounding the active surface 120, and the active surface 120 of the multiple chips 100 is attached to the second carrier T2, so that the semi-circular groove 140a forms the shielding space B. By means of the shielding space B, during the process of forming the heat dissipation layer 150, atoms of the sputtered target (not shown in the figure) are prevented from splashing and accumulating into the gap (not shown in the figure) between the second carrier T2 and the active surface 120, so as to form metal residues that contaminate the chip 100 or cause damage to the chip 100.
[0060] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to equivalent embodiments by using the above-disclosed technical content within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.
Claims
1. A chip structure, characterized in that, Comprising: A chip having a back surface, an active surface, side surfaces, and a semi-circular groove that surrounds the active surface and is located between the active surface and the side surfaces. The semi-circular groove has a first edge adjacent to the active surface and a second edge adjacent to the side surfaces; and A heat dissipation layer covering the back surface.
2. The chip structure according to claim 1, characterized in that, A first axis extends along the side surface and passes through the second edge. A second axis extends along the active surface and passes through the first edge. There is a first distance between the first edge and the first axis, and the first distance is not less than 3 μm and not greater than 10 μm. There is a second distance between the second edge and the second axis, and the second distance is not less than 5 μm and not greater than 120 μm. The ratio of the second distance to the first distance is not less than 0.5 and not greater than 40.
3. The chip structure according to claim 1, wherein, The semi-circular groove has a groove side surface and a groove bottom surface. The groove side surface includes the first edge, and the groove bottom surface includes the second edge. The groove side surface faces the first axis, and the groove bottom surface faces the second axis. The groove side surface connects the groove bottom surface, and there is an angle between the groove side surface and the groove bottom surface, and the angle is not less than 90 degrees.
4. The chip structure according to claim 3, wherein, The angle is greater than 90 degrees.
5. The chip structure according to claim 1, wherein, The semi-circular groove has a groove side surface that includes the first edge and the second edge, and the groove side surface faces the intersection of the first axis and the second axis.
6. The chip structure according to claim 1, wherein The semi-circular groove has a groove side surface and a groove bottom surface. The groove bottom surface includes the second edge. The groove side surface is an arc surface. The groove side surface connects the groove bottom surface, and the groove side surface is located between the groove bottom surface and the active surface.
7. The chip structure according to claim 6, wherein The groove side surface connects the active surface, and the groove side surface includes the first edge.
8. A manufacturing method of a chip structure, characterized in that, Comprising: Attach at least one chip to a second carrier, the chip having a back surface, an active surface, side surfaces, and a semi-circular groove that surrounds the active surface and is located between the active surface and the side surfaces. ， The semi-circular groove has a first edge adjacent to the active surface and a second edge adjacent to the side surface. The chip is attached to the second carrier with the active surface such that the semi-circular groove forms a shielding space between the chip and the second carrier; and Forming a heat dissipation layer on the back surface to form a plurality of chip structures.
9. The manufacturing method of the chip structure according to claim 8, characterized in that, Before attaching the chip to the second carrier, additionally providing a wafer having a plurality of the chips that are not separated. Then, attaching the wafer to a first carrier. The wafer is attached to the first carrier with the back surfaces of the plurality of chips and exposes the active surface. Then, forming a ring groove on the active surface. The ring groove surrounds the active surface. The ring groove has a bottom surface and two opposite first edges. Then, cutting the wafer along the bottom surface of the ring groove to separate the plurality of chips, so that the ring groove is formed into two semi-circular grooves, and the chip has the side surface, the first edge, the second edge, and the semi-circular groove. Then, attaching the active surfaces of the plurality of chips to the second carrier and removing the first carrier to expose the back surface.
10. The manufacturing method of the chip structure according to claim 9, characterized in that, There is a spacing between the side surfaces of two adjacent chips attached to the second carrier, and the spacing is not less than 20 μm and not greater than 1 mm.
11. The manufacturing method of the chip structure according to claim 8 or 10, characterized in that, A first axis extends along the side surface and passes through the second edge. A second axis extends along the active surface and passes through the first edge. There is a first distance between the first edge and the first axis, and the first distance is not less than 3 μm and not greater than 10 μm. There is a second distance between the second edge and the second axis, and the second distance is not less than 5 μm and not greater than 120 μm. The ratio of the second distance to the first distance is not less than 0.5 and not greater than 40.
12. The manufacturing method of the chip structure according to claim 9, characterized in that, In the step of forming the annular groove, the annular groove has two opposite groove side faces. The groove side face includes the first edge, the groove side face is connected to the bottom face, and there is an included angle between the groove side face and the bottom face. The included angle is not less than 90 degrees. In the step of separating the plurality of chips, the bottom face is formed into two groove bottom faces. The groove side face is connected to the groove bottom face. The groove bottom face includes the second edge, and there is the included angle between the groove side face and the groove bottom face.
13. The manufacturing method of the chip structure according to claim 12, characterized in that, The included angle is greater than 90 degrees.
14. The manufacturing method of the chip structure according to claim 9, characterized in that, In the step of forming the annular groove, the annular groove has two opposite groove side faces. The groove side face includes the first edge, the groove side face is connected to the bottom face, and there is an included angle between the groove side face and the bottom face. The included angle is greater than 90 degrees. In the step of separating the plurality of chips, the bottom face is removed, and the groove side face is retained in the semi-annular groove. The groove side face includes the second edge.
15. The manufacturing method of the chip structure according to claim 9, characterized in that, In the step of forming the annular groove, the annular groove has two opposite groove side faces. The groove side faces are arc-shaped, the groove side faces are connected to the bottom face. In the step of separating the plurality of chips, the bottom face is formed into two groove bottom faces. The groove bottom face includes the second edge, the groove side face is connected to the groove bottom face, and the groove side face is located between the groove bottom face and the active face.
16. The manufacturing method of the chip structure according to claim 15, characterized in that, The groove side face is connected to the active face, and the groove side face includes the first edge.