Converter for realizing soft switching

Abstract

The invention discloses a converter for realizing soft switching, which adopts an active resonance branch circuit, the active resonance branch circuit comprises two auxiliary switch tubes and an auxiliary inductor, the auxiliary inductor is connected in series between the two auxiliary switch tubes, the active resonance branch circuit is controlled by a main control unit, and before a main switch of the converter is about to be switched on, the auxiliary inductor is connected in series between the two auxiliary switch tubes. The auxiliary switch tube is conducted in advance to drive the resonance process, the node voltage of the switch tube is transited to zero, and soft switching operation is achieved. The high-power high-frequency PFC circuit is suitable for the design of a high-power high-frequency PFC The staggered parallel totem pole bridgeless PFC converter topology based on active resonance and the soft switching control method thereof have the comprehensive advantages of high efficiency, high power factor, low loss, high adaptability and the like, and have wide engineering application prospects and popularization value.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronic converters, and particularly relates to a converter for realizing soft switching. Background Art

[0002] In application scenarios with high current and high power density, BOOST-type power factor correction (PFC) circuits are widely adopted due to their simple structure and mature control technology. To meet higher output power requirements, traditional solutions usually adopt the method of paralleling multiple BOOST-type PFC circuits to achieve reasonable distribution of thermal losses, improve the fault tolerance and operation reliability of the system, and reduce costs to a certain extent.

[0003] According to the mandatory requirements of national standard GB / T 17626.3-2016 and international standard IEC 61000-3-2 for electromagnetic compatibility and harmonic current limits, for electrical equipment with a rated power exceeding 75W, an effective power factor correction (PFC) circuit must be configured. Although traditional PFC topologies can achieve a power factor PF≥0.9 to meet the basic compliance requirements, there are still the following two main technical deficiencies in practical applications:

[0004] 1. Adopting a hard-switching control method, it is easy to generate large switching losses under full-load conditions. The system efficiency usually cannot exceed 96%, and it is difficult to meet the technical requirements of high-efficiency standards such as 80Plus Titanium.

[0005] 2. Under hard switching, high-frequency switching devices are prone to serious switching losses and electromagnetic interference (EMI) problems, which not only affect the stability and reliability of the system, but also limit the process of miniaturization, high-frequency and high-power density integrated design of the whole machine.

[0006] When traditional parallel control methods are used and multiple PFC units operate simultaneously, it is easy to cause an increase in the ripple of the total input current, thus exacerbating electromagnetic interference (EMI), increasing the design difficulty of the EMI filter, and limiting the improvement of the overall system performance. To solve this problem, the industry widely adopts an interleaved parallel operation mode, that is, by making the switching tubes of each parallel branch conduct in turn with a certain phase difference (such as two-phase interleaving of 180°), so as to effectively suppress the high-frequency ripple of the input and output currents. However, at the same time, the increase in the switching frequency also brings significant switching loss problems. Especially when using third-generation wide-bandgap semiconductor devices (such as GaN devices), although they have the ability of high-frequency, high-voltage, and high-speed switching, when the frequency reaches the order of hundreds of kHz or even MHz, the switching loss may still become the main part of the total loss, thereby affecting the system efficiency, thermal stability, and device life. Summary of the Invention

[0007] The object of the present invention is to provide a converter for realizing soft switching, so as to solve the key technical bottleneck existing in the existing interleaved parallel Boost-type power factor correction (PFC) circuit in the continuous conduction mode (CCM), that is, a large turn-on loss is generated by the high-frequency switching device under the hard switching condition, which limits the operating frequency of the system and seriously restricts the improvement of the overall power density and energy efficiency level.

[0008] To achieve the above object of the invention, the present invention provides the following technical solutions:

[0009] A converter for realizing soft switching, characterized in that it adopts an active resonant branch, and the active resonant branch includes two auxiliary switching tubes and an auxiliary inductor. The auxiliary inductor is connected in series between the two auxiliary switching tubes. The active resonant branch is controlled by a main control unit. Before the main switch of the converter is about to conduct, the auxiliary switching tubes conduct in advance to drive the resonant process, and the node voltage of the switching tubes is transitioned to zero to realize soft switching operation.

[0010] Further, the converter circuit uses a typical interleaved parallel totem-pole Boost PFC topology as the design basis, including: an AC power supply, a first power inductor and a second power inductor, an auxiliary inductor, a first high-frequency switching tube, a second high-frequency switching tube, a third high-frequency switching tube, a fourth high-frequency switching tube, a first low-frequency switching tube, a second low-frequency switching tube, a first auxiliary switching tube, a second auxiliary switching tube, an output bus capacitor and a load resistor. The positive pole of the AC power supply is connected to the left ends of the first power inductor and the second power inductor. The source electrode of the first high-frequency switching tube is connected to the drain electrode of the second high-frequency switching tube and the source electrode of the second auxiliary switching tube. The source electrode of the third high-frequency switching tube is connected to the drain electrode of the fourth high-frequency switching tube and the source electrode of the first auxiliary switching tube. The drain electrode of the first high-frequency switching tube is connected to the drain electrode of the third high-frequency switching tube. The source electrode of the second high-frequency switching tube is connected to the source electrode of the fourth high-frequency switching tube. The left and right ends of the auxiliary inductor Lr are respectively connected to the source electrodes of the first auxiliary switching tube and the second auxiliary switching tube. The right end of the first power inductor is connected to the common terminal of the first high-frequency switching tube, the second high-frequency switching tube and the second auxiliary switching tube. The right end of the second power inductor is connected to the common terminal of the third high-frequency switching tube, the fourth high-frequency switching tube and the first auxiliary switching tube. The source electrode of the first low-frequency switching tube is connected to the drain electrode of the second low-frequency switching tube S2. The negative pole of the AC power supply is connected to the common terminal of the first low-frequency switching tube and the second low-frequency switching tube. The drain electrodes of the first high-frequency switching tube, the third high-frequency switching tube and the first low-frequency switching tube are respectively connected to the positive terminal of the output bus capacitor. The source electrodes of the second high-frequency switching tube, the fourth high-frequency switching tube and the second low-frequency switching tube are respectively connected to the negative terminal of the output bus capacitor. The load resistor is connected in parallel with the output bus capacitor Co.

[0011] The soft-switching topology of the interleaved parallel totem-pole bridgeless PFC converter adopts two high-frequency Boost bridge arms (the first high-frequency switch and the second high-frequency switch form the left half-bridge high-frequency bridge arm, and the third high-frequency switch and the fourth high-frequency switch form the right half-bridge high-frequency bridge arm), one auxiliary high-frequency bridge arm (the first auxiliary switch, the second auxiliary switch and the auxiliary inductor form the auxiliary bridge arm), and one low-frequency bridge arm (the first low-frequency switch and the second low-frequency switch form the low-frequency bridge arm), forming a two-way parallel interleaved structure. Compared with the structure of the traditional two-way interleaved parallel totem-pole bridgeless PFC converter, the power efficiency of the entire power converter is effectively improved. At the same time, since the two high-frequency bridge arms adopt switching control signals with the same frequency, the same duty cycle and 180° phase interleaved with each other, the two boost inductor circuits are charged and discharged interleaved by 180°, thus effectively reducing the input-side current and the output-side current ripple. The auxiliary bridge arm structure is used to control the charging and discharging process of the auxiliary inductor, thereby realizing zero turn-on loss of all high-frequency switches. The first power inductor and the second power inductor are the two-way power inductors respectively.

[0012] Further, the core of the converter control strategy lies in: by precisely coordinating the conduction and turn-off timings of the high-frequency main switches, the first high-frequency switch - the fourth high-frequency switch, and the auxiliary switches, the first auxiliary switch and the second auxiliary switch, zero-voltage turn-on / turn-off (ZVS) of the main switches and zero-current turn-on / turn-off (ZCS) of the auxiliary switches are achieved. Taking the positive half-cycle of the AC input as an example (that is, the first low-frequency switch in the low-frequency bridge arm is turned off and the second low-frequency switch is turned on), in order to achieve ZVS conduction of the first high-frequency switch, the second high-frequency switch, the third high-frequency switch, and the fourth high-frequency switch, the charge stored in the device drain-source capacitance Coss needs to be completely released before their conduction, so that their drain-source voltage is zero. To ensure the integrity of the resonance process, sufficient dead time must be provided for the main switches to complete the voltage transition of the auxiliary resonance branch, and then achieve turn-on under zero-voltage conditions. According to the relationship between the output voltage V o and the input voltage v ac , the system resonance characteristics are different. Therefore, the following will distinguish between V o ≥2v ac and V o <2v ac and analyze the two cases:

[0013] (1) When V o ≥2v ac :

[0014] Under this working condition, the resonance branch has sufficient energy storage capacity, which is conducive to achieving zero-voltage turn-on (ZVS) of each switching device. The specific soft-switching control process can be divided into the following four main stages:

[0015] The first stage (before the first high-frequency switching transistor turns off, the second high-frequency switching transistor realizes ZVS conduction):

[0016] At the initial moment, the first high-frequency switching transistor and the fourth high-frequency switching transistor are conducting, while the second high-frequency switching transistor, the third high-frequency switching transistor, and the auxiliary switches, namely the first auxiliary switch and the second auxiliary switch, are all in the off state. Before the first high-frequency switching transistor turns off, the first auxiliary switch is turned on in advance to form a resonant current i flowing from the second auxiliary switch to the first auxiliary switch Lr . As the resonant current gradually rises, when it reaches or exceeds the valley current of the first power inductor, the first high-frequency switching transistor is immediately turned off. At this time, the fourth high-frequency switching transistor remains conducting, and the auxiliary inductor, the first power inductor, and the drain-source capacitors of the first high-frequency switching transistor and the second high-frequency switching transistor form a series-parallel resonant circuit. The drain-source capacitor of the second high-frequency switching transistor starts to discharge, and the drain-source capacitor of the first high-frequency switching transistor starts to charge. When the drain-source voltage of the second high-frequency switching transistor drops to zero and the charge is completely released, turning on the second high-frequency switching transistor can realize the ZVS turn-on of the second high-frequency switching transistor.

[0017] The second stage (the third high-frequency switching transistor realizes ZVS conduction):

[0018] At the initial moment, the second high-frequency switching transistor and the fourth high-frequency switching transistor are conducting, while the first high-frequency switching transistor, the third high-frequency switching transistor, and the auxiliary switches, namely the first auxiliary switch and the second auxiliary switch, are all in the off state. When the fourth high-frequency switching transistor turns off, the second high-frequency switching transistor remains conducting, and all other switching devices are in the off state. The auxiliary inductor, the second power inductor, and the drain-source capacitors of the third high-frequency switching transistor and the fourth high-frequency switching transistor form a series-parallel resonant circuit. The drain-source capacitor of the third high-frequency switching transistor discharges rapidly, and the drain-source capacitor of the fourth high-frequency switching transistor charges rapidly. When the drain-source voltage of the fourth high-frequency switching transistor rises to the output voltage V o , the drain-source voltage of the third high-frequency switching transistor drops to zero, and its body diode D starts to conduct forward. At this time, turning on the third high-frequency switching transistor can realize the ZVS turn-on of the third high-frequency switching transistor.

[0019] The third stage (before the third high-frequency switching transistor turns off, the fourth high-frequency switching transistor realizes ZVS conduction):

[0020] At the initial moment, the second high-frequency switching transistor and the third high-frequency switching transistor are conducting, while the first high-frequency switching transistor, the fourth high-frequency switching transistor, and the first auxiliary switch and the second auxiliary switch are all in the off state. Before the third high-frequency switching transistor turns off, the second auxiliary switch is turned on in advance to form a resonant current i flowing from the first auxiliary switch to the second auxiliary switch LrAs the resonant current gradually rises, when it reaches or exceeds the valley current of the second power inductor of the power inductor, the third high-frequency switch is immediately turned off. At this time, the second high-frequency switch remains conducting, and the auxiliary inductor, the third high-frequency switch, and the drain-source capacitors of the fourth high-frequency switch form a series-parallel resonant circuit. The drain-source capacitor of the fourth high-frequency switch starts to discharge, and the drain-source capacitor of the third high-frequency switch starts to charge. When the drain-source voltage of the fourth high-frequency switch drops to zero and the charge is completely released, turning on the fourth high-frequency switch can achieve ZVS turn-on of the fourth high-frequency switch.

[0021] The fourth stage (ZVS turn-on of the first high-frequency switch):

[0022] At the initial moment, the second high-frequency switch and the fourth high-frequency switch are conducting, and the first high-frequency switch, the third high-frequency switch, and the auxiliary switches, the first auxiliary switch and the second auxiliary switch, are all in the off state. When the second high-frequency switch is turned off, the fourth high-frequency switch remains conducting, and all other switching devices are in the off state. The auxiliary inductor, the inductor, the first power inductor, and the drain-source capacitors of the first high-frequency switch and the second high-frequency switch form a series-parallel resonant circuit. The drain-source capacitor of the first high-frequency switch discharges rapidly, and the drain-source capacitor of the second high-frequency switch charges rapidly. When the drain-source voltage of the second high-frequency switch rises to the output voltage V o out, the drain-source voltage of the first high-frequency switch drops to zero, and its body diode D starts to conduct forward. At this time, turning on the first high-frequency switch can achieve ZVS turn-on of the first high-frequency switch.

[0023] (2) When V o <2v ac out:

[0024] Under this condition, the ZVS turn-on of the main switching tubes, the second high-frequency switch and the fourth high-frequency switch, depends on the energy transfer of the auxiliary inductor Lr during the resonant discharge process. To achieve their ZVS turn-on, it is necessary to ensure that there is sufficient energy in the resonant circuit to effectively extract the energy stored in the drain-source capacitor of the switching tube (the second high-frequency switch or the fourth high-frequency switch) to be turned on, and at the same time provide enough charging energy for the drain-source capacitor of the switching tube to be turned off, so as to construct a voltage waveform that meets the ZVS conditions.

[0025] The first stage (ZVS turn-on of the third high-frequency switch):

[0026] At the initial moment, the first high-frequency switch and the fourth high-frequency switch are conducting, and the second high-frequency switch, the third high-frequency switch, and the auxiliary switches, the first auxiliary switch and the second auxiliary switch, are all in the off state. Before the fourth high-frequency switch is turned off, the auxiliary switch, the first auxiliary switch, is turned on in advance to form a resonant current i flowing from the second auxiliary switch to the first auxiliary switch LrWhen the energy participating in resonance in the auxiliary inductor is sufficient to compensate for the total energy of the drain-source capacitances of the first high-frequency switching transistor and the second high-frequency switching transistor, the fourth high-frequency switching transistor is immediately turned off. At this time, the first high-frequency switching transistor remains in the conducting state, and the auxiliary inductor, the second power inductor, the third high-frequency switching transistor, and the drain-source capacitances of the fourth high-frequency switching transistor form a series-parallel resonance circuit, and the resonance current i Lr and the current of the second power inductor charge the drain-source capacitance of the fourth high-frequency switching transistor simultaneously. As the drain-source voltage of the fourth high-frequency switching transistor rises to the output voltage V o when the drain-source voltage of the third high-frequency switching transistor drops to zero, the body diode starts to conduct forward, and at this time, turning on the third high-frequency switching transistor can achieve ZVS turn-on of the third high-frequency switching transistor.

[0027] The second stage (realizing ZVS conduction of the second high-frequency switching transistor):

[0028] At the initial moment, the third high-frequency switching transistor remains conducting, the first high-frequency switching transistor is turned off, and the rest of the switching devices are all in the off state. In this stage, the auxiliary inductor Lr, the first power inductor, the first high-frequency switching transistor, and the drain-source capacitances of the second high-frequency switching transistor form a series-parallel resonance circuit, the drain-source capacitance of the second high-frequency switching transistor discharges rapidly, and the drain-source capacitance of the first high-frequency switching transistor is charged rapidly. When the drain-source voltage of the first high-frequency switching transistor rises to the output voltage V o when the drain-source voltage of the second high-frequency switching transistor drops to zero, the body diode of the second high-frequency switching transistor starts to conduct forward, and at this time, turning on the second high-frequency switching transistor can achieve ZVS turn-on of the second high-frequency switching transistor.

[0029] The third stage (realizing ZVS conduction of the first high-frequency switching transistor):

[0030] At the initial moment, the second high-frequency switching transistor and the third high-frequency switching transistor are conducting, and the first high-frequency switching transistor, the fourth high-frequency switching transistor, and the auxiliary switches, the first auxiliary switch and the second auxiliary switch are all in the off state. Before the second high-frequency switching transistor is turned off, the second auxiliary switch is turned on in advance to form a resonance current i Lr flowing from the first auxiliary switch to the second auxiliary switch. When the energy participating in resonance in the auxiliary inductor is sufficient to compensate for the total energy of the drain-source capacitances of the third high-frequency switching transistor and the fourth high-frequency switching transistor, the second high-frequency switching transistor is immediately turned off. At this time, the third high-frequency switching transistor remains in the conducting state, and the auxiliary inductor, the first power inductor, the first high-frequency switching transistor, and the drain-source capacitances of the second high-frequency switching transistor form a series-parallel resonance circuit, and the resonance current i Lr and the current of the first power inductor charge the drain-source capacitance of the second high-frequency switching transistor simultaneously. As the drain-source voltage of the second high-frequency switching transistor rises to the output voltage V oWhen the drain-source voltage of the first high-frequency switching transistor drops to zero, the body diode starts to conduct forward. At this time, turning on the first high-frequency switching transistor can achieve ZVS turn-on of the first high-frequency switching transistor.

[0031] The fourth stage (the fourth high-frequency switching transistor realizes ZVS conduction):

[0032] At the initial moment, the first high-frequency switching transistor remains conducting, the third high-frequency switching transistor is turned off, and the rest of the switching devices are in the off state. In this stage, the auxiliary inductor, the second power inductor of the inductor, and the drain-source capacitors of the third high-frequency switching transistor and the fourth high-frequency switching transistor form a series-parallel resonance circuit. The drain-source capacitor of the fourth high-frequency switching transistor discharges rapidly, and the drain-source capacitor of the third high-frequency switching transistor charges rapidly. When the drain-source voltage of the third high-frequency switching transistor rises to the output voltage Vo, the drain-source voltage of the fourth high-frequency switching transistor drops to zero, and the body diode D of the fourth high-frequency switching transistor starts to conduct forward. At this time, turning on the fourth high-frequency switching transistor can achieve ZVS turn-on of the fourth high-frequency switching transistor.

[0033] After the ZVS turn-on of the main switching transistor is completed, the voltage across the auxiliary active resonant bridge arm flips, and the current in the auxiliary inductor Lr gradually decreases until it approaches zero. Since the reverse resonant current is blocked by the body diode of the auxiliary switching transistor, the resonant current cannot continue to flow reversely, resulting in the energy on the auxiliary inductor being gradually dissipated or transferred to the output capacitor, and finally the resonant process naturally terminates. During this process, the auxiliary inductor current decreases linearly and cannot continue to build up reversely after passing through zero. The waveform of the auxiliary inductor current shows a typical single-sided decaying resonance characteristic throughout the process, providing good conditions for the subsequent zero-current (ZCS) turn-off of the auxiliary switching transistor, and at the same time avoiding current reverse shock and further reducing device stress and losses.

[0034] Furthermore, the sources of the two auxiliary switches in the resonant branch are respectively connected between the middle nodes of the two high-frequency bridge arm switches, and their drains are respectively connected to both ends of the auxiliary inductor. When the auxiliary switches are turned on, a resonant current path flowing from one bridge arm to the other bridge arm is formed.

[0035] Compared with the prior art, the remarkable advantages of the present invention are:

[0036] (1) Full-duty-cycle soft-switching ability under CCM: The present invention realizes zero-voltage turn-on of the high-frequency main switching transistor within the full-duty-cycle range in the continuous conduction (CCM) mode, effectively reducing the switching loss, simplifying the system thermal management design, and improving the stability and reliability of the system.

[0037] (2) Improvement of system efficiency and power density: By combining high-frequency soft-switching and interleaved control, the volume of the magnetic components and filters is effectively reduced, and the power output ability per unit volume is improved, meeting the design requirements of modern power systems with high performance and high integration.

[0038] (3) Input current quality optimization: By adopting the interleaved modulation and inductor ripple control strategy, the input current ripple is significantly reduced, the power factor is improved, and the input current ripple frequency is increased to twice that of the traditional design, effectively suppressing the losses and temperature rise of magnetic devices.

[0039] (4) The present invention is applicable to the switching power supply circuit structure with multi-phase interleaved parallel control, and has generality, reusability and portability. Description of the Drawings

[0040] Figure 1 It is the soft-switching circuit structure diagram of the interleaved parallel totem-pole PFC converter according to the implementation method of the present invention.

[0041] Figure 2 It is the schematic diagram of the relationship between the branch currents and the auxiliary inductor current corresponding drive signals during the positive half-cycle of the AC input in the embodiment of the present invention. Figure 2 In (a), it is the schematic diagram of the relationship when V o ≥2v ac ; Figure 2 In (b), it is the schematic diagram of the relationship when V o <2v ac .

[0042] Figure 3 It is the schematic diagram of the working stage of the V o ≥2v ac soft-switching circuit during the positive half-cycle of the AC input in the embodiment of the present invention. Figure 3 In (a), it is the schematic diagram of the [t0 - t1) stage. Figure 3 In (b), it is the schematic diagram of the [t1 - t2) stage. Figure 3 In (c), it is the schematic diagram of the [t2 - t3) stage. Figure 3 In (d), it is the schematic diagram of the [t3 - t4) stage. Figure 3 In (e), it is the schematic diagram of the [t4 - t5) stage. Figure 3 In (f), it is the schematic diagram of the [t5 - t6) stage. Figure 3 In (g), it is the schematic diagram of the [t6 - t7) stage. Figure 3 In (h), it is the schematic diagram of the [t7 - t8) stage. Figure 3 In (i), it is the schematic diagram of the [t8 - t9) stage.

[0043] Figure 4 It is the schematic diagram of the working stage of the V o <2v ac soft-switching circuit during the positive half-cycle of the AC input in the embodiment of the present invention. Figure 4 In (a), it is the schematic diagram of the [t′0 - t′1) stage. Figure 4 In (b), it is the schematic diagram of the [t′1 - t′2) stage.Figure 4 In (c), it is a schematic diagram of the [t′2 - t′3) stage, Figure 4 in (d), it is a schematic diagram of the [t′3 - t′4) stage, Figure 4 in (e), it is a schematic diagram of the [t′4 - t′5) stage, Figure 4 in (f), it is a schematic diagram of the [t′5 - t′6) stage, Figure 4 in (g), it is a schematic diagram of the [t′6 - t′7) stage, Figure 4 in (h), it is a schematic diagram of the [t′7 - t′8) stage, Figure 4 in (i), it is a schematic diagram of the [t′8 - t′9) stage.

[0044] Figure 5 It is the simulation waveform diagram of the ZVS turn - on of the main switch tube during the positive and negative half - cycles of the AC input in the embodiment of the present invention. Figure 5 In (a), when the AC input is in the positive half - cycle V o ≥2v ac it is the ZVS waveform diagram of the main switch tube Q2; Figure 5 In (b), when the AC input is in the positive half - cycle V o <2v ac it is the ZVS waveform diagram of the main switch tube Q2, Figure 5 In (c), when the AC input is in the negative half - cycle V o ≥2v ac it is the ZVS waveform diagram of the main switch tube Q1; Figure 5 In (d), when the AC input is in the negative half - cycle V o <2v ac it is the ZVS waveform diagram of the main switch tube Q1.

[0045] Figure 6 It is the simulation waveform diagram of the ZCS turn - on and turn - off of the auxiliary switch tube under the resonance assistance in the embodiment of the present invention. Figure 6 In (a), it is the ZCS turn - on and turn - off waveform diagram of the auxiliary switch tube S3, Figure 6 in (b), it shows the ZCS turn - on and turn - off waveform diagram of the auxiliary switch tube S4. Detailed implementation manners

[0046] The features and advantages of the present invention will be described in detail through implementation in combination with the accompanying drawings. It should be noted that, in case of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

[0047] In the following description, many specific details are set forth in order to provide a thorough understanding of the present invention. The described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0049] The present invention constructs a soft-switching path by introducing a set of active resonant branches composed of auxiliary switching devices and auxiliary inductors between two high-frequency bridge arms. Before the main switching device is turned on, by guiding the current into the resonant process, the switching node voltage is resonated to zero in advance, thereby realizing zero-voltage switching (ZVS) of the main power transistor. This method not only effectively reduces the energy loss during the high-frequency switching process, but also significantly alleviates the high-frequency electromagnetic interference (EMI) problem. Specifically, this embodiment designs a converter for realizing soft switching, which mainly includes:

[0050] (1) Soft-switching strategy design: The present invention proposes a soft-switching strategy that combines the continuous conduction mode condition and the interleaved control method to ensure a good resonant current transition channel before the main power transistor is turned on, and realizes ZVS turn-on.

[0051] (2) Active resonant branch construction: A set of active resonant branches composed of auxiliary inductors and auxiliary switching devices are connected in series and parallel between the midpoints of two phase bridge arms. This branch is controlled by the main control unit. Before the main switch is about to be turned on, the auxiliary switch is turned on in advance to drive the resonant process, and the switching node voltage is transitioned to zero to realize soft-switching operation.

[0052] (3) Current reverse path design: Auxiliary inductors and corresponding control logics are set in each phase channel to ensure that there is enough current reverse time after the main switch is turned off, enhance the ZVS coverage range, and improve the soft-switching operation stability of the system.

[0053] (4) Drive recognition and precise control: A matching ZVS drive recognition circuit is designed to accurately judge the soft-switching window, realize precise control of the auxiliary switch, and further reduce the device switching loss and EMI noise.

[0054] (5) Ripple Optimization and Inductance Control Mechanism: By adopting the interleaved modulation method of the dual-path power inductor current, the total harmonic distortion (THD) of the input current is significantly reduced through the phase cancellation of the current waveforms. Moreover, a current ripple superposition control strategy is introduced to increase the current ripple frequency, reduce the losses of magnetic devices, and improve the system efficiency and power density.

[0055] (6) Auxiliary Resonant Time Matching Control: According to the valley state of the power inductor current and the voltage change characteristics of the main switch device, the conduction time of the auxiliary switch is dynamically adjusted, so that the current in the auxiliary inductor completes the reverse compensation of the body diode current of the main power transistor before the main power transistor conducts, ensuring the reliability and consistency of ZVS implementation.

[0056] Based on the collaborative design of the above soft-switching topology and control strategy, the present invention effectively solves the efficiency bottleneck problem caused by hard switching in the traditional CCM mode, significantly reduces the turn-on loss on the premise of ensuring the continuity of the inductor current, broadens the working frequency range of the system, and improves the response ability, bus voltage regulation ability and anti-interference performance of the system under steady-state and dynamic conditions.

[0057] The solution of the present invention not only retains the inherent advantages of the interleaved parallel topology such as low input current ripple, high power density and high reliability, but also realizes soft-switching operation under high-frequency and high-efficiency conditions by introducing an active resonant mechanism, further improving the overall energy efficiency of the system and the service life of the devices. It is particularly suitable for application scenarios with strict requirements for energy efficiency and harmonic control, such as data center power supply and distribution systems, new energy electric vehicle charging modules, and high-performance industrial power supplies.

[0058] Embodiment

[0059] Figure 1 is an interleaved parallel totem-pole bridgeless PFC converter soft-switching topology. As Figure 1 shown, the interleaved parallel totem-pole bridgeless PFC converter soft-switching topology includes: an AC power supply, a first power inductor L1 and a second power inductor L2, an auxiliary inductor Lr, a first high-frequency switch Q1, a second high-frequency switch Q2, a third high-frequency switch Q3, a fourth high-frequency switch Q4, a first low-frequency switch S1, a second low-frequency switch S2, a first auxiliary switch S3 and a second auxiliary switch S4, an output bus capacitor Co, and a load resistor R L, wherein, the first high-frequency switching transistor Q1 and the second high-frequency switching transistor Q2 form a high-frequency bridge arm, and the middle node thereof is connected to the grid side through the first power inductor L1. The third high-frequency switching transistor Q3 and the fourth high-frequency switching transistor Q4 form another high-frequency bridge arm, and the middle node thereof is connected to the grid side through the second power inductor L2. Both ends of the two bridge arms are connected to both ends of the output side, and the output side is connected to the bus capacitor to output the bus capacitor Co. The two ends of the auxiliary inductor Lr are respectively connected to the drains of the first auxiliary switching transistor S3 and the second auxiliary switching transistor S4. The source of the first auxiliary switching transistor S3 is connected to the middle node of the high-frequency bridge arm formed by the third high-frequency switching transistor Q3 and the fourth high-frequency switching transistor Q4. The source of the second auxiliary switching transistor S4 is connected to the middle node of the high-frequency bridge arm formed by the first high-frequency switching transistor Q1 and the second high-frequency switching transistor Q2. The first low-frequency switching transistor S1 and the second low-frequency switching transistor S2 form a low-frequency bridge arm. The source of the first low-frequency switching transistor S1 is connected to the drain of the second low-frequency switching transistor S2, and the middle node thereof is connected to the grid side; the load resistor R L is connected in parallel with the output bus capacitor Co. In an embodiment of the present invention, the first high-frequency switching transistor Q1 to the fourth high-frequency switching transistor Q4 and the first auxiliary switching transistor S3 and the second auxiliary switching transistor S4 are all high-frequency switching transistors. For example, they can be: silicon carbide power semiconductors (SiC MOSFETs); the first low-frequency switching transistor S1 to the second low-frequency switching transistor S2 are power frequency switching transistors. For example, they can be: silicon carbide power semiconductors (SiC MOSFETs). The first high-frequency switching transistor Q1 to the fourth high-frequency switching transistor Q4 and the first low-frequency switching transistor S1 to the second auxiliary switching transistor S4 are respectively controlled by drive signals output by a digital processor (such as a DSP, Digital, digital signal processor, FPGA), such as PWM signals, to achieve conduction and turn-off.

[0060] To further elaborate the content and features of the present invention, the following combines the attached Figure 3 、 4 to specifically illustrate the working waveforms of the soft-switching topology of the present invention. For the convenience of analysis, the devices in the circuit structure are regarded as ideal devices. The second low-frequency switching transistor S2 works in the positive half-cycle of the AC input power supply, and the first low-frequency switching transistor S1 works in the negative half-cycle of the AC input power supply. Only the working process when V o ≥2v ac and V o <2v ac is analyzed. The working state in the negative half-cycle is analyzed in the same way.

[0061] (1) Working analysis when V o ≥2v ac , and the key waveforms are as Figure 2 (a) shown.

[0062] Stage 1: [t0 - t1)

[0063] As Figure 3 As shown in (a), at time t0, the first high-frequency switching transistor Q1 is turned on, the second high-frequency switching transistor Q2 is turned off, the fourth high-frequency switching transistor Q4 is turned on, the third high-frequency switching transistor Q3 is turned off, and the first auxiliary switching transistor S3 and the second auxiliary switching transistor S4 are turned off. The circuit is in the normal power transfer stage. In this stage, the current of the first power inductor L1 discharges through the first high-frequency switching transistor Q1 to provide energy for the load and the output capacitor output bus capacitor Co, and the voltage across the second power inductor L2 is v ac , and the current flows through the fourth high-frequency switching transistor Q4 for charging. Since the auxiliary resonant branch does not participate in the operation in this stage and the auxiliary transistor is always turned off, the resonant branch current is always zero during this process, that is, the auxiliary inductor current i Lr is zero.

[0064] Stage 2: [t1 - t2)

[0065] As Figure 3 As shown in (b), at time t1, the first auxiliary switching transistor S3 is turned on, and the circuit enters the resonant stage. In this stage, the first power inductor L1 continues to provide energy for the output capacitor output bus capacitor Co, while the second power inductor L2 is in the charging state. At the same time, the voltage across the auxiliary inductor Lr is V o , and the auxiliary inductor current i Lr gradually increases from zero, and the change of the auxiliary inductor current satisfies the following relational expression:

[0066]

[0067] The constraint condition is: i Lr (t1) = 0, i Lr (t2) = I L .

[0068] Since the auxiliary inductor current increases from zero and the current change rate is limited by the characteristics of the auxiliary inductor Lr, the first auxiliary switching transistor S3 realizes zero-current turn-on. During this process, D S4 will conduct naturally. The current of the first power inductor L1 supplies power to the output capacitor through the first high-frequency switching transistor Q1, and at the same time, part of the current is transferred to the auxiliary inductor Lr. At time t2, the current of the first power inductor L1 is all transferred to the auxiliary inductor Lr, and the current flowing through the first high-frequency switching transistor Q1 drops to zero, thus realizing zero-current turn-off of the first high-frequency switching transistor Q1. The duration T1 of this stage is:

[0069]

[0070] Stage 3: [t2 - t3)

[0071] As Figure 3As shown in (c), at time t2, the current of the first power inductor L1 has been completely transferred to the auxiliary inductor Lr. At this time, the current flowing through the first high-frequency switching transistor Q1 drops to zero, achieving its zero-current turn-off. At this moment, Q2 has not been turned on yet, and the drain-source voltage v ds_Q1 is still zero, and D Q1 will not show an obvious reverse recovery phenomenon, and the reverse recovery loss is almost zero. In this stage, the drain-source capacitances of the first high-frequency switching transistor Q1 and the second high-frequency switching transistor Q2 output the bus capacitance Co ss start to charge and discharge respectively, and resonate in series and parallel with the auxiliary inductor Lr. The expression of the resonance angular frequency is:

[0072]

[0073] During this resonance process, the voltage across the auxiliary inductor gradually decreases, and the resonance current continues to increase, providing conditions for the zero-voltage turn-on of Q2 in the next stage. At time t3, the voltage across the auxiliary inductor drops to zero, and the resonance current reaches the maximum value within this switching period, completing the entire resonance process. This process satisfies the following relationship:

[0074]

[0075] Among them, the inductor current at time t3 is:

[0076]

[0077] And the resonance duration T2 can be expressed as:

[0078]

[0079] Stage 4: [t3 - t4)

[0080] As Figure 3 (d) shows, at time t3, the series and parallel resonance of the drain-source capacitances of the first high-frequency switching transistor Q1, the second high-frequency switching transistor Q2 and the auxiliary inductor Lr ends. In this stage, D Q2 , the resonance branch and the fourth high-frequency switching transistor Q4 form a current path. Since the voltage across the auxiliary inductor is approximately zero, the resonance current maintains a continuous flow state in this path. During this period, the resonance current i Lr remains unchanged and maintains the maximum value within this period. At the same time, the drain-source capacitance of the second high-frequency switching transistor Q2 is completely discharged, the voltage across the source and drain drops to zero, and the body diode conducts naturally, reaching the zero-voltage turn-on condition. Therefore, in this stage, turning on the second high-frequency switching transistor Q2 at any time can achieve ZVS.

[0081] Stage 5: [t4 - t5)

[0082] As Figure 3(As shown in (e), at time t4, the voltage across the source and drain of Q2 drops to zero, achieving ZVS turn-on. During this stage, the first power inductor L1 is subjected to the AC input voltage v ac , and the inductor current shows a linearly increasing trend. Since the resonant current amplitude is greater than the current of the first power inductor L1, part of the resonant current flows back through the loop formed by the second high-frequency switch Q2, the resonant branch, and the fourth high-frequency switch Q4, forming a circulating current path. At the same time, the second power inductor L2 is still in the energy storage stage and remains in the charging state.

[0083] Stage 6: [t5 - t6)

[0084] As Figure 3 (shown in (f), at time t5, the fourth high-frequency switch Q4 turns off naturally with zero voltage. During this stage, both the third high-frequency switch Q3 and the fourth high-frequency switch Q4 are in the off state. At this time, the auxiliary inductor Lr resonates with the drain-source capacitors of the third high-frequency switch Q3 and the fourth high-frequency switch Q4. The drain-source capacitor of the third high-frequency switch Q3 discharges rapidly, and the drain-source capacitor of the fourth high-frequency switch Q4 charges rapidly. As the voltage across the drain-source capacitor of the fourth high-frequency switch Q4 rises to the output voltage V o , the voltage across the drain-source capacitor of the third high-frequency switch Q3 drops to zero, and D Q3 starts to conduct forward, providing the condition for the third high-frequency switch Q3 to achieve zero voltage. Since both the second power inductor L2 and the auxiliary inductor are at the peak current during this stage, the charge exchange process is completed rapidly, making this process very short.

[0085] Stage 7: [t6 - t7)

[0086] As Figure 3 (shown in (g), at time t6, the charge and discharge processes of the drain-source capacitors of the third high-frequency switch Q3 and the fourth high-frequency switch Q4 are completed, and the voltage across the drain-source capacitor of the fourth high-frequency switch Q4 rises to the output voltage V o . During this stage, D Q3 conducts, and the second power inductor L2 charges the output capacitor through D Q3 . Since the voltage across the auxiliary inductor is the reverse voltage of V o , the forward resonant current decreases linearly. At this time, the current in the auxiliary inductor gradually transfers to the second high-frequency switch Q2 until the resonant current drops to zero. The changes in this stage satisfy the following relationship:

[0087]

[0088] The boundary conditions for this stage are: i Lr (t6) = i L (t3), i Lr(t7) = 0, from which it can be deduced that the time T3 required for the resonant current to decay from the peak to zero is:

[0089]

[0090] Under ideal conditions, the resonant current i Lr After dropping to zero, it no longer changes until the next resonant startup, providing conditions for the natural turn-off of the first auxiliary switch tube S3. However, in practical applications, due to the presence of drain-source capacitance in the body diode of the switch tube, there is still a certain degree of conductivity during its turn-off process, resulting in a slight reverse flow of the resonant current, which finally ends at reverse cut-off.

[0091] Stage 8: [t7 - t8)

[0092] As Figure 3 (h) shows, at time t7, the voltage across the drain and source of the third high-frequency switch tube Q3 is zero, achieving zero-voltage turn-on, and the current in the auxiliary inductor Lr decreases to zero. During this stage, the first power inductor L1 is in the charging state, and the second power inductor L2 is in the discharging state.

[0093] Stage 9: [t8 - t9)

[0094] As Figure 3 (i) shows, at time t8, the first auxiliary switch tube S3 achieves zero-current natural turn-off. During this stage, the first power inductor L1 is in the charging state, and the second power inductor L2 is in the discharging state.

[0095] (2)V o <2v ac The working analysis at this time, the key waveforms are as Figure 2 (b) shows.

[0096] Stage 1: [t′0 - t′1)

[0097] As Figure 4 (a) shows, before t′0, the first high-frequency switch tube Q1 is conducting, the second high-frequency switch tube Q2 is off, the fourth high-frequency switch tube Q4 is conducting, the third high-frequency switch tube Q3 is off, and the first auxiliary switch tube S3 and the second auxiliary switch tube S4 are off. The circuit is in the normal power transfer stage. During this stage, the current in the first power inductor L1 discharges through the first high-frequency switch tube Q1 to provide energy for the load and the output capacitor output bus capacitor Co, and the voltage across the second power inductor L2 is v ac , and the current flows through the fourth high-frequency switch tube Q4 for charging. Since the auxiliary resonant branch does not participate in the operation during this stage and the auxiliary tube is always off, the resonant branch current is always zero during this process, that is, the auxiliary inductor current i Lr is zero.

[0098] Phase 2: [t′1 - t′2)

[0099] As Figure 4 (b) shows that at time t′1, the first auxiliary switch S3 achieves zero-current turn-on. In this stage, the first power inductor L1 is always in the state of supplying energy to the output capacitor and the bus capacitor Co, and the second power inductor L2 is in the charging state. Since the voltage across the auxiliary inductor Lr is V o , its current i Lr gradually increases from zero and satisfies the following formula:

[0100]

[0101] The constraint condition is:

[0102]

[0103] Since the resonant current gradually rises from zero and its rising rate is limited by the auxiliary inductor Lr, the first auxiliary switch S3 can achieve soft turn-on in the state of zero current, and D S4 also conducts naturally synchronously. As the resonant current increases, the current of the first power inductor L1 that originally charged the output capacitor via the first high-frequency switch Q1 gradually transfers to the auxiliary inductor Lr. At time t′2, D Q1 conducts naturally, and the voltage v ds_Q1 across the drain-source is zero, providing conditions for the zero-voltage turn-off of the first high-frequency switch Q1. At the same time, the resonant current reaches the maximum value of this period. The duration T′1 of this stage is:

[0104]

[0105] Phase 3: [t′2 - t′3)

[0106] As Figure 4 (c) shows that at time t′2, the charging of the auxiliary inductor Lr is completed. Due to the existence of the drain-source capacitance of the fourth high-frequency switch Q4, the rising speed dv / dt of the voltage across the drain-source during turn-off is reduced, thereby reducing the overlapping area of voltage and current and reducing the loss of the fourth high-frequency switch Q4 during turn-off, approximately achieving zero-voltage turn-off. In this stage, both the third high-frequency switch Q3 and the fourth high-frequency switch Q4 are in the off state, and the auxiliary inductor Lr resonates in series and parallel with the drain-source capacitances of the third high-frequency switch Q3 and the fourth high-frequency switch Q4. The drain-source capacitance of the third high-frequency switch Q3 discharges rapidly, and the drain-source capacitance of the fourth high-frequency switch Q4 charges rapidly. As the voltage across the drain-source capacitance of the fourth high-frequency switch Q4 rises to the output voltage V o , the voltage across the drain-source capacitance of the third high-frequency switch Q3 drops to zero, and D Q3The forward conduction starts, providing conditions for the third high-frequency switching transistor Q3 to achieve zero voltage. Since both the second power inductor L2 and the auxiliary inductor are at the peak current during this stage, the charge exchange process is completed rapidly, making this process very short in time.

[0107] Stage 4: [t′3 - t′4)

[0108] As Figure 4 (d) shows, at the moment of t′3, the drain-source capacitance of the fourth high-frequency switching transistor Q4 is charged to the output voltage V o . In this stage, the first high-frequency switching transistor Q1, the resonant branch, and D Q3 form a current loop. Since the voltage across the auxiliary inductor is approximately zero, the resonant current i Lr maintains the maximum value in the loop for freewheeling.

[0109] Stage 5: [t′4 - t′5)

[0110] As Figure 4 (e) shows, at the moment of t′4, the third high-frequency switching transistor Q3 achieves zero-voltage turn-on. In this stage, the second power inductor L2 charges the output capacitance and the bus capacitance Co through the third high-frequency switching transistor Q3; meanwhile, the current of the first power inductor L1 charges the output capacitance and the bus capacitance Co through the resonant circuit and the third high-frequency switching transistor Q3. During this time period, the voltage across the auxiliary inductor is zero, and its resonant current i Lr remains unchanged, maintaining the maximum value for freewheeling in the loop to store energy for the subsequent zero-voltage turn-on of Q2.

[0111] Stage 6: [t′5 - t′6)

[0112] As Figure 4 (f) shows, at the moment of t′5, the first high-frequency switching transistor Q1 achieves zero-voltage turn-off. In this stage, the drain-source capacitances of the first high-frequency switching transistor Q1 and the second high-frequency switching transistor Q2 and the bus capacitance Co ss start to charge and discharge respectively, and have series and parallel resonance with the auxiliary inductor Lr. The resonant angular frequency of this resonant process is:

[0113]

[0114] Under this operating stage, the voltage across the auxiliary inductor gradually increases, while the resonant current continuously decreases, providing conditions for the subsequent zero-voltage turn-on of the second high-frequency switching transistor Q2. At the moment of t′6, the drain-source capacitance voltage of the second high-frequency switching transistor Q2 drops to zero, and the series and parallel resonance process ends. According to the voltage and current changes, the following relational expressions can be obtained:

[0115]

[0116] Among them, at the moment t′6, the auxiliary inductor current is:

[0117]

[0118] Then the resonant time T′2 experienced by the resonant process is:

[0119]

[0120] Stage 7: [t′6 - t′7)

[0121] As Figure 4 (g) shows, at the moment t′6, the resonant process ends, and at this time D Q2 conducts. In this stage, the resonant current i Lr is greater than the current of the first power inductor L1. Therefore, part of the resonant current conducts freewheeling along the loop formed by D Q2 , the resonant branch, and the fourth high-frequency switch Q4. Since the working time of this process is short and the resonant current remains almost unchanged during this process, for the convenience of analysis, it can be assumed that the resonant current remains constant during this process.

[0122] Stage 8: [t′7 - t′8)

[0123] As Figure 4 (h) shows, at the moment t′7, the voltage across the source and drain of the second high-frequency switch Q2 is zero, achieving ZVS turn-on. In this stage, the first power inductor L1 bears the AC input voltage Vac, and the inductor current shows a linear increasing trend. Since the auxiliary inductor bears the reverse output voltage V o , the forward resonant current starts to linearly decrease until the resonant current drops to zero. The duration T′3 of this stage is:

[0124]

[0125] In the ideal case, after the auxiliary inductor current i Lr drops to zero, it no longer changes and continues until the next resonant stage of the resonant cavity, providing conditions for the zero-current turn-off of the first auxiliary switch S3.

[0126] Stage 9: [t′8 - t′9)

[0127] As Figure 4 (i) shows, at the moment t′8, the first auxiliary switch S3 achieves zero-current turn-off. In this stage, the first power inductor L1 is in the charging state, the second power inductor L2 is in the discharging state, and the resonant cavity exits the main power current transmission path in this stage until the next resonance starts.

[0128] As Figure 5The simulation waveforms of the zero-voltage switching (ZVS) turn-on of the main switching transistors of the converter during the positive and negative half-cycles of the AC input are shown. In the figure, v ds_Q1 and v ds_Q2 represent the drain-source voltages of the first high-frequency switching transistor Q1 and the second high-frequency switching transistor Q2, respectively, and v gs_Q1 and v gs_Q2 represent the gate-source drive signals of the first high-frequency switching transistor Q1 and the second high-frequency switching transistor Q2, respectively. Among them, Figure 5 (a) shows the ZVS waveform of the second high-frequency switching transistor Q2 when the positive half-cycle of the AC input V o ≥2v ac ; Figure 5 (b) shows the ZVS waveform of the second high-frequency switching transistor Q2 when the positive half-cycle of the AC input V o <2v ac . It can be seen from the waveforms that before the second high-frequency switching transistor Q2 turns on, its drain-source voltage v ds_Q2 has been reduced to 0V by the active resonant branch, and at the same time, the body diode has turned on, thus achieving ZVS turn-on, and the soft turn-on state is satisfied throughout the positive half-cycle. Figure 5 (c) shows the ZVS waveform of the first high-frequency switching transistor Q1 when the negative half-cycle of the AC input V o ≥2v ac ; Figure 5 (d) shows the ZVS waveform of the first high-frequency switching transistor Q1 when the negative half-cycle of the AC input V o <2v ac . Its waveform characteristics are similar to the operating state of Q2 in the positive half-cycle, indicating that the main switching transistors can achieve stable soft turn-on characteristics in both positive and negative half-cycles.

[0129] As Figure 6 shown are the zero-current switching (ZCS) waveforms of the auxiliary switching transistors under the resonance assistance. Among them, v gs_S3 and v gs_S4 represent the gate-source drive signals of the first auxiliary switching transistor S3 and the second auxiliary switching transistor S4, respectively, and i S3 and i S4 represent the currents on the corresponding switching transistors. Figure 6 (a) shows the ZCS turn-on and turn-off waveforms of the first auxiliary switching transistor S3. It can be seen from the figure that at the initial stage of the turn-on of the first auxiliary switching transistor S3, the auxiliary inductor Lr effectively suppresses the rising speed of the current i S3 , so that the first auxiliary switching transistor S3 turns on when the current is close to zero, achieving ZCS turn-on; at the same time, when the current i S3 drops to zero, the first auxiliary switching transistor S3 completes the turn-off, achieving the ZCS turn-off of the first auxiliary switching transistor S3, and the ZCS turn-on and turn-off are achieved throughout the process. Figure 6(b) shows the ZCS turn-on and turn-off waveforms of the auxiliary second auxiliary switch tube S4, and the working principle is the same as that of the first auxiliary switch tube S3.

[0130] The turn-on control time of the auxiliary switch tube can be calculated based on the drain-source capacitance of the switch tube and the detection of the real-time inductor current valley value, and is used to drive the turn-on and turn-off of the auxiliary bridge arm switch tube in the next cycle, so as to control the converter to achieve soft-switching control.

[0131] The goal is to achieve a high PF value and zero-voltage turn-on (ZVS) and zero-current turn-off (ZCS) of the power switch device under all operating conditions, which is beneficial to the high-frequency control of the system and improves the efficiency.

[0132] This converter is suitable for operating in the continuous conduction mode (CCM) and can convert the AC input voltage into a stable DC output.

[0133] The topology structure proposed by the present invention realizes more than 98% of the switching actions under soft-switching conditions by introducing the zero-voltage switching (ZVS) technology, significantly reducing the losses and device stresses generated during the switching process. At the same time, combined with the ripple cancellation characteristics of the two-phase interleaved parallel architecture, the current ripples on the input and output sides are effectively reduced, further improving the overall conversion efficiency and operation stability of the system. The technical solution of the present invention innovatively introduces a soft-switching control mechanism and deeply integrates it with the interleaved parallel structure, significantly reducing the switching losses and at the same time increasing the operating frequency and efficiency of the system, providing a reliable support for high-performance bidirectional AC-DC energy conversion. In summary, the interleaved parallel totem-pole bridgeless PFC converter topology based on active resonance and its soft-switching control method proposed by the present invention have comprehensive advantages such as high efficiency, high power factor, low loss, and strong adaptability, and have broad engineering application prospects and promotion value.

[0134] This paper takes the interleaved parallel totem-pole BOOST PFC topology as an example to illustrate the soft-switching structure, which is not limited to the interleaved parallel totem-pole BOOST PFC topology.

[0135] The above description is an explanation of the present invention, not a limitation of the invention. The scope defined by the present invention is referred to the claims, and any form of modification can be made within the protection scope of the present invention.

Claims

1. A converter for realizing soft switching, characterized in that, An active resonant branch is adopted. The active resonant branch includes two auxiliary switching tubes and an auxiliary inductor. The auxiliary inductor is connected in series between the two auxiliary switching tubes. The active resonant branch is controlled by the main control unit. Before the main switch of the converter is about to conduct, the auxiliary switching tubes conduct in advance to drive the resonant process, transition the switch node voltage to zero, and achieve soft-switching operation.

2. The converter for realizing soft switching according to claim 1, characterized in that Based on an interleaved totem-pole BOOST PFC topology, it includes an AC power supply, a first power inductor (L1) and a second power inductor (L2), an auxiliary inductor (Lr), a first high-frequency switching transistor (Q1), a second high-frequency switching transistor (Q2), a third high-frequency switching transistor (Q3), a fourth high-frequency switching transistor (Q4), a first low-frequency switching transistor (S1), a second low-frequency switching transistor (S2), a first auxiliary switching transistor (S3) and a second auxiliary switching transistor (S4), an output bus capacitor (Co), and a load resistor (R L ). The source of the first high-frequency switching transistor (Q1) is connected to the drain of the second high-frequency switching transistor (Q2) and the source of the second auxiliary switching transistor (S4). The source of the third high-frequency switching transistor (Q3) is connected to the drain of the fourth high-frequency switching transistor (Q4) and the source of the first auxiliary switching transistor (S3). The drain of the first high-frequency switching transistor (Q1) is connected to the drain of the third high-frequency switching transistor (Q3). The source of the second high-frequency switching transistor (Q2) is connected to the source of the fourth high-frequency switching transistor (Q4). Both ends of the auxiliary inductor (Lr) are respectively connected to the sources of the first auxiliary switching transistor (S3) and the second auxiliary switching transistor (S4). The positive pole of the AC power supply is respectively connected to one ends of the first power inductor (L1) and the second power inductor (L2). The other end of the first power inductor (L1) is connected to the common terminal of the first high-frequency switching transistor (Q1), the second high-frequency switching transistor (Q2), and the second auxiliary switching transistor (S4). The other end of the second power inductor (L2) is connected to the common terminal of the third high-frequency switching transistor (Q3), the fourth high-frequency switching transistor (Q4), and the second auxiliary switching transistor (S2). The source of the first low-frequency switching transistor (S1) is connected to the drain of the second low-frequency switching transistor (S2). The negative pole of the AC power supply is connected to the common terminal of the first low-frequency switching transistor (S1) and the second low-frequency switching transistor (S2). The drains of the first high-frequency switching transistor (Q1), the third high-frequency switching transistor (Q3), and the first low-frequency switching transistor (S1) are respectively connected to the positive pole of the output bus capacitor (Co). The sources of the second high-frequency switching transistor (Q2), the fourth high-frequency switching transistor (Q4), and the second low-frequency switching transistor (S2) are respectively connected to the negative pole of the output bus capacitor. The load resistor (R L ) is connected in parallel with the output bus capacitor (Co); By controlling the conduction and turn-off timings of the four high-frequency main switching tubes and the two auxiliary switching tubes, zero-voltage turn-on / turn-off of the main switching tubes and zero-current turn-on / turn-off of the auxiliary switching tubes are achieved.

3. The converter for implementing soft switching according to claim 2, wherein When V o ≥ 2v ac When this condition is met, by controlling the on / off timings of the four high-frequency main switching transistors and the two auxiliary switching transistors, zero-voltage turn-on / turn-off of the main switching transistors and zero-current turn-on / turn-off of the auxiliary switching transistors are achieved. Specifically, it includes: When V o ≥ 2v ac it includes: In the first stage, auxiliary resonance occurs before the first high-frequency switching tube (Q1) turns off, and the second high-frequency switching tube (Q2) achieves ZVS conduction. In the second stage, the third high-frequency switching tube (Q3) achieves ZVS conduction. In the third stage, auxiliary resonance occurs before the third high-frequency switching tube (Q3) turns off, and the fourth high-frequency switching tube (Q4) achieves ZVS conduction. In the fourth stage, the first high-frequency switching tube (Q1) achieves ZVS conduction. When V o <2v ac it includes: In the first stage, the third high-frequency switching tube (Q3) achieves ZVS conduction. In the second stage, the second high-frequency switching tube (Q2) achieves ZVS conduction. In the third stage, the first high-frequency switching tube (Q1) achieves ZVS conduction. In the fourth stage, the fourth high-frequency switching tube (Q4) achieves ZVS conduction. v ac is the AC power supply voltage, V o is the output voltage.

4. A converter for implementing soft switching according to claim 2, wherein, When V o ≥2v ac , the first stage specifically includes: at the initial moment, the first high-frequency switching transistors (Q1) and (Q4) are turned on, and the second high-frequency switching transistor (Q2), the third high-frequency switching transistor (Q3), and the first auxiliary switching transistor (S3) and the second auxiliary switching transistor (S4) are all in the off state. Before the first high-frequency switching transistor (Q1) is turned off, the first auxiliary switching transistor (S3) is turned on in advance to form a resonant current i Lr flowing from the second auxiliary switching transistor (S4) to the first auxiliary switching transistor (S3). As the resonant current gradually rises, when it reaches or exceeds the valley current of the first power inductor (L1), the first high-frequency switching transistor (Q1) is immediately turned off; at this time, the fourth high-frequency switching transistor (Q4) remains in the on state, and the auxiliary inductor (Lr), the first power inductor (L1), and the drain-source capacitors of the first high-frequency switching transistor (Q1) and the second high-frequency switching transistor (Q2) form a series-parallel resonant circuit. The drain-source capacitor of the second high-frequency switching transistor (Q2) starts to discharge, and the drain-source capacitor of the first high-frequency switching transistor (Q1) starts to charge; when the drain-source voltage of the second high-frequency switching transistor (Q2) drops to zero and the charge is completely released, the second high-frequency switching transistor (Q2) is turned on to achieve the ZVS turn-on of the second high-frequency switching transistor (Q2).

5. The converter for realizing soft switching according to claim 2, characterized in that When V o ≥ 2v ac , the second stage specifically includes: at the initial moment, the second high-frequency switching transistor (Q2) and the fourth high-frequency switching transistor (Q4) are turned on, and the second high-frequency switching transistor (Q1), the third high-frequency switching transistor (Q3), and the first auxiliary switching transistor (S3) and the second auxiliary switching transistor (S4) are all in the off state. When the fourth high-frequency switching transistor (Q4) is turned off, the second high-frequency switching transistor (Q2) remains turned on, and all other switching devices are in the off state; the auxiliary inductor (Lr), the second power inductor (L2), and the drain-source capacitors of the third high-frequency switching transistor (Q3) and the fourth high-frequency switching transistor (Q4) form a series-parallel resonance circuit. The drain-source capacitor of the third high-frequency switching transistor (Q3) discharges, and the drain-source capacitor of the fourth high-frequency switching transistor (Q4) charges. When the drain-source voltage of the fourth high-frequency switching transistor (Q4) rises to the output voltage V o , the drain-source voltage of the third high-frequency switching transistor (Q3) drops to zero. At this time, the third high-frequency switching transistor (Q3) is turned on to achieve the ZVS turn-on of the third high-frequency switching transistor (Q3).

6. A converter for implementing soft switching according to claim 2, characterized in that, When V o ≥ 2v ac In the third stage, specifically: at the initial moment, the second high-frequency switching transistor (Q2) and the third high-frequency switching transistor (Q3) are turned on, and the first high-frequency switching transistor (Q1), the fourth high-frequency switching transistor (Q4), the first auxiliary switching transistor (S3), and the second auxiliary switching transistor (S4) are all in the off state; before the third high-frequency switching transistor (Q3) is turned off, the second auxiliary switch (S4) is turned on in advance to form a resonant current i Lr flowing from the first auxiliary switching transistor (S3) to the second auxiliary switching transistor (S4). As the resonant current gradually rises and reaches or exceeds the valley current of the second power inductor (L2), the third high-frequency switching transistor (Q3) is turned off; at this time, the second high-frequency switching transistor (Q2) remains in the on state, and the auxiliary inductor (Lr) and the drain-source capacitors of the third high-frequency switching transistor (Q3) and the fourth high-frequency switching transistor (Q4) form a series-parallel resonant circuit. The drain-source capacitor of the fourth high-frequency switching transistor (Q4) starts to discharge, and the drain-source capacitor of the third high-frequency switching transistor (Q3) starts to charge. When the drain-source voltage of the fourth high-frequency switching transistor (Q4) drops to zero and all the charges are released, the fourth high-frequency switching transistor (Q4) is turned on to achieve ZVS turn-on of the fourth high-frequency switching transistor (Q4).

7. A converter for implementing soft switching according to claim 2, characterized in that, When V o ≥ 2v ac , the fourth stage specifically includes: at the initial moment, the second high-frequency switching transistor (Q2) and the fourth high-frequency switching transistor (Q4) are turned on, and the first high-frequency switching transistor (Q1), the third high-frequency switching transistor (Q3), the first auxiliary switching transistor (S3), and the second auxiliary switch (S4) are all in the off state; when the second high-frequency switching transistor (Q2) is turned off, the fourth high-frequency switching transistor (Q4) remains turned on, and all other switching devices are in the off state. The auxiliary inductor (Lr), the first power inductor (L1), and the drain-source capacitors of the first high-frequency switching transistor (Q1) and the second high-frequency switching transistor (Q2) form a series-parallel resonance circuit. The drain-source capacitor of the first high-frequency switching transistor (Q1) discharges, and the drain-source capacitor of the second high-frequency switching transistor (Q2) charges. When the drain-source voltage of the second high-frequency switching transistor (Q2) rises to the output voltage V o , the drain-source voltage of (Q1) drops to zero. At this time, turn on the first high-frequency switching transistor (Q1) to achieve the ZVS turn-on of the first high-frequency switching transistor (Q1).

8. A converter for implementing soft switching according to claim 2, characterized in that, When V o <2v ac During the first stage, specifically: at the initial moment, the first high-frequency switching transistor (Q1) and the fourth high-frequency switching transistor (Q4) are turned on, and the second high-frequency switching transistor (Q2), the third high-frequency switching transistor (Q3), the first auxiliary switching transistor (S3), and the second auxiliary switching transistor (S4) are all in the off state. Before the fourth high-frequency switching transistor (Q4) is turned off, the first auxiliary switch (S2) is turned on in advance to form a resonant current i flowing from the second auxiliary switching transistor (S4) to the first auxiliary switching transistor (S3). Lr When the energy participating in resonance in the auxiliary inductor (Lr) is sufficient to compensate for the total energy of the drain-source capacitances of the first high-frequency switching transistor (Q1) and the second high-frequency switching transistor (Q2), the fourth high-frequency switching transistor (Q4) is turned off. At this time, the first high-frequency switching transistor (Q1) remains in the on state, and the auxiliary inductor (Lr), the second power inductor (L2), and the drain-source capacitances of the third high-frequency switching transistor (Q3) and the fourth high-frequency switching transistor (Q4) form a series-parallel resonant circuit. The resonant current i Lr and the current of the second power inductor (L2) charge the drain-source capacitance of the fourth high-frequency switching transistor (Q4) at the same time. As the drain-source voltage of the fourth high-frequency switching transistor (Q4) rises to the output voltage V o when the drain-source voltage of the third high-frequency switching transistor (Q3) drops to zero, the third high-frequency switching transistor (Q3) is turned on to achieve ZVS turn-on of the third high-frequency switching transistor (Q3).

9. A converter for implementing soft switching according to claim 2, wherein, When V o <2v ac In the second stage, specifically: at the initial moment, the third high-frequency switching transistor (Q3) remains conducting, the first high-frequency switching transistor (Q1) is turned off, and the rest of the switching devices are all in the off state. The auxiliary inductor (Lr), the first power inductor (L1), and the drain-source capacitances of the first high-frequency switching transistor (Q1) and the second high-frequency switching transistor (Q2) form a series-parallel resonant circuit. The drain-source capacitance of the second high-frequency switching transistor (Q2) discharges, and the drain-source capacitance of the first high-frequency switching transistor (Q1) charges. When the drain-source voltage of the first high-frequency switching transistor (Q1) rises to the output voltage V o , the drain-source voltage of the second high-frequency switching transistor (Q2) drops to zero. At this time, the second high-frequency switching transistor (Q2) is turned on to achieve the ZVS turn-on of the second high-frequency switching transistor (Q2).

10. A converter for implementing soft switching according to claim 2, wherein When V o <2v ac In the third stage, specifically: at the initial moment, the second high-frequency switching transistor (Q2) and the third high-frequency switching transistor (Q3) are turned on, and the first high-frequency switching transistor (Q1), the fourth high-frequency switching transistor (Q4), and the first auxiliary switching transistor (S3) and the second auxiliary switching transistor (S4) are all in the off state. Before the second high-frequency switching transistor (Q2) is turned off, the second auxiliary switch (S4) is turned on in advance to form a resonant current i flowing from the first auxiliary switching transistor (S3) to the second auxiliary switching transistor (S4). Lr When the energy participating in resonance in the auxiliary inductor (Lr) is sufficient to compensate for the total energy of the drain-source capacitances of the third high-frequency switching transistor (Q3) and the fourth high-frequency switching transistor (Q4), the second high-frequency switching transistor (Q2) is turned off. At this time, the third high-frequency switching transistor (Q3) remains in the on state, and the auxiliary inductor (Lr), the first power inductor (L1), and the drain-source capacitances of the first high-frequency switching transistor (Q1) and the second high-frequency switching transistor (Q2) form a series-parallel resonant circuit. The resonant current i Lr and the current of the first power inductor (L1) charge the drain-source capacitance of the second high-frequency switching transistor (Q2) at the same time. As the drain-source voltage of the second high-frequency switching transistor (Q2) rises to the output voltage V o when, the drain-source voltage of the first high-frequency switching transistor (Q1) drops to zero. At this time, the first high-frequency switching transistor (Q1) is turned on to achieve the ZVS turn-on of the first high-frequency switching transistor (Q1). The fourth stage specifically includes: at the initial moment, the first high-frequency switching tube (Q1) maintains conduction, the third high-frequency switching tube (Q3) turns off, and the rest of the switching devices are in the off state. The auxiliary inductor (Lr), the second power inductor (L2), and the drain-source capacitors of the third high-frequency switching tube (Q3) and the fourth high-frequency switching tube (Q4) form a series-parallel resonant circuit. The drain-source capacitor of the fourth high-frequency switching tube (Q4) discharges, and the drain-source capacitor of the third high-frequency switching tube (Q3) charges. When the drain-source voltage of (Q3) rises to the output voltage Vo, the drain-source voltage of the fourth high-frequency switching tube (Q4) drops to zero. At this time, the fourth high-frequency switching tube (Q4) is turned on to achieve ZVS turn-on of (Q4).

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