RSSI (Received Signal Strength Indicator) sampling control device and method based on timer cascade mode

Abstract

The invention relates to the field of optical communication, in particular to an RSSI (Received Signal Strength Indicator) sampling control device and method based on a timer cascade mode, and the device comprises a main timer which is used for generating a main control signal, and the main control signal comprises the light-emitting starting and lasting time of an optical network unit I, a trigger signal A and a trigger signal B; the slave timer A is used for generating a slave control signal A according to the trigger signal A, and the slave control signal A comprises the light-emitting starting time and the light-emitting duration time of the optical network unit II; the slave timer B is used for generating a slave control signal B according to the trigger signal B, and the slave control signal B comprises the starting time and the duration time of the RSSI detection circuit; the register is used for realizing real-time dynamic adjustment of parameters of the master timer, the slave timer A and the slave timer B through mapping; the method has the advantages that accurate control of RSSI sampling can be realized without special hardware or complex interrupt logic by accurately configuring timer parameters.

Description

Technical Field

[0001] The present invention relates to the field of optical communication, and particularly to an RSSI sampling control device and method implemented based on a timer cascading method. Background Art

[0002] In the field of optical fiber communication, Passive Optical Network (PON), as the core technology for realizing "last mile" broadband access, realizes multi-user sharing of optical fiber resources through passive optical splitters. Its core advantage lies in reducing deployment costs and improving network capacity. With the continuous improvement of the requirements for uplink bandwidth and latency in services such as 5G and the Internet of Things, the optical signal transmission and reception performance of optical network units (ONUs) has become a key factor affecting system reliability. Among them, Received Signal Strength Indication (RSSI), as the core parameter for monitoring the quality of the optical link, its detection accuracy directly affects the implementation effects of functions such as optical power calibration, dynamic range adjustment, and fault diagnosis. In a passive optical network system, the optical line terminal (OLT) at the central office is responsible for global control, and the optical network unit on the user side provides terminal access. In terms of data transmission, in the downstream direction, a broadcast mechanism is adopted, and the signals sent by the OLT are distributed to all ONUs, and each terminal obtains exclusive data through address filtering. In the upstream direction, it works in burst mode. Due to the different luminous intensities, distances, and line losses of each optical network unit, the optical power reaching the optical line terminal is different. The OLT needs to detect the received optical power of each ONU at the OLT end to ensure the normal operation and performance optimization of the system. Precise timing control is required for communication between the OLT and the ONU to ensure synchronous data transmission and avoid signal conflicts. RSSI (Received Signal Strength Indication) is an important indicator for monitoring the optical signal strength in the PON system. In the upstream transmission of a passive optical network system, due to the use of Time Division Multiple Access (TDMA) mechanism, multiple optical network units need to send data within a strict time window allocated by the OLT. Guard Time is to solve this problem. Different products have different standard times for Guard Time. The typical value in GPON is 25.6ns, XG-PON is 51.2ns, and industrial-grade PON is 102.4ns.

[0003] There are significant differences in timing parameters among different manufacturers, and there are obvious disagreements on the timing requirements for RSSI trigger signals. In typical parameter configurations, the trigger delay time spans from 200 to 900 ns, and the pulse width difference is even more significant, ranging from 600 ns to 10 μs. Moreover, the precision required by manufacturers is also at the ns level. This lack of unified technical standards forces optical module manufacturers to carry out customized development, leading to a doubling of R & D investment, the complication of material management, and the increase in project operation and maintenance costs. Traditional RSSI calibration and testing methods usually rely on complex hardware devices such as phase-locked loop frequency synthesizer chips (PLL Frequency Synthesizer) and complex programmable logic devices (CPLD). Although this method has high flexibility and can achieve complex logic functions and precise timing control, its use also brings some problems: the chip itself is relatively expensive. For example, the unit price of XC95144XL is about $18.5, and the cost will also increase with the supporting circuits (such as clock distributors and level converters), which is several times higher than this solution; there are only a few suppliers globally that can provide such chips, and procurement is quite difficult; and it requires a professional development team for programming and debugging. This development process includes logic design, synthesis, placement and routing, and debugging and verification. The development cycle averages two to three months on average, and has high requirements for the technical level of developers. They need to be familiar with VHDL / Verilog, Timing Closure, signal integrity analysis, etc. For some manufacturers lacking CPLD development experience, the outsourcing development cost reaches $50k; the power consumption problem is particularly prominent when using CPLD, especially under complex logic control, and the power consumption increases by 80% compared to the MCU solution.

[0004] Based on this, this case is proposed. Summary of the Invention

[0005] One of the objectives of the present invention is to provide an RSSI sampling control device implemented based on the timer cascading method. By precisely configuring the timer parameters, precise control of RSSI sampling can be achieved without dedicated hardware or complex interrupt logic.

[0006] To achieve the above objective, the technical solution of the present invention is as follows:

[0007] An RSSI sampling control device implemented based on the timer cascading method, comprising:

[0008] A master timer for generating a master control signal, where the master control signal includes a reference time parameter signal of optical network unit one, a trigger signal A, and a trigger signal B;

[0009] A slave timer A, which generates a slave control signal A according to the trigger signal A, and the slave control signal A includes a reference time parameter signal of optical network unit two;

[0010] From Timer B, according to trigger signal B, generate slave control signal B, where the slave control signal B includes a reference time parameter signal of the RSSI detection circuit;

[0011] A register realizes real-time dynamic adjustment of the parameters of the master timer, slave timer A, and slave timer B through mapping.

[0012] Furthermore, it includes a multi-channel oscilloscope, which synchronously captures and analyzes the signals of the master timer, slave timer A, slave timer B, and the light of the optical module to verify the timing relationship and consistency among the signals.

[0013] The second object of the present invention is to provide a control method based on the above device, including the following processes:

[0014] Through register mapping, perform real-time dynamic adjustment of the parameters of the master timer, slave timer A, and slave timer B. Both slave timer A and slave timer B adopt the event trigger mode and the single-pulse working mode;

[0015] The master timer outputs a PWM waveform signal, which includes the reference time parameter of the optical network unit 1 and synchronously drives slave timer A and slave timer B;

[0016] The slave timer A outputs a PWM waveform signal with a phase opposite to that of the master timer. This PWM waveform signal includes the reference time parameter of the optical network unit 2, and a protection interval is inserted between the PWM waveform signal output by the slave timer A and the PWM waveform signal output by the master timer, so that the signal outputs of the optical network unit 1 and the optical network unit 2 do not overlap;

[0017] The slave timer B outputs a PWM waveform signal with the same phase as the master timer. This PWM waveform signal drives the RSSI detection circuit of the external optical module. By adjusting the trigger delay and trigger pulse width parameters of the slave timer B, the sampling window of the RSSI detection circuit is completely within the light emission time range of the optical network unit 2.

[0018] Furthermore, it includes a verification process: perform timing analysis using a multi-channel oscilloscope, synchronously capture the output waveforms of the master timer, slave timer A, slave timer B, and the optoelectronic conversion signal of the optical module, and verify the precision error of the trigger delay between the master timer and slave timer A and slave timer B, the consistency between the actual interval of the protection interval and the configured value, and the phase alignment degree between the RSSI trigger signal and the optical signal emission window.

[0019] The advantages of the present invention are:

[0020] By precisely configuring the timer parameters, precise control of RSSI sampling can be achieved without the need for dedicated hardware or complex interrupt logic. A timer is an important peripheral in a microcontroller (MCU) or microprocessor (MPU) used to generate precise time control signals. Compared with the CPLD solution, the MCU has a high integration level and integrates multiple functional modules (such as ADC, PWM, timer, etc.), which can reduce the use of peripheral components and thus lower the overall hardware cost. The production volume of MCUs in the market is very large, and common brands include the STM32 series of STMicroelectronics, the GD32 series of GigaDevice, etc. These MCUs are widely supplied in the market, and there are various purchase channels. Whether it is an online e-commerce platform or an offline electronics market, they can be easily obtained, and the prices are relatively transparent and low.

[0021] In addition, the development efficiency is also greatly improved. Without the need for a professional team or a complex development process, only firmware engineers need to configure the timer through the MCU using the C language and reuse the MCU self-check firmware to achieve this function. In the PON system, through this solution, the existing resource, the timer in the MCU, can be used to control the optical module of the ONU to emit light at a specific moment, trigger the RSSI sampling of the OLT or other timing-related operations, and achieve high-precision timing control required by the manufacturer by configuring parameters such as the counting period and duty cycle of multiple timers. Description of the Drawings

[0022] Figure 1 It is a schematic diagram of the control flow of the RSSI sampling control device implemented based on the timer cascade method in the embodiment;

[0023] Figure 2 It is a schematic diagram of the working process of optical network unit one, optical network unit two, and the RSSI detection circuit in the embodiment. Detailed Embodiment

[0024] The following further describes the present invention in detail with reference to the embodiments. It should be understood that the orientation or positional relationships indicated by the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc. in the text are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0025] This embodiment proposes an RSSI sampling control device implemented based on the timer cascade method. The control device adopts a master-slave timer cascade architecture to construct a three-layer timing control system. A timer is an important peripheral in a microcontroller (MCU) or microprocessor (MPU) used to generate precise time control signals. As Figure 1As shown in the figure, in the three-layer timing control system, there are a register, a master timer, a slave timer A, and a slave timer B.

[0026] The master timer is the core of timing control, outputting a positive-going PWM reference waveform that is low first and then high, and its duty cycle parameter can be dynamically adjusted. This waveform directly determines the reference time parameters of the optical network unit 1 (hereinafter referred to as ONU1), including the light emission start time and the light emission duration, and synchronously drives the slave timer A and the slave timer B through a hardware-level trigger signal (update event). As Figure 2 shown in the figure, in this embodiment, the falling edge of the master timer is used as the key time node, which is used to mark the starting point of the ONU1 optical signal emission and also serves as the synchronization reference for triggering the slave timer A / B.

[0027] The slave timer A operates in a reverse complementary mode and is started by the trigger signal of the master timer. Its output waveform is a PWM signal that is high first and then low and is opposite in phase to the master timer waveform, and a guard interval GuardTime is inserted between the two waveforms. As Figure 2 shown in the figure, this guard interval is achieved by adjusting the duty cycle of the slave timer A to ensure that the signals of the two ONUs do not overlap and avoid hardware conflicts caused by signal competition, that is, ONU2 is turned off when ONU emits light, and ONU2 emits light after the guard interval. The duty cycle and period of the slave timer A are independently adjustable and are used to control the duration and phase relationship of the optical network unit 2 (hereinafter referred to as ONU2) signal.

[0028] The slave timer B is dedicated to generating an external trigger (TRIGGER) signal and is also started by the trigger of the master timer. Its output uses a waveform that is low first and then high and is in the same phase as the master timer, but has independent trigger delay and trigger pulse width parameters. This trigger signal drives the RSSI detection circuit of the external optical module through a level transition event, and its falling edge marks the starting point of signal acquisition. As Figure 2 shown in the figure, by adjusting the trigger delay and trigger pulse width of this timer, the precise alignment of the RSSI sampling window and the optical signal emission window (the light emission duration of ONU2) can be achieved.

[0029] Both the slave timer A and the slave timer B are configured in the event-trigger mode, receiving the hardware-level cascade signal of the master timer, and adopting the single-pulse working mode. Only one pulse is output after being triggered, avoiding continuous occupation of CPU resources. The system parameter adjustment mechanism is based on a unified configuration interface, supporting independent control of TD (Trigger Delay), TW (Trigger Width), GuardTime (guard interval), and the optical signal emission duration. Among them, the duty cycle of the master timer adjusts the effective light-emitting time of ONU1; the duty cycle of the slave timer A determines the value of GuardTime and the light-emitting duration of ONU2; the trigger delay and trigger pulse width of the slave timer B correspond to the TD and TW parameters respectively. All parameters are dynamically adjusted in real time through register mapping to meet the timing adaptation requirements in different scenarios.

[0030] In terms of the integration of the RSSI trigger function, the trigger signal generated by the slave timer B is directly connected to the optical module control circuit, and its falling edge triggers the start of the RSSI sampling circuit. By adjusting the TD parameter, the phase shift of the RSSI detection window relative to the optical signal emission window can be realized to meet the detection requirements in different link delay scenarios. At the same time, the coordinated adjustment of the TW parameter and the duty cycle of the master timer can ensure that the RSSI sampling window completely covers the effective optical signal interval.

[0031] The verification and test scheme uses a multi-channel oscilloscope for timing analysis to synchronously capture the output waveforms of the master timer, slave timer A / B, and the optoelectronic conversion signal of the optical module. The following indicators are mainly verified: the precision error of the trigger delay of the master / slave timer, the consistency between the actual interval of GuardTime and the configured value, and the phase alignment degree between the RSSI trigger signal and the optical signal emission window. Finally, the precise matching between the RSSI detection window and the optical signal emission timing is realized to ensure the accuracy and reliability of the received signal strength measurement.

[0032] The solution of this embodiment is triggered by the master timer update event. The two slave timers adopt the event-trigger mode and the single-pulse working mode to achieve the master timer synchronously triggering the two slave timers to output one pulse, realizing the precise alignment between the RSSI detection window and the optical signal emission window. At the same time, it supports modifying the periods and duty cycles of the three timers through register mapping during operation to realize modifying the TD parameter and the TW parameter, and the required time for the double-ONU light-emitting duration, achieving high-precision timing control.

[0033] Based on the above device, the control process is as follows:

[0034] Through register mapping, the parameters of the master timer, slave timer A, and slave timer B are dynamically adjusted in real time. Both the slave timer A and the slave timer B adopt the event-trigger mode and the single-pulse working mode;

[0035] The master timer outputs a positive PWM waveform signal, which includes the reference time parameter of ONU1 and synchronously drives slave timer A and slave timer B. The reference time parameter of ONU1 is used to control the start and duration of ONU1;

[0036] Slave timer A outputs a PWM waveform signal with a phase opposite to that of the master timer. This PWM waveform signal includes the reference time parameter of ONU2. The reference time parameter of ONU2 is used to control the start and duration of ONU2, and a guard interval is inserted between the PWM waveform signal output by slave timer A and the PWM waveform signal output by the master timer, so that the signal outputs of ONU1 and ONU2 do not overlap;

[0037] Slave timer B outputs a PWM waveform signal with the same phase as the master timer. This PWM waveform signal drives the RSSI detection circuit of the external optical module. By adjusting the trigger delay and trigger pulse width parameters of slave timer B, the sampling window of the RSSI detection circuit is completely within the light-emitting time range of ONU2;

[0038] Verification and testing: Perform timing analysis using a multi-channel oscilloscope, synchronously capture the output waveforms of the master timer, slave timer A / B, and the optoelectronic conversion signal of the optical module, and verify the accuracy error of the trigger delay of the master / slave timer, the consistency between the actual interval of GuardTime and the configured value, and the phase alignment between the RSSI trigger signal and the optical signal emission window (the light-emitting duration of ONU2).

[0039] The above embodiments are only used to explain the concept of the present invention, rather than limiting the protection scope of the rights of the present invention. Any non-substantive changes made to the present invention using this concept shall fall within the protection scope of the present invention.

Claims

1. An RSSI sampling control device implemented based on a timer cascading method, characterized in that Comprising: A master timer for generating a master control signal, the master control signal including a reference time parameter signal of optical network unit 1, a trigger signal A, and a trigger signal B; A slave timer A for generating a slave control signal A according to the trigger signal A, the slave control signal A including a reference time parameter signal of optical network unit 2; A slave timer B for generating a slave control signal B according to the trigger signal B, the slave control signal B including a reference time parameter signal of the RSSI detection circuit; A register for realizing real-time dynamic adjustment of the parameters of the master timer, slave timer A, and slave timer B through mapping.

2. The RSSI sampling control device implemented based on the timer cascading method as described in claim 1, wherein, Comprising a multi-channel oscilloscope for verifying the timing relationship and consistency between signals by synchronously capturing and analyzing the signals of the master timer, slave timer A, slave timer B, and the light of the optical module.

3. A control method for an RSSI sampling control device implemented based on the timer cascade method according to any one of claims 1 to 2, characterized in that, Including the following process: Through register mapping, the parameters of the master timer, slave timer A, and slave timer B are adjusted in real time dynamically. Both the slave timer A and the slave timer B adopt an event trigger mode and a single-pulse working mode; The master timer outputs a PWM waveform signal, which includes the reference time parameter of optical network unit 1 and synchronously drives the slave timer A and the slave timer B; The slave timer A outputs a PWM waveform signal with a phase opposite to that of the master timer. This PWM waveform signal includes the reference time parameter of optical network unit 2, and a protection interval is inserted between the PWM waveform signal output by the slave timer A and the PWM waveform signal output by the master timer, so that the signal outputs of optical network unit 1 and optical network unit 2 do not overlap; The slave timer B outputs a PWM waveform signal with the same phase as the master timer. This PWM waveform signal drives the RSSI detection circuit of the external optical module. By adjusting the trigger delay and trigger pulse width parameters of the slave timer B, the sampling window of the RSSI detection circuit is completely within the light emission time range of optical network unit 2.

4. The control method for RSSI sampling implemented based on the timer cascading method as described in claim 3, wherein Including a verification process: performing timing analysis using a multi-channel oscilloscope, synchronously capturing the output waveforms of the master timer, slave timer A, and slave timer B and the optoelectronic conversion signal of the optical module, and verifying the precision error of the trigger delay between the master timer and the slave timer A and the slave timer B, the consistency between the actual interval of the protection interval and the configured value, and the phase alignment degree between the RSSI trigger signal and the optical signal emission window.

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