Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention relates to a semiconductor device, a manufacturing method thereof and electronic equipment, which are used for improving the accuracy of data reading. A memory cell of the device includes a capacitor, a first transistor, and a second transistor. The capacitor includes a first electrode and a second electrode. The first transistor includes a first gate, a first source / drain, and a second source / drain. The second transistor comprises a second grid electrode, a third source / drain electrode and a fourth source / drain electrode. A memory node of the memory cell includes a first electrode, a first gate, and a third source / drain having the same potential. The second electrode and the first word line have the same potential. The second gate and the second word line have the same potential. The first source / drain has the same potential as the first bit line. The second source / drain and the fourth source / drain have the same potential as the second bit line. The first word line is perpendicular to the substrate, and the first electrode at least partially surrounds the first word line. The size of the first grid electrode in the first direction is larger than that of the first electrode in the first direction.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technologies, and particularly to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technologies, the critical dimensions of devices are increasingly reduced, and the types and quantities of devices included in a single chip increase accordingly, such that any minor difference in the process production may affect the device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the requirements of current products. Summary of the Invention

[0004] Based on this, embodiments of the present disclosure provide a semiconductor device, a manufacturing method thereof, and an electronic device, which are beneficial to compensating the threshold voltage of a first transistor to ensure the accuracy of stored data reading, thereby further improving the performance of the semiconductor device and the electronic device.

[0005] According to some embodiments, the present disclosure provides a semiconductor device on one hand, including a substrate and at least one memory cell disposed on the substrate. The memory cell includes a capacitor, a first transistor, and a second transistor. The capacitor includes a first electrode and a second electrode disposed insulatingly. The first transistor includes a first gate, a first source / drain, and a second source / drain. The second transistor includes a second gate, a third source / drain, and a fourth source / drain. The first electrode, the first gate, and the third source / drain have the same potential, and the storage node of the memory cell includes the first electrode, the first gate, and the third source / drain. The second electrode has the same potential as a first word line. The second gate has the same potential as a second word line. The first source / drain has the same potential as a first bit line. The second source / drain and the fourth source / drain have the same potential as a second bit line. The first word line is perpendicular to the substrate, and the first electrode at least partially surrounds the first word line. The dimension of the first gate in a first direction is greater than the dimension of the first electrode in the first direction, and the first direction is parallel to the substrate.

[0006] According to some embodiments, the first transistor further includes a first semiconductor layer. The first source / drain and the second source / drain are respectively located in different regions of the first semiconductor layer. Wherein, the first semiconductor layer is in contact with the first bit line and is at least located on one side of the first bit line close to the substrate and on one side away from the substrate.

[0007] According to some embodiments, the first semiconductor layer is further located on one side of the first bit line close to the first word line.

[0008] According to some embodiments, the second transistor further includes a second semiconductor layer. The third source / drain and the fourth source / drain are respectively located in different regions of the second semiconductor layer; wherein, the second semiconductor layer is electrically connected to the second bit line through the first semiconductor layer.

[0009] According to some embodiments, the second gate overlaps with the first gate in a first direction and overlaps with the first electrode in a second direction. The second direction is parallel to the substrate and intersects with the first direction.

[0010] According to some embodiments, the first bit line and the second bit line respectively extend along the second direction and are spaced apart in the first direction; wherein, the second direction is parallel to the substrate and intersects with the first direction. The storage node is located between the first bit line and the second bit line and is insulated from both the first bit line and the second bit line.

[0011] According to some embodiments, the second transistor further includes a second semiconductor layer. The third source / drain and the fourth source / drain are respectively located in different regions of the second semiconductor layer. The second word line is perpendicular to the substrate. The second semiconductor layer at least partially surrounds the second word line.

[0012] According to some embodiments, the data read / write timing of the semiconductor device includes: a pre-charge stage, a data write stage, and a data read stage. The first bit line is configured to: provide a first reference voltage to the first transistor in the pre-charge stage, write data to the first transistor in the data write stage, and read data in response to the conduction state of the first transistor in the data read stage; wherein, the sum of the maximum data voltage corresponding to the data and the threshold voltage of the first transistor is the reference voltage; the first reference voltage is greater than the reference voltage.

[0013] According to some embodiments, the second bit line is configured to: provide the first reference voltage to both the first transistor and the second transistor simultaneously in the pre-charge stage, float in the data write stage, and provide a second reference voltage to both the first transistor and the second transistor simultaneously in the data read stage; wherein, the first reference voltage is greater than the second reference voltage.

[0014] According to some embodiments, a plurality of memory cells are arranged in columns along the second direction; wherein, the second direction is parallel to the substrate and intersects with the first direction; a column of memory cells shares a first bit line and a second bit line.

[0015] According to some embodiments, the semiconductor device further includes: a first isolation structure. The first isolation structure is located between the memory cells adjacent in the second direction, and between the second gate and the first gate in any memory cell.

[0016] According to some embodiments, the semiconductor device further includes: a second isolation structure. The second isolation structure is located between adjacent columns of memory cells; wherein, every two adjacent columns of memory cells are symmetric about the second isolation structure.

[0017] According to some embodiments, the semiconductor device further includes: a third isolation structure located between the first isolation structure and the first gate. The third isolation structure includes: a first sub-isolation structure. The first sub-isolation structure extends along a first direction, is located between a first bit line and a second bit line, and is located on a side of a first semiconductor layer of the first transistor facing away from the first gate.

[0018] According to some embodiments, the third isolation structure further includes: a second sub-isolation structure. The second sub-isolation structure extends along a third direction and is located between the first sub-isolation structure and the first isolation structure; the third direction is perpendicular to the substrate.

[0019] According to some embodiments, another aspect of the present disclosure further provides a manufacturing method of a semiconductor device for manufacturing the semiconductor device in the above-mentioned some embodiments, and the manufacturing method includes the following steps.

[0020] Provide a substrate and form a stacked structure on the substrate; the stacked structure includes a plurality of conductive material layers and a plurality of insulating material layers alternately stacked in a direction perpendicular to the substrate.

[0021] Etch the stacked structure in a direction perpendicular to the substrate to form a plurality of etched trenches and a plurality of first etched holes located between every two adjacent etched trenches.

[0022] Etch the conductive material layers respectively based on the etched trenches and the first etched holes, so that the remaining portions of the conductive material layers form a first gate, a virtual capacitor, and a virtual second transistor, and synchronously form a first accommodation region, a second accommodation region, and a third accommodation region.

[0023] Form a first gate dielectric layer and a first semiconductor layer in the first accommodation region, the second accommodation region, and the third accommodation region in sequence, form a first bit line covering the first semiconductor layer in the first accommodation region, and form a second bit line covering the first semiconductor layer in the second accommodation region; wherein, the first transistor includes a first gate, a first gate dielectric layer, and a first semiconductor layer.

[0024] Etch the stacked structure in a direction perpendicular to the substrate to form a second etched hole penetrating each virtual second transistor.

[0025] Remove each virtual second transistor based on the second etched hole to form a fourth accommodation region.

[0026] Form a second transistor in the fourth accommodation region; the second transistor includes: a second gate and a second semiconductor layer at least partially insulating and surrounding the circumference of the second gate.

[0027] According to some embodiments, after forming the second transistor in the fourth accommodation region, it further includes: etching the stacked structure in a direction perpendicular to the substrate to form a third etched hole and a first electrode penetrating each virtual capacitor.

[0028] A dielectric layer and a conductive structure are sequentially formed in the third etching hole. The conductive structure includes a second electrode and a first word line having the same potential as the second electrode. The capacitor includes a first electrode, a dielectric layer, and a second electrode.

[0029] According to some embodiments, a plurality of etching trenches are arranged at intervals in a first direction; wherein, the etching trenches extend in a second direction; the second direction intersects with the first direction and is parallel to the substrate. The first etching hole extends in the first direction, and a plurality of first etching holes are arranged at intervals in the second direction.

[0030] According to some embodiments, the third accommodating region communicates with the first accommodating region and the second accommodating region.

[0031] According to some embodiments, the fourth accommodating region exposes the virtual capacitor and the first semiconductor layer in contact with the second bit line.

[0032] According to some embodiments, the first electrode at least partially surrounds the first word line.

[0033] According to some embodiments, the method for manufacturing the memory further includes the following steps.

[0034] Before forming the etching trenches and the first etching holes, pattern the stacked structure to form a plurality of first isolation trenches; wherein, the first isolation trenches are used to define the formation positions of the memory cells and isolate adjacent memory cells in the second direction; the memory cells include a first transistor, a second transistor, and a capacitor.

[0035] Fill the first isolation trenches with an insulating material to form a first isolation structure.

[0036] According to some embodiments, forming a first gate dielectric layer and a first semiconductor layer in the first accommodating region, the second accommodating region, and the third accommodating region in sequence, forming a first bit line covering the first semiconductor layer in the first accommodating region, and forming a second bit line covering the first semiconductor layer in the second accommodating region includes the following steps.

[0037] In the etching regions of the etching trenches, the first etching holes, and the conductive material layer, form a first gate dielectric layer, a first semiconductor material layer, and a first sacrificial layer in sequence.

[0038] Remove the first sacrificial layer and the first semiconductor material layer in the etching trenches and the first etching holes, so that the remaining part of the first semiconductor material layer forms a first semiconductor layer, the remaining part of the first sacrificial layer in the first accommodating region forms a virtual first bit line, the remaining part of the first sacrificial layer in the second accommodating region forms a virtual second bit line, and the remaining part of the first sacrificial layer in the third accommodating region forms a first sub-isolation structure.

[0039] A second sacrificial layer is formed in the etched trench and the first etched hole.

[0040] The second sacrificial layer, the virtual first bit line, and the virtual second bit line in the etched trench are removed.

[0041] A first bit line covering the first semiconductor layer is formed in the first accommodating area.

[0042] A second bit line covering the first semiconductor layer is formed in the second accommodating area.

[0043] An insulating material is filled in the etched trench to form a second isolation structure.

[0044] Thus, the remaining portion of the second sacrificial layer in the first etched hole forms a second sub-isolation structure. The first sub-isolation structure and the second sub-isolation structure together constitute a third isolation structure.

[0045] According to some embodiments, a second transistor is formed in the fourth accommodating area, including the following steps.

[0046] A second semiconductor material layer and a third sacrificial layer are sequentially formed in the second etched hole and the fourth accommodating area.

[0047] The third sacrificial layer and the second semiconductor material layer in the second etched hole are removed, so that the remaining portion of the second semiconductor material layer forms a second semiconductor layer.

[0048] The remaining third sacrificial layer is removed.

[0049] A second gate dielectric layer and a second word line are sequentially formed in the second etched hole and the fourth accommodating area.

[0050] According to some embodiments, on the other hand, the present disclosure also provides an electronic device, including: the semiconductor device as described in the above embodiments.

[0051] The embodiments of the present disclosure may / at least have the following advantages:

[0052] In the embodiments of the present disclosure, by setting the first electrode of the capacitor, the first gate of the first transistor, and the third source / drain of the second transistor to have the same potential and forming a storage node of the storage unit therewith, and at the same time making the second electrode of the capacitor have the same potential as the first word line, the second gate of the second transistor have the same potential as the second word line, the first source / drain of the first transistor have the same potential as the first bit line, and the second source / drain of the first transistor and the fourth source / drain of the second transistor have the same potential as the second bit line, not only can the structural design of the storage node make full use of space and increase the storage capacity of the capacitor, but also the first bit line and the second bit line can provide different electrical signals to the first transistor at different stages of the data read / write cycle, and combined with the control of the gate voltages of the first transistor and the second transistor, the threshold voltage of the first transistor is retained at the storage node while data is written to the storage node in the data write stage, thereby facilitating reading of data not affected by the threshold voltage of the first transistor through the first bit line in the data read stage to ensure the accuracy of the stored data reading and further improve the performance of the semiconductor device.

[0053] Moreover, in the embodiments of the present disclosure, by setting the first word line perpendicular to the substrate, the first electrode at least partially surrounding the first word line, and the size of the first gate in the first direction being greater than the size of the first electrode in the first direction, it is also beneficial to increase the facing area between the first gate and the first semiconductor layer to improve the gate control ability of the first transistor.

[0054] In addition, in the embodiments of the present disclosure, the structure of the semiconductor device and its manufacturing method are as described above, which is also beneficial to reducing the process complexity to improve the production efficiency and process yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0056] Figure 1 FIG. is an equivalent circuit diagram of a 2T1C architecture storage unit provided in some embodiments of the present disclosure;

[0057] Figure 2 FIG. is an equivalent circuit diagram of a storage unit array in a three-dimensional memory provided in some embodiments of the present disclosure;

[0058] Figure 3 FIG. is a structural diagram of a storage unit and a memory provided in some embodiments of the present disclosure; wherein, Figure 3Figure (a) in [reference] is a top view schematic diagram of the shown structure. Figure 3 Figure (b) in [reference] is a cross-sectional schematic diagram perpendicular to the substrate along the A-A direction in Figure (a). Figure 3 Figure (c) in [reference] is a cross-sectional schematic diagram perpendicular to the substrate along the B-B direction in Figure (a). Figure 3 Figure (d) in [reference] is a cross-sectional schematic diagram perpendicular to the substrate along the C-C direction in Figure (a). Figure 3 Figure (e) in [reference] is a cross-sectional schematic diagram parallel to the substrate along the D-D direction in Figure (b).

[0059] Figure 4 is a schematic flow chart of a method for manufacturing a memory provided in some embodiments of the present disclosure.

[0060] Figure 5 is a schematic flow chart of another method for manufacturing a memory provided in some embodiments of the present disclosure.

[0061] Figure 6 is a schematic flow chart of a step S400 provided in some embodiments of the present disclosure.

[0062] Figure 7 is a schematic flow chart of a step S700 provided in some embodiments of the present disclosure.

[0063] Figure 8 is a schematic structural diagram of the obtained structure after forming a stacked structure; wherein, Figure 8 Figure (a) in [reference] is a top view schematic diagram of the obtained structure after forming a stacked structure. Figure 8 Figure (b) in [reference] is Figure 8 Figure (a) in [reference] Figure 1 is a cross-sectional schematic diagram perpendicular to the substrate along the A-A direction.

[0064] Figure 9 is a schematic structural diagram of the obtained structure after forming a first isolation structure; wherein, Figure 9 Figure (a) in [reference] is a top view schematic diagram of the obtained structure after forming a first isolation structure. Figure 9 Figure (b) in [reference] is Figure 9 Figure (a) in [reference] Figure 1 is a cross-sectional schematic diagram perpendicular to the substrate along the A-A direction.

[0065] Figure 10 is a schematic structural diagram of the obtained structure after forming an etching trench and a first etching hole; wherein, Figure 10 Figure (a) in [reference] is a top view schematic diagram of the obtained structure after forming an etching trench and a first etching hole.Figure 10 Figure (b) in Figure 10 Figure (a) in Figure 1 is a schematic cross-sectional view perpendicular to the substrate along the A-A direction, Figure 10 Figure (c) in Figure 10 Figure (a) in Figure 1 is a schematic cross-sectional view perpendicular to the substrate along the B-B direction;

[0066] Figure 11 is a schematic structural view of a structure obtained after forming a first accommodating region, a second accommodating region, and a third accommodating region in some embodiments of the present disclosure; wherein, Figure 11 Figure (a) in Figure 11 is a top view of the structure obtained after forming the first accommodating region, the second accommodating region, and the third accommodating region, Figure 11 Figure (a) in Figure 1 is a schematic cross-sectional view perpendicular to the substrate along the A-A direction, Figure 11 Figure (c) in Figure 11 Figure (a) in Figure 1 is a schematic cross-sectional view perpendicular to the substrate along the B-B direction;

[0067] Figure 12 is a schematic structural view of a structure obtained after forming a first gate dielectric layer, a first semiconductor material layer, and a first sacrificial layer in some embodiments of the present disclosure; wherein, Figure 12 Figure (a) in Figure 12 is a top view of the structure obtained after forming the first gate dielectric layer, the first semiconductor material layer, and the first sacrificial layer, Figure 12 Figure (a) in Figure 1 is a schematic cross-sectional view perpendicular to the substrate along the A-A direction, Figure 12 Figure (c) in Figure 12 Figure (a) in Figure 1 is a schematic cross-sectional view perpendicular to the substrate along the B-B direction;

[0068] Figure 13 is a schematic structural view of a structure obtained after forming a first semiconductor layer and a second sacrificial layer in some embodiments of the present disclosure; wherein, Figure 13 Figure (a) in Figure 13 is a top view of the structure obtained after forming the first semiconductor layer and the second sacrificial layer, Figure 13 Figure (a) in Figure 1 is a schematic cross-sectional view perpendicular to the substrate along the A-A direction, Figure 13 Figure (c) in Figure 13 Figure (a) in Figure 1 is a schematic cross-sectional view perpendicular to the substrate along the B-B direction;

[0069] Figure 14 Schematic diagram of a structure obtained after forming a bit line material layer in some embodiments of the present disclosure; wherein, Figure 14 Figure (a) in [the figure] is a top view schematic diagram of the structure obtained after forming the bit line material layer, Figure 14 Figure (b) in [the figure] is Figure 14 Figure (a) in [the figure] Figure 1 a schematic cross-sectional view perpendicular to the substrate along the A-A direction, Figure 14 Figure (c) in [the figure] is Figure 14 Figure (a) in [the figure] Figure 1 a schematic cross-sectional view perpendicular to the substrate along the B-B direction;

[0070] Figure 15 Schematic diagram of a structure obtained after forming a first bit line, a second bit line, and a second isolation structure in some embodiments of the present disclosure; wherein, Figure 15 Figure (a) in [the figure] is a top view schematic diagram of the structure obtained after forming the first bit line, the second bit line, and the second isolation structure, Figure 15 Figure (b) in [the figure] is Figure 15 Figure (a) in [the figure] Figure 1 a schematic cross-sectional view perpendicular to the substrate along the A-A direction, Figure 15 Figure (c) in [the figure] is Figure 15 Figure (a) in [the figure] Figure 1 a schematic cross-sectional view perpendicular to the substrate along the B-B direction, Figure 15 Figure (d) in [the figure] is Figure 15 Figure (a) in [the figure] Figure 1 a schematic cross-sectional view perpendicular to the substrate along the C-C direction;

[0071] Figure 16 Schematic diagram of a structure obtained after forming a second etching hole and a fourth accommodating region in some embodiments of the present disclosure; wherein, Figure 16 Figure (a) in [the figure] is a top view schematic diagram of the shown structure, Figure 16 Figure (b) in [the figure] is a schematic cross-sectional view perpendicular to the substrate along the A-A direction in Figure (a) of the shown structure;

[0072] Figure 17 Schematic diagram of a structure obtained after forming a second semiconductor material layer and a third sacrificial layer in some embodiments of the present disclosure; wherein, Figure 17 Figure (a) in [the figure] is a top view schematic diagram of the shown structure, Figure 17 Figure (b) in [the figure] is a schematic cross-sectional view perpendicular to the substrate along the A-A direction in Figure (a) of the shown structure;

[0073] Figure 18Schematic diagram of a structure obtained after forming a second semiconductor layer, a second gate dielectric layer, and a second word line in some embodiments of the present disclosure; wherein, Figure 18 Figure (a) in [reference] is a top view schematic diagram of the shown structure, Figure 18 Figure (b) in [reference] is a cross-sectional schematic diagram perpendicular to the substrate along the A-A direction in Figure (a) of the shown structure;

[0074] Figure 19 Schematic diagram of a structure obtained after forming a first electrode, a dielectric layer, a second electrode, and a first word line in some embodiments of the present disclosure; wherein, Figure 19 Figure (a) in [reference] is a top view schematic diagram of the shown structure, Figure 19 Figure (b) in [reference] is a cross-sectional schematic diagram perpendicular to the substrate along the A-A direction in Figure (a) of the shown structure;

[0075] Figure 20 Timing diagram of a driving method for a semiconductor device provided in some embodiments of the present disclosure;

[0076] Figure 21 Timing diagram of another driving method for a semiconductor device provided in some embodiments of the present disclosure;

[0077] Figure 22 Timing diagram of yet another driving method for a semiconductor device provided in some embodiments of the present disclosure;

[0078] Figure 23 Graph of the current-voltage characteristics of a first transistor during a data reading stage provided in some embodiments of the present disclosure.

[0079] Reference numerals:

[0080] U - storage unit, 1 - substrate, N - stacked structure, T1 - first transistor, G1 - first gate, S / D11 - first source / drain, S / D12 - second source / drain, T2 - second transistor, G2 - second gate, S / D21 - third source / drain, S / D22 - fourth source / drain, 21 - first semiconductor layer, 22 - second semiconductor layer, SN - storage node, BL1 - first bit line, BL2 - second bit line, WL1 - first word line, WL2 - second word line, YM - hard mask layer, L1 - conductive material layer, L2 - insulating material layer, H1 - first etching hole, H2 - second etching hole, H3 - third etching hole, 3 - capacitor, 3' - dummy capacitor, 31 - first electrode, 32 - second electrode, S - etching trench, R1 - first accommodating region, R2 - second accommodating region, R3 - third accommodating region, R4 - fourth accommodating region, T2' - dummy second transistor, BL1' - dummy first bit line, BL2' - dummy second bit line, 210 - first semiconductor material layer, 220 - second semiconductor material layer, 11 - first isolation structure, 111 - first sub - isolation part, 112 - second sub - isolation part, 12 - first gate dielectric layer, 13 - first sacrificial layer, 14 - second sacrificial layer, 15 - bit line material layer, 16 - second isolation structure, 17 - third sacrificial layer, 18 - second gate dielectric layer, 19 - dielectric layer, 4 - third isolation structure, 41 - first sub - isolation structure, 42 - second sub - isolation structure. Detailed implementation manners

[0081] For ease of understanding the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present disclosure are given in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present disclosure is more thorough and comprehensive.

[0082] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this disclosure belongs. The terms used in the specification of this disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0083] The mention of "embodiments" herein means that a particular feature, structure, or characteristic described in connection with the embodiments can be included in at least one embodiment of the present disclosure. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0084] It can be understood that the terms "first", "second", "third", "fourth", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, the first transistor may be referred to as the second transistor, and similarly, the second transistor may be referred to as the first transistor. Both the first transistor and the second transistor are transistors, but they are not the same transistor.

[0085] It can be understood that for the "connection" in the following embodiments, if there is a transfer of electrical signals or data between the connected circuits, modules, units, etc., it should be understood as "electrical connection", "communication connection", etc.

[0086] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprise / include" or "have" etc. specify the presence of the stated features, wholes, steps, operations, components, parts or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the related listed items.

[0087] Some embodiments of the present disclosure provide a semiconductor device, including a substrate and at least one memory cell, wherein the memory cell has 2T and 1C, 2T participates in pre-charging simultaneously, and 2T participates in writing data simultaneously, so as to realize the compensation of the threshold voltage of the first transistor in the writing stage.

[0088] Figure 1 The equivalent circuit diagram of a memory cell U in some embodiments of the present disclosure is shown. Please refer to Figure 1, the storage unit U is electrically connected to the first word line WL1, the first bit line BL1, the second word line WL2, and the second bit line BL2 respectively. The storage unit U includes: a first transistor T1, a second transistor T2, and a capacitor 3. Among them, the first transistor T1 includes: a first gate G1, a first source / drain S / D11, and a second source / drain S / D12. The second transistor T2 includes a second gate G2, a third source / drain S / D21, and a fourth source / drain S / D22. The capacitor 3 includes a first electrode 31 and a second electrode 32. Among them, the second electrode 32 of the capacitor 3 is connected to the first word line WL1, the first electrode 31 of the capacitor 3 is connected to the first gate G1, and the intersection point where the first electrode 31 is connected to the first gate G1 is the storage node SN. The second gate G2 is connected to the second word line WL2. The first source / drain S / D11 of the first transistor T1 is connected to the first bit line BL1. The third source / drain S / D21 of the second transistor T2 is connected to the storage node SN. The second source / drain S / D12 of the first transistor T1 and the fourth source / drain S / D22 of the second transistor T2 are respectively connected to the second bit line BL2.

[0089] Here, matching the transmission direction of the current, in the first source / drain S / D11 and the second source / drain S / D12 of the first transistor T1, one can be the source electrode and the other can be the drain electrode. In the third source / drain S / D21 and the fourth source / drain S / D22 of the second transistor T2, one can be the source electrode and the other can be the drain electrode. And, Figure 1 in the case where both the first transistor T1 and the second transistor T2 are N-type transistors is taken as an example for introduction, and the type of the transistor is not limited in practical applications.

[0090] And, it can be understood that a semiconductor device can be, for example, a memory, and usually includes a plurality of storage units U, and each storage unit U can be distributed in a two-dimensional single layer or a three-dimensional multi-layer. Exemplarily, the three-dimensional multi-layer distribution of each storage unit U and the related wiring can refer to Figure 2 the circuit shown for layout, and the embodiments of the present disclosure do not elaborate on this.

[0091] Figure 3 is a schematic structural diagram of a semiconductor device and its storage unit U in some embodiments of the present disclosure, for implementing the equivalent circuit of the storage unit U described in the above embodiments.

[0092] Please refer to Figure 1 and Figure 3It is understood that the semiconductor device includes a substrate 1 and at least one memory cell U. The memory cell U includes: a capacitor 3, a first transistor T1, and a second transistor T2. The capacitor 3 includes a first electrode 31 and a second electrode 32 which are insulated from each other. The first transistor T1 includes a first gate G1, a first source / drain S / D11, and a second source / drain S / D12. The second transistor T2 includes a second gate G2, a third source / drain S / D21, and a fourth source / drain S / D22. Among them, the first electrode 31, the first gate G1, and the third source / drain S / D21 have the same potential, and the storage node SN of the memory cell U may include the first electrode 31, the first gate G1, and the third source / drain S / D21. The second electrode 32 has the same potential as the first word line WL1. The second gate G2 has the same potential as the second word line WL2. The first source / drain S / D11 has the same potential as the first bit line BL1. Both the second source / drain S / D12 and the fourth source / drain S / D22 have the same potential as the second bit line BL2. The first word line WL1 is perpendicular to the substrate 1, and the first electrode 31 at least partially surrounds the first word line WL1. The size of the first gate G1 in the first direction (e.g., the X direction) is larger than the size of the first electrode 31 in the first direction (e.g., the X direction), and the first direction (e.g., the X direction) is parallel to the substrate 1.

[0093] Exemplarily, the first transistor T1 further includes a first semiconductor layer 21. The first source / drain S / D11 and the second source / drain S / D12 ( Figure 3 not shown in the figure) are respectively located in different regions of the first semiconductor layer 21.

[0094] Exemplarily, the second transistor T2 further includes a second semiconductor layer 22. The third source / drain S / D21 and the fourth source / drain S / D22 ( Figure 3 not shown in the figure) are respectively located in different regions of the second semiconductor layer 22.

[0095] In the embodiments of the present disclosure, by setting the first electrode 31 of the capacitor 3, the first gate G1 of the first transistor T1, and the third source / drain S / D21 of the second transistor T2 to have the same potential and forming a storage node SN of the storage unit U therewith, and at the same time making the second electrode 32 of the capacitor 3 have the same potential as the first word line WL1, the second gate G2 of the second transistor T2 have the same potential as the second word line WL2, the first source / drain S / D11 of the first transistor T1 have the same potential as the first bit line BL1, and both the second source / drain S / D12 of the first transistor T1 and the fourth source / drain S / D22 of the second transistor T2 have the same potential as the second bit line BL2, not only can the structural design of the storage node SN be utilized to fully utilize the space and increase the storage capacity of the capacitor 3, but also different electrical signals can be provided to the first transistor T1 by the first bit line BL1 and the second bit line BL2 at different stages of the data read / write cycle, and combined with the control of the gate voltages of both the first transistor T1 and the second transistor T2, the threshold voltage of the first transistor T1 is retained at the storage node SN while writing data to the storage node SN in the data writing stage, thereby facilitating reading, through the first bit line BL1, of data that is not affected by the threshold voltage of the first transistor T1 in the data reading stage, so as to ensure the accuracy of the stored data reading and further improve the performance of the semiconductor device.

[0096] Moreover, in the embodiments of the present disclosure, by setting the first word line WL1 perpendicular to the substrate 1, the first electrode 31 at least partially surrounding the first word line WL1, and the size of the first gate G1 in the first direction (e.g., the X direction) being larger than the size of the first electrode 31 in the first direction (e.g., the X direction), it is also beneficial to increase the facing area between the first gate G1 and the first semiconductor layer 21 in the first transistor T1, so as to improve the gate control ability of the first transistor T1.

[0097] In some embodiments, please continue to refer to Figure 3 , the first semiconductor layer 21 is in contact with the first bit line BL1 and is at least located on one side of the first bit line BL1 close to the substrate 1 and on one side away from the substrate 1.

[0098] In some embodiments, please continue to refer to Figure 3 , the first semiconductor layer 21 is also located on one side of the first bit line BL1 close to the first word line WL1.

[0099] In some embodiments, please continue to refer to Figure 3 , the second semiconductor layer 22 is electrically connected to the second bit line BL2 through the first semiconductor layer 21.

[0100] In some embodiments, please continue to refer to Figure 3, the second gate G2 overlaps with the first gate G1 in a first direction (e.g., the X direction) and overlaps with the first electrode 31 in a second direction (e.g., the Y direction). The second direction (e.g., the Y direction) is parallel to the substrate 1 and intersects with the first direction (e.g., the X direction), for example, orthogonally. Thus, it is beneficial to further improve the space utilization rate of the semiconductor device to increase the storage density.

[0101] In some embodiments, please continue to refer to Figure 3 , the first bit line BL1 and the second bit line BL2 extend along the second direction (e.g., the Y direction) respectively and are spaced apart in the first direction (e.g., the X direction). The storage node SN is located between the first bit line BL1 and the second bit line BL2 and is insulated from both the first bit line BL1 and the second bit line BL2.

[0102] In some embodiments, please continue to refer to Figure 3 , the second word line WL2 is perpendicular to the substrate 1. The second semiconductor layer 22 at least partially surrounds the second word line WL2.

[0103] As described above, some of the following embodiments of the present disclosure provide more specific examples for the structure and application of the above semiconductor device.

[0104] Please refer to Figure 3 , in some embodiments of the present disclosure, the capacitor 3 includes: a first electrode 31, a dielectric layer 19, and a second electrode 32. The first electrode 31 has an annular structure. The dielectric layer 19 covers the inner sidewall of the first electrode 31. The second electrode 32 covers the surface of the dielectric layer 19 facing away from the first electrode 31 and fills the inner region of the ring of the first electrode 31, and has the same potential as the first word line WL1.

[0105] The first transistor T1 includes: a first gate G1 and a first semiconductor layer 21. The first gate G1 has the same potential as the first electrode 31 and extends along the first direction (e.g., the X direction). The first semiconductor layer 21 is insulatingly disposed on the sidewall of the first gate G1 facing away from the first electrode 31, and covers the sidewall and the upper and lower surfaces of the first bit line BL1 close to the first gate G1, and the sidewall and the upper and lower surfaces of the second bit line BL2 close to the first gate G1. In this first transistor T1, the portions of the first semiconductor layer 21 corresponding to the connection with the first bit line BL1 and the second bit line BL2 are respectively used to form a first source / drain S / D11 and a second source / drain S / D12. Moreover, the first semiconductor layer 21 covers the sidewall and the upper and lower surfaces of the first bit line BL1 close to the first gate G1, and the sidewall and the upper and lower surfaces of the second bit line BL2 close to the first gate G1, which can ensure that the first transistor T1 and the first bit line BL1 and the second bit line BL2 all have a large contact area, so as to facilitate reducing the contact resistance.

[0106] The second transistor T2 includes: a second gate G2 and a second semiconductor layer 22. The second gate G2 is located on one side of the first electrode 31 in the first direction (e.g., the X direction) and on the side of the first gate G1 closer to the first electrode 31 in the second direction (e.g., the Y direction), and has the same potential as the second word line WL2. The second direction (e.g., the Y direction) and the first direction (e.g., the X direction) intersect, e.g., are orthogonal. The second semiconductor layer 22 is insulated and surrounds the circumference of the second gate G2. The first side wall of the second semiconductor layer 22 that is close to the first electrode 31 and extends in the second direction (e.g., the Y direction) is electrically connected to the first electrode 31, and the second side wall of the second semiconductor layer 22 that extends in the second direction (e.g., the Y direction) and is opposite to the first side wall is electrically connected to the second bit line BL2.

[0107] It should be added that the data read / write timing of the storage unit U includes: a data writing stage, a data reading stage, and a standby stage (which can be understood as the standby stage) before data writing or reading; wherein, in the embodiments of the present disclosure, a pre-charge stage is further included before the data writing stage, and a data holding stage is further included after the data writing stage. Thus, the above-mentioned first word line WL1, first bit line BL1, second word line WL2, and second bit line BL2 that are correspondingly electrically connected to the storage unit U can provide corresponding electrical signals to the storage unit U according to the requirements of different timing stages of the storage unit U. The following takes the first transistor T1 and the second transistor T2 both being N-type transistors as an example for illustration.

[0108] Exemplarily, the first bit line BL1 is configured to: provide a first reference voltage to the first transistor T1 in the pre-charge stage, write data to the first transistor T1 in the data writing stage, and read data in response to the conduction state of the first transistor T1 in the data reading stage; wherein, the sum of the maximum data voltage corresponding to the data and the threshold voltage of the first transistor T1 is the reference voltage; the first reference voltage is greater than the reference voltage.

[0109] Exemplarily, the second bit line BL2 is configured to: provide the first reference voltage to both the first transistor T1 and the second transistor T2 in the pre-charge stage, be floating in the data writing stage, and provide the second reference voltage to both the first transistor T1 and the second transistor T2 in the data reading stage. The first reference voltage is greater than the second reference voltage.

[0110] Exemplarily, in the standby stage, the first bit line BL1 is configured to provide the first reference voltage to the first transistor T1, and the second bit line BL2 is configured to provide the first reference voltage to both the first transistor T1 and the second transistor T2.

[0111] In the embodiments of the present disclosure, by setting the first electrode 31 of the capacitor 3 to be an annular structure, and insulating the first gate G1 on the sidewall of the first semiconductor layer 21 extending in the first direction (e.g., the X direction) and electrically connecting the first gate G1 to the first electrode 31, the second gate G2 of the second transistor T2 can be disposed on one side of the first electrode 31 in the first direction (e.g., the X direction) and on the side of the first gate G1 close to the first electrode 31 in the second direction (e.g., the Y direction), and the second semiconductor layer 22 of the second transistor T2 is electrically connected to the first electrode 31 and the second bit line BL2 respectively while insulatingly surrounding the circumference of the second gate G2. Based on this, the embodiments of the present disclosure can use the first bit line BL1 and the second bit line BL2 to provide different electrical signals to the first transistor T1 at different stages of the data read / write cycle, and combine the control of the control voltages of the first transistor T1 and the second transistor T2, so as to retain the threshold voltage of the first transistor T1 at the storage node SN while writing data to the storage node SN during the data writing stage, and then facilitate reading data that is not affected by the threshold voltage of the first transistor T1 through the first bit line BL1 during the data reading stage, so as to ensure the accuracy of the stored data reading and further improve the memory performance. In addition, in the embodiments of the present disclosure, the structure of the storage unit U and the memory is as described above, which is also conducive to reducing the process complexity to improve the production efficiency and process yield.

[0112] In some embodiments, please continue to refer to Figure 3 , the storage unit U further includes: a first gate dielectric layer 12 disposed between the first gate G1 and the first semiconductor layer 21, and a second gate dielectric layer 18 disposed between the second semiconductor layer 22 and the second gate G2.

[0113] Exemplarily, the materials of the first gate dielectric layer 12 and the second gate dielectric layer 18 include but are not limited to silicon oxide.

[0114] In some embodiments, please refer to Figure 3 in FIGS. (b) and (e) of

[0115] The second semiconductor layer 22 is electrically connected to the second bit line BL2 through the first semiconductor layer 21, which can be manifested as: the second sidewall of the second semiconductor layer 22 contacts and covers the sidewall of the first semiconductor layer 21 covering the second bit line BL2.

[0116] In some embodiments, please refer to Figure 3 in FIGS. (d) and (e) of

[0117] In some embodiments, referring to Figure 3 FIGS. (a) and (b) in

[0118] In the embodiments of the present disclosure, the first bit line BL1 and the second bit line BL2 are arranged in parallel and spaced apart, which is beneficial to realizing the compact arrangement of the memory cells U within the space between the first bit line BL1 and the second bit line BL2, and effectively utilizing the connection node (i.e., the storage node SN) between the first electrode 31 and the first gate G1 to realize the connection and position demarcation between the first transistor T1 and the second transistor T2.

[0119] According to some embodiments, the first word line WL1 and the second word line WL2 extend along a third direction (e.g., the Z direction) perpendicular to the substrate 1, and the third direction (e.g., the Z direction) intersects both the first direction (e.g., the X direction) and the second direction (e.g., the Y direction); wherein, the second electrode 32 and the first word line WL1 may be an integral structure; the second gate G2 and the second word line WL2 may be an integral structure.

[0120] In some embodiments, continue to refer to Figure 3 , a plurality of memory cells U are arranged in columns along the second direction (e.g., the Y direction); wherein, one column of memory cells U shares one first bit line BL1 and one second bit line BL2.

[0121] In some embodiments, continue to refer to Figure 3 , the memory further includes: a first isolation structure 11. The first isolation structure 11 is located between the memory cells U adjacent in the second direction (e.g., the Y direction), and between the second gate G2 and the first gate G1 in any one of the memory cells U.

[0122] In some embodiments, continue to refer to Figure 3 , the memory further includes: a second isolation structure 16. The second isolation structure 16 is located between adjacent columns of memory cells U; wherein, every two adjacent columns of memory cells U are symmetric about the second isolation structure 16.

[0123] In some embodiments, continue to refer to Figure 3, the memory further includes: a third isolation structure 4 located between the first isolation structure 11 and the first gate G1 in the adjacent memory cell U. The third isolation structure 4 includes: a first sub-isolation structure 41. The first sub-isolation structure 41 extends in a first direction (e.g., the X direction) between the first bit line BL1 and the second bit line BL2 and is located on a side of the first semiconductor layer 21 facing away from the first gate G1.

[0124] In some embodiments, please continue to refer to Figure 3 , the third isolation structure 4 further includes: a second sub-isolation structure 42. The second sub-isolation structure 42 extends in a third direction (e.g., the Z direction perpendicular to the substrate 1) and is located between the first sub-isolation structure 41 and the first isolation structure 11.

[0125] Some embodiments of the present disclosure also provide a method for manufacturing a semiconductor device for manufacturing the semiconductor device in the above-mentioned some embodiments. The technical advantages possessed by the aforementioned semiconductor device are also possessed by the method for manufacturing the semiconductor device, which will not be elaborated here.

[0126] Please refer to Figure 4 , in some embodiments of the present disclosure, the method for manufacturing the semiconductor device includes the following steps S100 to S900.

[0127] S100, providing a substrate and forming a stacked structure on the substrate; the stacked structure includes multiple layers of conductive material layers and multiple layers of insulating material layers alternately stacked in a direction perpendicular to the substrate.

[0128] S200, etching the stacked structure in a direction perpendicular to the substrate to form multiple etching trenches and multiple first etching holes located between every two adjacent etching trenches.

[0129] Exemplarily, the multiple etching trenches are arranged at intervals in a first direction; wherein, the etching trenches extend in a second direction; the second direction intersects with the first direction and is parallel to the substrate. The first etching holes extend in the first direction, and the multiple first etching holes are arranged at intervals in the second direction.

[0130] S300, etching the conductive material layers based on the etching trenches and the first etching holes respectively, so that the remaining portions of the conductive material layers form storage gates and virtual write transistors, and simultaneously forming a first accommodation area, a second accommodation area, and a third accommodation area.

[0131] Exemplarily, the third accommodation area communicates with the first accommodation area and the second accommodation area.

[0132] S400, form a first gate dielectric layer and a first semiconductor layer in a first accommodation area, a second accommodation area, and a third accommodation area in sequence, form a first bit line covering the first semiconductor layer in the first accommodation area, and form a second bit line covering the first semiconductor layer in the second accommodation area; wherein, the first transistor includes a first gate, a first gate dielectric layer, and a first semiconductor layer.

[0133] S500, etch the stacked structure along a direction perpendicular to the substrate to form a second etch hole penetrating each virtual second transistor.

[0134] S600, remove each virtual second transistor based on the second etch hole to form a fourth accommodation area.

[0135] Exemplarily, the fourth accommodation area may expose the virtual capacitor and the first semiconductor layer in contact with the second bit line.

[0136] S700, form a second transistor in the fourth accommodation area. The second transistor includes: a second gate and a second semiconductor layer at least partially insulating and surrounding the circumferential direction of the second gate.

[0137] S800, etch the stacked structure along a direction perpendicular to the substrate to form a third etch hole and a first electrode penetrating each virtual capacitor.

[0138] S900, form a dielectric layer and a conductive structure in the third etch hole in sequence. The conductive structure includes a second electrode and a first word line having the same potential as the second electrode. The capacitor includes a first electrode, a dielectric layer, and a second electrode.

[0139] Exemplarily, the first electrode at least partially surrounds the first word line.

[0140] Please refer to Figure 5 , in some embodiments of the present disclosure, before performing step S200 to form an etch trench and a first etch hole, the manufacturing method of the memory further includes the following steps S110 and S120.

[0141] S110, pattern the stacked structure to form a plurality of first isolation trenches; wherein, the first isolation trenches are used to define the formation positions of memory cells and isolate adjacent memory cells in a second direction; the memory cells include a first transistor, a second transistor, and a capacitor.

[0142] S120, fill an insulating material in the first isolation trenches to form a first isolation structure.

[0143] Please refer to Figure 6, in some embodiments of the present disclosure, in step S400, a first gate dielectric layer and a first semiconductor layer are sequentially formed in a first accommodation area, a second accommodation area, and a third accommodation area, and a first bit line covering the first semiconductor layer is formed in the first accommodation area, and a second bit line covering the first semiconductor layer is formed in the second accommodation area, including the following steps S410 to S460.

[0144] S410, in the etching trench, the first etching hole, and the etching area of the conductive material layer, a first gate dielectric layer, a first semiconductor material layer, and a first sacrificial layer are sequentially formed.

[0145] S420, the first sacrificial layer and the first semiconductor material layer in the etching trench and the first etching hole are removed, so that the remaining part of the first semiconductor material layer forms a first semiconductor layer, the remaining part of the first sacrificial layer in the first accommodation area forms a virtual first bit line, the remaining part of the first sacrificial layer in the second accommodation area forms a virtual second bit line, and the remaining part of the first sacrificial layer in the third accommodation area forms a first sub-isolation structure.

[0146] S430, a second sacrificial layer is formed in the etching trench and the first etching hole.

[0147] S440, the second sacrificial layer, the virtual first bit line, and the virtual second bit line in the etching trench are removed.

[0148] S450, a first bit line covering the first semiconductor layer is formed in the first accommodation area, and a second bit line covering the first semiconductor layer is formed in the second accommodation area.

[0149] S460, an insulating material is filled in the etching trench to form a second isolation structure.

[0150] Thus, the remaining part of the second sacrificial layer in the first etching hole forms a second sub-isolation structure. The first sub-isolation structure and the second sub-isolation structure together constitute a third isolation structure.

[0151] Please refer to Figure 7 , in some embodiments of the present disclosure, in step S700, a second transistor is formed in a fourth accommodation area, including the following steps S710 to S740.

[0152] S710, a second semiconductor material layer and a third sacrificial layer are sequentially formed in the second etching hole and the fourth accommodation area.

[0153] S720, the third sacrificial layer and the second semiconductor material layer in the second etching hole are removed, so that the remaining part of the second semiconductor material layer forms a second semiconductor layer.

[0154] S730, the remaining third sacrificial layer is removed.

[0155] At S740, a second gate dielectric layer and a second word line are sequentially formed in the second etching hole and the fourth accommodating region.

[0156] In the above embodiments of the present disclosure, unless there is a clear description herein, the execution of each step in the method does not have a strict order limit. These steps may not necessarily be executed in the described order and may be executed in other ways. Moreover, at least a part of any step may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time but may be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential but may be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0157] To more clearly illustrate the manufacturing method of the memory in some of the above embodiments, some of the following embodiments are described in detail by taking the Figure 5 shown method as an example, and please refer to Figures 8 - 19 for understanding.

[0158] In step S100, please refer to Figure 8 , provide a substrate 1, and form a stacked structure N on the substrate 1; the stacked structure N includes multiple conductive material layers L1 and multiple insulating material layers L2 alternately stacked along the direction perpendicular to the substrate 1 (for example, the Z direction).

[0159] Exemplarily, the substrate 1 can be composed of a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate 1 can be a layered substrate including, for example, Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator.

[0160] Exemplarily, the number of stacked layers of the conductive material layer L1 and the insulating material layer L2 can be selected and set according to requirements. And the alternating stacking of the conductive material layer L1 and the insulating material layer L2 can start with the conductive material layer L1 and end with the insulating material layer L2. However, it is not limited thereto. For example, it can start with the insulating material layer L2 and end with the conductive material layer L1; or start with the conductive material layer L1 and end with the conductive material layer L1, etc.; all are allowed. Here, it can be understood that in the example starting with the conductive material layer L1, the conductive material layer L1 should be insulated from the substrate 1.

[0161] In some examples, please continue to refer toFigure 8 Taking the case where the film layers deposited on the substrate 1 start with the conductive material layer L1 and end with the insulating material layer L2 as an example. Moreover, the film layers deposited on the substrate 1 may further include a protective layer covering the top insulating material layer L2, such as a hard mask layer YM.

[0162] Exemplarily, the hard mask layer YM includes, but is not limited to, a silicon nitride layer.

[0163] In steps S110 and S120, refer to Figure 9 , pattern the stacked structure N to form a plurality of first isolation trenches; the first isolation trenches are used to define the formation positions of the corresponding storage cells U and isolate the storage cells U adjacent in the second direction (e.g., the Y direction). Fill the first isolation trenches with an insulating material to form a first isolation structure 11.

[0164] Here, the first isolation structure 11 is obtained by filling the first isolation trenches, and the shape of the first isolation trenches is the same as that of the first isolation structure 11.

[0165] Exemplarily, the material of the first isolation structure 11 includes, but is not limited to, a high-k dielectric material. Where k is the dielectric constant, which is used to measure the ability of the material to store charges. Generally, materials can be classified into low-k (low dielectric constant) materials and high-k (high dielectric constant) materials according to the value of k; generally, the k value of low-k materials is less than 3.0, and the k value of high-k materials is greater than 3.9. High-k dielectric materials include, for example: aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanate (SrTiO3), etc.

[0166] Exemplarily, as shown in FIG. (a) in Figure 9 , in any storage cell U, the first isolation structure 11 includes an L-shaped first sub-isolation portion 111 and a linear second sub-isolation portion 112; wherein, the second sub-isolation portion 112 is used to define the interval between the second semiconductor layer 22 and the first gate G1 in the second transistor T2; the long side of the first sub-isolation portion 111 extends in the first direction (e.g., the X direction), and is used to define the isolation boundary between adjacent storage cells U in the second direction (e.g., the Y direction); the wide side of the first sub-isolation portion 111 extends in the second direction (e.g., the Y direction), and is used to define the space on the side of the capacitor 3 away from the second transistor T2, so as to effectively isolate the first bit line BL1 and the first electrode 31 of the capacitor 3.

[0167] In step S200, refer to Figure 10, etch the stacked structure N along the direction perpendicular to the substrate (e.g., the Z direction) to form a plurality of etched trenches S arranged at intervals in the first direction (e.g., the X direction), and a plurality of first etched holes H1 located between every two adjacent etched trenches S.

[0168] Exemplarily, the etched trenches S extend in the second direction (e.g., the Y direction), the first etched holes H1 extend in the first direction (e.g., the X direction), and the plurality of first etched holes H1 are arranged at intervals in the second direction (e.g., the Y direction). The second direction (e.g., the Y direction) and the first direction (e.g., the X direction) intersect, for example, orthogonally.

[0169] Here, there is a gap between the first etched hole H1 and the adjacent etched trench S, and the dimension of this gap in the first direction (e.g., the X direction) can be used to define the line width of the subsequent corresponding first bit line BL1 or second bit line BL2.

[0170] In step S300, please refer to Figure 11 , etch the sidewalls of the conductive material layer L1 based on the etched trenches S and the first etched holes H1 respectively, so that the remaining part of the conductive material layer L1 forms the first gate G1, the dummy capacitor 3', and the dummy second transistor T2', and simultaneously form the first accommodation region R1, the second accommodation region R2, and the third accommodation region R3.

[0171] Exemplarily, the third accommodation region R3 communicates with the first accommodation region R1 and the second accommodation region R2.

[0172] Here, the dummy second transistor T2' means that the to-be-formed region of the second transistor T2 is filled with other materials (e.g., the remaining part of the conductive material layer L1), and the to-be-formed region of the second transistor T2 is reserved and occupied in advance, so as to be removed and replaced with the second transistor T2 in the subsequent process.

[0173] Similarly, the dummy capacitor 3' means that the to-be-formed region of the capacitor 3 is filled with other materials (e.g., the remaining part of the conductive material layer L1), and the to-be-formed region of the capacitor 3 is reserved and occupied in advance, so as to be removed and replaced with the capacitor 3 in the subsequent process.

[0174] Thus, it can be understood that the aforementioned conductive material layer L1 can also be a dielectric material layer different from the insulating material layer L2 to implement the corresponding components or replace the conductive material in a suitable step process. The embodiments of the present disclosure do not limit some possible implementation manners based on this, and specific adaptations can be made with reference to the various step schemes disclosed in the embodiments of the present disclosure.

[0175] In step S400, please refer to Figures 12 - 15, a first gate dielectric layer 12 and a first semiconductor layer 21 are sequentially formed in a first accommodation region R1, a second accommodation region R2, and a third accommodation region R3, a first bit line BL1 covering the first semiconductor layer 21 is formed in the first accommodation region R1, and a second bit line BL2 covering the first semiconductor layer 21 is formed in the second accommodation region R2.

[0176] In some embodiments, step S400 includes but is not limited to steps S410 to S460.

[0177] In step S410, please refer to Figure 12 , a first gate dielectric layer 12, a first semiconductor material layer 210, and a first sacrificial layer 13 are sequentially formed in an etching trench S, a first etching hole H1, and an etching region of a conductive material layer L1.

[0178] Exemplarily, the first gate dielectric layer 12, the first semiconductor material layer 210, and the first sacrificial layer 13 are all formed by a deposition process. The deposition process includes but is not limited to an atomic layer deposition process.

[0179] Exemplarily, the material of the first gate dielectric layer 12 includes but is not limited to silicon oxide.

[0180] Exemplarily, the material of the first semiconductor material layer 210 includes but is not limited to metal oxide semiconductor, for example, it can be indium gallium zinc oxide (Indium Gallium Zinc Oxide, abbreviated as IGZO).

[0181] In step S420, please refer to Figure 13 , the first sacrificial layer 13 and the first semiconductor material layer 210 in the etching trench S and the first etching hole H1 are removed, so that the remaining part of the first semiconductor material layer 210 forms the first semiconductor layer 21, the remaining part of the first sacrificial layer 13 in the first accommodation region R1 forms a virtual first bit line BL1', the remaining part of the first sacrificial layer 13 in the second accommodation region R2 forms a virtual second bit line BL2', and the remaining part of the first sacrificial layer 13 in the third accommodation region R3 forms a first sub-isolation structure 41.

[0182] Here, the virtual first bit line BL1' and the virtual second bit line BL2' can be understood with reference to the aforementioned virtual second transistor T2'; that is, the virtual structure means that other materials (such as the remaining part of the first sacrificial layer 13) are used to fill the to-be-formed region of the target structure, and the to-be-formed region of the target structure is reserved and occupied in advance, so as to be removed and replaced with the target structure in the subsequent process.

[0183] Exemplarily, the first sacrificial layer 13 and the first semiconductor material layer 210 in the etching trench S and the first etching hole H1 can be removed by a dry etching process with self-alignment.

[0184] In step S430, please continue to refer to Figure 13 , a second sacrificial layer 14 is formed in the etching trench S and the first etching hole H1.

[0185] Here, it can be understood that the second sacrificial layer 14 also covers the sidewalls of the first gate dielectric layer 12, the virtual first bit line BL1', and the virtual second bit line BL2' exposed in the etching trench S and the first etching hole H1.

[0186] Exemplarily, the materials of the second sacrificial layer 14 and the first sacrificial layer 13 are different.

[0187] In step S440, please refer to Figure 14 , the second sacrificial layer 14, the virtual first bit line BL1', and the virtual second bit line BL2' in the etching trench S are removed.

[0188] Here, the remaining part of the second sacrificial layer 14 in the first etching hole H1 forms a second sub-isolation structure 42. The first sub-isolation structure 41 and the second sub-isolation structure 42 together constitute the third isolation structure 4.

[0189] In step S450, please refer to Figure 14 and Figure 15 , a first bit line BL1 covering the first semiconductor layer 21 is formed in the first accommodation area R1; a second bit line BL2 covering the first semiconductor layer 21 is formed in the second accommodation area R2.

[0190] Exemplarily, as shown in Figure 14 , a bit line material layer 15 is filled in the removal areas of the virtual first bit line BL1' and the virtual second bit line BL2' and the etching trench S. As shown in Figure 15 , the bit line material layer 15 in the etching trench S is removed to form a first bit line BL1 replacing the virtual first bit line BL1' in the first accommodation area R1 and a second bit line BL2 replacing the virtual second bit line BL2' in the second accommodation area R2.

[0191] Exemplarily, the bit line material layer 15 can be formed by a deposition process, including but not limited to an atomic layer deposition process.

[0192] Exemplarily, after filling to form the bit line material layer 15, a polishing process can be used to planarize the surface of the obtained structure.

[0193] In step S460, please continue to refer to Figure 15 , an insulating material is filled in the etching trench S to form a second isolation structure 16.

[0194] Exemplarily, the second isolation structure 16 is made of the same material as the first isolation structure 11.

[0195] In step S500, please refer toFigure 16 Etch the stacked structure N along the direction perpendicular to the substrate 1 (e.g., the Z direction) to form a second etching hole H2 that penetrates through each virtual second transistor T2'.

[0196] In step S600, please continue to refer to Figure 16 Remove each virtual second transistor T2' based on the second etching hole H2 to form a fourth accommodating region R4.

[0197] Exemplarily, on opposite sides of the fourth accommodating region R4 in the first direction (e.g., the Y direction), the side walls of the virtual capacitor 3' and the first semiconductor layer 21 are respectively exposed.

[0198] Exemplarily, the upper and lower surfaces of the second bit line BL2 and the side wall close to the first gate G1 (or the first electrode 31) are coated with the first semiconductor layer 21. Correspondingly, it is sufficient that the fourth accommodating region R4 exposes the first semiconductor layer 21 connected to the second bit line BL2.

[0199] In step S700, please refer to Figure 17 and Figure 18 Form a second transistor T2 in the fourth accommodating region R4; the second transistor T2 includes: a second gate G2 and a second semiconductor layer 22 insulatingly surrounding the circumference of the second gate G2; a first side wall of the second semiconductor layer 22 that is close to the virtual capacitor 3' and extends in the second direction (e.g., the Y direction) is electrically connected to the virtual capacitor 3'; a second side wall of the second semiconductor layer 22 that extends in the second direction (e.g., the Y direction) and is opposite to its first side wall is electrically connected to the second bit line BL2. Form a second word line WL2 electrically connected to the second gate G2 in the second etching hole H2.

[0200] In some embodiments, step S700 may include steps S710 to S740.

[0201] In step S710, please refer to Figure 17 Form a second semiconductor material layer 220 and a third sacrificial layer 17 in sequence in the second etching hole H2 and the fourth accommodating region R4.

[0202] In step S720, please refer to Figure 18 Remove the third sacrificial layer 17 and the second semiconductor material layer 220 in the second etching hole H2, so that the remaining portion of the second semiconductor material layer 220 forms the second semiconductor layer 22.

[0203] In step S730, please combine Figure 17 and Figure 18 Understand and remove the remaining third sacrificial layer 17.

[0204] Exemplarily, the third sacrificial layer 17 can be removed by a wet etching process.

[0205] In step S740, please refer to Figure 18 , and a second gate dielectric layer 18 and a second word line WL2 are sequentially formed in the second etching hole H2 and the fourth accommodating region R4.

[0206] Exemplarily, the second word line WL2 can be obtained by filling a conductive material in the second etching hole H2 and the fourth accommodating region R4. In this way, the second gate G2 and the second word line WL2 are an integral structure; in other words, the second gate G2 can be regarded as a component part of the second word line WL2 in the corresponding region.

[0207] In steps S800 and S900, please refer to Figure 19 , the stacked structure N is etched along the direction perpendicular to the substrate (e.g., the Z direction) to form a third etching hole (not shown in Figure 19 ) that penetrates through each virtual capacitor 3', and the remaining part of the virtual capacitor 3' constitutes the first electrode 31. A dielectric layer 19 and a conductive structure are sequentially formed in the third etching hole, and the conductive structure includes a second electrode 32 and a first word line WL1 having the same potential as the second electrode 32. The capacitor 3 includes the first electrode 31 and the dielectric layer 19 and the second electrode 32 in the corresponding region.

[0208] Exemplarily, the first electrode 31 has an annular structure.

[0209] Here, the second electrode 32 and the first word line WL1 are an integral structure; in other words, the second electrode 32 can be regarded as a component part of the first word line WL1 in the corresponding region, or the second electrode 32 and the first word line WL1 can be the same structure.

[0210] It should be added that in some of the above embodiments, after the film layers such as the first sacrificial layer 13, the second sacrificial layer 14, and the third sacrificial layer 17 are respectively formed, a polishing process can be used to planarize the surface of the obtained structure.

[0211] The semiconductor device and its manufacturing method provided by the embodiments of the present disclosure are as described above. In the semiconductor device provided by some embodiments of the present disclosure, the first transistor T1 and the second transistor T2 can participate in pre-charging simultaneously and write data simultaneously to achieve threshold voltage compensation of the first transistor T1 in the writing stage. Figure 20 , Figure 21 and Figure 22 respectively show some possible data reading and writing driving methods of the semiconductor device provided by the embodiments of the present disclosure.

[0212] In some embodiments, please refer to Figures 20 - 22 , the data reading and writing cycle t of the storage unit U includes a writing cycle t W , a reading cycle t R and a standby stage (e.g., the first standby stage t D1and the second standby stage t D2 )

[0213] In some embodiments, as Figure 20 shown in, the write cycle t W includes a pre-charge stage t W1 and a data write stage t W2

[0214] In the pre-charge stage t W1 , the first bit line BL1 provides a first reference voltage V1 to the first transistor T1, and the second bit line BL2 provides the first reference voltage V1 to both the first transistor T1 and the second transistor T2 simultaneously; a first write control voltage V CW1 is applied to the second electrode 32 of the capacitor 3, and the second word line WL2 provides a third write control voltage V CW3 to the second gate G2 of the second transistor T2, and the second transistor T2 is turned on to pre-charge the storage node SN; wherein, the sum of the maximum data voltage corresponding to the data and the threshold voltage V th of the first transistor T1 is the reference voltage, and the first reference voltage V1 is greater than the reference voltage.

[0215] Here, after the pre-charge of the storage node SN is completed, the voltage of the storage node SN is the first reference voltage V1.

[0216] Exemplarily, the data that the storage cell U can store includes data "0" and data "1", wherein, the data voltage Vdata1 corresponding to data "1" is greater than the data voltage Vdata0 corresponding to data "0". Based on this, the data voltage Vdata1 corresponding to data "1" can be the maximum data voltage that the storage cell U can store. Vice versa. Based on this, when the data voltage Vdata1 corresponding to data "1" is the maximum data voltage that the storage cell U can store, the reference voltage is Vdata1 + Vth, and the first reference voltage is greater than Vdata1 + Vth. And, the difference between the first reference voltage V1 and the reference voltage can be reasonably set according to requirements.

[0217] Here, the reference voltage is a definition given to the sum of the maximum data voltage and the threshold voltage Vth of the first transistor T1 for the convenience of description, and it is only used to indicate the value range of the first reference voltage with the reference voltage as the reference standard.

[0218] Exemplarily, it is also allowed that the first transistor T1 and the second transistor T2 are N-type transistors or P-type transistors. For the convenience of description, in the following some embodiments, the first transistor T1 and the second transistor T2 are taken as N-type transistors as examples for description.

[0219] In some embodiments, please continue to refer to Figure 20 ​, during the pre-charge phase t W1 , the first word line WL1 applies a first write control voltage V to the capacitor 3 CW1 . The second word line WL2 provides a third write control voltage V to the second gate G2 of the second transistor T2 CW3 . At this time, the first bit line BL1 provides a first reference voltage V1 to the first source / drain S / D11 of the first transistor T1, the second bit line BL2 provides a first reference voltage V1 to the second source / drain S / D12 of the first transistor T1, and the first transistor T1 is in a non-conducting state. Exemplarily, the first write control voltage V CW1 and the third write control voltage V CW3 are both high-level voltages.

[0220] Exemplarily, the first write control voltage V CW1 is less than the third write control voltage V CW3 , and the first write control voltage V CW1 can be reasonably set according to requirements.

[0221] During the data write phase t W2 , in response to a write command, the second bit line BL2 floats, the first bit line BL1 provides a data voltage Vdata to the first transistor T1, and the first transistor T1 conducts. The storage node SN discharges to a stable state, and the data data corresponding to the written data voltage Vdata is written.

[0222] Here, the storage node SN discharging to a stable state means that the voltage change of the storage node SN tends to 0. After the storage node SN discharges to a stable state, the voltage of the storage node SN is Vdata + Vth (including approximately equal to).

[0223] And, as shown in Figure 20 , during the data write phase t W2 , the first word line WL1 continuously applies the first write control voltage V to the second electrode 32 of the capacitor 3 CW1 . The second word line WL2 continuously provides the third write control voltage V to the second gate G2 of the second transistor T2 CW3 . At this time, the first bit line BL1 provides a data voltage Vdata to the first source / drain S / D11 of the first transistor T1, and the second bit line BL2 floats.

[0224] In addition, the data voltage Vdata provided by the first bit line BL1 is related to the data to be written. For example, when the data to be written is the data "1", the data voltage provided by the first bit line BL1 during the data write phase t W2 is Vdata1. Or, for another example, when the data to be written is the data "0", the data voltage provided by the first bit line BL1 during the data write phase t W2 is Vdata0.

[0225] The second bit line BL2 is floating, which means that all external circuits connected to the second bit line BL2 are in an off state, and no signal is input at the end of the second bit line BL2 connected to the external circuit.

[0226] In some embodiments, please refer to Figure 21 , write cycle t W It further includes: a data holding stage t W2 after the data writing stage t W3 .

[0227] In the data holding stage t W3 , pull up the voltage of the first bit line BL1 to the first reference voltage V1, and after the voltage of the first bit line BL1 is the first reference voltage, turn off the second transistor T2 first, and then pull up the voltage of the second bit line BL2 to the first reference voltage V1.

[0228] In addition, please continue to refer to Figure 21 , after turning off the second transistor T2, apply a second write control voltage V CW2 to the second electrode 32 of the capacitor 3. CW2 The second write control voltage V CW1 is less than the first write control voltage V

[0229] In the embodiment of the present disclosure, in the data holding stage t W3 after writing data data to the storage node SN, the voltage of the first bit line BL1 can be pulled up to the first reference voltage V1, and the first transistor T1 is turned off by the voltage difference between the first source / drain S / D11 of the first transistor T1 and the storage node SN. At this time, the second transistor T2 connecting the storage node SN and the second bit line BL2 is in an on state. Based on the coupling effect between the capacitor 3, the first bit line BL1 and the second bit line BL2, the voltage of the storage node SN can be kept stable (for example, kept at Vdata + Vth). Then, turn off the second transistor T2 first, and then provide the first reference voltage V1 to the first transistor T1 and the second transistor T2 simultaneously through the second bit line BL2, so that the data data can be retained in the storage node SN (the voltage of the storage node SN includes Vdata + Vth).

[0230] It can be understood that in the data reading stage t R , the first bit line BL1 reads the data data in response to whether the first transistor T1 is turned on, which can be manifested as reading the data data through the change of the current or voltage transmitted by the first bit line BL1. Therefore, in the data holding stage t W3, after turning off the second transistor T2, the second write control voltage V can also be applied to the second electrode 32 of the capacitor 3 by using the first word line WL1. CW2 . The second write control voltage V CW2 is less than the first write control voltage V CW1 , and the voltage of the storage node SN can be pulled down. In this way, not only can the off state of the first transistor T1 be further ensured to avoid leakage current generated by the first transistor T1, but it is also convenient to apply the read control voltage V CR to the second electrode 32 of the capacitor 3 through the first word line WL1 subsequently, so as to realize the read scan control of the data data.

[0231] Here, please combine with Figure 21 to understand that during the data holding stage t W3 , after turning off the second transistor T2, it is also allowed to first pull up the voltage of the second bit line BL2 to the first reference voltage V1, or first apply the second write control voltage V CW2 to the second electrode 32 of the capacitor 3 through the first word line WL1, or both at the same time.

[0232] And, after turning off the second transistor T2, when the first word line WL1 applies the second write control voltage V CW2 to the second electrode 32 of the capacitor 3, the voltage of the storage node SN will change accordingly. For example, if the second write control voltage V CW2 is a low-level voltage, and if the data written in the storage node SN is data "1", the voltage of the storage node SN can correspondingly change to: Vdata1 + Vth - △V; if the data written in the storage node SN is data "0", the voltage of the storage node SN can correspondingly change to: Vdata0 + Vth - △V.

[0233] Correspondingly, during the subsequent data reading stage t R , when the first word line WL1 applies the read control voltage V CR to the second electrode 32 of the capacitor 3, the voltage of the storage node SN will change accordingly. For example, if the read control voltage V CR is a high-level voltage, and if the data written in the storage node SN is data "1", the voltage of the storage node SN can correspondingly change to: Vdata1 + Vth - △V + △V'; if the data written in the storage node SN is data "0", the voltage of the storage node SN can correspondingly change to: Vdata0 + Vth - △V + △V'.

[0234] In the embodiments of the present disclosure, the voltage of the storage node SN when the first word line WL1 applies the second write control voltage V CW2 or the read control voltage V CRAfter that, although there are changes, the voltage of the storage node SN always includes the data voltage Vdata corresponding to the written data and the threshold voltage Vth of the first transistor T1, and corresponding to different data voltages (such as Vdata1 and Vdata0), the voltage change of the storage node SN is the same, which does not affect the data reading stage t R Accurately read the data.

[0235] In some other examples, please refer to Figure 22 , in the data holding stage t W3 , first apply a second write control voltage V to the second electrode 32 of the capacitor 3 CW2 , pull up the voltage of the first bit line BL1 to the first reference voltage V1; then turn off the second transistor T2, and pull up the voltage of the second bit line BL2 to the first reference voltage V1. Among them, the second write control voltage V CW2 is less than the first write control voltage V CW1 .

[0236] Here, it can be understood that the turning off of the second transistor T2 can be realized by the turn-off control voltage (i.e., the fourth write control voltage V CW4 ) applied to the second gate G2 by the second word line WL2.

[0237] Exemplarily, the second write control voltage V CW2 and the fourth write control voltage V CW4 are the same.

[0238] Exemplarily, both the first transistor T1 and the second transistor T2 are N-type transistors. Correspondingly, the second write control voltage V CW2 and the fourth write control voltage V CW4 are both low-level voltages.

[0239] In the embodiments of the present disclosure, after writing the data data to the storage node SN, first apply a second write control voltage V to the second electrode 32 of the capacitor 3 CW2 . The second write control voltage V CW2 is less than the first write control voltage V CW1 , which can pull down the voltage of the storage node SN to control the first transistor T1 to be in the off state. After that, pull up the voltage of the first bit line BL1 to the first reference voltage V1. Since the second transistor T2 connecting the storage node SN and the second bit line BL2 remains in the on state at this time, the voltage of the storage node SN remains stable (for example, remains at Vdata + Vth). Finally, turn off the second transistor T2, and then provide the first reference voltage V1 to both the first transistor T1 and the second transistor T2 through the second bit line BL2, which can avoid the leakage current of the second transistor T2 and stabilize the data data at the storage node SN (for example, the voltage of the storage node SN is Vdata + Vth).

[0240] In some embodiments, such as Figure 20 , Figure 21 and Figure 22 shown in, the read cycle t R includes: a data reading stage t R .

[0241] During the data reading stage t R , in response to a read command, a read control voltage V CR is applied to the second electrode 32 of the capacitor 3, and a second reference voltage V2 is simultaneously provided to the first transistor T1 and the second transistor T2 through the second bit line BL2; wherein, the first bit line BL1 is further configured to: read data in response to whether the first transistor T1 is turned on.

[0242] Exemplarily, the second reference voltage V2 is less than the first reference voltage V1.

[0243] Exemplarily, the second reference voltage V2 is greater than the minimum data voltage that the storage unit U can store data and less than the maximum data voltage that the storage unit U can store data. For example, Vdata1 > V2 > Vdata0.

[0244] Here, it can be understood that in the actual application of the data reading and writing circuit, considering the coupling effect between the capacitor 3, the first bit line BL1 and the second bit line BL2, the second reference voltage V2 can be greater than the sum of the minimum data voltage and the voltage variable (vector) brought by the coupling effect, and less than the sum of the maximum data voltage and the voltage variable (vector) brought by the coupling effect.

[0245] In some embodiments, the first write control voltage V W provided by the first word line WL1 during the write cycle t CW1 and the read control voltage V R provided by it during the read cycle t CR can be the same or different.

[0246] Exemplarily, the first write control voltage V CW1 and the read control voltage V CR are the same.

[0247] Exemplarily, the first write control voltage V CW1 is less than the read control voltage V CR .

[0248] Here, the read control voltage V CR applied to the second electrode 32 of the capacitor 3 in response to a read command means that: the appropriate voltage applied through the first word line WL1 can ensure that the first transistor T1 is in different states corresponding to storing different data at the storage node SN.

[0249] Figure 23 Figures (a) and (b) therein respectively show the current-voltage characteristic curves of the first transistor T1 when two different read control voltages V are applied to the second electrode 32 of the capacitor 3; among them, the read control voltage V corresponding to Figure (a) CR is less than the read control voltage V corresponding to Figure (b). CR By comparing Figures (a) and (b) in CR . Figure 23 It can be seen from Figures (a) and (b) in that by reasonably selecting the magnitude of the read control voltage V, when storing data "0" or data "1" in the storage node SN, it can be ensured that the first transistor T1 can have an obvious on or off state, which is beneficial to data reading. CR

[0250] In some embodiments, please refer to Figure 20 , Figure 21 , Figure 22 and Figure 23 for understanding. The data written into the storage node SN includes "1" or "0". During the data reading phase t R , after applying the read control voltage V to the second electrode 32 of the capacitor 3 CR :

[0251] If the data stored in the storage node SN is "1", then the gate-source voltage V of the first transistor T1 GS (that is, the voltage difference between the first gate G1 and its second source / drain S / D12) is large and greater than the threshold voltage Vth of the first transistor T1, and the first transistor T1 is in the on state.

[0252] If the data stored in the storage node SN is "0", then the gate-source voltage V of the first transistor T1 GS (that is, the voltage difference between the first gate G1 and its second source / drain S / D12) is small and less than the threshold voltage Vth of the first transistor T1, and the first transistor T1 is in the off state.

[0253] To more clearly illustrate the data reading process during the data reading phase t R , the following takes the data reading methods shown in Figure 20 and Figure 22 as examples, and the data reading methods shown in Figure 21 can be understood adaptively.

[0254] During the data reading phase t R, if the voltage of the first gate G1 in the first transistor T1 is the voltage after writing the data "1" to the storage node SN, i.e., = Vdata1 + Vth. The voltage of the second source / drain S / D12 in the first transistor T1 is the second reference voltage V2 provided by the second bit line BL2. The gate-source voltage V of the first transistor T1 GS = Vdata1 + Vth - V2. Since V2 is less than Vdata1, the gate-source voltage V of the first transistor T1 GS is greater than Vth.

[0255] In the data read phase t R , if the voltage of the first gate G1 in the first transistor T1 is the voltage after writing the data "0" to the storage node SN, i.e., = Vdata0 + Vth. The voltage of the second source / drain S / D12 in the first transistor T1 is the second reference voltage V2 provided by the second bit line BL2. The gate-source voltage V of the first transistor T1 GS = Vdata0 + Vth - V2. Since V2 is greater than Vdata0, the gate-source voltage V of the first transistor T1 GS is less than Vth.

[0256] In addition, the way the first bit line BL1 reads data in response to whether the first transistor T1 is turned on can be specifically manifested as: current sensing read or voltage sensing read.

[0257] It is worth mentioning that in some embodiments, please refer to Figure 20 , Figure 21 and Figure 22 , the data read / write cycle t further includes: a standby phase (i.e., the Standby phase) located before the pre-charge phase t W1 and / or before the data read phase t R .

[0258] Exemplarily, as shown in Figure 21 and Figure 22 , the data read / write cycle t further includes: a data hold phase t W2 located after the data write phase t W3 . The data read phase t R is located after the data hold phase t W3 . The standby phase includes: a first standby phase t W1 located before the pre-charge phase t D1 , and a second standby phase t W3 located after the data hold phase t R and before the data read phase t D2 .

[0259] Correspondingly, in the standby phase (including the first standby phase t D1and the second standby stage t D2 ), the first transistor T1 and the second transistor T2 are in the off state. The first bit line BL1 provides a first reference voltage V1 to the first transistor T1, and the second bit line BL2 provides the first reference voltage V1 to both the first transistor T1 and the second transistor T2 simultaneously.

[0260] In the standby stage of the embodiments of the present disclosure, the first reference voltage V1 can be provided to the first pole of the first transistor T1 by the first bit line BL1, and the first reference voltage V1 can be provided to the second pole of the second transistor T2 by the second bit line BL2, so as to ensure that there is no large voltage difference between the first pole and the second pole of the first transistor T1, thereby effectively reducing the risk of leakage current generation. Especially when the first reference voltage V1 is a high-level voltage.

[0261] In addition, it can be understood that the first standby stage t mentioned in some of the above embodiments D1 and the second standby stage t D2 Among them, in the first standby stage t D1 can be independent of the write cycle t w Outside, the second standby stage t D2 can be independent of the read cycle t R Outside. And, based on the first standby stage t D1 and the second standby stage t D2 When the voltage signals provided by the first bit line BL1, the second bit line BL2, the first word line WL1 and the second word line WL2 are the same, the first standby stage t D1 and the second standby stage t D2 can also be regarded as the same standby stage to enter different read and write cycles in response to different received commands. For example, when a write command is received, it enters the write cycle correspondingly, or when a read command is received, it enters the read cycle correspondingly.

[0262] It can be understood that in the first standby stage t D1 and the second standby stage t D2 , the first word line WL1 applies a second write control voltage V to the second electrode 32 of the capacitor 3 CW2 ; the second word line WL2 applies a fourth write control voltage V to the second gate G2 of the second transistor T2 CW4 .

[0263] Exemplarily, the second write control voltage V CW2 and the fourth write control voltage V CW4 are the same.

[0264] Exemplarily, both the first transistor T1 and the second transistor T2 are N-type transistors. The second write control voltage V CW2 and the fourth write control voltage V CW4 are both low-level voltages.

[0265] In an embodiment of the present disclosure, the storage unit U is configured to store data, including a capacitor 3 connected to a storage node SN, a first transistor T1, and a second transistor T2. In the embodiment of the present disclosure, by connecting the first bit line BL2 to the first transistor T1 in the storage unit U and connecting the second bit line BL2 to the first transistor T1 and the second transistor T2 in the storage unit U, during the pre-charge stage t W1 , the first bit line BL1 provides a first reference voltage V1 to the first transistor T1, the second bit line BL2 provides the first reference voltage V1 to the first transistor T1 and the second transistor T2 simultaneously, and the first word line WL1 provides a first write control voltage V to the second electrode 32 of the capacitor 3 CW1 , and after turning on the second transistor T2, the storage node SN is pre-charged. Based on the fact that the first reference voltage V1 is greater than the reference voltage (i.e., the sum of the maximum data voltage corresponding to the data that can be stored in the storage unit U and the threshold voltage of the first transistor T1, for example, Vdata1 + Vth), that is, V1 > (Vdata1 + Vth), after pre-charging the storage node SN, the voltage of the storage node SN (= or ≈ V1) can be greater than the reference voltage, for example, greater than (Vdata1 + Vth). Thus, during the data write stage t W2 , in response to a write command, after floating the second bit line BL2 and the first bit line BL1 provides a data voltage Vdata to the first transistor T1, the first transistor T1 is turned on, and the storage node SN can discharge naturally to a stable state to write the data data corresponding to the foregoing data voltage Vdata.

[0266] In the embodiment of the present disclosure, since the voltage of the storage node SN after pre-charging is greater than the reference voltage, for example, greater than (Vdata1 + Vth), that is: the voltage of the storage node SN is not only greater than the data voltage Vdata provided by the first bit line BL1, but also the difference between the voltage of the storage node SN and the foregoing data voltage Vdata is greater than the threshold voltage Vth of the first transistor T1. Therefore, after the storage node SN discharges to a stable state, the voltage of the storage node SN corresponds to the sum of the foregoing data voltage Vdata and the threshold voltage Vth of the first transistor T1 (i.e., = or ≈ Vdata + Vth), so that the threshold voltage (= or ≈ Vth) of the first transistor T1 can be retained in the storage node SN while writing the data data.

[0267] On this basis, after writing the data data, some embodiments of the present disclosure can turn off the first transistor T1 and the second transistor T2 (see the relevant description of the data retention stage t W3 ). And, during the second standby stage t D2, the first bit line BL1 and the second bit line BL2 are used to respectively supply a first reference voltage V1 to the first transistor T1, and the second bit line BL2 is used to supply the first reference voltage V1 to the second transistor T2. At this time, both the first transistor T1 and the second transistor T2 are in the off state, and the voltage of the storage node SN can be kept stable.

[0268] After that, in the data reading stage t R , in response to a read command, a read control voltage V can be supplied to the second electrode 32 of the capacitor 3 CR , and a second reference voltage V2 is simultaneously supplied to the first transistor T1 and the second transistor T2 through the second bit line BL2. When the first reference voltage V1 is supplied to the first bit line BL1, the second reference voltage V2 is supplied to the second bit line BL2, and the read control voltage V is supplied to the second electrode 32 of the capacitor 3 CR After that, the magnitude of the voltage of the storage node SN can affect the conduction between the first source / drain S / D11 and the second source / drain S / D12 of the first transistor T1, so that the first bit line BL1 reads data in response to whether the first transistor T1 is conducting. Since the voltage of the storage node SN includes the threshold voltage (= or ≈ Vth) of the first transistor T1, the data read by the first bit line BL1 in response to whether the first transistor T1 is conducting can be unaffected by the threshold voltage Vth of the first transistor T1, so as to ensure the accuracy of the stored data data reading, thereby further improving the performance of the memory.

[0269] Some embodiments of the present disclosure also provide an electronic device, such as a data storage device, a photocopier, a network device, a household appliance, an instrument, a mobile phone, a computer, etc., which have a data storage function. The electronic device may include a housing, a circuit board disposed in the housing, and a memory or a data reading and writing circuit integrated on the circuit board. The structure of the memory or the data reading and writing circuit can refer to the relevant descriptions in the above-mentioned some embodiments. Other necessary elements or components may also be included in the electronic device, and the embodiments of the present disclosure do not limit this.

[0270] In some embodiments, the memory may be coupled to an external control device such as a processor or an actuator. The processor is coupled to the memory, and the processor can control the read and write operations of the memory.

[0271] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0272] The above-described embodiments merely represent several implementation manners of the present disclosure. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can be made, and these all fall within the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the appended claims.

Claims

1. A semiconductor device, characterized in that, Comprising a substrate and at least one memory cell disposed on the substrate; the memory cell includes: a capacitor, a first transistor, and a second transistor; the capacitor includes a first electrode and a second electrode disposed in insulation; the first transistor includes a first gate, a first source / drain, and a second source / drain; the second transistor includes a second gate, a third source / drain, and a fourth source / drain; Wherein, the first electrode, the first gate, and the third source / drain have the same potential, and the storage node of the memory cell includes the first electrode, the first gate, and the third source / drain; the second electrode has the same potential as the first word line; the second gate has the same potential as the second word line; the first source / drain has the same potential as the first bit line; both the second source / drain and the fourth source / drain have the same potential as the second bit line; The first word line is perpendicular to the substrate, and the first electrode at least partially surrounds the first word line; The size of the first gate in the first direction is greater than the size of the first electrode in the first direction, and the first direction is parallel to the substrate.

2. The semiconductor device according to claim 1, characterized in that, The first transistor further includes a first semiconductor layer; Wherein, the first semiconductor layer is in contact with the first bit line and is at least located on one side of the first bit line close to the substrate and one side away from the substrate.

3. The semiconductor device according to claim 2, characterized in that, The first semiconductor layer is also located on one side of the first bit line close to the first word line.

4. The semiconductor device according to claim 2, wherein, The second transistor further includes a second semiconductor layer; Wherein, the second semiconductor layer is electrically connected to the second bit line through the first semiconductor layer.

5. The semiconductor device according to claim 1, wherein, The second gate overlaps with the first gate in the first direction and overlaps with the first electrode in the second direction; the second direction is parallel to the substrate and intersects with the first direction.

6. The semiconductor device according to claim 1, wherein, The first bit line and the second bit line extend along the second direction respectively and are spaced apart in the first direction; wherein, the second direction is parallel to the substrate and intersects with the first direction; the storage node is located between the first bit line and the second bit line and is insulated from both the first bit line and the second bit line.

7. The semiconductor device according to claim 1, wherein The second transistor further includes a second semiconductor layer; Wherein, the second word line is perpendicular to the substrate; The second semiconductor layer at least partially surrounds the second word line.

8. The semiconductor device according to claim 1, wherein, The data read / write timing of the semiconductor device includes: a precharge stage, a data write stage, and a data read stage; Wherein, the first bit line is configured to: provide a first reference voltage to the first transistor in the precharge stage, write data to the first transistor in the data write stage, and read data in response to the conduction state of the first transistor in the data read stage; the sum of the maximum data voltage corresponding to the data and the threshold voltage of the first transistor is the reference voltage; the first reference voltage is greater than the reference voltage.

9. The semiconductor device according to claim 8, characterized in that, The second bit line is configured to: simultaneously provide the first reference voltage to the first transistor and the second transistor during the pre-charge phase, float during the data write phase, and simultaneously provide a second reference voltage to the first transistor and the second transistor during the data read phase; Wherein, the first reference voltage is greater than the second reference voltage.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that, A plurality of the memory cells are arranged in columns along a second direction; wherein, the second direction is parallel to the substrate and intersects the first direction; one column of the memory cells shares one of the first bit lines and one of the second bit lines.

11. The semiconductor device according to claim 10, wherein, Further comprising: A first isolation structure, located between the memory cells adjacent to each other in the second direction, and between the second gate and the first gate in any one of the memory cells.

12. The semiconductor device according to claim 11, wherein, Further comprising: A second isolation structure, located between adjacent columns of the memory cells; wherein, every two adjacent columns of the memory cells are symmetric about the second isolation structure.

13. The semiconductor device according to claim 11, wherein, Further comprising: A third isolation structure located between the first isolation structure and the first gate; The third isolation structure comprises: a first sub-isolation structure; The first sub-isolation structure extends along the first direction, is located between the first bit line and the second bit line, and is located on a side of the first semiconductor layer of the first transistor away from the first gate.

14. The semiconductor device according to claim 13, wherein, The third isolation structure further comprises: a second sub-isolation structure; The second sub-isolation structure extends along a third direction and is located between the first sub-isolation structure and the first isolation structure; the third direction is perpendicular to the substrate.

15. A method for manufacturing a semiconductor device, characterized in that, Comprising: Providing a substrate, and forming a stacked structure on the substrate; the stacked structure comprises a plurality of conductive material layers and a plurality of insulating material layers alternately stacked in a direction perpendicular to the substrate; Etching the stacked structure in a direction perpendicular to the substrate to form a plurality of etching trenches and a plurality of first etching holes located between every two adjacent ones of the etching trenches; Based on the etching trenches and the first etching holes, respectively etching the conductive material layers such that the remaining portions of the conductive material layers form a first gate, a virtual capacitor, and a virtual second transistor, and simultaneously forming a first accommodation region, a second accommodation region, and a third accommodation region; Sequentially forming a first gate dielectric layer and a first semiconductor layer in the first accommodation region, the second accommodation region, and the third accommodation region, forming a first bit line covering the first semiconductor layer in the first accommodation region, and forming a second bit line covering the first semiconductor layer in the second accommodation region; wherein, the first transistor comprises the first gate, the first gate dielectric layer, and the first semiconductor layer; Etching the stacked structure in a direction perpendicular to the substrate to form second etching holes penetrating through each of the virtual second transistors; Removing each of the virtual second transistors based on the second etching holes to form a fourth accommodation region; Forming a second transistor in the fourth accommodation region; the second transistor comprises: a second gate and a second semiconductor layer at least partially insulatingly surrounding the circumference of the second gate.

16. The manufacturing method of the semiconductor device according to claim 15, characterized in that, After forming the second transistor in the fourth accommodation region, the method further includes: etching the stacked structure along a direction perpendicular to the substrate to form a third etching hole and a first electrode that penetrate through each of the dummy capacitors; Forming a dielectric layer and a conductive structure in sequence within the third etching hole, where the conductive structure includes a second electrode and a first word line having the same potential as the second electrode; the capacitor includes the first electrode, the dielectric layer, and the second electrode.

17. The manufacturing method of the semiconductor device according to claim 16, characterized in that, A plurality of the etching trenches are arranged at intervals in a first direction; wherein, The etching trenches extend along a second direction; the second direction intersects with the first direction and is parallel to the substrate; The first etching holes extend along the first direction, and a plurality of the first etching holes are arranged at intervals in the second direction.

18. The manufacturing method of the semiconductor device according to claim 16, characterized in that, The third accommodation region communicates with the first accommodation region and the second accommodation region.

19. The manufacturing method of the semiconductor device according to claim 16, characterized in that, The fourth accommodation region exposes the dummy capacitors and the first semiconductor layer in contact with the second bit line.

20. The manufacturing method of the semiconductor device according to claim 16, characterized in that, The first electrode at least partially surrounds the first word line.

21. The manufacturing method of the semiconductor device according to claim 20, wherein, The method further includes: Before forming the etching trenches and the first etching holes, patterning the stacked structure to form a plurality of first isolation trenches; wherein, the first isolation trenches are used to define the formation positions of the memory cells and isolate the memory cells adjacent in the second direction; the memory cells include the first transistor, the second transistor, and the capacitor; Filling an insulating material within the first isolation trenches to form a first isolation structure.

22. The manufacturing method of the semiconductor device according to claim 21, wherein, Forming a first gate dielectric layer and a first semiconductor layer in sequence within the first accommodation region, the second accommodation region, and the third accommodation region, and forming a first bit line covering the first semiconductor layer within the first accommodation region, and forming a second bit line covering the first semiconductor layer within the second accommodation region, includes: Forming a first gate dielectric layer, a first semiconductor material layer, and a first sacrificial layer in sequence within the etching trenches, the first etching holes, and the etching regions of the conductive material layer; Removing the first sacrificial layer and the first semiconductor material layer within the etching trenches and the first etching holes, such that the remaining portion of the first semiconductor material layer forms the first semiconductor layer, the remaining portion of the first sacrificial layer within the first accommodation region forms a dummy first bit line, the remaining portion of the first sacrificial layer within the second accommodation region forms a dummy second bit line, and the remaining portion of the first sacrificial layer within the third accommodation region forms a first sub-isolation structure; Forming a second sacrificial layer within the etching trenches and the first etching holes; Removing the second sacrificial layer within the etching trenches, the dummy first bit line, and the dummy second bit line; Forming a first bit line covering the first semiconductor layer within the first accommodation region; Forming a second bit line covering the first semiconductor layer within the second accommodation region; Filling an insulating material within the etching trenches to form a second isolation structure; Wherein, the remaining portion of the second sacrificial layer within the first etching holes forms a second sub-isolation structure; the first sub-isolation structure and the second sub-isolation structure together constitute a third isolation structure.

23. The manufacturing method of the semiconductor device according to claim 22, wherein, Forming a second transistor in the fourth accommodating region, comprising: Sequentially forming a second semiconductor material layer and a third sacrificial layer in the second etching hole and the fourth accommodating region; Removing the third sacrificial layer and the second semiconductor material layer in the second etching hole, so that the remaining part of the second semiconductor material layer forms the second semiconductor layer; Removing the remaining third sacrificial layer; Sequentially forming a second gate dielectric layer and a second word line in the second etching hole and the fourth accommodating region.

24. An electronic device, characterized in that, Comprising: The semiconductor device according to any one of claims 1 to 14.

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