Semiconductor structure, preparation method thereof and electronic equipment

Abstract

The embodiment of the invention discloses a semiconductor structure and a preparation method thereof, and electronic equipment, and the semiconductor structure comprises a plurality of active columns which are distributed in an array manner in a first direction and a second direction; wherein the extension direction of the active columns is perpendicular to the first direction and the second direction, and the first direction intersects with the second direction; each word line extends along the first direction, and the word lines are arranged at intervals in the second direction; the word line comprises a plurality of grid electrodes and a plurality of connecting structures which are alternately arranged in the first direction; wherein the grid electrode wraps the side wall of the channel of the active column; the connecting structure is connected with two adjacent grids; the sum of the maximum sizes of the grid electrode and the active column in the second direction is greater than the size of the connecting structure in the second direction; thickness of the grid electrode on two opposite sides of the active column along the second direction is basically the same. The semiconductor structure enables the threshold voltage of the transistor to be stable, and facilitates the reduction of power consumption.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technologies, and in particular, to a semiconductor structure, a method for manufacturing the same, and an electronic device. Background Art

[0002] A storage cell of a dynamic random access memory (DRAM) includes a transistor and a capacitor. The gate of the transistor is connected to a word line, the drain is connected to a bit line, and the source is connected to the capacitor.

[0003] As the integration degree of the dynamic random access memory increases, the power consumption of the dynamic random access memory increases. Therefore, how to reduce the power consumption of the dynamic random access memory has become a technical problem to be solved urgently. Summary of the Invention

[0004] According to a first aspect of embodiments of the present disclosure, there is provided a semiconductor structure, including:

[0005] A plurality of active pillars, which are arranged in an array in a first direction and a second direction; wherein, an extending direction of the active pillar is perpendicular to both the first direction and the second direction, and the first direction and the second direction intersect;

[0006] A plurality of word lines, each of the word lines extends along the first direction and the word lines are arranged at intervals in the second direction; the word line includes a plurality of gates and a plurality of connection structures which are alternately arranged along the first direction; wherein, the gate covers side walls of a channel of the active pillar; the connection structure is connected to two adjacent gates; a sum of maximum dimensions of the gate and the active pillar in the second direction is greater than a dimension of the connection structure in the second direction; dimensions of the gate on opposite sides of the active pillar along the second direction are substantially the same.

[0007] In some embodiments, the semiconductor structure further includes: a word line isolation structure, which extends along the first direction and is located between two adjacent word lines; wherein, dimensions of the gates on opposite sides of the word line isolation structure along the second direction are substantially the same.

[0008] In some embodiments, dimensions of the connection structures of at least two of the word lines in the second direction are substantially the same.

[0009] In some embodiments, along the second direction, a symmetry axis of the connection structure of the same word line coincides with a symmetry axis of the gate.

[0010] In some embodiments, along the second direction, the axis of symmetry of the connection structure of the same word line is offset from the axis of symmetry of the gate, and half of the difference between the sum of the maximum dimensions of the gate and the active pillar in the second direction and the dimension of the connection structure in the second direction is greater than the amount of the offset.

[0011] In some embodiments, the active pillar includes a first doped region, the channel, and a second doped region sequentially arranged along the extending direction of the active pillar; the semiconductor structure further includes:

[0012] A word line mask layer located above the word line; wherein, the word line mask layer covers the sidewalls of the second doped region.

[0013] In some embodiments, the word line mask layer includes:

[0014] A first sub-mask layer located between two adjacent active pillars in the first direction; wherein, the dimension of the first sub-mask layer in the second direction is smaller than the dimension of the active pillar in the second direction;

[0015] A second sub-mask layer covering two opposite sidewalls of the first sub-mask layer and the active pillar in the second direction; the sum of the maximum dimensions of the first sub-mask layer and the second sub-mask layer in the second direction is substantially equal to the dimension of the connection structure in the second direction, and the dimension of the second sub-mask layer in the second direction is greater than or equal to the dimension of the gate in the second direction.

[0016] In some embodiments, the semiconductor structure further includes:

[0017] A bit line and a storage structure respectively connected to opposite sides of the active pillar far from the channel.

[0018] In some embodiments, the cross-section of the active pillar perpendicular to the extending direction is rectangular, circular or elliptical.

[0019] According to a second aspect of the embodiments of the present disclosure, a method for manufacturing a semiconductor structure is provided, including:

[0020] Providing a plurality of active pillars; wherein, the plurality of active pillars are arranged in an array in the first direction and the second direction; the extending direction of the active pillar is perpendicular to both the first direction and the second direction, and the first direction and the second direction intersect;

[0021] Form a plurality of word lines; wherein each of the word lines extends along the first direction and the word lines are arranged at intervals in the second direction; the word line includes a plurality of gates and a plurality of connection structures alternately arranged along the first direction; the gate covers the sidewalls of the channel of the active column; the connection structure is connected to two adjacent gates; the sum of the maximum dimensions of the gate and the active column in the second direction is greater than the dimension of the connection structure in the second direction; the dimensions of the gate on the opposite sides of the active column along the second direction are substantially the same.

[0022] In some embodiments, the manufacturing method further includes: forming a word line isolation structure extending along the first direction between two adjacent word lines.

[0023] In some embodiments, the plurality of active columns include:

[0024] A substrate;

[0025] A plurality of first trenches located in the substrate; each of the first trenches extends along the second direction, and the plurality of first trenches are arranged at intervals along the first direction;

[0026] A first dielectric layer filling a partial depth of the first trench;

[0027] A plurality of second trenches located in the substrate and the first dielectric layer; each of the second trenches extends along the first direction, and the plurality of second trenches are arranged at intervals along the second direction, and the depth of the second trench is less than the depth of the first trench; wherein the first trench and the second trench divide the substrate into a plurality of active columns;

[0028] A second dielectric layer filling a partial depth of the second trench, and the second dielectric layer and the first dielectric layer jointly cover the sidewalls of the first doped region of the active column, and the channels of the active column and the sidewalls of the second doped region are exposed in the first trench and the second trench.

[0029] In some embodiments, the method for forming the plurality of active columns includes:

[0030] Provide a substrate;

[0031] Etch the substrate to form a plurality of first trenches arranged at intervals along the first direction, the first trenches extend along the second direction, and the bottoms of the first trenches are located in the substrate;

[0032] Fill the first trenches to form a first dielectric layer;

[0033] Etch the substrate and the first dielectric layer to form a plurality of second trenches spaced along the second direction, the second trenches extending along the first direction, and the depth of the second trenches being less than the depth of the first trenches; wherein, the first trenches and the second trenches divide the substrate into a plurality of the active columns;

[0034] The preparation method further includes:

[0035] Fill the second trenches to form a second dielectric layer;

[0036] Etch and remove part of the second dielectric layer and part of the first dielectric layer until the sidewalls of the channels of the active columns are exposed; wherein, the remaining second dielectric layer and the first dielectric layer jointly coat the sidewalls of the first doped regions of the active columns.

[0037] In some embodiments, the forming of the plurality of word lines includes:

[0038] Form a word line material layer on the second dielectric layer and the first dielectric layer, the word line material layer coating the exposed sidewalls of the channels;

[0039] Form a plurality of word line mask layers on the word line material layer, each word line mask layer extending along the first direction and the word line mask layers being spaced apart in the second direction; wherein, the word line mask layer is located between two adjacent active columns in the first direction and covers two opposite sidewalls of the active columns in the second direction; the sum of the maximum dimensions of the active columns and the word line mask layer covering the sidewalls of the active columns in the second direction is greater than the dimension of the word line mask layer between two adjacent active columns in the second direction;

[0040] Etch the word line material layer using the word line mask layer as a mask to form word line isolation trenches; wherein, the bottom of the word line isolation trenches exposes the second dielectric layer; the remaining word line material layer constitutes the word lines.

[0041] In some embodiments, the forming of the word line mask layer includes forming a first sub-mask layer and forming a second sub-mask layer; the forming of the first sub-mask layer includes:

[0042] Form a first sub-mask material layer covering the second doped regions of the active columns and the word line material layer; wherein, the surface of the first sub-mask material layer away from the word line material layer is at least flush with the top surface of the active columns;

[0043] Form a plurality of mask patterns on the first sub-mask material layer; wherein, each of the mask patterns extends along the first direction and is located above the active pillar, and the mask patterns are arranged at intervals in the second direction; the size of the mask pattern in the second direction is smaller than the size of the active pillar in the second direction, and there is a spacing between the two opposite boundaries of the orthographic projection of the mask pattern on the substrate and the top surface of the active pillar in the second direction;

[0044] Using the mask pattern as a mask, etch the first sub-mask material layer to expose the second doping region of the active pillar within the spacing, and the remaining first sub-mask material layer constitutes the first sub-mask layer; wherein, the first sub-mask layer is located between two adjacent active pillars in the first direction; the size of the first sub-mask layer in the second direction is smaller than the size of the active pillar in the second direction;

[0045] The forming of the second sub-mask layer includes:

[0046] Form a second sub-mask material layer covering the first sub-mask layer, the exposed second doping region, and the word line material layer;

[0047] Etch back the second sub-mask material layer to form the second sub-mask layer on the side walls of the exposed first sub-mask layer and the second doping region.

[0048] In some embodiments, the etching of the word line material layer using the word line mask layer as a mask includes:

[0049] The second sub-mask layer covering the side wall of the second doping region correspondingly forms the gate;

[0050] The first sub-mask layer and the second sub-mask layer covering the side wall of the first sub-mask layer correspondingly form the connection structure.

[0051] In some embodiments, the cross-section of the active pillar perpendicular to the extending direction is rectangular, circular or elliptical; the circular or elliptical active pillar is formed by performing a thermal oxidation process on the rectangular active pillar.

[0052] According to a third aspect of the embodiments of the present disclosure, there is provided an electronic device, including:

[0053] A processing device; and

[0054] A storage device electrically connected to the processing device, and the storage device includes the semiconductor structure described in any one of the above.

[0055] In the embodiments of the present disclosure, by setting the word line to include a plurality of gates and a plurality of connection structures alternately arranged in a first direction, the gates cover the side walls of the channels of the active pillars, the connection structures are connected to two adjacent gates, and the sizes of the gates on the opposite sides of the active pillar in a second direction are substantially the same, which can ensure the uniform thickness of the surrounding gate of a single transistor, make the threshold voltage of the transistor stable, enable the transistor to be normally turned on without increasing the voltage applied to the word line, and reduce the turn-off current when the transistor is turned off, which is beneficial to reducing power consumption. Description of the Drawings

[0056] Figure 1a is a schematic diagram of a semiconductor structure shown according to an exemplary embodiment;

[0057] Figure 1b is a partial schematic diagram of a semiconductor structure shown according to an exemplary embodiment;

[0058] Figure 1c is a top view schematic diagram of a semiconductor structure shown according to an exemplary embodiment;

[0059] Figure 1d is a schematic diagram of the manufacturing process of a semiconductor structure shown according to an exemplary embodiment;

[0060] Figure 1e is a schematic diagram of an ideal word line and an actual word line shown according to an exemplary embodiment;

[0061] Figure 2 is a flowchart of a method for manufacturing a semiconductor structure shown according to an embodiment of the present disclosure;

[0062] Figure 3 is a top view schematic diagram of a semiconductor structure shown according to an embodiment of the present disclosure;

[0063] Figures 4 to 21 is a schematic diagram of the manufacturing process of a semiconductor structure shown according to an embodiment of the present disclosure;

[0064] Figure 22 is a first top view schematic diagram of a semiconductor structure shown according to an embodiment of the present disclosure;

[0065] Figure 23 is a top view schematic of a semiconductor structure shown according to an embodiment of the present disclosure Figure Two ;

[0066] Figure 24 is a top view schematic of a semiconductor structure shown according to an embodiment of the present disclosure Figure Three ;

[0067] Figure 25 is a top view schematic of a semiconductor structure shown according to an embodiment of the present disclosureFigure Four 。 Detailed implementation manners

[0068] The technical solutions of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation manners described herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0069] The present disclosure will be described more specifically by way of example with reference to the accompanying drawings in the following paragraphs. The advantages and features of the present disclosure will be clearer according to the following description and claims. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0070] It can be understood that the meanings of "on...", "above...", and "over..." in the present disclosure should be interpreted in the broadest manner, so that "on..." not only means "on" something "without any intervening features or layers therebetween (i.e., directly on something)", but also includes the meaning of being "on" something with intervening features or layers therebetween.

[0071] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence.

[0072] In the embodiments of the present disclosure, the term "layer" refers to a part of a material including a region having a thickness. The layer can extend over the entire underlying or overlying structure, or can have a scope smaller than the scope of the underlying or overlying structure. In addition, the layer can be a region of a homogeneous or inhomogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure, or the layer can be between any horizontal planes at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface. The layer can include multiple sub-layers.

[0073] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0074] Figure 1a is a schematic diagram of a semiconductor structure 100 shown according to an exemplary embodiment, Figure 1b is a partial schematic diagram of a semiconductor structure 100 shown according to an exemplary embodiment, Figure 1c is a top view schematic diagram of a semiconductor structure 100 shown according to an exemplary embodiment, Figure 1dIt is a schematic diagram of the manufacturing process of a semiconductor structure 100 shown according to an exemplary embodiment. The semiconductor structure 100 and its manufacturing process will be described below in conjunction with Figures 1a to 1d the description of the semiconductor structure 100 and its manufacturing process.

[0075] Referring to Figures 1a to 1c as shown, the semiconductor structure 100 includes a plurality of memory cells, a plurality of word lines 130, and a plurality of bit lines 140; the memory cells include transistors and capacitors 120, the transistors include active regions 110 and gates, the first doped region of the active region 110 is connected to the bit line 140, the second doped region of the active region 110 is connected to the capacitor 120, and the gate surrounds the channel of the active region 110 (also known as a surround gate); each word line 130 extends along a first direction and is connected to a plurality of gates in the first direction; each bit line 140 extends along a second direction and is connected to a plurality of first doped regions in the second direction. It can be understood that in this example, the arrangement directions of the first doped region, the channel, and the second doped region are the extension directions of the active region 110, the transistors are vertical channel transistors (VCTs), and the word lines 130 control the turning on or off of the transistors.

[0076] The semiconductor structure 100 includes, but is not limited to, a dynamic random access memory (DRAM). Taking the dynamic random access memory as an example, by using vertical channel transistors, the integration degree of the dynamic random access memory can be improved. However, during the execution of logic operations (such as writing), a relatively large turn-on voltage needs to be applied to the word lines 130, resulting in high power consumption.

[0077] Referring to Figure 1d as shown, the formation process of the word lines 130 at least includes: forming a self-aligned pattern 150 by using a self-aligned exposure process; etching a word line material layer 130' with the self-aligned pattern 150 as a mask to form a plurality of word line isolation trenches, and the plurality of word line isolation trenches separate the word line material layer 130' into a plurality of word lines 130; here, the word line material layer surrounding the channel forms the gate. The ideal word line 130 is as shown in the left figure of Figure 1e , and the thickness of the surround gate of a single transistor is uniform, and the transistor can be turned on by using a relatively small turn-on voltage.

[0078] However, the inventors of the present application have found that: during actual manufacturing, the formation positions of the word line isolation trenches are randomly shifted, resulting in inconsistent thicknesses of the surround gates of single transistors. For example, among the upper and lower rows of active pillars, the gates obtained by disconnecting the upper row are thick (or thin), and the gates obtained by disconnecting the lower row are thin (or thick), and the thicknesses of the surround gates of single transistors are not uniform. The actual word line 130A is as shown in Figure 1eAs shown in the middle right figure, the threshold voltage of the transistor drifts. To ensure the normal turn-on of the transistor, it is necessary to ensure that the turn-on voltage of the word line 130 is large enough, which increases the power consumption.

[0079] In addition, the drift of the threshold voltage of the transistor will also cause an increase in the turn-off current when the transistor is turned off and a drift in the holding time of the capacitor 120.

[0080] Based on this, to solve the above problems, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure.

[0081] Figure 2 is a flowchart of a method for manufacturing a semiconductor structure shown according to an embodiment of the present disclosure; Figure 3 is a top view schematic diagram of a semiconductor structure shown according to an embodiment of the present disclosure; Figures 4 to 21 is a schematic diagram of the manufacturing process of a semiconductor structure shown according to an embodiment of the present disclosure. The following will be combined with Figure 2 、 Figure 3 、 Figures 4 to 21 to describe in detail the method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure. Referring to Figure 2 shown, the manufacturing method at least includes the following steps:

[0082] S210: Provide a plurality of active pillars; wherein, the plurality of active pillars are arranged in an array in the first direction and the second direction; the extending direction of the active pillars is perpendicular to both the first direction and the second direction, and the first direction and the second direction intersect;

[0083] S220: Form a plurality of word lines; wherein, each word line extends along the first direction and the word lines are spaced apart in the second direction; the word line includes a plurality of gates and a plurality of connection structures alternately arranged along the first direction; the gate coats the side walls of the channels of the active pillars; the connection structure is connected to two adjacent gates; the sum of the maximum dimensions of the gate and the active pillar in the second direction is greater than the dimension of the connection structure in the second direction; the dimensions of the gate on the opposite sides of the active pillar along the second direction are substantially the same.

[0084] It should be understood that Figure 2 the steps shown in Figure 2 are not exclusive, and other steps may be executed before, after, or between any of the shown operations;

[0085] Referring to Figure 3As shown, the semiconductor structure 300 can be divided into an array region 300a and a peripheral region 300b; the semiconductor structure 300 includes a substrate 301, a plurality of word lines 330, and a plurality of bit lines 340; a plurality of active pillars 310 are formed in the substrate 301, and the active pillars 310 are located in the array region 300a; the plurality of word lines 330 are arranged in parallel in the array region 300a, the plurality of bit lines 340 are arranged in parallel in the array region 300a, and the orthographic projections of the plurality of word lines 330 on the substrate 301 intersect with the orthographic projections of the plurality of bit lines 340 on the substrate 301. Figures 4 to 21 The cross-sectional views of aa', bb', cc', and dd' in Figure 3 are the cross-sectional views at the positions of aa', bb', cc', and dd' in Figures 4 to 21 The manufacturing process of the semiconductor structure 300 will be described below in conjunction with

[0086] In step S210, a plurality of active pillars 310 are provided; among them, the plurality of active pillars 310 are arranged in an array in the first direction and the second direction; the extending direction of the active pillars 310 is perpendicular to both the first direction and the second direction, and the first direction and the second direction intersect.

[0087] Referring to Figure 4 As shown, the method for forming the plurality of active pillars 310 in the above step S210 may include: providing a substrate 301; etching the substrate 301 to form a plurality of first trenches (not shown in the figure) arranged at intervals in the first direction (for example, the y direction), the first trenches extend in the second direction (for example, the x direction), and the bottoms of the first trenches are located in the substrate 301; filling the first trenches to form a first dielectric layer 302, and the first dielectric layer 302 simultaneously covers the surface of the substrate 301. In other embodiments, the first dielectric layer 302 covering the surface of the substrate 301 may be removed by an etching or planarization process.

[0088] The material of the substrate 301 includes semiconductor materials, such as elemental semiconductor materials (such as silicon (Si) or germanium (Ge), etc.), III-V compound semiconductor materials (such as gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), II-VI compound semiconductor materials (such as zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art.

[0089] The forming process of the first trenches includes but is not limited to at least one of dry etching and wet etching; the etched substrate 301 includes a main body part and a plurality of strip-shaped parts protruding from the main body part, the extending direction of the strip-shaped parts is the same as the extending direction of the first trenches, and the first trenches are located between two adjacent strip-shaped parts.

[0090] The material of the first dielectric layer 302 includes a dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride, etc. In this example, the first dielectric layer 302 is silicon oxide. The formation process of the first dielectric layer 302 includes a thin film deposition process, such as at least one of physical vapor deposition process, chemical vapor deposition process, plasma enhanced chemical vapor deposition process, and atomic layer deposition process.

[0091] Referring to Figure 4 As shown, the above step S210 further includes: etching the substrate 301 and the first dielectric layer 302 to form a plurality of second trenches 3031 spaced along the second direction (e.g., the x - direction), the second trenches 3031 extending along the first direction (e.g., the y - direction), and the depth of the second trenches 3031 being less than the depth of the first trench; wherein, the first trench and the second trenches 3031 divide the substrate 301 into a plurality of active pillars 310.

[0092] The second trenches 3031 can be formed by etching the strip - like portion and the first dielectric layer 302, and the bottom of the second trenches 3031 exposes the substrate 301 and the first dielectric layer 302; a plurality of first trenches extending along the x - direction and a plurality of second trenches 3031 extending along the y - direction can divide the substrate 301 into a plurality of active pillars 310, and the active pillars 310 can serve as the active regions of transistors. In this way, a plurality of vertical transistors can be formed, which is beneficial to improving the integration degree. Here, the depth refers to the dimension of the trench in the z - direction.

[0093] It should be noted that in the present disclosure, the first direction and the second direction are respectively represented as the y - direction and the x - direction, both the y - direction and the x - direction are parallel to the surface of the substrate 301, and the z - direction is perpendicular to the surface of the substrate 301. The y - direction and the x - direction intersect, and the included angle between the y - direction and the x - direction includes an acute angle, a right angle, or an obtuse angle, which will not be elaborated hereinafter. In this example, the included angle between the y - direction and the x - direction is a right angle, that is, the y - direction, the x - direction, and the z - direction are perpendicular to each other pairwise.

[0094] Referring to Figure 3 As shown, the cross - section of the active pillar 310 in the vertical extension direction is rectangular, specifically, it can be a rounded - corner rectangle. The dimension of the rectangular active pillar 310 in the x - direction and the dimension in the y - direction can be equal or unequal.

[0095] In some embodiments, the above preparation method further includes: etching the substrate 301 exposed at the bottom of the second trenches 3031 along the second direction to form a plurality of bit - line trenches (not shown in the figure), the bit - line trenches extending along the second direction; forming bit - lines 340 in the bit - line trenches; wherein, the substrate 301 located above the bit - lines constitutes the active pillars 310, and the substrate 301 located below the bit - lines constitutes the substrate layer. The method provided by the embodiments of the present disclosure can form buried bit - lines 340 in the substrate 301, with a simple process and high integration degree.

[0096] In a specific embodiment, the formation of the bit line trenches includes: forming a protective layer (not shown in the figure) covering the first dielectric layer 302, the sidewalls and the bottom of the second trench 3031; etching back to remove the protective layer covering the bottom of the second trench 3031 to expose the substrate 301; using the remaining protective layer as a mask to laterally etch the substrate 301 to form a plurality of bit line trenches, and adjacent two bit line trenches are spaced apart by the first dielectric layer 302. Here, wet etching can be used to form the bit line trenches.

[0097] In a specific embodiment, the formation of the bit lines includes: depositing a metal material into the bit line trenches to form bit lines 340; the material of the bit lines 340 includes a metal material, for example, at least one of tungsten, tantalum, titanium, nickel, and platinum.

[0098] In a specific embodiment, the above preparation method further includes: performing a heat treatment on the metal material to form a bit line connection layer (not shown in the figure); during the heat treatment of the metal material, a chemical reaction occurs between the metal material and the substrate 301 material to generate a metal silicide. The metal silicide can reduce the contact resistance between the bit lines 340 and the active pillars 310 and improve the electrical performance of the semiconductor structure. The material of the bit line connection layer includes a metal silicide, for example, nickel silicide, tungsten silicide, cobalt silicide, tantalum silicide, or titanium silicide, etc.

[0099] In some embodiments, the above preparation method further includes: removing the protective layer after the bit lines are formed. The material of the protective layer includes silicon oxide, silicon nitride, or silicon oxynitride, etc. In this example, the protective layer is silicon nitride. The protective layer is used to protect the active pillars during the formation of the bit lines and avoid damage to the active pillars.

[0100] In some embodiments, the above preparation method further includes: doping the top and bottom of the active pillar 310 to form the active region of the transistor; the formation process of the active region includes, but is not limited to, ion implantation process or ion diffusion process; the doping ions include: P-type ions or N-type ions, for example, boron, phosphorus, arsenic, or nitrogen, etc.

[0101] In some embodiments, referring to Figure 5 and Figure 6 as shown, the above preparation method further includes: filling the second trench 3031 to form the second dielectric layer 303; etching away part of the second dielectric layer 303 and part of the first dielectric layer 302 until the sidewall of the channel 310b of the active pillar is exposed; wherein, the remaining second dielectric layer 303 and the first dielectric layer 302 jointly coat the sidewall of the first doped region 310a of the active pillar.

[0102] Referring to Figure 5As shown, the second dielectric layer 303 covers the surface of the first dielectric layer 302 simultaneously. Of course, in other embodiments, the second dielectric layer 303 covering the surface of the first dielectric layer 302 can be removed by etching or planarization processes. The material of the second dielectric layer 303 includes dielectric materials, such as silicon oxide, silicon nitride, or silicon oxynitride, etc. In this example, the formation process of the second dielectric layer 303 is similar to that of the first dielectric layer 302, and will not be elaborated here.

[0103] Still referring to Figure 5 As shown, the first dielectric layer 302 covers the opposite sidewalls of the active pillar 310 along the y direction, and the second dielectric layer 303 covers the opposite sidewalls of the active pillar 310 along the x direction and the opposite sidewalls of the first dielectric layer 302 along the x direction. The first dielectric layer 302 and the second dielectric layer 303 are sequentially formed on the top of the active pillar 310.

[0104] In a specific embodiment, dry etching can be used to remove a part of the first dielectric layer 302 and a part of the second dielectric layer 303 to form the third trench 304. For example, remove a part of the second dielectric layer 303 on the opposite sidewalls of the active pillar 310 along the x direction, a part of the second dielectric layer 303 on the opposite sidewalls of the first dielectric layer 302 along the x direction, and a part of the first dielectric layer 302 on the opposite sidewalls of the active pillar 310 along the y direction to form the third trench 304 as Figure 6 shown. The third trench 304 is in a mesh shape. Here, the second dielectric layer 303 and the first dielectric layer 302 on the top of the active pillar 310 are removed simultaneously.

[0105] In a specific embodiment, the active pillar 310 includes a first doped region 310a, a channel 310b, and a second doped region 310c arranged in sequence along the z direction. The sidewalls of the third trench 304 expose the channel 310b and the second doped region 310c; the first doped region 310a includes a drain (or source), and the second doped region 310c includes a source (or drain); the first doped region 310a is connected to the bit line 340 through a bit line connection layer, and the second doped region 310c is connected to a subsequent formed storage structure (such as a capacitor). Of course, in other embodiments, the bit line connection layer can be omitted, that is, the first doped region 310a is directly connected to the bit line 340, and the present disclosure has no special limitation on this.

[0106] In some embodiments, the doping types of the first doped region 310a and the second doped region 310c are the same, and the doping types of the first doped region 310a and the channel 310b are different. In another embodiment, the doping types of the first doped region 310a, the channel 310b, and the second doped region 310c are the same to form a junctionless transistor.

[0107] In some embodiments, referring to Figure 19 as shown, the above preparation method further includes: forming a gate dielectric layer 305, and the gate dielectric layer 305 covers the sidewalls of the channel 310b of the active pillar. The formation process of the gate dielectric layer 305 includes thermal oxidation or thin film deposition process.

[0108] In a specific embodiment, Figure 6 the exposed active pillar 310 is thermally oxidized to form a thermal oxide layer 305' as shown in Figure 7 . The thermal oxide layer 305' covers the sidewalls of the channel 310b, the sidewalls and the top of the second doped region 310c. The thermal oxide layer 305' covering the sidewalls and the top of the second doped region 310c will be removed in subsequent processes, and the remaining thermal oxide layer 305' constitutes the gate dielectric layer 305. In this example, the material of the gate dielectric layer 305 is silicon oxide. Of course, in other embodiments, the gate dielectric layer 305 can also be formed by a thin film deposition process, and the material of the gate dielectric layer 305 can be other dielectric materials known in the art.

[0109] In some embodiments, the multiple active pillars 310 formed in the above step S210 can also be directly provided for step S220. In a specific embodiment, the multiple provided active pillars 310 include: a substrate 301; a plurality of first trenches (not shown in the figure), located in the substrate; each first trench extends in the second direction, and the plurality of first trenches are spaced along the first direction; a first dielectric layer 302, filling a partial depth of the first trench; a plurality of second trenches 3031, located in the substrate 301 and the first dielectric layer 302; each second trench 3031 extends in the first direction, and the plurality of second trenches 3031 are spaced along the second direction, and the depth of the second trench 3031 is less than the depth of the first trench; wherein, the first trench and the second trench 3031 divide the substrate 301 into multiple active pillars 310; a second dielectric layer 303, filling a partial depth of the second trench, and the second dielectric layer 303 and the first dielectric layer 302 jointly cover the sidewalls of the first doped region 310a of the active pillar, and the sidewalls of the channel 310b and the second doped region 310c of the active pillar are exposed in the first trench and the second trench 3031.

[0110] In step S220, referring to Figure 21 and Figure 22As shown, a plurality of word lines 330 are formed; among them, each word line 330 extends along a first direction and the word lines 330 are arranged at intervals in a second direction; the word line 330 includes a plurality of gates 3301 and a plurality of connection structures 3302 alternately arranged along the first direction; the gate 3301 covers the sidewalls of the channel 310b of the active column 310; the connection structure 3302 is connected to two adjacent gates 3301; the sum of the dimensions of the gate 3301 and the active column 310 in the second direction is greater than the dimension of the connection structure 3302 in the second direction; the dimensions of the gate 3301 on the opposite sides of the active column 310 along the second direction are substantially the same.

[0111] In some embodiments, the above step S220 includes: forming a word line material layer 330' on the second dielectric layer 303 and the first dielectric layer 302, and the word line material layer 330' covers the sidewalls of the exposed channel 310b.

[0112] Referring to Figure 7 and Figure 10 As shown, a word line material layer 330' is formed in the third trench 304 formed with a thermal oxide layer 305'. The word line material layer 330' is located on the remaining second dielectric layer 303 and the first dielectric layer 302, and the height of the word line material layer 330' is less than the depth of the third trench 304. For example, the height of the word line material layer 330' is equal to the height of the channel 310b. In a specific example, the word line material layer 330' includes an adhesion material layer 331' and a conductive material layer 332'. The adhesion material layer 331' includes titanium nitride, and the conductive material layer 332' includes tungsten.

[0113] In a specific embodiment, the above forming the word line material layer 330' includes: forming an initial word line material layer 330' that fills the third trench 304. The initial word line material layer 330' includes an initial adhesion material layer 331' and an initial conductive material layer 332', as Figure 8 shown; performing a planarization process on the initial word line material layer 330' until the second dielectric layer 303 in the peripheral area is exposed, as Figure 9 shown; etching back the initial word line material layer 330' until the initial word line material layer 330' on the top and sidewalls of the second doping region is removed, and the remaining initial word line material layer is the word line material layer 330', as Figure 10 shown. The planarization process includes but is not limited to a chemical mechanical polishing process.

[0114] In some embodiments, referring to Figure 20As shown, the above-mentioned step S220 further includes: forming a plurality of word line mask layers 350 on the word line material layer 330'; each word line mask layer 350 extends along the first direction and the word line mask layers 350 are arranged at intervals in the second direction; wherein, the word line mask layer 350 is located between two adjacent active pillars 310 in the first direction and covers two opposite side walls of the active pillar 310 in the second direction; the sum of the sizes of the active pillar 310 and the word line mask layer 350 covering the side wall of the active pillar 310 in the second direction is greater than the size of the word line mask layer 350 between two adjacent active pillars 310 in the second direction.

[0115] In some embodiments, forming the word line mask layer 350 includes: forming a first sub-mask layer 351. The preparation process of the first sub-mask layer 351 will be described below in conjunction with Figures 11 to 19 the following.

[0116] Referring to Figure 11 As shown, forming a second doped region 310c covering the active pillar 310 and a first sub-mask material layer 351' covering the word line material layer 330'; wherein, the surface of the first sub-mask material layer 351' away from the word line material layer 330' is at least flush with the top surface of the active pillar 310. In this example, the surface of the first sub-mask material layer 351' away from the word line material layer 330' is higher than the top surface of the active pillar 310. In other embodiments, the first sub-mask material layer 351' can be planarized until it is flush with the top surface of the active pillar 310. The first sub-mask material layer 351' is used to form the first sub-mask layer 351 in subsequent processes, and the material of the first sub-mask material layer 351' includes but is not limited to silicon oxide.

[0117] Referring to Figure 13 As shown, forming a mask structure 362 covering the first sub-mask material layer 351'; the forming process of the mask structure 362 includes a thin film deposition process, and the mask structure 362 includes a single film layer or a composite film layer composed of multiple film layers. Before forming the mask structure 362, an isolation layer 361 as shown in Figure 12 can also be formed first. The material of the isolation layer 361 includes but is not limited to silicon nitride. The isolation layer 361 is used to isolate the mask structure 362 from the structures formed below the isolation layer 361 and plays a protective role.

[0118] In a specific embodiment, the mask structure 362 includes a first mask layer 3621, a second mask layer 3622, a third mask layer 3623, and a fourth mask layer 3624; the first mask layer 3621 includes but is not limited to amorphous carbon, the second mask layer 3622 includes but is not limited to silicon oxynitride, the third mask layer 3623 includes but is not limited to spin-on hard mask, and the fourth mask layer 3624 includes but is not limited to silicon oxynitride.

[0119] Referring toFigure 14 As shown, a patterned photoresist layer 363 is formed on the mask structure. The photoresist layer 363 has multiple strips, each strip extending along the first direction and spaced apart in the second direction. The exposed portions of the mask structure are exposed between adjacent strips. For example, the fourth mask layer 3624 at the position cc' is exposed. Here, the patterned photoresist layer 363 can be formed through processes such as exposure and development. The material of the photoresist layer 363 includes but is not limited to photosensitive compounds.

[0120] Refer to Figure 15 As shown, the exposed fourth mask layer and the third mask layer are etched according to the photolithography pattern to form multiple mandrels 364 arranged at intervals. Each mandrel 364 extends along the y direction, and the second mask layer 3622 is exposed between two adjacent mandrels 364. For example, the second mask layer 3622 at the position cc' is exposed. It can be understood that the mandrel 364 includes the etched fourth mask layer and the third mask layer. After the mandrel 364 is formed, the photoresist layer can be removed by ashing.

[0121] Refer to Figure 16 As shown, a spacer material layer 365' covering the second mask layer, the sidewalls and the top of the mandrel is formed. The spacer material layer 365' includes but is not limited to silicon oxide. The formation process of the spacer material layer 365' includes atomic layer deposition process. The mandrel is removed to form multiple openings. Before removing the mandrel, the spacer material layer 365' on the top of the mandrel needs to be removed first to expose the mandrel. At this time, the spacer material layer 365' covering the second mask layer is also removed, and the spacer material layer 365' on the sidewalls of the mandrel remains to form the spacer layer 365, as Figure 17 shown, the openings are located between two adjacent spacer layers 365.

[0122] The removal of the spacer material layer 365' on the top of the mandrel and the second mask layer can be achieved by etching back the spacer material layer 365'.

[0123] Refer to Figure 18 As shown, the second mask layer and the third mask layer are etched using the spacer layer 365 as a mask to form multiple mask patterns 366 on the first sub-mask material layer 351'. Each mask pattern 366 extends along the first direction and is located above the active pillar 310. The mask patterns 366 are spaced apart from each other in the second direction. The size of the mask pattern 366 in the second direction is smaller than the size of the active pillar 310 in the second direction. There is a spacing between the two opposite boundaries of the orthographic projection of the mask pattern 366 on the substrate 301 and the top surface of the active pillar 310 in the second direction.

[0124] It can be understood that in this example, each mask pattern 366 includes an etched second mask layer and a first mask layer. Each mask pattern 366 extends in the y direction and is located directly above the active pillars 310 arranged alternately in the y direction; the dimension of the mask pattern 366 in the x direction is smaller than the dimension of the active pillar 310 in the x direction; there is a spacing between the two opposite boundaries in the x direction of the positive projection of the mask pattern 366 on the substrate 301 and the top surface of the active pillar 310.

[0125] In some embodiments, the mask pattern 366 includes a first sidewall and a second sidewall opposite to each other in the x direction; the top surface of the active pillar 310 includes a first boundary and a second boundary opposite to each other in the x direction; there is a first spacing between the positive projection of the first sidewall on the substrate 301 and the first boundary, and there is a second spacing between the positive projection of the second sidewall on the substrate 301 and the second boundary. Here, the first sidewall is relatively close to the first boundary, and the second sidewall is relatively close to the second boundary.

[0126] In some embodiments, the first spacing is equal to the second spacing, and subsequently, a word line 330 as shown in Figure 22 can be formed based on the mask pattern 366. In other embodiments, the first spacing and the second spacing are not equal, and subsequently, a word line 330 as shown in Figure 23 or Figure 24 can be formed based on the mask pattern 366.

[0127] The formation process of the mask pattern 366 includes a self-alignment process; the self-alignment process includes one or more of a self-aligned double patterning process (SADP), a self-aligned triple patterning process (SATP), a self-aligned quadruple patterning process (SAQP), and a self-aligned octuple patterning process, so as to obtain a finer mask pattern. Correspondingly, the mask pattern includes one or more of a self-aligned double exposure mask pattern, a self-aligned triple exposure mask pattern, a self-aligned quadruple exposure mask pattern, or a self-aligned octuple exposure mask pattern.

[0128] Referring to Figure 18 as shown, using the mask pattern 366 as a mask to etch the first sub-mask material layer 351', exposing the second doped region 310c of the active pillar within the spacing, and the remaining first sub-mask material layer 351' constitutes the first sub-mask layer 351. As shown in Figure 19 the first sub-mask layer 351 is located between two adjacent active pillars 310 in the first direction; the dimension of the first sub-mask layer 351 in the second direction is smaller than the dimension of the active pillar 310 in the second direction.

[0129] In a specific embodiment, the first sub-mask material layer 351' can be dry-etched using the mask pattern 366 as a mask until the word line material layer 330' is exposed, as shown in Figure 19As shown, since the material of the thermal oxide layer 305' is the same as that of the first sub-mask material layer 351', the thermal oxide layer 305' covering the sidewalls and the top of the second doped region 310c is etched away simultaneously, and the remaining thermal oxide layer 305' constitutes the gate dielectric layer 305.

[0130] Referring to Figure 19 As shown, the first sub-mask layer 351 is located above the word line material layer 330' and is alternately arranged with the active pillars 310 (e.g., the second doped region 310c) in the y direction. The size of the first sub-mask layer 351 in the x direction is smaller than the size of the active pillar 310 in the x direction, and there is a spacing between the two opposite boundaries of the first sub-mask layer 351 and the active pillar 310 in the second direction.

[0131] In some embodiments, referring to FIG. 20, the above-mentioned formation of the word line mask layer 330' further includes: forming a second sub-mask layer 352. For example, the second sub-mask layer 352 is formed on the opposite sidewalls of the first sub-mask layer 351 in the x direction and the exposed sidewalls of the second doped region 310c. The second sub-mask layer 352 and the first sub-mask layer 351 together constitute the word line mask layer 350, and the word line mask layer 350 can define the shape and position of the word line 330.

[0132] In some embodiments, the above-mentioned formation of the second sub-mask layer 352 includes: forming a second sub-mask material layer covering the first sub-mask layer 351, the exposed second doped region 310c, and the word line material layer 330'. The second sub-mask material layer includes, but is not limited to, silicon oxide, and the formation process of the second sub-mask material layer includes an atomic layer deposition process; etching back the second sub-mask material layer to form the second sub-mask layer 352 on the exposed sidewalls of the first sub-mask layer 351 and the second doped region 310c. The preparation process of the second sub-mask layer 352 can refer to the above-mentioned spacer layer 365, which will not be elaborated here. In this example, the first sub-mask layer 351 and the second doped region 310c alternately arranged in the y direction can be used as the mandrel in the self-alignment process, so that the second sub-mask layer 352 can be formed without additional photolithography processes and can be compatible with the existing manufacturing processes.

[0133] In some embodiments, referring to Figure 21 As shown, the above-mentioned step S220 further includes: etching the word line material layer 330' using the word line mask layer 350 as a mask to form word line isolation trenches 370; wherein, the bottom of the word line isolation trenches 370 exposes the second dielectric layer 303; the remaining word line material layer 330' constitutes the word line 330.

[0134] Referring to Figures 21 to 24As shown, each word line 330 extends along a first direction and the word lines 330 are arranged at intervals in a second direction; the word line 330 includes a plurality of gates 3301 and a plurality of connection structures 3302 alternately arranged along the first direction; the gate 3301 covers the side walls of the channel 310b of the active column 310; the connection structure 3302 is connected to two adjacent gates 3301; the sum of the dimensions of the gate 3301 and the active column 310 in the second direction is greater than the dimension of the connection structure 3302 in the second direction; the dimensions of the gate 3301 on the opposite sides of the active column 310 in the second direction are substantially the same.

[0135] In some embodiments, etching the word line material layer 330' using the word line mask layer 350 as a mask includes: the second sub-mask layer 352 covering the side walls of the second doped region 310c correspondingly forms the gate 3301; the first sub-mask layer 351 and the second sub-mask layer 352 covering the side walls of the first sub-mask layer 351 correspondingly form the connection structure 3302.

[0136] It can be understood that etching the word line material layer 330' using the second sub-mask layer 352 covering the side walls of the second doped region 310c as a mask can correspondingly form the gate 3301; etching the word line material layer 330' using the first sub-mask layer 351 and the second sub-mask layer 352 covering the side walls of the first sub-mask layer 351 as a mask can correspondingly form the connection structure 3302. Since the sum of the dimensions of the active column 310 and the second sub-mask layers 352 on both side walls in the second direction is greater than the sum of the dimensions of the first sub-mask layer 351 and the second sub-mask layers 352 on both side walls in the second direction, therefore, the sum of the dimensions of the active column 310, the gate dielectric layer 305, and the gate 3301 in the second direction is greater than the dimension of the connection structure 3302 in the second direction. Since the dimension of the gate dielectric layer 305 in the second direction is much smaller than the dimension of the active column 310 or the gate 3301 in the second direction, therefore, the thickness of the gate dielectric layer 305 can be ignored, so that the sum of the dimensions of the active column 310 and the gate 3301 in the second direction is greater than the dimension of the connection structure 3302 in the second direction. Here, the gate dielectric layer 305 refers to the gate dielectric layers 305 on the two side walls of the active column 310 in the second direction, and the gate 3301 refers to the gates 3301 on the two side walls of the active column 310 in the second direction.

[0137] In some embodiments, the cross-section of the active pillar 310 in the vertically extending direction may be circular or elliptical. The circular or elliptical active pillar 310 can be obtained by further processing the rectangular active pillar 310 through a thermal oxidation method in step S210. In step S220, the sum of the dimensions of the gate 3301 and the active pillar 310 in the second direction is the sum of the maximum dimensions of the gate 3301 and the active pillar 310 in the second direction. Therefore, when forming the mask pattern 366, the orthographic projection of the mask pattern 366 on the top surface of the active pillar 310 exposes two regions of the top surface, and the two regions are respectively located on the opposite sides of the mask pattern 366 along the x direction, so that when forming the word line mask layer 350, the sum of the maximum dimensions of the active pillar 310 and the word line mask layer 350 covering the side wall of the active pillar 310 in the second direction is greater than the dimension of the word line mask layer 350 between two adjacent active pillars 310 in the second direction.

[0138] In some embodiments, the above preparation method further includes: forming a word line isolation structure (not shown in the figure) extending along the first direction between two adjacent word lines 330, and the word line isolation structure fills the word line isolation trench 370. The material of the word line isolation structure includes insulating materials, such as silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0139] In some embodiments, the above preparation method further includes: forming a storage structure on the active pillar 310, and the storage structure is connected to the second doped region 310c. The storage structure includes but is not limited to a capacitor. Since the threshold voltage of the transistor is stable, the retention time of the capacitor can be guaranteed to be stable.

[0140] It should be noted that Figure 1d In the shown solution, for the photoresist pattern for presetting the formation of word lines, the width of each photoresist in the second direction is relatively large, and there may be an offset during actual exposure. In order to ensure that the word lines cover the active pillars in the same row (corresponding to the y direction) and do not cover the active pillars in adjacent rows, the spacing between adjacent rows of active pillars is usually designed to be relatively large, resulting in a low density of active pillars in the same area, which is not conducive to improving the integration degree.

[0141] In the solution provided by the embodiments of the present disclosure (which can be referred to Figures 14 to 18 ), for the photoresist pattern for presetting the formation of word lines, the width of each photoresist in the second direction is relatively small. Even if there is an offset during actual exposure, since the word line material layer is etched to form the gate with the active pillar and the second sub-mask layer covering the side wall of the active pillar as the mask, there is no situation where the word line covers the adjacent row after the offset. Therefore, the spacing between adjacent rows of active pillars can be designed to be smaller, which is conducive to increasing the density of active pillars, and more transistors can be formed in the same area, which is conducive to improving the integration degree.

[0142] In a specific embodiment, the pitch between adjacent rows of active pillars is greater than or equal to 30 nanometers and less than or equal to 42 nanometers. The pitch between adjacent rows of active pillars is the pitch between the same boundaries of two rows of active pillars in the x direction, such as the first boundary of the active pillar.

[0143] In the manufacturing method provided by the present disclosure, in the first aspect, by forming multiple word lines, each word line includes a plurality of gates and a plurality of connection structures alternately arranged in a first direction. The gates cover the side walls of the channels of the active pillars, and the connection structures are connected to two adjacent gates. The sizes of the gates on the opposite sides of the active pillar in the second direction are substantially the same, which can ensure the uniform thickness of the gate-all-around of a single transistor, making the threshold voltage of the transistor stable, enabling the transistor to be normally turned on without increasing the voltage applied to the word line and reducing the off-current when the transistor is turned off, which is beneficial to reducing power consumption; in the second aspect, using a word line mask layer including a first sub-mask layer and a second sub-mask layer as a mask to etch a word line material layer to form word lines and word line isolation trenches can fix the position of the word line isolation structure and the thickness of the gates, making the electrical performance of the semiconductor structure more stable; in the third aspect, fixing the position of the word line isolation structure can increase the process window, and there is no situation where the word line shifts and covers adjacent rows, and the pitch between adjacent rows of active pillars can be designed to be smaller, which is beneficial to increasing the density of the active pillars and thus improving the integration; in the fourth aspect, since the threshold voltage of the transistor is stable, the retention time of the capacitor connected to the transistor can be ensured to be stable.

[0144] Based on the manufacturing method of the above semiconductor structure 300, an embodiment of the present disclosure further provides a semiconductor structure 300. Figure 22 is a schematic diagram of a semiconductor structure 300 shown according to an embodiment of the present disclosure. Refer to Figure 22 As shown, the semiconductor structure 300 includes:

[0145] A plurality of active pillars 310, the plurality of active pillars 310 are arranged in an array in the first direction and the second direction; wherein, the extending direction of the active pillar 310 is perpendicular to both the first direction and the second direction, and the first direction and the second direction intersect;

[0146] Multiple word lines 330, each word line 330 extends in the first direction and the word lines 330 are spaced apart in the second direction; the word line 330 includes a plurality of gates 3301 and a plurality of connection structures 3302 alternately arranged in the first direction; wherein, the gates 3301 cover the side walls of the channels 310b of the active pillars; the connection structures 3302 are connected to two adjacent gates 3301; the sum of the sizes of the gates 3301 and the active pillars 310 in the second direction is greater than the size of the connection structures 3302 in the second direction; the sizes of the gates 3301 on the opposite sides of the active pillar 310 in the second direction are substantially the same.

[0147] In a specific embodiment, the semiconductor structure 300 includes a substrate, in which a plurality of active pillars 310 are distributed in an array, and the extending direction of the active pillars 310 is the thickness direction of the substrate. The material of the substrate can refer to the description in the above method embodiments and will not be elaborated here.

[0148] In a specific embodiment, the substrate has a plurality of first trenches (extending in the x direction) and a plurality of second trenches (extending in the y direction), and the first trenches and the second trenches divide a plurality of active pillars 310 distributed in an array; wherein, the depth of the first trenches is less than the thickness of the substrate, and the depth of the second trenches is less than the depth of the first trenches. The formation processes of the first trenches and the second trenches have been described above and will not be elaborated here.

[0149] In a specific embodiment, the dimensions of the gate 3301 on the opposite sides of the active pillar 310 along the x direction are substantially the same, and substantially the same includes being exactly the same or having a deviation within the process allowable error range. Further, the dimensions of the gate 3301 on the opposite sides of the active pillar 310 along the x direction are substantially the same as the dimensions of the gate 3301 on the opposite sides of the active pillar 310 along the y direction.

[0150] In the embodiments of the present disclosure, by setting the word line to include a plurality of gates and a plurality of connection structures alternately arranged in a first direction, the gates cover the side walls of the channels of the active pillars, the connection structures are connected to two adjacent gates, and the dimensions of the gates on the opposite sides of the active pillar along a second direction are substantially the same, which can ensure the uniform thickness of the surrounding gate of a single transistor, make the threshold voltage of the transistor stable, can turn on the transistor normally without increasing the voltage applied to the word line, and reduce the turn-off current when the transistor is turned off, which is beneficial to reducing power consumption.

[0151] In some embodiments, referring to Figure 22 as shown, the semiconductor structure 300 further includes: a word line isolation structure (not shown in the figure), extending in the first direction and located between two adjacent word lines 330; wherein, the dimensions of the gates 3301 on the opposite sides of the word line isolation structure along the second direction are substantially the same.

[0152] Figure 22 Two rows of active pillars 310 and two word lines 330 are shown, the word line isolation structure fills the word line isolation trench 370 between the two word lines 330, and the material of the word line isolation structure can refer to the description in the above method embodiments and will not be elaborated here.

[0153] In some embodiments, the dimensions of the gates 3301 located on opposite sides of the word line isolation structure in the x-direction are substantially the same, that is, the two opposite gates exposed by the word line isolation trench 370 have the same thickness. In other embodiments, the dimensions of the gates 3301 located on opposite sides of the word line isolation structure in the second direction are different, that is, the two opposite gates exposed by the word line isolation trench 370 have different thicknesses.

[0154] It can be understood that in this example, each gate 3301 of the same word line 330 has the same thickness on opposite sides of the active pillar 310 in the x-direction; the thicknesses of the gates 3301 of different word lines 330 on opposite sides of the active pillar 310 in the x-direction can be the same or different, and the present disclosure has no special restrictions on this. In actual applications, those skilled in the art can make selections according to requirements, which increases the design flexibility and process window.

[0155] In some embodiments, referring to Figure 22 As shown, the dimensions of the connection structures 3302 of at least two word lines 330 in the second direction are substantially the same, that is, the two opposite connection structures 3302 exposed by a word line isolation trench 370 have substantially the same dimensions in the x-direction. It should be noted that multiple word lines 330 and multiple word line isolation trenches 370 are formed in the semiconductor structure, and the two opposite connection structures 3302 exposed by at least one word line isolation trench 370 have substantially the same dimensions in the x-direction.

[0156] In a specific embodiment, the dimensions of the connection structures 3302 of each word line 330 in the x-direction are substantially the same, that is, the two opposite connection structures 3302 exposed by each word line isolation trench 370 have substantially the same dimensions in the x-direction.

[0157] In another specific embodiment, the dimensions of the connection structures 3302 of at least two of the multiple word lines 330 in the x-direction are substantially the same, and the dimensions of the connection structures 3302 of the word lines other than the at least two word lines among the multiple word lines are different in the x-direction.

[0158] In some embodiments, referring to Figure 22 As shown, along the second direction, the symmetry axis of the connection structure 3302 of the same word line 330 coincides with the symmetry axis of the gate 3301. For example, the connection structure 3302 and the gate 3301 of the same word line 330 are both symmetric about the first symmetry axis L1.

[0159] It can be understood that when Figure 18When the first distance between the positive projection of the first side wall of the middle mask pattern 366 on the substrate and the first boundary of the active column 310 is equal to the second distance between the positive projection of the second side wall of the mask pattern 366 on the substrate and the second boundary of the active column 310, etching based on the mask pattern 366 can make the symmetry axis of the connection structure 3302 of the same word line 330 coincide with the symmetry axis of the gate 3301.

[0160] In some other embodiments, along the second direction, the symmetry axis of the connection structure 3302 of the same word line 330 is offset from the symmetry axis of the gate 3301.

[0161] For example, referring to Figure 23 As shown, the gate 3301 of the word line 330 is symmetric about the first symmetry axis L1, the connection structure 3302 of the word line 330 is symmetric about the second symmetry axis L2, and the second symmetry axis L2 is offset in the negative x-axis direction compared with the first symmetry axis L1.

[0162] Another example, referring to Figure 24 As shown, the gate 3301 of the word line 330 is symmetric about the first symmetry axis L1, the connection structure 3302 of the word line 330 is symmetric about the third symmetry axis L3, and the third symmetry axis L3 is offset in the positive x-axis direction compared with the first symmetry axis L1.

[0163] It can be understood that when Figure 18 the first distance between the positive projection of the first side wall of the middle mask pattern 366 on the substrate and the first boundary of the active column 310 is not equal to the second distance between the positive projection of the second side wall of the mask pattern 366 on the substrate and the second boundary of the active column 310, for example, when the first distance is greater than or less than the second distance, etching based on the mask pattern 366 can make the symmetry axis of the connection structure 3302 of the same word line 330 offset from the symmetry axis of the gate 3301.

[0164] It should be noted that in this example, even if the symmetry axis of the connection structure 3302 of the same word line 330 is offset from the symmetry axis of the gate 3301, it can still ensure that the dimensions of the gate on the two opposite sides of the active column along the second direction are basically the same. Therefore, there is no need to increase the voltage applied to this word line, which is beneficial to reducing power consumption.

[0165] In some embodiments, referring to Figure 23 As shown, half of the difference between the sum of the dimensions W1 of the gate 3301 and the active column 310 in the second direction and the dimension W2 of the connection structure 3302 in the second direction is greater than the offset amount. To ensure good connection between the connection structure 3302 and the gate 3301 of the same word line 330, the magnitude of the offset amount should satisfy: offset amount + W2 / 2 ≤ W1 / 2, that is, the offset amount ≤ (W1 - W2) / 2.

[0166] In the manufacturing process, the condition that the above-mentioned offset amount needs to satisfy can be achieved by making the size of the mask pattern 366 in the x direction smaller than the size of the active pillar 310 in the x direction and having a spacing between the two opposite boundaries in the x direction of the top surface of the active pillar 310 and the positive projection of the mask pattern 366 on the substrate 301.

[0167] It can be understood that when the offset amount > (W1 - W2) / 2, one of the opposite boundaries (for example, the upper boundary or the lower boundary) of the connection structure 3302 of the same word line in the x direction will exceed the gate 3301, and the contact area between the connection structure and the gate decreases, resulting in an increase in the resistance of the word line.

[0168] In the embodiments of the present disclosure, by controlling that half of the difference between the sum of the sizes of the gate and the active pillar in the second direction and the size of the connection structure in the second direction is greater than the offset amount, it can be ensured that one of the opposite boundaries of the connection structure in the second direction does not exceed the gate, which is beneficial to ensuring a good connection between the connection structure and the gate.

[0169] In some embodiments, the active pillar includes a first doped region, a channel 310b, and a second doped region sequentially arranged along the extending direction of the active pillar. The first doped region includes a drain (or a source), and the second doped region includes a source (or a drain).

[0170] In some embodiments, the cross-section of the active pillar 310 in the vertical extending direction is rectangular, circular, or elliptical. For example, as Figure 21 shown, the cross-section of the active pillar 310 is rectangular; or for another example, as Figure 25 shown, the cross-section of the active pillar 310 is circular. Of course, the cross-section of the active pillar can also be other shapes known in the art, and the present disclosure has no special limitation on this.

[0171] In some embodiments, as shown in combination with Figure 20 the semiconductor structure 300 further includes: a word line mask layer 350, located above the word line 330; wherein, the word line mask layer 350 covers the side walls of the second doped region. For the word line mask layer 350, reference can be made to the description in the above method embodiments, and details are not described herein again.

[0172] In some embodiments, as shown in combination with Figure 20 the word line mask layer 350 includes:

[0173] a first sub-mask layer 351, located between two adjacent active pillars in the first direction; wherein, the size of the first sub-mask layer 351 in the second direction is smaller than the size of the active pillar in the second direction;

[0174] A second sub-mask layer 352 covers two sidewalls of the first sub-mask layer 351 opposite to the active pillar along the second direction; the sum of the sizes of the first sub-mask layer 351 and the second sub-mask layer 352 in the second direction is substantially equal to the size of the connection structure 3302 in the second direction, and the size of the second sub-mask layer 352 in the second direction is greater than or equal to the size of the gate 3301 in the second direction. For the descriptions of the first sub-mask layer 351 and the second sub-mask layer 352, reference may be made to the descriptions in the above method embodiments, which will not be elaborated here. It can be understood that the word line mask layer 350 can be retained and form a part of the semiconductor structure.

[0175] In some embodiments, the materials of the first sub-mask layer 351 and the second sub-mask layer 352 can be the same or different. For example, the material of the first sub-mask layer 351 can be silicon oxide, and the material of the second sub-mask layer 352 can be silicon oxide or silicon nitride.

[0176] In some embodiments, the semiconductor structure 300 further includes: bit lines and storage structures, which are respectively connected to opposite sides of the active pillar 310 away from the channel 310b. For example, the bit line is located under the active pillar 310 and connected to the first doped region 310a of the active pillar, and the storage structure is located above the active pillar 310 and connected to the second doped region 310c of the active pillar. The storage structure includes but is not limited to a capacitor.

[0177] In some embodiments, the semiconductor structure 300 includes: a memory, which can be a dynamic random access memory, and can also be a memory known in the art, such as a phase change memory or a ferroelectric memory, etc.

[0178] It should be noted that the active pillar in the embodiments of the present disclosure can be located in the array region and / or the peripheral region. When the active pillar is located in the array region, the transistor including the active pillar and the storage structure together form a storage cell; when the active pillar is located in the peripheral region, the transistor including the active pillar and electronic components such as capacitors and resistors form a peripheral circuit.

[0179] The embodiments of the present disclosure further provide an electronic device, including a processor device and a storage device electrically connected to the processor device. The storage device includes the semiconductor structure shown in any of the above embodiments. The electronic device can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or can also be a personal computer (PC), a server, a workstation, etc. The storage function in the electronic device can be implemented by the following storage devices: dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), magnetic random access memory (MRAM), or resistive random access memory (RRAM).

[0180] As described above, this is only the specific implementation manner of the present disclosure. However, the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A plurality of active pillars, wherein the plurality of active pillars are distributed in an array in a first direction and a second direction; wherein the extension direction of the active pillars is perpendicular to both the first direction and the second direction, and the first direction and the second direction intersect; A plurality of word lines, each of which extends along the first direction and is arranged at intervals in the second direction; the word lines include a plurality of gates and a plurality of connection structures alternately arranged along the first direction; wherein the gates cover the side walls of the channels of the active pillars; the connection structure is connected to two adjacent gates; the sum of the maximum dimensions of the gates and the active pillars in the second direction is greater than the dimension of the connection structure in the second direction; and the dimensions of the gates on opposite sides of the active pillars along the second direction are substantially the same.

2. The semiconductor structure according to claim 1, wherein The semiconductor structure further comprises: A word line isolation structure extends along the first direction and is located between two adjacent word lines; wherein the gates located on two opposite sides of the word line isolation structure along the second direction have substantially the same size.

3. The semiconductor structure according to claim 1, wherein The connection structures of at least two of the word lines have substantially the same size in the second direction; or Along the second direction, the symmetry axis of the connection structure of the same word line coincides with the symmetry axis of the gate; or, Along the second direction, the symmetry axis of the connection structure of the same word line is offset from the symmetry axis of the gate, and the sum of the maximum dimensions of the gate and the active column in the second direction and half of the difference in the dimension of the connection structure in the second direction is greater than the offset.

4. The semiconductor structure according to claim 1, wherein The semiconductor structure further comprises: The bit line and the storage structure are respectively and correspondingly connected to two opposite sides of the active pillar away from the channel.

5. A method for manufacturing a semiconductor structure, characterized in that, include: Providing a plurality of active pillars; wherein the plurality of active pillars are distributed in an array in a first direction and a second direction; the extension direction of the active pillars is perpendicular to both the first direction and the second direction, and the first direction and the second direction intersect; A plurality of word lines are formed; wherein each of the word lines extends along the first direction and the word lines are arranged at intervals in the second direction; the word lines include a plurality of gates and a plurality of connection structures alternately arranged along the first direction; the gates cover the side walls of the channels of the active pillars; the connection structure is connected to two adjacent gates; the sum of the maximum dimensions of the gates and the active pillars in the second direction is greater than the dimension of the connection structure in the second direction; the dimensions of the gates on opposite sides of the active pillars along the second direction are substantially the same.

6. The preparation method according to claim 5, wherein, The plurality of active pillars include: substrate; A plurality of first grooves are located in the substrate; each of the first grooves extends along the second direction, and the plurality of first grooves are arranged at intervals along the first direction; A first dielectric layer filling a portion of the depth of the first trench; A plurality of second trenches, located in the substrate and the first dielectric layer; each of the second trenches extends along the first direction, the plurality of second trenches are spaced along the second direction, and the depth of the second trench is less than the depth of the first trench; wherein, the first trench and the second trench divide the substrate into a plurality of the active columns; A second dielectric layer, filling a partial depth of the second trench, the second dielectric layer and the first dielectric layer jointly coating the sidewalls of the first doped region of the active column, and the channels of the active column and the sidewalls of the second doped region are exposed in the first trench and the second trench; or, The method for forming the plurality of active columns includes: Providing a substrate; Etching the substrate to form a plurality of first trenches spaced along the first direction, the first trenches extending along the second direction, and the bottoms of the first trenches being located in the substrate; Filling the first trenches to form a first dielectric layer; Etching the substrate and the first dielectric layer to form a plurality of second trenches spaced along the second direction, the second trenches extending along the first direction, and the depth of the second trench being less than the depth of the first trench; wherein, the first trench and the second trench divide the substrate into a plurality of the active columns; The preparation method further includes: Filling the second trenches to form a second dielectric layer; Etching and removing a part of the second dielectric layer and a part of the first dielectric layer until the sidewalls of the channels of the active columns are exposed; wherein, the remaining second dielectric layer and the first dielectric layer jointly coat the sidewalls of the first doped region of the active column.

7. The preparation method according to claim 6, characterized in that, The forming of the plurality of word lines includes: Forming a word line material layer on the second dielectric layer and the first dielectric layer, the word line material layer coating the exposed sidewalls of the channels; Forming a plurality of word line mask layers on the word line material layer, each of the word line mask layers extending along the first direction and the word line mask layers being spaced in the second direction; wherein, the word line mask layer is located between two adjacent active columns in the first direction and covers two opposite sidewalls of the active column in the second direction; the sum of the maximum dimensions of the active column and the word line mask layer covering the sidewall of the active column in the second direction is greater than the dimension of the word line mask layer between two adjacent active columns in the second direction; Etching the word line material layer using the word line mask layer as a mask to form word line isolation trenches; wherein, the bottoms of the word line isolation trenches expose the second dielectric layer; the remaining word line material layer constitutes the word lines.

8. The preparation method according to claim 7, characterized in that, The forming of the word line mask layer includes forming a first sub-mask layer and forming a second sub-mask layer; The forming of the first sub-mask layer includes: Forming a first sub-mask material layer covering the second doped region of the active column and the word line material layer; wherein, the surface of the first sub-mask material layer away from the word line material layer is at least flush with the top surface of the active column; Form a plurality of mask patterns on the first sub-mask material layer; wherein, each of the mask patterns extends along the first direction and is located above the active pillar, and the mask patterns are arranged at intervals in the second direction; the size of the mask pattern in the second direction is smaller than the size of the active pillar in the second direction, and there is a spacing between the two opposite boundaries of the top surface of the active pillar in the second direction of the orthographic projection of the mask pattern on the substrate; Etch the first sub-mask material layer using the mask pattern as a mask to expose the second doped region of the active pillar within the spacing, and the remaining first sub-mask material layer forms the first sub-mask layer; wherein, the first sub-mask layer is located between two adjacent active pillars in the first direction; the size of the first sub-mask layer in the second direction is smaller than the size of the active pillar in the second direction; The forming of the second sub-mask layer includes: Form a second sub-mask material layer covering the first sub-mask layer, the exposed second doped region, and the word line material layer; Etch back the second sub-mask material layer to form the second sub-mask layer on the sidewalls exposed by the first sub-mask layer and the second doped region.

9. The preparation method according to claim 8, wherein The etching of the word line material layer using the word line mask layer as a mask includes: The second sub-mask layer covering the sidewall of the second doped region correspondingly forms the gate; The first sub-mask layer and the second sub-mask layer covering the sidewall of the first sub-mask layer correspondingly form the connection structure.

10. An electronic device, characterized in that, Includes: A processing device; And A storage device electrically connected to the processing device, the storage device including the semiconductor structure according to any one of claims 1 to 4.

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