Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a plurality of bit line structures, a plurality of plug structures, a gap wall structure and a plurality of bonding pads. The bit line structures and the plug structures are alternately disposed on the substrate. The bit line structures include at least one first bit line structure and at least one second bit line structure. The gap wall structures are arranged between the bit line structures and the plug structures, and the first gap wall structures and the second gap wall structures are arranged on the side walls of the at least one first bit line structure and the at least one second bit line structure respectively. A pad is disposed on the bit line structure and the plug structure. The first gap wall structure partially covers and contacts the top surface of the at least one first bit line structure, and the at least one bonding pad covers and contacts the top surface of the at least one second bit line structure, so that the operation performance of the semiconductor device can be optimized.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly to a semiconductor device having a gate structure and a bit line structure and a manufacturing method thereof. Background Art

[0002] With the trend of miniaturization of various electronic products, the design of semiconductor devices must also meet the requirements of high integration and high density. For a dynamic random access memory (DRAM) with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitive structure, it has gradually replaced the dynamic random access memory with only a planar gate structure under the current mainstream development trend. Generally speaking, a dynamic random access memory with a recessed gate structure is formed by aggregating a large number of memory cells into an array region for storing information, and each memory cell can be composed of a transistor component and a capacitor component connected in series to receive voltage information from a word line (WL) and a bit line (BL). In response to product requirements, the memory cell density in the array region must be continuously increased, resulting in an increasing difficulty and complexity in related manufacturing processes and designs. Therefore, the existing technologies or structures need to be further improved to effectively improve the performance and reliability of related memory devices. Summary of the Invention

[0003] One object of the present invention is to provide a semiconductor device. By providing different spacer structures on the sidewalls of the bit line structure, the bit line structure in the adjacent peripheral region can effectively isolate the surrounding components by means of the spacer structures on its sidewalls and maintain the structural integrity of the components in the cell region. Thus, the semiconductor device of the present invention has a more optimized component structure and performance, thereby improving the operation performance of the semiconductor device.

[0004] Another object of the present invention is to provide a manufacturing method of a semiconductor device. On the premise of simplifying the manufacturing process, different spacer structures are formed on the sidewalls of the bit line structure, so that the bit line structure formed in the adjacent peripheral region can achieve the effects of effectively isolating the surrounding components and maintaining the structural integrity of the components in the cell region by means of the spacer structures formed on its sidewalls. Thus, the semiconductor device manufactured by the manufacturing method of the present invention can obtain an optimized component structure and performance, thereby improving its operation performance.

[0005] To achieve the above object, an embodiment of the present invention provides a semiconductor device, including a substrate, a plurality of bit line structures and a plurality of plug structures, a spacer structure, and a plurality of pads. The plurality of bit line structures and the plurality of plug structures are alternately disposed on the substrate, wherein the bit line structure includes at least a first bit line structure and at least a second bit line structure. The spacer structure is disposed between each of the bit line structures and each of the plug structures, and the spacer structure further includes a first spacer structure disposed on the sidewalls of the at least one first bit line structure and a second spacer structure disposed on the sidewalls of the at least one second bit line structure. The plurality of pads are disposed on the bit line structures and the plug structures. The first spacer structure further partially covers and contacts the top surface of the at least one first bit line structure, and at least one of the pads covers and contacts the top surface of the at least one second bit line structure.

[0006] To achieve the above object, an embodiment of the present invention provides a semiconductor device, including a substrate, a first bit line structure, a first spacer structure, a first plug structure, a second plug structure, and a spacer. The first bit line structure is disposed on the substrate. The first spacer structure is disposed on two opposite sidewalls of the first bit line structure, and the first spacer structure at least partially covers the top surface of the first bit line structure. The first plug structure is disposed on one side of the first bit line structure, the bottom surface of the first plug is higher than the substrate and the top surface is higher than the first bit line structure. The second plug structure is disposed on the other side of the first bit line structure, the bottom surface of the second plug is lower than the substrate and the top surface is lower than the second bit line structure. The second plug structure is disposed on the other side of the first bit line structure, the bottom surface of the second plug is lower than the substrate and the top surface is lower than the second bit line structure. The spacer is only disposed on the sidewall of the first spacer on the side of the first bit line structure close to the second plug structure, and the spacer contacts the top surface of the second plug structure.

[0007] To achieve the above object, an embodiment of the present invention provides a method for manufacturing a semiconductor device, including the following steps. Provide a substrate, and form a plurality of bit line structures on the substrate. The bit line structures include at least one first bit line structure and at least one second bit line structure. Sequentially form a spacer material layer on the substrate to cover the at least one first bit line structure and the at least one second bit line structure. Form a sacrificial layer between the bit line structures. Perform an etching process through a mask to remove the spacer material layer formed on the top surface of the at least one second bit line structure and a part of the sacrificial layer, and retain the spacer material layer formed on the top surface of the at least one first bit line structure. Perform an etching process through a mask to remove the spacer material layer formed on the top surface of the at least one second bit line structure and a part of the sacrificial layer, and retain the spacer material layer formed on the top surface of the at least one first bit line structure. Form a plurality of plug structures on the substrate. Form a plurality of pads on the bit line structures and the plug structures, and at least one of the pads covers and contacts the top surface of the at least one second bit line structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings provide a deeper understanding of the embodiments of the present invention and are incorporated into this specification as a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all the drawings are schematic diagrams, for the purpose of illustration and drawing convenience, and the relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0009] Figures 1 to 3 The following is a schematic diagram of a semiconductor device according to the first embodiment of the present invention, where:

[0010] Figure 1 is a top view schematic diagram of the semiconductor device;

[0011] Figure 2 is Figure 1 a cross-sectional schematic diagram taken along the tangents A-A' and B-B' in; and

[0012] Figure 3 is Figure 1 a cross-sectional schematic diagram taken along the tangents C-C' and D-D' in.

[0013] Figures 4 to 11 The following is a schematic diagram of the method for manufacturing a semiconductor device according to a preferred embodiment of the present invention, where:

[0014] Figure 4 is a top view schematic diagram of the semiconductor device after forming the gate structure;

[0015] Figure 5 is a cross-sectional schematic diagram taken along the tangents A-A' and B-B' in;

[0016] Figure 6 It is a top view schematic diagram of a semiconductor device after forming a bit line structure;

[0017] Figure 7 It is a cross-sectional schematic diagram taken along tangents A-A' and B-B';

[0018] Figure 8 It is a cross-sectional schematic diagram of a semiconductor device after forming a photoresist layer;

[0019] Figure 9 It is a cross-sectional schematic diagram of a semiconductor device after forming a first plug;

[0020] Figure 10 It is a cross-sectional schematic diagram of a semiconductor device after forming a second plug; and

[0021] Figure 11 It is a cross-sectional schematic diagram of a semiconductor device after forming a spacer structure and a pad.

[0022] Figure 12 The figure shows a cross-sectional schematic diagram of a semiconductor device according to the second embodiment of the present invention.

[0023] Figure 13 The figure shows a cross-sectional schematic diagram of a semiconductor device according to the third embodiment of the present invention.

[0024] The reference numerals are explained as follows:

[0025] 10, 30, 50 - semiconductor device;

[0026] 100 - substrate;

[0027] 100a - peripheral region;

[0028] 100b - cell region;

[0029] 100t - top surface;

[0030] 102 - shallow trench isolation;

[0031] 104 - active region;

[0032] 110 - dielectric layer;

[0033] 112 - silicon oxide layer;

[0034] 114 - silicon nitride layer;

[0035] 116 - silicon oxide layer;

[0036] 120 - bit line structure;

[0037] 120a - first bit line structure;

[0038] 120b - Second bit line structure;

[0039] 120c - Third bit line structure;

[0040] 121 - Bit line plug;

[0041] 122 - Semiconductor layer;

[0042] 124 - Barrier layer;

[0043] 126 - Metal layer;

[0044] 128 - Capping layer;

[0045] 130 - Gate spacer;

[0046] 132 - Etch stop layer;

[0047] 134 - Insulating layer;

[0048] 138 - Overlay;

[0049] 140 - Spacer structure;

[0050] 140a - First spacer structure;

[0051] 140b - Second spacer structure;

[0052] 140c - Third spacer structure;

[0053] 142a, 142b, 142c - Second spacer;

[0054] 144a, 144b, 144c - Spacer;

[0055] 146a, 146b, 146c - First spacer;

[0056] 148a, 148b, 148c - Third spacer;

[0057] 150 - Plug structure;

[0058] 150a - First plug;

[0059] 150b - Second plug;

[0060] 154 - Metal silicide layer;

[0061] 156 - Plug spacer;

[0062] 160, 160a, 160b - Pad;

[0063] 162 - Insulating spacer;

[0064] 170 - Word line structure;

[0065] 172 - Dielectric layer;

[0066] 174 - Gate dielectric layer;

[0067] 176 - Gate;

[0068] 178 - Capping layer;

[0069] 220 - Gate structure;

[0070] 238 - Capping material layer;

[0071] 246 - Spacer material layer;

[0072] 250 - Sacrificial layer;

[0073] 340, 540 - Spacer structure;

[0074] 340a, 540a - First spacer structure;

[0075] 340b, 540b - Second spacer structure;

[0076] 340c, 540c - Third spacer structure;

[0077] 342a, 342b, 342c - Second spacer;

[0078] 344a, 344b, 344c - Spacer;

[0079] 346a, 346b, 346c - First spacer;

[0080] 348a, 348b, 348c - Third spacer;

[0081] 350 - Spacer;

[0082] 542a, 542b, 542c - Second spacer;

[0083] 544a, 544b, 544c - Spacer;

[0084] 546a, 546b, 546c - First spacer;

[0085] 548a, 548b, 548c - Third spacer;

[0086] D1 - First direction;

[0087] D2 - Second direction;

[0088] D3 - Extension direction;

[0089] GS - bit - line stacked layer structure;

[0090] h1, h2, h3 - extension height;

[0091] HM - mask layer;

[0092] OP1 - plug hole;

[0093] OP2 - opening;

[0094] PR - photoresist layer;

[0095] t1, t2, t3 - top surface;

[0096] Y - vertical direction. Detailed implementation manners

[0097] To enable those of ordinary skill in the art to which the present invention pertains to further understand the present invention, the following specifically lists the preferred embodiments of the present invention and, in conjunction with the accompanying drawings, details the composition and the effects to be achieved of the present invention. It should be noted that, without departing from the spirit of the present invention, the features in several different embodiments can be replaced, recombined, and mixed to complete other embodiments.

[0098] Please refer to Figures 1 to 3 as shown. What is illustrated is a schematic diagram of a semiconductor device 10 according to the first embodiment of the present invention. Among them, Figure 1 is a top - view schematic diagram of the semiconductor device 10, Figure 2 , and Figure 3 are cross - sectional schematic diagrams of the semiconductor device 10. First, as Figure 1 and Figure 2 shown, the semiconductor device 10 includes a substrate 100, a plurality of bit - line structures 120 and a plurality of plug structures 150 alternately disposed on the substrate 100, a spacer structure 140 disposed between each bit - line structure 120 and each plug structure 150, and a plurality of pads 160 disposed on the bit - line structures 120 and the plug structures 150. To clearly present the relative arrangement positions among the bit - line structure 120, the spacer structure 140, and the plug structure 150, Figure 1 the components disposed above the bit - line structure 120, the spacer structure 140, and the plug structure 150 are omitted in Figures 2 to 3 . However, those skilled in the art should be able to easily understand the specific positions of the omitted components on Figure 1 from the cross - sectional schematic diagram shown.

[0099] The substrate 100 includes, for example, a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate, etc., and a peripheral region 100a with a relatively low component integration density and a cell region 100b with a relatively high component integration density are simultaneously defined on the substrate 100. In one embodiment, the cell region 100b and the peripheral region 100a are, for example, adjacent to each other as shown in Figure 1 and Figure 2 , but not limited thereto. At least one shallow trench isolation 102 as shown in Figure 1 and Figure 2 is further provided in the substrate 100, and a plurality of active regions 104 are defined on the substrate 100. The bit line structure 120 includes at least one first bit line structure 120a and at least one second bit line structure 120b, both of which are located in the cell region 100b, and the spacer structure 140 includes a first spacer structure 140a provided on the sidewall of at least one first bit line structure 120a and a second spacer structure 140b provided on the sidewall of at least one second bit line structure 120b. It should be particularly noted that the first spacer structure 140a also partially covers and contacts the top surface t1 of at least one first bit line structure 120a, and a pad 160b covers and contacts the top surface t2 of at least one second bit line structure 120b. Thus, by providing the first spacer structure 140a and the second spacer structure 140b with different stacked structures on the sidewalls of at least one first bit line structure 120a and at least one second bit line structure 120b, at least one first bit line structure 120a located adjacent to the peripheral region 100a can be effectively isolated from adjacent components (such as the pad 160b provided above), optimizing the component structure in the cell region 100b, thereby improving the structural reliability and performance of the semiconductor device 10.

[0100] The bit line structure 120 further includes at least one third bit line structure 120c also provided in the cell region 100b, which has a width W1 that is relatively greater than the width W2 of at least one first bit line structure 120a or at least one second bit line structure 120b in the first direction D1, as shown in Figure 1 and Figure 2as shown, but not limited thereto. Specifically, the bit line structure 120 includes, for example, a plurality of second bit line structures 120b located in the cell region 100b, at least one first bit line structure 120a, and at least one third bit line structure 120c. They are respectively disposed on the dielectric layer 110, and further include, in the vertical direction Y, a semiconductor layer 122 (e.g., including semiconductor materials such as doped polysilicon and doped amorphous silicon) stacked in sequence, a barrier layer 124 (e.g., including conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide), a metal layer 126 (e.g., including low-resistance metal materials such as tungsten, aluminum, or copper), a capping layer 128 (e.g., including insulating materials such as silicon nitride, silicon carbonitride, or silicon oxynitride), and a cover layer 138 (e.g., including insulating materials such as silicon nitride, silicon carbonitride, or silicon oxynitride). Among them, at least one bit line plug 121 (bit line contact, BLC) integrally formed with the semiconductor layer 122 is further disposed under at least one first bit line structure 120a and each second bit line structure 120b. The bit line plug 121 extends into the substrate 100 to be electrically connected to the corresponding active region 104 in the cell region 100b. No bit line plug is disposed under at least one third bit line structure 120c, which serves as a dummy bit line. In addition, the cover layer 138 of at least one third bit line structure 120c also partially extends onto the insulating layer 134 on one side thereof, as Figure 2 shown, but not limited thereto. In one embodiment, the dielectric layer 110 includes, for example, a silicon oxide layer 112, a silicon nitride layer 114, and a silicon oxide layer 116 stacked in sequence and has an oxide-nitride-oxide (ONO) structure, but not limited thereto.

[0101] The plug structure 150 further includes a first plug 150a disposed on one side of at least one first bit line structure 120a and a second plug 150b disposed on one side of each second bit line structure 120b. Among them, the bottom surface of the first plug 150a is higher than the top surface 100t of the substrate 100, and the top surface is higher than the top surface t1 of at least one first bit line structure 120a, while the second plug 150b partially extends into the substrate 100, so that its bottom surface is lower than the top surface 100t of the substrate 100, and the top surface is lower than the top surface t2 of each second bit line structure 120b. In one embodiment, the second plug 150b includes, for example, semiconductor materials such as doped polysilicon and doped amorphous silicon, or low-resistance metal materials such as tungsten, aluminum, or copper, and is electrically connected to the active region 104 in the unit region 100b; while the first plug 150a includes, for example, insulating materials such as silicon oxide and silicon oxynitride, and is not electrically connected to any components. Thus, the second plug 150b can serve as a storage node contact (SC) of the semiconductor device 10 to receive and transfer the voltage signal of the substrate 100 (such as the source or drain of a transistor component in the substrate 100), while the first plug 150a serves as a dummy plug.

[0102] On the other hand, the pads 160 are alternately arranged with a plurality of insulating spacers 162 disposed above the spacer wall structure 140 in the first direction D1, and further include a pad 160a and a pad 160b respectively disposed on the first plug 150a and the second plug 150b. Among them, the pad 160a is disposed above the first plug 150a and at least one third bit line structure 120c at the same time; while the pad 160b is disposed above the second plug 150b and at least one first bit line structure 120a at the same time, or is disposed above the second plug 150b and a second bit line structure 120b at the same time. The pad 160b disposed above the second plug 150b and a second bit line structure 120b directly covers and contacts the covering layer 138 of the second bit line structure 120b; while the pad 160b disposed above the second plug 150b and at least one first bit line structure 120a does not contact the covering layer 138 of at least one first bit line structure 120a, as Figure 2 shown. In one embodiment, each pad 160 includes, for example, low-resistance metal materials such as tungsten, aluminum, or copper, and the insulating spacer 162 includes, for example, insulating materials such as silicon nitride and silicon carbonitride, but is not limited thereto. Thus, the pad 160b can be electrically connected to the corresponding second plug 150b through the metal silicide layer 154 disposed below and directly contacting the second plug 150b; while the pad 160a directly contacts the first plug 150a serving as the dummy plug.

[0103] The spacer wall structure 140 further includes a third spacer wall structure 140c disposed on the sidewalls of at least one third bit line structure 120c. Thus, the first spacer wall structure 140a, the second spacer wall structure 140b, and the third spacer wall structure 140c are respectively disposed on the sidewalls of at least one first bit line structure 120a, each second bit line structure 120b, and at least one third bit line structure 120c extending in the second direction D2, as Figure 1 and Figure 2 shown. Specifically, the first spacer wall structure 140a, for example, includes a first spacer wall 146a (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.) covering one sidewall and the top surface t1 of at least one first bit line structure 120a, a spacer wall 144a (e.g., made of materials such as silicon oxide, silicon oxynitride, etc.) disposed on the entire sidewall, a second spacer wall 142a (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.) covering and contacting the entire sidewall and the top surface t1, and a third spacer wall 148a (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.) disposed on the upper half of the sidewall. Among them, the third spacer wall 148a is disposed between the first spacer wall 146a and a pad 160b. The second spacer wall structure 140b, for example, includes a first spacer wall 146b (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.) disposed on the entire sidewall of each second bit line structure 120b, a spacer wall 144b (e.g., made of materials such as silicon oxide, silicon oxynitride, etc.), and a second spacer wall 142b (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.), and a third spacer wall 148b (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.) disposed only on the upper half of the sidewall. Among them, the third spacer wall 148b is located between the first spacer wall 146b and a pad 160b. The third spacer wall structure 140c includes a first spacer wall 146c (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.) disposed on the entire sidewall and the top surface t3 of at least one third bit line structure 120c, a spacer wall 144c (e.g., made of materials such as silicon oxide, silicon oxynitride, etc.) disposed on the entire sidewall, and a second spacer wall 142c (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.) disposed on the entire sidewall and the top surface t3, as Figure 2 shown, but not limited thereto. In one embodiment, the third spacer wall 148a of the first spacer wall structure 140a and the third spacer wall 148b of the second spacer wall structure 140b can be fabricated by the same process and include the same materials as each other, and the first spacer wall 146a of the first spacer wall structure 140a, the first spacer wall 146b of the second spacer wall structure 140b, and the first spacer wall 146c of the third spacer wall structure 140c can also be fabricated by the same process and include the same materials as each other; and, the spacer walls 144a, 144b, 144c or the first spacer walls 146a, 146b, 146c of the foregoing three spacer wall structures can also be optionally fabricated by the same process and include the same materials as each other, but not limited thereto.

[0104] It should be noted that the second spacer wall 142a of the first spacer wall structure 140a continuously covers the two opposite sidewalls and the top surface t1 of at least one first bit line structure 120a, and directly contacts the two opposite sidewalls and the top surface t1, so that the pad 160b disposed above does not contact the top surface t1. Moreover, the first spacer wall 146a of the first spacer wall structure 140a continuously covers the one sidewall and the top surface t1, and may partially cover and contact the second spacer wall 142a below. The second spacer wall 142c and the first spacer wall 146c of the third spacer wall structure 140c both continuously cover the one sidewall and the top surface t3 of at least one third bit line structure 120c, so that the pad 160a disposed above does not contact the top surface t3. In addition, the first spacer wall 146c also continuously covers the surface of the substrate 100 between at least one third bit line structure 120c and at least one first bit line structure 120a, and the other sidewall of at least one first bit line structure 120a. Furthermore, it should be noted that the third spacer walls 148a and 148b of the first spacer wall structure 140a and the second spacer wall structure 140b are disposed on a second plug 150b, so that the third spacer wall 148b of the second spacer wall structure 140b can partially contact the top surface of the second plug 150b and the side surface of the pad 160b above it. The third spacer wall 148a of the first spacer wall structure 140a is only disposed on the sidewall of at least one first bit line structure 120a close to the second plug 150b, and does not contact any of the insulating spacings 162. Thus, the third spacer wall 148a of the first spacer wall structure 140a has a relatively large extension height h1 in the vertical direction Y. The third spacer wall 148b of the second spacer wall structure 140b is disposed on the two opposite sidewalls of each second bit line structure 120b at the same time. Among them, the third spacer wall 148b disposed on one sidewall contacts the insulating spacing 162 above it and has a smaller extension height h2 in the vertical direction Y. Thus, the third spacer walls 148a disposed on the two opposite sidewalls of each second bit line structure 120b have different extension heights h2 and h3 in the vertical direction Y respectively, and both are smaller than the extension height h1.

[0105] Again, Figure 1 and Figure 2As shown, the semiconductor device 10 further includes a gate structure 220 disposed in the peripheral region 100a and on one side of all the bit line structures 120, and a gate spacer 130 (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.) disposed on the sidewalls of the gate structure 220. Specifically, the gate structure 220 is, for example, disposed on the silicon oxide layer 112, and also includes a semiconductor layer 122 (e.g., made of semiconductor materials such as doped polysilicon, doped amorphous silicon, etc.), a barrier layer 124 (e.g., made of conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide, etc.), a metal layer 126 (e.g., made of low-resistance metal materials such as tungsten, aluminum, or copper), and a capping layer 128 (e.g., made of insulating materials such as silicon nitride, silicon carbonitride, or silicon oxynitride) stacked in sequence in the vertical direction Y, but not limited thereto. In one embodiment, the manufacturing process of the gate structure 220 disposed in the peripheral region 100a is, for example, the same as that of the bit line structure 120 disposed in the cell region 100b, such that each gate structure 220 and each bit line structure 120 include similar stacked layers and materials, but not limited thereto. It should be noted that the gate spacer 130 is also disposed on the other sidewalls of at least one third bit line structure 120c, and an etch stop layer 132 (e.g., made of insulating materials such as silicon nitride, silicon carbonitride, etc.) is covered thereon, which continuously extends from the other sidewalls of at least one third bit line structure 120c to the two opposite sidewalls and the top surface of the gate structure 220, as Figure 2 shown.

[0106] Again, Figure 2 as shown, an insulating layer 134 and a capping layer 138 are also simultaneously disposed in the peripheral region 100a, sequentially disposed on the etch stop layer 132 and integrally covering the gate structure 220. Moreover, a first spacer 146c and a second spacer 142c of the third spacer structure 140c are also simultaneously disposed in the peripheral region 100a, and sequentially cover the capping layer 138 and the gate structure 220. In another embodiment (not shown in the figure), the first spacer (not shown) and the second spacer (not shown) of the third spacer structure may also be selectively not covering the capping layer 138 and the gate structure 220 in the peripheral region 100a, but not limited thereto. The semiconductor device 10 further includes a plug 260 disposed in the peripheral region 100a, which is simultaneously disposed in the insulating layer 134 and the capping layer 138, penetrates the etch stop layer 132 and the silicon oxide layer 112, and is electrically connected to the doped region 106 in the substrate 100 on one side of the gate structure 220. In one embodiment, the manufacturing process of the plug 260 disposed in the peripheral region 100a is, for example, the same as that of the pad 160 disposed in the cell region 100b, such that the plug 260 also includes low-resistance metal materials such as tungsten, aluminum, or copper, but not limited thereto.

[0107] As Figure 1 and Figure 3As shown, the semiconductor device 10 further includes a plurality of word line structures 170 disposed in the cell region 100b, and a plurality of storage node contact isolations (SCISOs) 156 disposed on the substrate 100. The word line structures 170 are, for example, buried in the substrate 100, separated from each other, extend in the second direction D2, and pass through the corresponding active regions 104 and shallow trench isolations 102. The plug spacers 156 are disposed above each of the word line structures 170 and are alternately arranged with the plug structures 150 in the second direction D2. Specifically, each of the word line structures 170 includes, for example, a dielectric layer 172, a gate dielectric layer 174, a gate 176, and a capping layer 178 stacked in sequence. Among them, the surface of the capping layer 178 can be flush with the top surface 100t of the substrate 100 and is covered by the dielectric layer 110, so that each of the word line structures 170 can serve as a buried word line (WL) of the semiconductor device 100 to receive or transmit voltage signals from within the substrate 100.

[0108] For another example Figure 3 As shown, in the extending direction D3 of each active region 104 (such as Figure 3 the tangent C-C' shown), the second bit line structure 120b is located between two adjacent second plugs 150b, so that the bit line plug 121 of the second bit line structure 120b is disposed between two adjacent word line structures 170 and contacts the capping layers 178 of the two word line structures 170. A second spacer structure 140b is also disposed between the second bit line structure 120b and the two second plugs 150b to isolate them from each other. It should be noted that in the extending direction D3, the plug spacers 156 are also disposed between the first spacer 146b and the third spacer 148b of the second spacer structure 140b and partially cover the top surfaces of the first spacer 146b, the spacer 144b, and the third spacer 148b. In this way, the top surface of the plug spacer 156 can be flush with the top surface t2 of the second bit line structure 120b. In another tangential direction (such as Figure 3On the shown tangent line D-D'), at least one first bit line structure 120a is located between the adjacent second plug 150b and the first plug 150a, and the bit line plug 121 of at least one first bit line structure 120a is also disposed between two adjacent word line structures 170 and contacts the capping layers 178 of the two word line structures 170. A first spacer structure 140a is further disposed between at least one first bit line structure 120a and the first plug 150a and the second plug 150b to isolate them from each other. It should be noted that in the extending direction D3, the first spacer 146a of the first spacer structure 140a also covers one side sidewall and the top surface t1 of at least one first bit line structure 120a, and the first spacer 146c of the third spacer structure 140c covers the other side sidewall of at least one first bit line structure 120a, and the plug spacer 156 is disposed on the first spacer 146a of the first spacer structure 140a and the first spacer 146c of the third spacer structure 140c, and partially located between the first spacer 146a of the first spacer structure 140a and the third spacer 148a. That is to say, in this extending direction D3, the first spacer 146a of the first spacer structure 140a can be continuously provided with the first spacer 146c of the third spacer structure 140c, so that the top surface of the plug spacer 156 disposed on the first spacer 146a of the first spacer structure 140a or disposed on the first spacer 146c of the third spacer structure 140c can also be flush with the top surface of the first spacer structure 140a or the top surface of the third spacer structure 140c, as Figure 3 shown (tangent line D-D').

[0109] According to the semiconductor device 10 of the first embodiment of the present invention, a first spacer structure 140a that also covers its top surface t1 is provided on the sidewalls of at least one first bit line structure 120a adjacent to the cell region 100b. Thereby, the first spacer 146a of the first spacer structure 140a covers the entire sidewalls and the top surface t1 of at least one first bit line structure 120a, and / or the second spacer 142a of the first spacer structure 140a covers and contacts the entire sidewalls and the top surface t1 of at least one first bit line structure 120a, so that the pad 160b provided above at least one first bit line structure 120a does not contact it. That is to say, the semiconductor device 10 effectively isolates at least one first bit line structure 120a from its adjacent components by means of the first spacer structure 140a, reducing the chance of short circuit caused by structural defects in at least one first bit line structure 120a provided in a specific area, so that the semiconductor device 10 can have a more optimized structure and performance. Thus, the semiconductor device 10 of this embodiment and the capacitor structure (not shown) subsequently provided in the cell region 100b can jointly form a dynamic random access memory (DRAM) device, and the transistor components (not shown) provided in the substrate 100 and the capacitor jointly constitute the smallest memory cell in the dynamic random access memory array to receive voltage information from the bit line structure 120 and the word line structure 170.

[0110] In order to enable those of ordinary skill in the art to which the present invention pertains to easily understand the semiconductor device 10 of the present invention, the manufacturing method of the semiconductor device 10 of the present invention will be further described below.

[0111] Please refer to Figures 4 to 11 shown, which is a schematic diagram of the manufacturing method of the semiconductor device in a preferred embodiment of the present invention. First, as Figure 4 and Figure 5As shown, a substrate 100 is provided, and shallow trench isolation 102 is formed in the peripheral region 100a and the cell region 100b of the substrate 100, and an active region 104 is defined in the substrate 100. In one embodiment, the formation of the shallow trench isolation 102 is, for example, to first form at least one trench (not shown) in the substrate 100 by etching, and then fill the at least one trench with an insulating material (such as including silicon oxide or silicon oxynitride, etc.), but not limited thereto. Then, a gate structure 220 (including a semiconductor layer 122, a barrier layer 124, a metal layer 126, and a capping layer 128 stacked in sequence) and a bit line stack layer structure GS (including a semiconductor layer 122, a barrier layer 124, a metal layer 126, and a capping layer 128 stacked in sequence) are formed on the peripheral region 100a and the cell region 100b of the substrate 100 by a similar process. Specifically, before forming the gate structure 220 and the bit line stack layer structure GS, a silicon oxide layer 112 is first formed in the peripheral region 100a of the substrate 100, and a dielectric layer 110 (including a silicon oxide layer 112, a silicon nitride layer 114, and a silicon oxide layer 116 formed in sequence) is formed in the cell region 100b. In one embodiment, the manufacturing methods of the silicon oxide layer 112 in the peripheral region 100a and the dielectric layer 110 in the cell region 100b include but are not limited to the following steps. For example, a first oxide material layer (not shown), a nitride material layer (not shown), and a second oxide material layer (not shown) that entirely cover the peripheral region 100a and the cell region 100b are first formed on the substrate 100, and then the second oxide material layer and the nitride material layer covering the peripheral region 100a are removed, so that the remaining first oxide material layer forms the silicon oxide layer 112. Or, in another embodiment, it is also possible to choose to completely remove the second oxide material layer, the nitride material layer, and the first oxide material layer covering the peripheral region 100a, and then re-form the silicon oxide layer 112 in the peripheral region 100a.

[0112] Then, a patterning process is performed by means of a mask layer (not shown), and the second oxide material layer, the nitride material layer, and the first oxide material layer in the cell region 100b are partially removed to form a plurality of openings (not shown) that can partially expose the substrate 100, so as to define as Figure 1 and Figure 2The formation position of the bit line plug 121 shown is then used to completely remove the mask layer. Subsequently, a semiconductor material layer (not shown, such as doped polysilicon, doped amorphous silicon, etc.), a barrier material layer (not shown, such as a conductive barrier material including titanium and / or titanium nitride, tantalum and / or tantalum oxide, etc.), a metal material layer (not shown, such as a low-resistance metal material including tungsten, aluminum, or copper, etc.), and a capping material layer (not shown, such as an insulating material including silicon nitride, silicon carbonitride, or silicon oxynitride, etc.) are synchronously formed on the peripheral region 100a and the cell region 100b in sequence from bottom to top. Part of the semiconductor material layer fills the opening. Another patterning process is performed using another mask layer (not shown), and part of the capping material layer, the metal material layer, the semiconductor material layer, the barrier material layer, and the first oxide material layer formed in the peripheral region 100a are removed to form a gate structure 220 and a silicon oxide layer 112 in the peripheral region 100a. And synchronously, part of the capping material layer, the metal material layer, the semiconductor material layer, the barrier material layer, and the dielectric layer 110 formed in the cell region 100b are removed to form a bit line stack layer structure GS and a dielectric layer 110 in the cell region 100b, as Figure 4 and Figure 5 shown. Among them, the semiconductor material layer filling the opening forms the bit line plug 121. Then, the another mask layer is completely removed.

[0113] Again, as Figure 5 shown, a deposition and etch-back process is synchronously performed in the peripheral region 100a and the cell region 100b to form gate spacer walls 130 on the sidewalls of the gate structure 220 and the bit line stack layer structure GS. Then, a deposition process is performed to form a stop etch material layer (not shown, such as an insulating material including silicon nitride, silicon carbonitride, etc.) and an insulating material layer (not shown, such as an insulating material including silicon oxide, silicon oxynitride, etc.) that integrally cover the gate structure 220 and the bit line stack layer structure GS in the peripheral region 100a and the cell region 100b. Then, a planarization process is performed using the top surface of the bit line stack layer structure GS as a stop layer, and part of the stop etch material layer and the insulating material layer are removed to form an etch stop layer 132 and an insulating layer 134 that integrally cover the gate structure 220 and the gate spacer walls 130 and cover the sidewalls of the bit line stack layer structure GS. Then, a capping material layer 238 that integrally covers the insulating layer 134 and the bit line stack layer structure GS is formed in the peripheral region 100a and the cell region 100b, such as an insulating material including silicon nitride, silicon carbonitride, or silicon oxynitride, etc., but not limited thereto.

[0114] As Figure 6 and Figure 7As shown, by means of a patterning process implemented with the coverage of a further mask layer (not shown), the capping material layer 238 within the cell region 100b and the bit line stack layer structure GS thereunder are patterned into bit line structures 120, such that each bit line structure 120 details include a semiconductor layer 122, a barrier layer 124, a metal layer 126, a capping layer 128, and a capping layer 138 stacked in sequence in the vertical direction Y. The bit line structures 120 include a plurality of second bit line structures 120b, at least one first bit line structure 120a and at least one third bit line structure 120c adjacent to the peripheral region 100a. Among them, the capping layer 138 of at least one third bit line structure 120c also partially extends onto the insulating layer 134 on one side thereof, but is not limited thereto. Then, after removing the further mask layer, at least one deposition and etch-back process is performed to simultaneously form a second spacer 142a (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.) covering and contacting the entire sidewall and the top surface t1 on at least one first bit line structure 120a, and a spacer 144a (e.g., made of materials such as silicon oxide, silicon oxynitride, etc.) located on the second spacer 142a; form a second spacer 142b (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.) covering and contacting the entire sidewall on each second bit line structure 120b, and a spacer 144b (e.g., made of materials such as silicon oxide, silicon oxynitride, etc.) located on the second spacer 142b; and sequentially form a second spacer 142c (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.) covering and contacting the entire sidewall and the top surface t3 on at least one third bit line structure 120c, and a spacer 144c (e.g., made of materials such as silicon oxide, silicon oxynitride, etc.) located on the second spacer 142c. Moreover, the second spacer 142c is also simultaneously formed within the peripheral region 100a, entirely covering the capping layer 138 and the gate structure 220. Then, a deposition and planarization process is performed within the cell region 100b to sequentially form a spacer material layer 246 (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.) and a sacrificial layer 250 (e.g., made of materials such as silicon oxide, silicon oxynitride, etc.) conformally covering the bit line structures 120 and the spacers 144a, 144b, 144c. The spacer material layer 246 is also formed within the peripheral region 100a and entirely covers the second spacer 142c. Among them, the sacrificial layer 250 fills the space between each bit line structure 120.

[0115] As Figure 8As shown, a mask layer HM and a photoresist layer PR are sequentially formed on the sacrificial layer 250. Among them, the mask layer HM includes materials such as silicon oxide, etc., and integrally covers the peripheral region 100a and the cell region 100b. The photoresist layer PR covers the peripheral region 100a and at least one first bit line structure 120a and at least one third bit line structure 120c located in the cell region 100b. That is to say, the photoresist layer PR covers the sacrificial layer 250 formed on one side of at least one first bit line structure 120a, and exposes the sacrificial layer 250 formed on the other side of at least one first bit line structure 120a and the spacer material layer 246 formed on the top surface t2 of the second bit line structure 120b.

[0116] As Figure 9 shown, through Figure 8 the mask layer HM and the photoresist layer PR shown, an etching process is performed to remove the mask layer HM, the sacrificial layer 250, and the spacer material layer 246 exposed from the photoresist layer PR. A first spacer 146b (including materials such as silicon nitride, silicon carbonitride, etc.) located on the spacer 144b is formed on the spacer 144b of each second bit line structure 120b. And, an opening (not shown) exposing the top surface 100t of the substrate 100 is formed between each second bit line structure 120b and between at least one first bit line structure 120a and an adjacent second bit line structure 120b. On the other hand, the spacer material layer 246 covered under the photoresist layer PR still continuously covers the side walls and the top surfaces t1, t3 of at least one first bit line structure 120a and at least one third bit line structure 120c. The sacrificial layer 250 covered under the photoresist layer PR still remains between at least one first bit line structure 120a and at least one third bit line structure 120c, and forms a first plug 150a as the dummy plug. Then, after completely removing the mask layer HM and the photoresist layer PR, another etching process is performed by means of the first spacer 146b and the spacer material layer 246 to partially etch the substrate 100 (including the active region 104 and the shallow trench isolation 102) downward from the opening, forming a plurality of plug holes OP1.

[0117] As Figure 10 shown, a deposition and etch-back process is performed to fill semiconductor materials such as doped polysilicon, doped amorphous silicon, etc. or low-resistance metal materials such as tungsten, aluminum, or copper into each plug hole OP1, forming a second plug 150b. Among them, the formed second plug 150b partially extends into the substrate 100 and has a bottom surface lower than the top surface 100t of the substrate 100. And, the top surface of the second plug 150b is lower than the top surface of the first plug 150a or the top surface t2 of each second bit line structure 120b. Thus, the first plug 150a and the second plug 150b together form as Figure 1 and Figure 2The plug structure 150 of the semiconductor device 10 shown. Next, the deposition and etch-back processes are performed again to form a third spacer 148b and a third spacer 148a (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.) on the upper half sidewalls of the plug hole OP1, located on each second plug 150b. It should be noted that since the first plug 150a and the second plug 150b are formed on the two opposite sides of at least one first bit line structure 120a respectively, the third spacer 148a can only be formed on the side where the second plug 150b is located and is located on the spacer material layer 246. Thus, the third spacer 148a has a relatively large extension height h1 in the vertical direction Y, while the third spacer 148b is formed on the first spacer 146b and has a relatively small extension height h3, but this is not limiting. Then, a metal silicidation process is performed to form a metal silicide layer 154 on each second plug 150b.

[0118] As Figure 11 shown, a deposition process is synchronously performed in the peripheral region 100a and the cell region 100b to form a conductive material layer (not shown, e.g., made of low-resistance metal materials such as tungsten, aluminum, or copper) on the substrate 100. Then, a plurality of openings OP2 are formed in the conductive material layer through a mask layer (not shown), and then the mask layer is removed. It should be noted that when forming the openings OP2, the spacer material layer 246 formed on at least one first bit line structure 120a is partially etched by adjusting the etching conditions (such as the etching selectivity ratio, etc.). Finally, a first spacer 146a (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.) covering the sidewall and the top surface t1 of at least one first bit line structure 120a on the said side, and a first spacer 146c (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.) covering the sidewall and the top surface t3 of the whole sidewall of at least one third bit line structure 120c and the sidewall and the top surface of at least one first bit line structure 120a on the other side are formed. Among them, the first spacer 146c is also partially formed in the peripheral region 100a and entirely covers the second spacer 142c. Thus, the second spacer 142a, the spacer 144a, the first spacer 146a, and the third spacer 148a sequentially formed on at least one first bit line structure 120a together form the first spacer structure 140a of the semiconductor device 10, and the second spacer 142c, the spacer 144c, and the first spacer 146c sequentially formed on at least one third bit line structure 120c together form the third spacer structure 140c of the semiconductor device 10.

[0119] Moreover, when forming the opening OP2, the third spacer 148b formed on the sidewall of each second bit line structure 120b is partially etched together, such that it has a height h3 which is less than the height h2 in the vertical direction Y. Thus, the third spacers 148a formed on the two opposite sidewalls of each second bit line structure 120b have different heights h2 and h3 in the vertical direction Y, and both are less than the height h1. Thus, the second spacer 142b, the spacer 144b, the first spacer 146b, and the third spacer 148b formed on each second bit line structure 120b in sequence together form the second spacer structure 140b of the semiconductor device 10. On the other hand, the formation of the opening OP2 truncates the conductive material layer into a plurality of pads 160, including the pad 160a and the pad 160b respectively disposed on the first plug 150a and the second plug 150b. Among them, the pad 160a is formed above the first plug 150a and at least one third bit line structure 120c, and contacts the first plug 150a and the first spacer 146c formed above at least one third bit line structure 120c. The pad 160b is formed above the second plug 150b and at least one first bit line structure 120a, or above the second plug 150b and at least one second bit line structure 120b. Among them, the pad 160b formed above the second plug 150b and at least one first bit line structure 120a simultaneously contacts the metal silicide layer 154 formed on the second plug 150b and the first spacer 146a formed above at least one first bit line structure 120a, and the pad 160b formed above the second plug 150b and the second bit line structure 120b contacts the metal silicide layer 154 formed on the second plug 150b and the top surface t2 of the second bit line structure 120b.

[0120] In addition, in one embodiment, before forming the conductive material layer, a plug hole (not shown) may also be selectively formed on one side of the gate structure 220 in the peripheral region 100a through the mask layer, such that the plug hole penetrates through the insulating layer 134, the capping layer 138, the etch stop layer 132, and the silicon oxide layer 112 simultaneously, exposing the doped region 106 in the substrate 100 on one side of the gate structure 220. Then, when forming the pad 160, a plug 260 (such as a low-resistance metal material including tungsten, aluminum, or copper, etc.) electrically connected to the doped region 106 is formed together, but not limited thereto. Alternatively, in other embodiments, the deposition and patterning processes may also be selectively performed before or after forming the pad 160 to form the plug 260. Subsequently, the deposition and etch-back processes are performed again on the substrate 100, and then an insulating spacer 162 as shown in Figure 1 and Figure 2 is formed in the opening OP2. Thus, the fabrication of the semiconductor device 10 in the preferred embodiment of the present invention is completed.

[0121] Those skilled in the art should easily understand that the manufacturing method of the semiconductor device 10 of this embodiment may further include forming a plurality of word line structures 170 and a plurality of plug spacings 156 in the unit region 100b. The word line structures 170 are buried in the substrate 100, extend in the second direction D2 separately from each other, and pass through the corresponding active regions 104 and shallow trench isolations 102, while the plug spacings 156 are disposed above each word line structure 170. Thus, the semiconductor device 10 and a capacitor structure (not shown) formed subsequently above it can jointly form a dynamic random access memory device, and the transistor assembly in the substrate 100 and the capacitor jointly form the smallest storage unit in the dynamic random access memory array to receive voltage information from the bit line structure 120 and the word line structure 170.

[0122] According to the manufacturing method of the semiconductor device 10 of a preferred embodiment of the present invention, a first spacer structure 140a covering the top surface t1 thereof is formed on the sidewall of at least one first bit line structure 120a adjacent to the unit region 100b. In this operation, when forming the opening OP2 of the insulating spacer 162 in the unit region 100b, the spacer material layer 246 in the peripheral region 100a is etched synchronously, and the first spacers 146a, 146c of the first spacer structure 140a and the third spacer structure 140c are formed, without the need for additional steps. And by forming the first spacer 146a of the first spacer structure 140a to cover the entire sidewall and the top surface t1 of at least one first bit line structure 120a, the pad 160b formed above does not contact at least one first bit line structure 120a. In this way, at least one first bit line structure 120a can be effectively isolated from its adjacent components, reducing the chance of short circuit caused by structural defects of at least one first bit line structure 120a disposed in a specific region, so that the formed semiconductor device 10 has a more optimized structure and performance.

[0123] Those of ordinary skill in the art to which the present invention pertains should easily understand that, in order to meet the requirements of actual products, the semiconductor device of the present invention may have other aspects and is not limited to the foregoing. Other embodiments or variations of the semiconductor device of the present invention will be further described below. And for simplicity of description, the following description mainly details the differences of each embodiment, and the same parts will not be repeated. In addition, the same components in each embodiment of the present invention are labeled with the same reference numerals for easy comparison between embodiments.

[0124] Please refer to Figure 12As shown, it is a schematic diagram of a semiconductor device 30 according to a second embodiment of the present invention. The semiconductor device 30 of this embodiment is generally the same as the semiconductor device 10 in the foregoing embodiment. The main difference is that in the semiconductor device 30 of this embodiment, the spacer structure 340 further includes spacers 350 additionally disposed on the lower sidewalls of at least one first bit line structure 120a, each second bit line structure 120b, and at least one third bit line structure 120c, and the sidewalls of each bit line plug 121, while the first spacer structure 340a, the second spacer structure 340b, and the third spacer structure 340c are respectively disposed on the upper sidewalls of at least one first bit line structure 120a, each second bit line structure 120b, and at least one third bit line structure 120c, and are located above the spacers 350. In one embodiment, the spacers 350 include, for example, materials such as silicon oxide, silicon nitride, silicon carbonitride, or silicon oxynitride, preferably including materials different from the first spacer structure 340a, the second spacer structure 340b, and the third spacer structure 340c, but not limited thereto.

[0125] Specifically, the first spacer structure 340a includes, for example, a second spacer 342a (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.), a spacer 344a (e.g., made of materials such as silicon oxide, silicon oxynitride, etc.), a first spacer 346a (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.), and a third spacer 348a (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.), which are sequentially disposed on the upper half sidewalls of at least one first bit line structure 120a. Among them, the second spacer 342a covers and contacts the upper half sidewalls and the top surface t1 of at least one first bit line structure 120a, while the first spacer 346a covers the upper half sidewalls and the top surface t1 on one side of at least one first bit line structure 120a and can partially contact the second spacer 342a disposed below. The second spacer structure 340b includes, for example, a second spacer 342b (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.), a spacer 344b (e.g., made of materials such as silicon oxide, silicon oxynitride, etc.), a first spacer 346b (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.), and a third spacer 348b (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.), which are sequentially disposed on the upper half sidewalls of each second bit line structure 120b. The third spacer structure 340c includes a second spacer 342c (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.), a spacer 344c (e.g., made of materials such as silicon oxide, silicon oxynitride, etc.), and a first spacer 346c (e.g., made of materials such as silicon nitride, silicon carbonitride, etc.), which are sequentially disposed on the upper half sidewalls of at least one third bit line structure 120c. The first spacer 346c and the second spacer 342c of the third spacer structure 340c also extend into the peripheral region 100a and sequentially cover the cover layer 138 and the gate structure 220. Among them, the second spacer 342c covers and contacts the upper half sidewalls and the top surface t3 of at least one third bit line structure 120c, while the first spacer 346c covers the upper half sidewalls and the top surface t3 of at least one third bit line structure 120c and can partially contact the second spacer 342c disposed below, as Figure 12 shown, but not limited thereto.

[0126] In this setting, the first spacer structure 340a of this embodiment still partially covers and contacts the top surface t1 of at least one first bit line structure 120a and does not contact the pad 160b disposed above it. Thus, by disposing the first spacer structure 340a on the upper half sidewalls of at least one first bit line structure 120a, at least one first bit line structure 120a located adjacent to the peripheral region 100a can still be effectively isolated from adjacent components (such as the pad 160b disposed above), optimizing the component structure in the cell region 100b, thereby improving the structural reliability and performance of the semiconductor device 30.

[0127] Please refer to Figure 13As shown, it is a schematic diagram of a semiconductor device 50 according to the third embodiment of the present invention. The semiconductor device 50 of this embodiment is generally the same as the semiconductor device 10 in the foregoing embodiment. The main difference is that in the semiconductor device 50 of this embodiment, the spacer structure 540 includes a first spacer structure 540a, a second spacer structure 540b, and a third spacer structure 540c respectively disposed on the sidewalls of at least one first bit line structure 120a, each second bit line structure 120b, and at least one third bit line structure 120c. The first spacer structure 540a also partially covers the top surface t1 of at least one first bit line structure 120a, so that the pad 160b disposed above the at least one first bit line structure 120a can partially contact the covering layer 138 of the at least one first bit line structure 120a.

[0128] Specifically, the first spacer structure 540a of this embodiment, for example, includes a second spacer 542a (for example, including materials such as silicon nitride and silicon carbonitride) disposed on two opposite sidewalls and a partial top surface t1 of at least one first bit line structure 120a, a spacer 544a (for example, including materials such as silicon oxide and silicon oxynitride) disposed on the two opposite sidewalls, a first spacer 546a (for example, including materials such as silicon nitride and silicon carbonitride) disposed on a single sidewall and the partial top surface t1 of at least one first bit line structure 120a, and a third spacer 548a (for example, including materials such as silicon nitride and silicon carbonitride) disposed on the first spacer 546a. Among them, the second spacer 542a covers and contacts the two opposite sidewalls and the partial top surface t1 of at least one first bit line structure 120a, and partially contacts the first spacer 546a located above it. Moreover, the third spacer 548a is also partially located on the second spacer 542a and the first spacer 546a disposed on the top surface t1. In addition, in this embodiment, the second spacer 542a, the spacer 544a, and the first spacer 546a disposed on the side closer to the second plug 150b respectively have top surfaces lower than the top surface t1 of at least one first bit line structure 120a. Thus, the third spacer 548a is partially disposed on the adjacent second plug 150b, and partially disposed on the top surfaces and sidewalls of the second spacer 542a and the first spacer 546a on the side adjacent to the second plug 150b, and on the second spacer 542a and the first spacer 546a disposed on the top surface t1, presenting a discontinuous film layer as Figure 13 shown.

[0129] The second spacer structure 540b of this embodiment, for example, includes second spacers 542b (for example, made of materials such as silicon nitride, silicon carbonitride, etc.), spacers 544b (for example, made of materials such as silicon oxide, silicon oxynitride, etc.), first spacers 546b (for example, made of materials such as silicon nitride, silicon carbonitride, etc.), and third spacers 548b (for example, made of materials such as silicon nitride, silicon carbonitride, etc.) that are sequentially disposed on two opposite sidewalls of each second bit line structure 120b. Since the second spacers 542b, the first spacers 546b, and the third spacers 548b of the second spacer structure 540b also have top surfaces lower than the top surface t2 of the second bit line structure 120b, the third spacers 548b are partially disposed on the adjacent second plug 150b, and partially disposed on the top surfaces and sidewalls of the second spacers 542b and the first spacers 546b on one side adjacent to the second plug 150b, thus presenting a discontinuous film layer as shown in Figure 13 The third spacer structure 540c of this embodiment includes second spacers 542c (for example, made of materials such as silicon nitride, silicon carbonitride, etc.) that are simultaneously disposed on a single sidewall and the top surface t3 of at least one third bit line structure 120c, spacers 544c (for example, made of materials such as silicon oxide, silicon oxynitride, etc.) disposed on the single sidewall, and first spacers 546c (for example, made of materials such as silicon nitride, silicon carbonitride, etc.) that continuously cover the single sidewall and the top surface t3 of at least one third bit line structure 120c, the surface of the substrate 100 between at least one third bit line structure 120c and at least one first bit line structure 120a, and the other sidewall of at least one first bit line structure 120a. Among them, the second spacers 542c cover and contact the single sidewall and the top surface t3 of at least one third bit line structure 120c, and partially contact the first spacers 546c located above it. In addition, the first spacers 546c and the second spacers 52c of the third spacer structure 540c of this embodiment are also simultaneously disposed in the peripheral region 100a, sequentially covering the covering layer 138 and also integrally covering the gate structure 220.

[0130] Under this setting, the first spacer structure 540a of this embodiment still partially covers and contacts the top surface t1 of at least one first bit line structure 120a, such that the pad 160b disposed above only partially contacts the top surface t1 of at least one first bit line structure 120a, and the contact surface between the pad 160b and at least one first bit line structure 120a is lower than the topmost surface of the first spacer structure 540a. Thereby, by disposing the first spacer structure 540a on the sidewall of at least one first bit line structure 120a, it is still possible to effectively isolate at least one first bit line structure 120a adjacent to the peripheral region 100a from adjacent components (such as the pad 160b disposed above), optimize the component structure within the unit region 100b, and thus improve the structural reliability and performance of the semiconductor device 50.

[0131] Generally speaking, according to the semiconductor device and its manufacturing method of the present invention, different spacer structures are formed on the sidewalls of the bit line structure in the vicinity of the peripheral region without performing additional steps, thereby effectively isolating the bit line structure and its surrounding components and maintaining the structural integrity of the components in the cell region. Thus, the semiconductor device of the present invention can have a more optimized component structure and performance, thereby improving the overall operation performance.

[0132] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate; A plurality of bit line structures and a plurality of plug structures, alternately arranged on the substrate, wherein the bit line structure includes at least one first bit line structure and at least one second bit line structure; A spacer structure, arranged between each of the bit line structures and each of the plug structures, the spacer structure further includes a first spacer structure arranged on the side wall of the at least one first bit line structure and a second spacer structure arranged on the side wall of the at least one second bit line structure; and A plurality of pads, arranged on the bit line structures and the plug structures; Wherein, the first spacer structure also partially covers and contacts the top surface of the at least one first bit line structure, and one of the pads covers and contacts the top surface of the at least one second bit line structure.

2. The semiconductor device according to claim 1, wherein The first spacer structure and the second spacer structure respectively include a first spacer of the same material, and the first spacer of the first spacer structure covers the top surface of the at least one first bit line structure.

3. The semiconductor device according to claim 2, wherein The first spacer structure and the second spacer structure also respectively include a second spacer of the same material, the second spacer of the first spacer structure contacts the side wall and the top surface of the at least one first bit line structure, and the second spacer of the second spacer structure contacts the side wall of the at least one second bit line structure.

4. The semiconductor device according to claim 3, wherein The first spacer of the first spacer structure partially covers and contacts the second spacer of the first spacer structure, and the one pad covers and contacts the top surface of the second spacer of the second spacer structure.

5. The semiconductor device according to claim 3, characterized in that, The plug structure further includes a first plug arranged on one side of the at least one first bit line structure and a second plug arranged on one side of the at least one second bit line structure, the bottom surface of the first plug is higher than the substrate and the top surface is higher than the at least one first bit line structure, and the bottom surface of the second plug is lower than the substrate and the top surface is lower than the at least one second bit line structure.

6. The semiconductor device according to claim 5, wherein The first spacer structure and the second spacer structure respectively include a third spacer of the same material, the third spacer of the second spacer structure contacts the top surface of the second plug and the side surface of the one pad, and the third spacer of the first spacer structure is higher than the third spacer of the second spacer structure.

7. The semiconductor device according to claim 6, wherein Further comprising: A plurality of insulating spacings, arranged on the spacer structure, wherein the insulating spacings contact the third spacer of the second spacer structure and do not contact the third spacer of the first spacer structure.

8. The semiconductor device according to claim 6, wherein, The third spacer of the first spacer structure is only arranged on the side wall of the single side of the at least one first bit line structure.

9. The semiconductor device according to claim 6, wherein The third spacer of the second spacer structure is simultaneously arranged on the side walls of the two opposite sides of the at least one second bit line structure and has different heights in the vertical direction respectively.

10. The semiconductor device according to claim 1, wherein The bit line structure includes a semiconductor layer, a metal layer and a covering layer arranged in sequence, the first spacer structure covers and contacts the covering layer of the at least one first bit line structure, and at least one of the pads covers and contacts the covering layer of the at least one second bit line structure.

11. The semiconductor device according to claim 10, wherein One of the pad portions contacts the covering layer of the at least one first bit line structure, and the contact surface of the one pad and the covering layer is lower than the topmost surface of the first spacer wall structure.

12. The semiconductor device according to claim 9, wherein The third spacer wall of the first spacer wall structure also covers and contacts the sidewalls of the first spacer wall and the second spacer wall of the first spacer wall structure.

13. A semiconductor device, characterized in that, Comprising: A substrate; A first bit line structure disposed on the substrate; A first spacer wall structure disposed on two opposite sidewalls of the first bit line structure, the first spacer wall structure at least partially covering the top surface of the first bit line structure; A first plug disposed on one side of the first bit line structure, the bottom surface of the first plug being higher than the substrate and the top surface being higher than the first bit line structure; And A second plug disposed on the other side of the first bit line structure, the bottom surface of the second plug being lower than the substrate and the top surface being lower than the first bit line structure; The first spacer wall structure further includes a spacer wall disposed on the top surface of the second plug and covering the sidewall of the first spacer wall.

14. The semiconductor device according to claim 13, wherein, Further included is a pad disposed on the first bit line structure and the second plug, and the spacer wall contacts the sidewall of the pad.

15. The semiconductor device according to claim 13, characterized in that, Further included is an insulating spacer disposed on the first plug.

16. The semiconductor device according to claim 14, wherein The pad also partially contacts the top surface of the first bit line structure.

17. A method for manufacturing a semiconductor device, characterized in that, Comprising: Providing a substrate; Forming a plurality of bit line structures on the substrate, wherein the bit line structures include at least one first bit line structure and at least one second bit line structure; Sequentially forming a spacer wall material layer on the substrate to cover the at least one first bit line structure and the at least one second bit line structure; Forming a sacrificial layer between the bit line structures; Performing an etching process through a mask layer to remove the spacer wall material layer formed on the top surface of the at least one second bit line structure and a part of the sacrificial layer, and retaining the spacer wall material layer formed on the top surface of the at least one first bit line structure; Forming a plurality of plug structures on the substrate; and Forming a plurality of pads on the bit line structures and the plug structures, and at least one of the pads covers and contacts the top surface of the at least one second bit line structure.

18. The manufacturing method of the semiconductor device according to claim 17, characterized in that, After removing the mask layer, a first spacer wall is respectively formed on the sidewalls of the at least one first bit line structure and the at least one second bit line structure, wherein the first spacer wall formed on the at least one first bit line structure continuously covers the top surface and the sidewalls of the at least one first bit line structure.

19. The method for manufacturing a semiconductor device according to claim 18, wherein, Before forming the spacer wall material layer, further comprising: Performing a deposition process and a re-etching process to respectively form a second spacer wall on the at least one first bit line structure and the at least one second bit line structure, the second spacer wall of the first bit line structure contacting the sidewall and the top surface of the at least one first bit line structure, and the second spacer wall of the second bit line structure contacting the sidewall of the at least one second bit line structure.

20. The method for manufacturing a semiconductor device according to claim 18, wherein, After forming the plug structures, further comprising: Another deposition process and a re-etching process are performed to form third spacer walls on the at least one first bit line structure and the at least one second bit line structure, respectively, wherein the third spacer wall of the second bit line structure contacts the side surface of the at least one pad, the third spacer wall of the first bit line structure contacts the first spacer wall of the first bit line, and the height of the third spacer wall of the first bit line structure in the vertical direction is higher than the height of the third spacer wall of the second bit line structure in the vertical direction.

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