Electrified erasable programmable read-only memory and preparation method thereof

Abstract

The invention provides a charged erasable programmable read-only memory and a preparation method thereof, and the method comprises the steps: obtaining a first semiconductor substrate which comprises a suspension gate covered with a dielectric layer; performing a lithography operation by placing a target photomask on the first semiconductor substrate, resulting in a second semiconductor substrate comprising a barrier layer formed over the floating gate by the lithography operation; ion implantation is carried out on the second semiconductor substrate to form a double-diffusion drain region, a third semiconductor substrate is obtained, and the double-diffusion drain region is limited by the barrier layer in the ion implantation process; forming a control gate in an area corresponding to the suspension gate on the third semiconductor substrate from which the barrier layer is removed to obtain a fourth semiconductor substrate; and respectively performing ion implantation on the fourth semiconductor substrate to form a drain electrode and a source electrode so as to prepare an electrified erasable programmable read-only memory unit, and constructing the electrified erasable programmable read-only memory through the electrified erasable programmable read-only memory unit.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technologies, and particularly to an electrically erasable programmable read-only memory and a manufacturing method thereof. Background Art

[0002] As the sizes of the constituent units of an electrically erasable programmable read-only memory cell (EEPROM Cell) are gradually reduced, and in order to meet the working conditions of the erasing operation, writing operation, and reading operation of the EEPROM Cell, it is required that the select gate (SG) has a high breakdown voltage. Therefore, the select gate device is basically a short-channel MOS device, but it is prone to the short-channel effect (SCE). In some process designs, in order to improve the hot carrier injection effect (HCI), the double-diffused drain technology (DDD) is selected, that is, two different-quality doping ions are selected to be implanted into the substrate to form the source / drain active regions, so that a graded junction rather than a abrupt junction is formed between the source / drain active regions and the substrate. After thermal annealing treatment, a lightly doped region with a certain width is also formed between the drain and the channel, which can effectively reduce the peak electric field near the drain, weaken the HCI effect, and increase the source / drain breakdown voltage. However, this will further enhance the influence of the short-channel effect.

[0003] In the actual process adjustment direction, there is a high demand for the breakdown voltage of the EEPROM. The conditions of the double-diffused drain ion implantation may be adjusted, for example, the breakdown voltage can be increased within a certain range by increasing the ion implantation dose or the energy during ion implantation. However, when exceeding a certain limit, the influence of the short-channel effect will be aggravated, resulting in a decrease in the breakdown voltage, and this limit is different for devices with different channel lengths. When the high-voltage devices in the peripheral circuit reach the target requirements of their corresponding breakdown voltages, the select gate device has been affected by the short-channel effect, and the breakdown voltage corresponding to the select gate device has decreased, resulting in the inability of the peripheral circuit and the select gate device to reach their respective corresponding breakdown voltages in coordination, affecting the normal operation of the EEPROM device. When the EEPROM device is operating, the breakdown voltage of the select gate is lower than the port voltage of the bit line (BL) during the writing operation, which is prone to leakage. It is actually necessary to reduce the port voltage during the completion of the writing operation, but this will affect the writing operation efficiency and the normal operation of the device. Summary of the Invention

[0004] In view of this, the purpose of the present application is to provide at least one electrically erasable programmable read-only memory and its manufacturing method. During the process of manufacturing the electrically erasable programmable read-only memory, a target mask with a blocking pattern is set to perform a lithography operation on the first semiconductor substrate, thereby depositing a blocking layer on the floating gate covered with a dielectric layer on the first semiconductor substrate to obtain a second semiconductor substrate. Under the limitation of the blocking layer, ion implantation is performed on the second semiconductor substrate to form a double-diffused drain region to obtain a third semiconductor substrate. After removing the blocking layer, a control gate is formed in the region corresponding to the floating gate of the third semiconductor substrate to obtain a fourth semiconductor substrate. Then, a gate and a source are formed on the fourth semiconductor substrate to manufacture an electrically erasable programmable read-only memory cell, and on the basis of manufacturing the electrically erasable programmable read-only memory cell, an electrically erasable programmable read-only memory is manufactured, solving the technical problem of the influence of the double-diffused drain region on the short-channel effect in the prior art and achieving the technical effect of reducing the short-channel effect.

[0005] The present application mainly includes the following aspects: In a first aspect, an embodiment of the present application provides a manufacturing method for an electrically erasable programmable read-only memory. The method includes: obtaining a first semiconductor substrate, where the first semiconductor includes a floating gate covered with a dielectric layer; performing a lithography operation by placing a target mask on the first semiconductor substrate to obtain a second semiconductor substrate. The target mask includes a blocking pattern, and there is an overlapping region between a preset region where the floating gate projects onto the target mask and the blocking pattern. The second semiconductor substrate includes a blocking layer formed above the floating gate through the lithography operation; performing ion implantation on the second semiconductor substrate to form a double-diffused drain region to obtain a third semiconductor substrate, and the double-diffused drain region is limited by the blocking layer during the ion implantation process; forming a control gate in the region corresponding to the floating gate on the third semiconductor substrate after removing the blocking layer to obtain a fourth semiconductor substrate; performing ion implantation on the fourth semiconductor substrate respectively to form a drain and a source to manufacture an electrically erasable programmable read-only memory cell, and constructing an electrically erasable programmable read-only memory through the electrically erasable programmable read-only memory cell.

[0006] Optionally, the first semiconductor further includes a select gate covered with a dielectric layer. The double-diffused drain region includes a first double-diffused drain region, a second double-diffused drain region, and a third double-diffused drain region. Among them, the first double-diffused drain region is located between the select gate and the floating gate, the second double-diffused drain region is located on the side of the select gate away from the floating gate, and the third double-diffused drain region is located on the side of the floating gate away from the select gate. Among them, the blocking layer is used to limit the channel width between the first double-diffused drain region and the second double-diffused drain region.

[0007] Optionally, the first semiconductor substrate is obtained by the following steps: ion implantation is performed on an initial silicon substrate to obtain a well region; ion implantation is performed in the well region to adjust the surface doping, and a tunneling oxide layer is formed above the well region; a polysilicon layer is deposited above the tunneling oxide layer to form a select gate and a floating gate on the polysilicon layer, and a channel is formed without contact between the select gate and the floating gate; a dielectric layer is formed above the tunneling oxide layer after the select gate and the floating gate are formed, and the dielectric layer covers the select gate and the floating gate to obtain the first semiconductor substrate.

[0008] Optionally, the method further includes: performing ion implantation on the select gate, wherein the turn-on voltage of the select gate is changed by adjusting the ion implantation conditions of the select gate, and there is a positive correlation between the ion implantation conditions of the select gate and the turn-on voltage, and the ion implantation conditions of the select gate include the energy and dose of ion implantation.

[0009] Optionally, the thickness of the blocking layer has a positive correlation with the degree of limitation for the double-diffused drain region, wherein the thickness of the blocking layer at least limits that the target edge corresponding to the select gate does not belong to the double-diffused drain region, and the target edge refers to the side close to the floating gate obtained by vertically projecting the select gate onto the well region.

[0010] Optionally, the second semiconductor substrate is obtained by the following steps: a photoresist is coated on the first semiconductor substrate, and a semiconductor substrate to be exposed is obtained by baking; the semiconductor substrate to be exposed is sequentially subjected to an exposure process and a development process to obtain a semiconductor substrate to be etched; the semiconductor substrate to be etched is etched to obtain the second semiconductor substrate.

[0011] Optionally, the control gate covers the sidewall and the top surface of the floating gate.

[0012] In a second aspect, an embodiment of the present application further provides a charged erasable programmable read-only memory, and the charged erasable programmable read-only memory is prepared by the preparation method described in any one of the above first aspect or any possible implementation manner in the first aspect.

[0013] Optionally, when the charged erasable programmable read-only memory performs an erase operation, a write operation, or a read operation, an operation voltage corresponding to the operation is applied to the control gate.

[0014] In a third aspect, an embodiment of the present application further provides an electronic device, and the electronic device includes the charged erasable programmable read-only memory described in the above second aspect or any possible implementation manner in the second aspect.

[0015] A charged erasable programmable read-only memory and a manufacturing method thereof provided by an embodiment of the present application. The method includes: obtaining a first semiconductor substrate, where the first semiconductor includes a floating gate covered with a dielectric layer; performing a lithography operation by placing a target mask on the first semiconductor substrate to obtain a second semiconductor substrate. The target mask includes a blocking pattern, and there is an overlapping area between the blocking pattern and a preset area projected by the floating gate onto the target mask. The second semiconductor substrate includes a blocking layer formed above the floating gate through the lithography operation; performing ion implantation on the second semiconductor substrate to form a double-diffused drain region, obtaining a third semiconductor substrate, and the double-diffused drain region is restricted by the blocking layer during the ion implantation process; forming a control gate in an area corresponding to the floating gate on the third semiconductor substrate after removing the blocking layer, obtaining a fourth semiconductor substrate; performing ion implantation on the fourth semiconductor substrate to form a drain and a source respectively to manufacture a charged erasable programmable read-only memory cell, and constructing a charged erasable programmable read-only memory through the charged erasable programmable read-only memory cell. By setting a target mask with a blocking pattern to perform a lithography operation on the first semiconductor substrate during the manufacturing process of the charged erasable programmable read-only memory, a blocking layer is deposited on the floating gate covered with the dielectric layer of the first semiconductor substrate to obtain a second semiconductor substrate. The second semiconductor substrate is subjected to ion implantation under the restriction of the blocking layer to form a double-diffused drain region to obtain a third semiconductor substrate. After removing the blocking layer, a control gate is formed in an area corresponding to the floating gate of the third semiconductor substrate to obtain a fourth semiconductor substrate. Then, a source and a drain are formed on the fourth semiconductor substrate to manufacture a charged erasable programmable read-only memory cell, and a charged erasable programmable read-only memory is manufactured based on the charged erasable programmable read-only memory cell, solving the technical problem of the influence of the double-diffused drain region on the short-channel effect in the prior art and achieving the technical effect of reducing the short-channel effect.

[0016] To make the above objects, features, and advantages of the present application more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can also be obtained based on these drawings without creative efforts.

[0018] Figure 1 The flowchart of a manufacturing method of a charged erasable programmable read-only memory provided by an embodiment of the present application is shown.

[0019] Figure 2 Shows a cross-sectional view of the first semiconductor substrate provided by the embodiments of the present application.

[0020] Figure 3 Shows a top view of the target photomask provided by the embodiments of the present application.

[0021] Figure 4 Shows a schematic structural diagram of the third semiconductor substrate provided by the embodiments of the present application.

[0022] Figure 5 Shows a schematic structural diagram of the fourth semiconductor substrate provided by the embodiments of the present application. Detailed implementation manners

[0023] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It should be understood that the accompanying drawings in the present application are only for the purposes of illustration and description, and are not used to limit the protection scope of the present application. In addition, it should be understood that the schematic drawings are not drawn to actual scale. The flowcharts used in the present application show operations implemented according to some embodiments of the present application. It should be understood that the operations in the flowchart may not be implemented in sequence, and steps without logical context relationships may be reversed or implemented simultaneously. In addition, those skilled in the art may add one or more other operations to the flowchart or remove one or more operations from the flowchart under the guidance of the content of the present application.

[0024] In addition, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application usually described and illustrated in the drawings here may be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts fall within the protection scope of the present application.

[0025] When the EEPROM device is operating, if the breakdown voltage of the select gate is lower than the port voltage of the bit line (BL) during the write operation, it is likely to cause leakage. If the port voltage used to complete the write operation is reduced, it will affect the write operation efficiency and the normal operation of the device. Therefore, during the development of the EEPROM device, it is necessary to ensure that the breakdown voltage of the select gate meets the requirements. In the current manufacturing process of the electrically erasable programmable read-only memory EEPROM, the electrical performance of the select gate mainly comes from well region ion implantation (CW, Cell well), source / drain ion implantation, double-diffused drain (DDD, Double Diffuse Drain) ion implantation, ion implantation of the select gate device, and adjustment of the photomask required before ion implantation. In the commonly used EEPROM manufacturing process, generally, an additional photomask is added or halo ion implantation is used to adjust the performance of the select gate, resulting in an increase in the number of photomasks. However, if the ion implantation conditions of these layers are changed to adjust the performance of the select gate device, it may simultaneously affect the entire EEPROM and the devices sharing the photomask with the external circuit, bringing additional adjustment requirements.

[0026] Based on this, the embodiments of the present application provide an electrically erasable programmable read-only memory and a manufacturing method thereof. During the process of manufacturing the electrically erasable programmable read-only memory, a target photomask with a blocking pattern is set to perform a photolithography operation on the first semiconductor substrate, thereby depositing a blocking layer on the floating gate of the first semiconductor substrate covered with a dielectric layer to obtain a second semiconductor substrate. Under the limitation of the blocking layer, ion implantation is performed on the second semiconductor substrate to form a double-diffused drain region to obtain a third semiconductor substrate. After removing the blocking layer, a control gate is formed in the region corresponding to the floating gate of the third semiconductor substrate to obtain a fourth semiconductor substrate. Then, a gate and a source are formed on the fourth semiconductor substrate to manufacture an electrically erasable programmable read-only memory cell, and based on the manufactured electrically erasable programmable read-only memory cell, an electrically erasable programmable read-only memory is manufactured, solving the technical problem of the influence of the double-diffused drain region on the short-channel effect in the prior art and achieving the technical effect of reducing the short-channel effect, specifically as follows: Please refer to Figure 1 , Figure 1 which is a flowchart of a manufacturing method of an electrically erasable programmable read-only memory provided by the embodiments of the present application. As Figure 1 shown, the manufacturing method of the electrically erasable programmable read-only memory provided by the embodiments of the present application includes the following steps: S101: Obtain a first semiconductor substrate.

[0027] Wherein, the first semiconductor includes a floating gate (FG, floatingl gate) covered with a dielectric layer.

[0028] Among them, the first semiconductor substrate is obtained in the following manner: ion implantation is performed on an initial silicon substrate to obtain a well region; ion implantation is performed in the well region to adjust the surface doping, and a tunneling oxide layer is formed above the well region; a polysilicon layer is deposited above the tunneling oxide layer to form a select gate and a floating gate on the polysilicon layer, and a channel is formed without contact between the select gate and the floating gate; a dielectric layer is formed above the tunneling oxide layer after the select gate and the floating gate are formed, and the dielectric layer covers the select gate and the floating gate to obtain the first semiconductor substrate.

[0029] Exemplarily, a P-type silicon substrate can be selected as the initial silicon substrate, and ion implantation is performed on the P-type silicon substrate according to the well region type of the EEPROM to form a well region. The well region is a partial area extending downward from the surface of the P-type silicon substrate, and not all of the P-type silicon substrate is turned into a well region. Among them, the well region types include N-well and P-well. Among them, if the well region type of the EEPROM is N-well, it can be achieved by implanting phosphorus (P) or arsenic (As). If the well region type of the EEPROM is P-well, it can be achieved by implanting boron (B). Furthermore, after the well region is formed and before the tunneling oxide layer is formed, the surface doping of the P-type silicon substrate is adjusted by ion implantation (such as implanting boron). After the surface doping is adjusted, the tunneling oxide layer can be formed by methods such as thermal oxidation. The material of the tunneling oxide layer is usually selected as silicon dioxide (SiO2). The specific production method of the tunneling oxide layer is prior art and is not limited in this application.

[0030] Exemplarily, after the tunneling oxide layer is formed, a polysilicon layer (poly) is deposited on the tunneling oxide layer, and a select gate and a floating gate are etched on the polysilicon layer by photolithography etching, and there is no contact between the select gate and the floating gate. The region without contact between the select gate and the floating gate forms a channel. Thus, a dielectric layer is deposited on the tunneling oxide layer after the select gate and the floating gate are formed, and the dielectric layer covers the tunneling oxide layer, the select gate and the floating gate, that is, the surface and the sides of the select gate and the floating gate are covered with the dielectric layer, so as to obtain the first semiconductor substrate. Among them, the dielectric layer is an ONO (Oxide-Nitride-Oxide) dielectric layer. The oxide is generally silicon dioxide, and the nitride is generally silicon nitride (Si3N4).

[0031] Please refer to Figure 2 , Figure 2 which is a cross-sectional view of the first semiconductor substrate provided by the embodiment of the present application. As Figure 2As shown, a well region is formed on a P-type silicon substrate by ion implantation, and then ion implantation is performed on the surface of the well region to form a surface doping (TIM) on the surface of the well region, that is, ion implantation is performed before the tunneling oxide layer is formed, and the thickness of the surface doping formed should be less than the thickness of the well region. The surface doping (TIM) includes a part covered by the floating gate and a part covered by the channel between the floating gate and the select gate. Polysilicon is deposited on the surface of the well region after the surface doping is formed, and a select gate (SG, select gate) and a floating gate (FG, floating gate) are formed by photolithography etching. Then, a dielectric layer is deposited on the surfaces of the select gate, the floating gate, and the well region, and the dielectric layer covers the surfaces and sidewalls of the select gate and the floating gate, and does not fill the channel formed between the select gate and the floating gate.

[0032] Wherein, the method further includes: performing ion implantation on the select gate, wherein the turn-on voltage of the select gate is changed by adjusting the ion implantation conditions of the select gate, and there is a positive correlation between the ion implantation conditions of the select gate and the turn-on voltage, and the ion implantation conditions of the select gate include the energy and dose of ion implantation.

[0033] Specifically, the turn-on voltage (VT_SG) of the select gate can be understood as the trigger voltage at which a conductive path is formed in the channel under the select gate (SG), that is, when the gate voltage of the select gate (SG) reaches the turn-on voltage, current is allowed to flow from the drain to the source. That is to say, after the dielectric layer is deposited, only P-type ion implantation (SG VT IMP) is performed on the select gate, and the turn-on voltage (VT_SG) of the select gate is adjusted by changing the energy and dose of ion implantation. That is, the higher the energy and dose of ion implantation, the higher the turn-on voltage of the select gate, and the lower the energy and dose of ion implantation, the lower the turn-on voltage of the select gate.

[0034] S102: Perform a photolithography operation by placing a target mask on the first semiconductor substrate to obtain a second semiconductor substrate.

[0035] Wherein, the target mask includes a blocking pattern, there is an overlapping area between the preset area projected by the floating gate onto the target mask and the blocking pattern, and the second semiconductor substrate includes a blocking layer formed above the floating gate through the photolithography operation.

[0036] That is to say, a preset area is obtained by vertically projecting the floating gate onto the target mask, there is an overlapping area between the preset area and the blocking pattern, and the preset area and the blocking pattern may not completely overlap, that is, the overlapping area may be a partial overlapping area or a complete overlapping area between the two.

[0037] Specifically, the width of the blocking pattern is less than or equal to the width of the floating gate, where the direction of the width refers to the direction perpendicular to the direction in which the channel between the select gate and the floating gate divides the select gate and the floating gate.

[0038] That is to say, the direction of the width of the blocking pattern is parallel to the direction of the width of the floating gate. The direction of the width of the blocking pattern may not coincide with the direction of the width of the floating gate, that is, the width of the blocking pattern and the width of the floating gate may not be on the same straight line. Taking a cross-section of the first semiconductor substrate along the direction of the width to obtain a target cross-section, the target cross-section can see the bottom and two side edges of the select gate, the floating gate, and the channel between the select gate and the floating gate.

[0039] Please refer to Figure 3 , Figure 3 which is the top view of the target photomask provided by the embodiment of the present application. As Figure 3 shown, the x-axis refers to the direction in which the channel between the select gate and the floating gate divides the select gate and the floating gate, and the y-axis refers to the direction perpendicular to the x-axis, that is, the direction of the width. Furthermore, taking a cross-section of the first semiconductor substrate along the direction of the y-axis can obtain a target cross-section (as Figure 2 ). Place the target photomask on the first semiconductor substrate, and the target photomask is parallel to the surface of the first semiconductor substrate, and a blocking pattern is provided on the target photomask, and the blocking pattern can cover a part of the floating gate. Exemplarily, the width h1 of the blocking pattern is less than or equal to the width h2 of the floating gate, and the length l1 of the blocking pattern is less than or greater than the length l2 of the floating gate. And, the length and width of the blocking pattern should change with the length and width of the floating gate, that is, as the width of the floating gate increases, the width of the blocking pattern should also increase.

[0040] Wherein, the second semiconductor substrate is obtained by the following method: coating a photoresist on the first semiconductor substrate and baking to obtain a semiconductor substrate to be exposed; sequentially performing an exposure process and a development process on the semiconductor substrate to be exposed to obtain a semiconductor substrate to be etched; etching the semiconductor substrate to be etched to obtain the second semiconductor substrate.

[0041] That is to say, the photoresist is coated on the first semiconductor substrate by a coating method and baked to increase the adhesion and uniformity of the photoresist, thereby obtaining a semiconductor substrate to be exposed. The semiconductor substrate to be exposed is first subjected to an exposure process and then a development process to transfer the blocking pattern to the photoresist, and finally a blocking layer is formed on the semiconductor substrate to be etched by etching to obtain the second semiconductor substrate, and the blocking layer is located above the area corresponding to the floating gate of the second semiconductor substrate.

[0042] S103: Ion implant the second semiconductor substrate to form a double-diffused drain region, obtaining a third semiconductor substrate.

[0043] Wherein, during the ion implantation process of the double-diffused drain region, the double-diffused drain region is restricted by the barrier layer, and there is a positive correlation between the thickness of the barrier layer and the degree of restriction on the double-diffused drain region.

[0044] Exemplarily, due to the presence of the barrier layer on the second semiconductor substrate, when ion implantation is performed to form a double-diffused drain region, the ion implantation angle should be set to an inclined angle, that is, the ion implantation angle is not parallel to the direction perpendicular to the surface of the semiconductor substrate, and multiple rotational implantations are performed. By the blocking of the barrier layer, the ions entering the double-diffused drain region under the channel of the select gate are reduced, so as to reduce the influence of the double-diffused drain region on the short-channel effect and ensure the performance of the peripheral circuit and other devices of the EEPROM Cell.

[0045] Wherein, the first semiconductor further includes a select gate covered with a dielectric layer, and the double-diffused drain region includes a first double-diffused drain region, a second double-diffused drain region, and a third double-diffused drain region. Among them, the first double-diffused drain region is located between the select gate and the floating gate, the second double-diffused drain region is located on the side of the select gate away from the floating gate, and the third double-diffused drain region is located on the side of the floating gate away from the select gate. Wherein, the barrier layer is used to limit the channel width between the first double-diffused drain region and the second double-diffused drain region.

[0046] Specifically, there is a positive correlation between the thickness of the barrier layer formed by the blocking pattern and the degree of restriction on the double-diffused drain region. Wherein, the thickness of the barrier layer at least restricts that the target edge corresponding to the select gate does not belong to the double-diffused drain region, and the target edge refers to the side close to the floating gate obtained by vertically projecting the select gate onto the well region.

[0047] That is to say, by adjusting the thickness of the photoresist coated on the first semiconductor substrate to adjust the thickness of the barrier layer, during the ion implantation of the double-diffused drain region, since the ion implantation angle is inclined, the barrier layer can at least block the side close to the floating gate obtained by vertically projecting the select gate onto the well region, so that the projection of the side of the select gate close to the floating gate in the well region does not fall into the double-diffused drain region, that is, the projection of the side of the select gate close to the floating gate in the well region does not undergo ion implantation of the double-diffused drain region. Thus, the channel width between the first double-diffused drain region and the second double-diffused drain region is increased, thereby increasing the breakdown voltage of the select gate.

[0048] Among them, the target mask further includes a double-diffused drain pattern to generate a double-diffused drain pattern on the second semiconductor substrate through a lithography operation, so that a double-diffused drain region can be generated in a corresponding region when performing ion implantation in the double-diffused drain region. That is to say, the target mask is the mask used to generate the double-diffused drain region pattern. Furthermore, depositing the barrier layer through the target mask can eliminate the need to add an additional mask, reduce mask consumption and lithography steps, and lower production costs.

[0049] Exemplarily, the target mask further includes an external circuit pattern to generate an external circuit pattern on the second semiconductor substrate through a lithography operation, so as to generate a double-diffused drain pattern on the second semiconductor substrate through a lithography operation, which serves to save masks. That is to say, the barrier layer only blocks the projection of the side of the select gate close to the floating gate in the well region and does not affect other structures in the external circuit and the charged erasable programmable read-only memory cell.

[0050] Exemplarily, the external circuit can be understood as other external connection structures such as bit lines, source lines, word lines, and control gate lines in the charged erasable programmable read-only memory except for the charged erasable programmable read-only memory cells.

[0051] Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of the third semiconductor substrate provided by the embodiment of the present application. As Figure 4 shown, due to the presence of the barrier layer and through ion implantation at an inclined angle (represented by the green arrowed line), the first double-diffused drain region HVNDDD1, the second double-diffused drain region HVNDDD2, and the third double-diffused drain region HVNDDD3 are formed. Moreover, the first double-diffused drain region is located between the select gate and the floating gate, that is, at the channel between the select gate and the floating gate in the well region. And due to the shielding of the barrier layer, the channel width l3 between the first double-diffused drain region and the second double-diffused drain region is restricted. The projection (black dashed line) of the side of the select gate in the well region close to the floating gate does not belong to the first double-diffused drain region. The second double-diffused drain region is located on the side of the select gate away from the floating gate, and the third double-diffused drain region is located on the side of the floating gate away from the select gate. And the double-diffused drain region in the present application refers to the high-voltage device N-type ion double-diffused drain region.

[0052] Among them, one ion implantation is performed using one mask to obtain the first double-diffused drain region HVNDDD1, the second double-diffused drain region HVNDDD2, and the third double-diffused drain region HVNDDD3. And the positions of the source and the drain are not limited. One of the positions on the side of the select gate away from the floating gate and on the side of the floating gate away from the select gate is the source, and the other is the drain. Sometimes the source or the drain is shared.

[0053] S104: Form a control gate in the region corresponding to the floating gate on the third semiconductor substrate after removing the blocking layer, to obtain a fourth semiconductor substrate.

[0054] Wherein, the control gate covers the sidewall and top surface of the floating gate. That is to say, remove the blocking layer on the third semiconductor substrate and form a control gate in the corresponding region on the floating gate, and the control gate surrounds the floating gate, covering both the top and sidewalls of the floating gate.

[0055] S105: Perform ion implantation on the fourth semiconductor substrate respectively to form a drain and a source, so as to fabricate a charged erasable programmable read-only memory cell, and construct a charged erasable programmable read-only memory through the charged erasable programmable read-only memory cell.

[0056] Please refer to Figure 5 , Figure 5 which is a schematic structural diagram of the charged erasable programmable read-only memory cell provided by the embodiment of the present application. As Figure 5 shown, this side of the second double-diffused drain region HVNLDDD1 is the source, and this side of the second double-diffused drain region HVNDDD2 is the drain. BL (Bit line) refers to the bit line, which is connected to the drain and used to connect the port of the peripheral circuit. The corresponding operating voltage is provided and transmitted to the floating gate by turning on or off the bit line, so that the floating gate can be programmed and erased. SL (Source line) refers to the source line, which is connected to the source. The control gate (CG, control gate) covers the floating gate, and the turn-on voltage of the select gate refers to the voltage when the channel between HVNDDD1 and HVNDDD2 is conducting.

[0057] Wherein, a word line is arranged on the select gate, which is a signal line connecting the gate of the read-only memory cell and is mainly used to select and enable the memory cell to control its conduction or cutoff; a control gate line is arranged on the control gate, which is used to adjust the electric field of the floating gate and affect the charge storage state.

[0058] Furthermore, there are changes in the electrical parameters between the updated EEPROM Cell prepared by the preparation method of the present application and the original EEPROM Cell. The electrical parameters include the erase operation voltage (VT_ERS), the write operation voltage (VT_PGM), the cell window voltage, the erase operation current (IBL_ERS), the write operation current (IBL_PGM), the breakdown voltage of the select gate (BVD_SG), and the turn-on voltage of the select gate (VT_SG). Among them, the erase operation voltage refers to the voltage used to erase the content stored in the EEPROM during the erase operation. The erase operation current refers to the current detected in the EEPROM transistor channel after the erase operation. The write operation voltage refers to the voltage used to write data into the EEPROM storage cell during the write operation. The write operation current refers to the current detected in the EEPROM transistor channel after the programming write operation. The cell window voltage refers to the voltage of ultraviolet irradiation when the EEPROM performs the erase operation. The breakdown voltage of the select gate refers to the maximum reverse voltage borne by the channel between HVNDDD1 and HVNDDD2 under the select gate. When the applied voltage exceeds this value, the device may undergo avalanche breakdown or thermal breakdown.

[0059] Please refer to Table 1, which refers to the electrical parameter table of the updated EEPROM Cell and the initial EEPROM Cell.

[0060] Table 1:

[0061] As shown in Table 1, the breakdown voltage of the select gate has a significant increase, enhancing the breakdown resistance of the select gate. The turn-on voltage of the select gate is controlled by adjusting the ion implantation conditions of the select gate to keep the turn-on voltage stable, with only a 0.05V fluctuation.

[0062] Furthermore, at least one electrically erasable programmable read-only memory cell and an external circuit are combined to form an electrically erasable programmable read-only memory. Multiple electrically erasable programmable read-only memory cells can be arranged in m rows and n columns to form an electrically erasable programmable read-only memory, which will not be elaborated in this application.

[0063] Based on the same inventive concept, the embodiments of the present application also provide an electrically erasable programmable read-only memory corresponding to the preparation method provided in the above embodiments. Since the principle of solving problems by the electrically erasable programmable read-only memory in the embodiments of the present application is similar to that of the preparation method in the above embodiments of the present application, the implementation of the electrically erasable programmable read-only memory can refer to the implementation of the preparation method, and the repeated parts will not be elaborated.

[0064] An embodiment of the present application also provides an electrically erasable programmable read-only memory, and the electrically erasable programmable read-only memory is prepared by the preparation method described in any of the foregoing embodiments.

[0065] When the electrically erasable programmable read-only memory performs an erasing operation, a writing operation or a reading operation, an operating voltage corresponding to the operation is applied to the control gate.

[0066] An embodiment of the present application also provides an electronic device, and the electronic device includes the electrically erasable programmable read-only memory described in any of the foregoing embodiments. The electronic device may be any electronic product or device such as a mobile phone or a tablet computer that applies the electrically erasable programmable read-only memory, or may be any intermediate product including the electrically erasable programmable read-only memory.

[0067] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems and devices described above may refer to the corresponding processes in the foregoing method embodiments, and will not be described in detail here. In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods may be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For another example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other may be through some communication interfaces, and the indirect couplings or communication connections of the devices or units may be in electrical, mechanical or other forms.

[0068] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0069] In addition, each functional unit in the various embodiments of the present application may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0070] When the above-mentioned function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a non-volatile computer-readable storage medium executable by a processor. Based on such an understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0071] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of changes or substitutions, which should all be covered by the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.

Claims

1. A method for preparing an electrically erasable programmable read-only memory, characterized in that, The method includes: Obtaining a first semiconductor substrate, where the first semiconductor includes a floating gate covered with a dielectric layer; Performing a lithography operation by placing a target mask on the first semiconductor substrate to obtain a second semiconductor substrate. The target mask includes a blocking pattern, and there is an overlapping area between a preset area projected by the floating gate onto the target mask and the blocking pattern. The second semiconductor substrate includes a blocking layer formed above the floating gate through the lithography operation; Performing ion implantation on the second semiconductor substrate to form a double-diffused drain region, obtaining a third semiconductor substrate. The double-diffused drain region is restricted by the blocking layer during the ion implantation process; Forming a control gate in the area corresponding to the floating gate on the third semiconductor substrate after removing the blocking layer, obtaining a fourth semiconductor substrate; Performing ion implantation on the fourth semiconductor substrate respectively to form a drain and a source, so as to fabricate a charged erasable programmable read-only memory cell, and constructing a charged erasable programmable read-only memory through the charged erasable programmable read-only memory cell.

2. The preparation method according to claim 1, characterized in that, The first semiconductor further includes a select gate covered with a dielectric layer, and the double-diffused drain region includes a first double-diffused drain region, a second double-diffused drain region, and a third double-diffused drain region. Wherein, the first double-diffused drain region is located between the select gate and the floating gate, the second double-diffused drain region is located on the side of the select gate away from the floating gate, and the third double-diffused drain region is located on the side of the floating gate away from the select gate. Wherein, the blocking layer is used to limit the channel width between the first double-diffused drain region and the second double-diffused drain region.

3. The preparation method according to claim 1, wherein The first semiconductor substrate is obtained by the following method: Performing ion implantation on an initial silicon substrate to obtain a well region; Performing ion implantation in the well region to adjust the surface doping, and generating a tunneling oxide layer above the well region; Depositing a polysilicon layer above the tunneling oxide layer to form a select gate and a floating gate on the polysilicon layer. The select gate and the floating gate do not contact each other to form a channel; Forming a dielectric layer above the tunneling oxide layer after generating the select gate and the floating gate. The dielectric layer covers the select gate and the floating gate to obtain the first semiconductor substrate.

4. The preparation method according to claim 3, characterized in that, The method further includes: Performing ion implantation on the select gate. Wherein, the turn-on voltage of the select gate is changed by adjusting the ion implantation conditions of the select gate. There is a positive correlation between the ion implantation conditions of the select gate and the turn-on voltage. The ion implantation conditions of the select gate include the energy and dose of ion implantation.

5. The preparation method according to any one of claims 1 to 4, characterized in that, There is a positive correlation between the thickness of the blocking layer and the degree of restriction on the double-diffused drain region. Wherein, the thickness of the blocking layer at least restricts that the target edge corresponding to the select gate does not belong to the double-diffused drain region. The target edge refers to the side close to the floating gate obtained by vertically projecting the select gate onto the well region.

6. The preparation method according to claim 1, characterized in that, The second semiconductor substrate is obtained by the following method: Coating a photoresist on the first semiconductor substrate, and baking to obtain a semiconductor substrate to be exposed; The semiconductor substrate to be exposed is successively subjected to an exposure process and a development process to obtain a semiconductor substrate to be etched; The semiconductor substrate to be etched is etched to obtain a second semiconductor substrate.

7. The preparation method according to claim 1, wherein, The control gate covers the sidewalls and the top surface of the floating gate.

8. An electrically erasable programmable read-only memory, characterized in that, The electrically erasable programmable read-only memory is prepared by the preparation method according to any one of claims 1 to 7.

9. The electrically erasable programmable read-only memory according to claim 8, characterized in that, When the electrically erasable programmable read-only memory performs an erase operation, a write operation, or a read operation, an operating voltage corresponding to the operation is applied to the control gate.

10. An electronic device, characterized in that, The electronic device includes the electrically erasable programmable read-only memory according to claim 8 or 9.

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