Semiconductor memory device

Abstract

Provided is a semiconductor memory device having improved operation speed and reliability. A semiconductor memory device includes: a bit line; a first laminated body which is disposed above the bit line, in which a plurality of first insulating layers and a plurality of first conductive layers are alternately laminated, and which has a first step region and a first bridge region; and a second laminate disposed above the first laminate, in which a plurality of second insulating layers and a plurality of second conductive layers are alternately laminated, and which has a second step region and a second bridge region. A width in the third direction of a first bridge region associated with a lowermost layer of the plurality of first conductive layers is greater than a width in the third direction of a second bridge region associated with a lowermost layer of the plurality of second conductive layers.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a semiconductor memory device. Background Art

[0002] There is known a semiconductor package using a NAND type flash memory as a semiconductor memory device. In order to increase the capacity of such a NAND type flash memory, a three-dimensional NAND type flash memory having a structure in which a plurality of memory cells are stacked has been put into practical use. In such a stacked three-dimensional NAND type flash memory, improving the operation speed and reliability has become an issue. Summary of the Invention

[0003] Embodiments of the present disclosure provide a semiconductor memory device that improves operation speed and reliability.

[0004] A semiconductor memory device according to an embodiment includes: bit lines; a first stack body disposed above the bit lines, in which a plurality of first insulating layers and a plurality of first conductive layers are alternately stacked in a first direction, the first stack body having a first stepped region and a first bridging region, the first stepped region being at the center in a second direction intersecting the first direction, causing ends of the plurality of first conductive layers to be stepped in the second direction, the first bridging region being adjacently disposed to the first stepped region in a third direction intersecting the first direction and the second direction, and for each of the plurality of first conductive layers, electrically connecting storage cell regions on both sides in the second direction across the first stepped region; and a second stack body disposed above the first stack body, in which a plurality of second insulating layers and a plurality of second conductive layers are alternately stacked in the first direction, the second stack body having a second stepped region and a second bridging region, the second stepped region being at the center in the second direction, causing ends of the plurality of second conductive layers to be stepped in the second direction, the second bridging region being adjacently disposed to the second stepped region in the third direction, and for each of the plurality of second conductive layers, electrically connecting storage cell regions on both sides in the second direction across the second stepped region, and a width in the third direction of the first bridging region related to the lowermost layer among the plurality of first conductive layers is greater than a width in the third direction of the second bridging region related to the lowermost layer among the plurality of second conductive layers. Brief Description of the Drawings

[0005] Figure 1 is a cross-sectional view showing an overall configuration of a semiconductor memory device according to an embodiment. Figure 2 is a cross-sectional view showing a configuration of a memory cell array of a semiconductor memory device according to an embodiment. Figure 3 is a cross-sectional view showing a configuration of a memory cell of a semiconductor memory device according to an embodiment. Figure 4 This is a perspective view showing an overview of a connection area of a semiconductor memory device according to an embodiment. Figure 5 This is an enlarged perspective view showing an overview of a connection area of a semiconductor memory device according to an embodiment. Figure 6 This is a perspective view showing a configuration example of a word line of a semiconductor memory device according to an embodiment. Figure 7A This is an enlarged top view showing a connection area of a semiconductor memory device according to an embodiment. Figure 7B This is an enlarged cross-sectional view showing a connection area of a semiconductor memory device according to an embodiment. Detailed Embodiments

[0006] Hereinafter, a semiconductor memory device according to the present embodiment will be specifically described with reference to the drawings.

[0007] In the following description, elements having substantially the same functions and configurations are given the same reference numerals or reference numerals with letters appended thereto, and repeated description is made only when necessary. Each of the following embodiments illustrates a device and a method for embodying the technical concept of the embodiment. The embodiment can be variously modified without departing from the gist of the invention. These embodiments and their modified examples are included in the scope equivalent to the invention described in the claims.

[0008] For further clarity of explanation, the drawings may schematically show the widths, thicknesses, shapes, etc. of each part as compared with the actual manner, but this is only an example and does not limit the interpretation of the present invention. In this specification and each drawing, elements having the same functions as those described in the accompanying drawings are given the same reference numerals, and repeated description may be omitted.

[0009] Unless otherwise specified, the expression "α includes A, B, or C" in this specification does not exclude the case where α includes a combination of A to C. In addition, these expressions do not exclude the case where α includes other elements.

[0010] The following embodiments can be combined with each other as long as there is no technical contradiction.

[0011] In each embodiment of the present invention, the direction from the substrate toward the storage unit is referred to as upward. Conversely, the direction from the storage unit toward the substrate is referred to as downward. Thus, for ease of explanation, statements such as upward or downward are used, but for example, the vertical relationship between the substrate and the storage unit may be configured in a manner opposite to that shown in the drawings. In addition, in the following description, expressions such as a storage unit on a substrate merely illustrate the vertical relationship between the substrate and the storage unit as described above, and other components may also be disposed between the substrate and the storage unit.

[0012] [Overall Configuration of Semiconductor Memory Device] Use Figure 1 The overall configuration of the semiconductor memory device according to the present embodiment will be described. Figure 1 FIG. is a cross-sectional view showing a configuration example of the semiconductor memory device 1 according to the present embodiment. The semiconductor memory device 1 is configured by bonding a memory chip C1 and a CMOS (Complementary Metal Oxide Semiconductor) chip C2 to each other. The memory chip C1 is a semiconductor chip including a memory cell array 10m_1, 10m_2, and a connection region 10s. The CMOS chip C2 is a semiconductor chip including a peripheral circuit. The memory chip C1 and the CMOS chip C2 are bonded on a bonding surface FB.

[0013] The memory cell array 10m_1 includes: a stack 100 including a plurality of word lines WL1 stacked in the Z direction and insulated from each other, a plurality of columnar portions CL1 extending in the Z direction within the plurality of word lines WL1, and a plurality of bit lines BL1 provided on the stack 100. The columnar portion CL1 is electrically connected to a certain bit line BL1 via a via contact VY1. The bit line BL1 is electrically connected to the CMOS chip C2 via a wiring (not shown).

[0014] The memory cell array 10m_2 includes: a stack 100 including a plurality of word lines WL2 stacked in the Z direction and insulated from each other, a plurality of columnar portions CL2 extending in the Z direction within the plurality of word lines WL2, and a plurality of bit lines BL2 provided on the stack 100. Each layer of the word line WL2 corresponds to each layer of the word line WL1. The columnar portion CL2 is electrically connected to a certain bit line BL2 via a via contact VY2. The bit line BL2 is electrically connected to the CMOS chip C2 via a wiring (not shown). The configurations of the memory cell arrays 10m_1 and 10m_2 may also be the same.

[0015] The connection region 10s is provided between the memory cell arrays 10m_1 and 10m_2. The connection region 10s is disposed substantially at the center in the X direction of the memory chip C1. The connection region 10s includes a plurality of word lines WL3 stacked in the Z direction. The plurality of word lines WL3 are configured in a stepped shape such that the middle portion of the connection region 10s is closest to the CMOS chip C2, and the ends of the memory cell arrays 10m_1 and 10m_2 on both sides of the middle portion of the connection region 10s are farther from the CMOS chip C2. That is, the plurality of word lines WL3 are configured in a stepped shape such that they are farther from the CMOS chip C2 as they approach the memory cell arrays 10m_1 and 10m_2 from the middle portion of the connection region 10s. In addition, the orientation of the steps is merely an example and is not necessarily limited thereto. For example, it may be configured such that they approach the CMOS chip C2 as they approach the memory cell arrays 10m_1 and 10m_2 from the middle portion of the connection region 10s. It may also be configured such that they approach the CMOS chip C2 as they approach the memory cell array 10m_1 from the end portion on the memory cell array 10m_2 side in the connection region 10s, or the opposite direction thereof. The plurality of word lines WL3 stacked in the Z direction are exposed from the word lines WL3 in the upper stage (CMOS chip C2 side) at the respective step difference surfaces (platform regions) configured in a stepped shape. In addition, when observing locally, there are also portions where the plurality of word lines WL3 are configured in a manner that they approach the CMOS chip C2 as they approach the memory cell arrays 10m_1 and 10m_2 from the middle portion.

[0016] Each layer of the word line WL3 corresponds to each layer of the word line WL1 and the word line WL2 respectively. The word lines WL1 to WL3 are located at substantially the same height in their respective corresponding layers. Each layer of the word lines WL1 to WL3 is formed by processing a continuous same material layer. The word lines WL1 to WL3 are made of, for example, conductive metals such as copper and tungsten. Hereinafter, each layer of the mutually corresponding word lines WL1 to WL3 is also referred to as a word line layer WL. The plurality of word line layers WL stacked in the Z direction and insulated from each other are also referred to as a stack 100.

[0017] In the word line layer WL, the word line WL3 is electrically connected to the word line WL1 and the word line WL2 via a bridging portion WLB. The bridging portion WLB is formed by processing the same material layer as the word lines WL1 to WL3. The bridging portion WLB is a layer remaining in the Y direction when the word line WL3 is processed into a stepped shape, and is continuously provided among the word lines WL1 to WL3. Each word line layer WL of the word lines WL1 to WL3 is electrically connected via the bridging portion WLB.

[0018] Among multiple word line layers WL, there may also be a word line layer WL without a bridging portion WLB provided. At the word line layer WL where the bridging portion WLB does not exist, a metal bridge MB is provided between the word line WL1 and the word line WL2. The metal bridge MB is a wiring layer separately provided from the word line layers WL of the word lines WL1 to WL3, and electrically connects between the word line WL1 and the word line WL2. The contact plugs CC1 and CC2 connected to the metal bridge MB are respectively connected to the word lines WL1 and WL2 located at both ends of the connection region 10s. The metal bridge MB is connected between the contact plug CC1 connected to the word line WL1 at one end of the connection region 10s and the contact plug CC2 connected to the word line WL2 at the other end of the connection region 10s. The contact plug CC1 is connected between the metal bridge MB and the word line WL1. The contact plug CC2 is connected between the metal bridge MB and the word line WL2.

[0019] Multiple word lines WL3 are respectively electrically connected to the contact plugs CC extending in the Z direction on each stepped surface (platform region). In addition, as Figure 1 shown, the diameter (diameter in the X or Y direction) of the contact plug CC is formed to be tapered at the tip in such a manner that it becomes narrower as it goes toward the substrate side in the stacking direction (Z direction) in the stacked body 100.

[0020] The contact plug CC connected to the word line WL3 is electrically connected to the wiring WG11 via the wiring WG1. The wiring WG11 is a wiring exposed on the bonding surface FB of the memory chip C1 and the CMOS chip C2, and is bonded to the wiring WG21 on the CMOS chip C2 side on the bonding surface FB.

[0021] The CMOS chip C2 includes multiple switches SW, wirings WG2, and WG21. The switch SW is a part of the row decoder module and includes, for example, a MOSFET (metal-oxide-semiconductor field-effect transistor). The switch SW is connected to the wiring WG21 via the wiring WG2 having a multilayer wiring structure.

[0022] Each switch SW applies a word line voltage to the word line layer WL (word lines WL1 to WL3) connected thereto. For example, the switch selected from the multiple switches SW becomes conductive during a read operation, a write operation, and an erase operation, so that a word line voltage can be applied to the selected word lines WL1 to WL3.

[0023] A plurality of switches SW are provided corresponding to a plurality of word line layers WL respectively. The plurality of switches SW are electrically connected to contact plugs CC respectively connected to the word line layer WL. The word line WL3 is configured in a stepped shape in the following manner: in the middle part of the connection area 10s, it is closest to the switch SW, and as it goes towards the end of the connection area 10s close to the memory cell arrays 10m_1 and 10m_2, it moves away from the switch SW in the Z direction. The contact plug CC contacts the step difference surface (platform area) provided on the stepped word line WL3 from the Z direction. The switch SW is electrically connected to its corresponding word line WL3 via the contact plug CC.

[0024] [Configuration of Memory Cell Array] Use Figure 2 The configuration of the memory cell array according to this embodiment will be described. Figure 2 It is a perspective view showing the configuration of the memory cell array according to this embodiment. In addition, Figure 2 Relative to Figure 1 the memory chip C1 is displayed upside down. In addition, since the configurations of the memory cell arrays 10m_1 and 10m_2 can be the same, the memory cell array 10m_1 will be described here, and the description of the memory cell array 10m_2 will be omitted. In Figure 2 , two directions parallel to and orthogonal to each other with respect to the main surface of the substrate 10 are referred to as the X direction and the Y direction, and a plane parallel to the main surface of the substrate 10 is referred to as the XY plane. A direction orthogonal to both the X direction and the Y direction is referred to as the Z direction (stacking direction).

[0025] As Figure 2 shown, the memory cell array 10m_1 includes a substrate 10, a stacked body 100 provided on the substrate 10, a plurality of columnar body portions CL1, and a plurality of bit lines BL1 provided on the stacked body 100.

[0026] The substrate 10 is, for example, a semiconductor substrate made of P-type silicon (Si) containing P-type impurities such as boron (B). On the surface of the substrate 10, for example, a P-type well region containing P-type impurities is provided. However, it is not limited thereto, and a polysilicon layer may be formed between the substrate 10 and the stacked body 100, and after the memory chip C1 and the CMOS chip C2 are bonded, the substrate 10 may be peeled off.

[0027] The stacked body 100 includes a lower stacked body T1 disposed on the substrate 10, a middle stacked body T2 disposed on the side opposite to the substrate 10 of the lower stacked body T1, and an upper stacked body T3 disposed on the side opposite to the lower stacked body T1 of the middle stacked body T2 (here, when not distinguishing the lower stacked body T1, the middle stacked body T2, and the upper stacked body T3, it is referred to as the stacked body 100).

[0028] The stacked body 100 has a plurality of word lines WL1 stacked on the substrate 10. The plurality of word lines WL1 are periodically stacked in a direction (stacking direction) perpendicular to the main surface of the substrate 10 via a plurality of insulating layers 40. Each word line WL1 is a single layer. That is, when observing the cross-sectional shape of one word line WL1, it can be a single material continuous in the film thickness direction (Z direction) of the word line WL1. In addition, there may be no interface inside one word line WL1. The material of the word line WL1 can be, for example, tungsten.

[0029] An insulating layer 40 is formed between the word lines WL1 adjacent to each other in the stacking direction. The plurality of word lines WL1 and the plurality of insulating layers 40 are alternately arranged. An insulating layer 40 is also formed between the substrate 10 and the lowermost word line WL1. An insulating layer 41 is disposed at the boundary between the lower stacked body T1 and the middle stacked body T2. The film thickness of the insulating layer 41 disposed at the boundary between the lower stacked body T1 and the middle stacked body T2 in the stacking direction may be greater than the film thickness of the insulating layer 40 between the other word lines WL1 in the stacking direction. An insulating layer 42 is disposed at the boundary between the middle stacked body T2 and the upper stacked body T3. The film thickness of the insulating layer 42 disposed at the boundary between the middle stacked body T2 and the upper stacked body T3 in the stacking direction may be greater than the film thickness of the insulating layer 40 between the other word lines WL1 in the stacking direction. However, this is not limited thereto, and the film thicknesses of the insulating layer 41 and the insulating layer 42 in the stacking direction may be equal to the film thickness of the insulating layer 40 between the other word lines WL1 in the stacking direction.

[0030] It is only necessary that the word lines WL1 adjacent to each other in the stacking direction are insulated from each other. The materials of the insulating layer 40, the insulating layer 41, and the insulating layer 42 can be, for example, silicon oxide such as silicon dioxide (SiO2) and TEOS (Tetra Ethyl Ortho Silicate). The insulating layer 40 is deposited, for example, using a CVD (Chemical Vapor Deposition) apparatus.

[0031] In the stacked body 100, a plurality of word lines WL1 insulated from each other, and slits ST and MH shared by the plurality of word lines WL1 are formed. The slits ST and MH extend in the stacking direction (Z direction) and penetrate the stacked body 100 to reach the substrate 10. The slit ST extends in the X direction and separates the stacked body 100 into a plurality of blocks BLK in the Y direction. A columnar body portion CL1 (refer to Figure 3 ) is formed in the opening MH, and the details will be described later.

[0032] The columnar body portion CL1 is formed as a cylinder extending in the stacking direction within the stacked body 100. The plurality of columnar body portions CL1 are, for example, arranged in a staggered manner. Alternatively, the plurality of columnar body portions CL1 may be arranged in a square lattice along the X direction and the Y direction.

[0033] In addition, as Figure 1 shown, the diameter of the columnar portion CL1 (the diameter in the X or Y direction) is formed to taper at the tip in such a manner that it becomes narrower as it goes toward the substrate side in the stacking direction (Z direction) in each of the lower stacked body T1, the middle stacked body T2, and the upper stacked body T3.

[0034] The plurality of bit lines BL1 are separated from each other in the X direction, and each bit line BL1 extends in the Y direction.

[0035] The upper end of the semiconductor layer 20 (refer to Figure 3 ) of the columnar body portion CL1 described later is connected to the bit line BL1 via the via contact VY1. The plurality of columnar body portions CL1 selected one by one from each block BLK separated in the Y direction by the slit ST are connected to a common one bit line BL1.

[0036] In addition, an insulating layer is formed in the slit ST, and an insulating layer is formed above the stacked body 100. However, for the sake of simplicity of explanation, these insulating layers are omitted in Figure 1 .

[0037] [Configuration of the memory cell] The configuration of the memory cell according to the present embodiment will be described using Figure 3 . Figure 3 is a cross-sectional view showing the configuration of the memory cell according to the present embodiment. Figure 3 is Figure 2 an enlarged cross-sectional view of the columnar body portion CL1 in

[0038] As Figure 3 shown, the columnar body portion CL1 is a structure having a storage layer 30, a semiconductor layer 20, and an insulating core layer 50. The semiconductor layer 20 continuously extends in the stacking direction (Z direction) within the stacked body 100. The material of the semiconductor layer 20 includes, for example, amorphous or polycrystalline silicon. The core layer 50 is provided inside the cylindrical semiconductor layer 20. The material of the core layer 50 includes, for example, silicon oxide. The storage layer 30 is provided between the word line WL1 and the semiconductor layer 20. The storage layer 30 surrounds the semiconductor layer 20 from the outer peripheral side of the semiconductor layer 20.

[0039] The storage layer 30 includes a tunnel insulating layer 31, a charge storage layer 32, and a blocking insulating layer 33 (herein, the tunnel insulating layer 31, the charge storage layer 32, and the blocking insulating layer 33 are referred to as the storage layer 30 when they are not distinguished). The blocking insulating layer 33, the charge storage layer 32, and the tunnel insulating layer 31 extend continuously along the stacking direction of the stacked body 100 together with the semiconductor layer 20. Between the word line WL1 and the semiconductor layer 20, the blocking insulating layer 33, the charge storage layer 32, and the tunnel insulating layer 31 are sequentially provided starting from the word line WL1 side. The tunnel insulating layer 31 is in contact with the semiconductor layer 20. The blocking insulating layer 33 is in contact with the word line WL1. The charge storage layer 32 is provided between the blocking insulating layer 33 and the tunnel insulating layer 31.

[0040] The semiconductor layer 20, the memory layer 30 and the word line WL1 constitute a memory cell MC. Figure 3 In FIG. 1 , one memory cell MC is schematically indicated by a dotted line. The memory cell MC has a vertical transistor structure in which a word line WL1 surrounds a semiconductor layer 20 via a memory layer 30 .

[0041] In the memory cell MC of the vertical transistor structure, the semiconductor layer 20 functions as a channel, the word line WL1 functions as a control gate of the memory cell, and the charge storage layer 32 functions as a data layer for storing charges injected from the semiconductor layer 20 .

[0042] As described above, a plurality of memory cells MC are arranged in the stacking direction of a plurality of word lines WL1, and a plurality of word lines WL1 are respectively connected to a plurality of memory cells MC. The word lines WL1 near the blocking insulating layer 33 function as control gates. By controlling the voltage of the word lines WL1 connected to the memory cells MC, writing or erasing to the memory cells MC can be controlled.

[0043] The semiconductor memory device of this embodiment is a nonvolatile semiconductor device that can electrically freely write or erase data to or from a memory cell MC and can retain the content even when power is turned off.

[0044] The memory cell MC is, for example, a charge trapping type memory cell. The charge storage layer 32 has a plurality of trapping sites for trapping charges in an insulating layer. The material of the charge storage layer 32 includes, for example, silicon nitride.

[0045] The tunnel insulating layer 31 serves as a potential barrier when charges are injected from the semiconductor layer 20 to the charge storage layer 32 or when charges stored in the charge storage layer 32 diffuse toward the semiconductor layer 20. The material of the tunnel insulating layer 31 includes silicon oxide, for example.

[0046] The blocking insulating layer 33 prevents the charges stored in the charge storage layer 32 from diffusing toward the word line WL1. The material of the blocking insulating layer 33 includes, for example, silicon oxide.

[0047] As shown Figure 2 in FIG. 1, a source-side selection transistor STS is provided on the lower layer of the stacked body 100. A drain-side selection transistor STD is provided on the upper layer of the stacked body 100. For example, the lowermost word line WL1 functions as a control gate of the source-side selection transistor STS. For example, the uppermost word line WL1 functions as a control gate of the drain-side selection transistor STD. A plurality of memory cells MC are provided between the source-side selection transistor STS and the drain-side selection transistor STD.

[0048] A plurality of memory cells MC are provided between the drain-side selection transistor STD and the source-side selection transistor STS. The plurality of memory cells MC, the drain-side selection transistor STD, and the source-side selection transistor STS are connected in series through a semiconductor layer 20 to form a memory string. The memory string is, for example, arranged in a staggered manner in a plane direction parallel to the X-Y plane, and the plurality of memory cells MC are three-dimensionally arranged in the X direction, Y direction, and Z direction.

[0049] [Configuration of connection region] Use Figure 4 and Figure 5 to describe the configuration of the connection region according to the present embodiment. Figure 4 FIG. 2 is a perspective view showing an outline of a connection region 10s of a certain block BLK. Figure 5 FIG. 3 is an enlarged perspective view showing an outline of the connection region 10s of a certain block BLK. In addition, Figure 4 and Figure 5 The memory chip C1 is displayed upside down with respect to Figure 1 As shown Figure 4 in FIG. 4, a stepped region SSA of the connection region 10s is an opening region in which the word line WL3 is formed in a stepped shape. As Figure 5 shown in FIG. 5, in the stepped region SSA, a platform region TRC is provided for connecting a plurality of contact plugs CC to the plurality of word lines WL3 respectively. In the platform region, the plurality of word lines WL3 are respectively exposed from the word line WL3 in the upper stage (CMOS chip C2 side). In addition, a holding member HR is formed on the stepped region SSA, and an insulator 43 is formed above the stepped region SSA (opening region). However, for the sake of simplicity of explanation, they are omitted in Figure 4 FIG. 6.

[0050] The bridging portion WLB is composed of a part of the plurality of word lines WL3 and extends in the X direction (the extending direction of the slit ST), and electrically connects the word line WL1 of the memory cell array 10m_1 and the word line WL2 of the memory cell array 10m_2 for each word line layer WL. Therefore, at the word line layer WL where the bridging portion WLB exists, the word lines WL1 to WL3 are electrically connected across the opening region.

[0051] In the connection region 10s, the bridging portion WLB is adjacently disposed with respect to the stepped region SSA in the Y direction (a direction substantially perpendicular to the extending direction (X direction) of the slit ST), and a stepped shape that is steeper than the stepped region SSA in the Y direction is formed. On the other hand, no stepped shape is formed in the X direction.

[0052] [Configuration of the bridging portion] Use Figure 6 , Figure 7A and Figure 7B to describe the configuration of the bridging portion according to the present embodiment. Figure 6 is a perspective view showing a configuration example of word lines WL1 to WL3. Figure 7A is an enlarged top view showing a part of the connection region ( Figure 4 region A). Figure 7B is an enlarged cross-sectional view showing a part of the connection region ( Figure 4 B - B' cross-section). In Figure 6 , for convenience, three word line layers are respectively shown for the lower laminate T1, the middle laminate T2, and the upper laminate T3, but the word lines may be four or more layers. In addition, in the present embodiment, the laminate group is divided into three, but it may also be two or less, or four or more. As Figure 7A and Figure 7B shown, a holding member HR that penetrates the laminate 100 and an insulator 43 that fills the region above the stepped region SSA are disposed in the stepped region SSA.

[0053] The bridging portion WLB is disposed between the slit ST and the stepped region SSA. In addition, as Figure 7A shown, the width of the slit ST in the Y direction (a direction substantially perpendicular to the extending direction (X direction) of the slit ST) is formed to be tapered at the tip so as to become narrower as it goes toward the substrate side in the stacking direction (Z direction) in the laminate 100.

[0054] At the word line layer of the lower laminate T1 that is relatively far from the CMOS chip C2, the interval between the word line WL3 and the word lines WL1 and WL2 is narrow, and the length of the bridging portion WLB in the X direction (the connection direction of the word line WL3 and the word lines WL1 and WL2) is short. On the other hand, at the word line layer of the upper laminate T3 that is relatively close to the CMOS chip C2, the interval between the word line WL3 and the word lines WL1 and WL2 is wide, and the length of the bridging portion WLB in the X direction is long. In the present embodiment, the shorter the length of the bridging portion WLB in the X direction is in the word line layer of the lower laminate T1 such as the switch SW that is farther from the CMOS chip C2. The longer the length of the bridging portion WLB in the X direction is in the word line layer of the upper laminate T3 such as the switch SW that is closer to the CMOS chip C2. That is, regarding the length of the bridging portion WLB in the X direction, that of the middle laminate T2 is longer than that of the lower laminate T1, and that of the upper laminate T3 is longer than that of the middle laminate T2.

[0055] Regarding the width of the bridging portion WLB of the present embodiment in the Y direction (the direction perpendicular to the connection direction of the word line WL3 and the word lines WL1 and WL2), the middle laminate T2 is different from the upper laminate T3. The width W3 of the bridging portion WLB of the uppermost layer of the upper laminate T3 in the Y direction is wider than the width W2 of the bridging portion WLB of the uppermost layer of the middle laminate T2 in the Y direction. With respect to 100% of the width of the bridging portion WLB of the uppermost layer of the upper laminate T3 in the Y direction, the width of the bridging portion WLB of the uppermost layer of the middle laminate T2 in the Y direction may be in the range of 40% or more and 80% or less. Here, the bridging portion WLB of the uppermost layer refers to the bridging portion WLB of the uppermost word line layer WL among the word line layers WL (without using the metal bridge MB) including the bridging portion WLB in the middle laminate T2 and the upper laminate T3 respectively.

[0056] By making the width W3 of the bridging portion WLB of the upper laminate T3 in the Y direction wider than the width W2 of the bridging portion WLB of the middle laminate T2 in the Y direction, it is possible to suppress an increase in the resistance of the bridging portion WLB of the upper laminate T3 due to the fact that the length of the bridging portion WLB of the upper laminate T3 in the X direction is longer than the length of the bridging portion WLB of the middle laminate T2 in the X direction. By suppressing an increase in the resistance of the bridging portion WLB, it is possible to improve the read and programming operation speeds of the semiconductor memory device 1. By making the width W2 of the bridging portion WLB of the middle laminate T2 in the Y direction narrower than the width W3 of the bridging portion WLB of the upper laminate T3 in the Y direction, it is possible to ensure the space on the stepped area SSA and improve the filling property of the insulator 43. By improving the filling property of the insulator 43, it is possible to suppress the generation of cracks in the heat treatment process and the like, and improve the reliability and manufacturing yield of the semiconductor memory device 1.

[0057] Regarding the width of the bridging portion WLB in the Y direction (the direction perpendicular to the connection direction of the word lines WL3 and WL1, WL2) of the present embodiment, the middle layer stack T2 is different from the lower layer stack T1. The width W2 in the Y direction of the bridging portion WLB of the uppermost layer of the middle layer stack T2 is narrower than the width W1 in the Y direction of the bridging portion WLB of the uppermost layer of the lower layer stack T1. With respect to 100% of the width in the Y direction of the bridging portion WLB of the uppermost layer of the lower layer stack T1, the width in the Y direction of the bridging portion WLB of the uppermost layer of the middle layer stack T2 can be in the range of 40% or more and 80% or less. Here, the uppermost bridging portion WLB refers to the bridging portion WLB of the uppermost word line layer WL (without using the metal bridge MB) containing the bridging portion WLB in each of the lower layer stack T1 and the middle layer stack T2.

[0058] By making the width W1 in the Y direction of the bridging portion WLB of the lower layer stack T1 wider than the width W2 in the Y direction of the bridging portion WLB of the middle layer stack T2, the resistance of the bridging portion WLB of the lower layer stack T1 can be suppressed. By suppressing the resistance of the bridging portion WLB, the read and programming operation speeds of the semiconductor memory device 1 can be further improved. By making the width W2 in the Y direction of the bridging portion WLB of the middle layer stack T2 narrower than the width W1 in the Y direction of the bridging portion WLB of the lower layer stack T1, the space on the stepped region SSA can be ensured, and the filling property of the insulator 43 can be improved. By improving the filling property of the insulator 43, the generation of cracks in the heat treatment process etc. can be suppressed, and the reliability and manufacturing yield of the semiconductor memory device 1 can be improved.

[0059] Regarding the width of the bridging portion WLB in the Y direction (the direction perpendicular to the connection direction of the word lines WL3 and WL1, WL2) of the present embodiment, the upper layer stack T3 can also be different from the lower layer stack T1. The width W3 in the Y direction of the bridging portion WLB of the uppermost layer of the upper layer stack T3 can also be wider than the width W1 in the Y direction of the bridging portion WLB of the uppermost layer of the lower layer stack T1. With respect to 100% of the width in the Y direction of the bridging portion WLB of the uppermost layer of the upper layer stack T3, the width in the Y direction of the bridging portion WLB of the uppermost layer of the lower layer stack T1 can be in the range of 50% or more and less than 100%. Here, the uppermost bridging portion WLB refers to the bridging portion WLB of the uppermost word line layer WL (without using the metal bridge MB) containing the bridging portion WLB in each of the lower layer stack T1 and the upper layer stack T3.

[0060] By making the width W3 in the Y direction of the bridging portion WLB of the upper stacked body T3 wider than the width W1 in the Y direction of the bridging portion WLB of the lower stacked body T1, it is possible to suppress an increase in the resistance of the bridging portion WLB of the upper stacked body T3 due to the length of the bridging portion WLB of the upper stacked body T3 in the X direction being longer than the length of the bridging portion WLB of the lower stacked body T1 in the X direction. By suppressing the increase in the resistance of the bridging portion WLB, the read and programming operation speeds of the semiconductor memory device 1 can be improved. By making the width W1 in the Y direction of the bridging portion WLB of the lower stacked body T1 narrower than the width W3 in the Y direction of the bridging portion WLB of the upper stacked body T3, it is possible to ensure a space on the stepped area SSA and improve the filling property of the insulator 43. By improving the filling property of the insulator 43, it is possible to suppress the generation of cracks in the heat treatment process or the like, and improve the reliability and manufacturing yield of the semiconductor memory device 1.

[0061] In addition, regarding the width in the Y direction of the bridging portion WLB, in each of the lower stacked body T1, the middle stacked body T2, and the upper stacked body T3, the lower layer farther from the CMOS chip C2 is wider, and it becomes narrower as it approaches the CMOS chip C2. There is no bridging portion WLB at the top word line layer of each of the lower stacked body T1, the middle stacked body T2, and the upper stacked body T3. This is because when the word line WL3 is processed into a stepped shape, the etching process and the photoresist thinning process are repeatedly performed. In the lower stacked body T1, the middle stacked body T2, and the upper stacked body T3, as going from the lower layer to the upper layer, the width of the bridging portion WLB gradually becomes narrower, and there is no bridging portion WLB at the top layer. In addition, the photoresist is re-coated for each of the lower stacked body T1, the middle stacked body T2, and the upper stacked body T3, and the word line WL3 is processed for each of the lower stacked body T1, the middle stacked body T2, and the upper stacked body T3. Therefore, the bridging portion WLB at the top layer of each of the lower stacked body T1, the middle stacked body T2, and the upper stacked body T3 is removed. At the top word line layer, the word line WL3 becomes an electrically floating state. In addition, the top word lines WL1 and WL2 are not connected by the bridging portion WLB, but are electrically connected via the metal bridge MB.

[0062] In the present embodiment, in the top word line layer of each of the lower stacked body T1, the middle stacked body T2, and the upper stacked body T3, the metal bridge MB electrically connects the word line WL1 and the word line WL2 instead of the bridging portion WLB. However, in a plurality of word line layers starting from the top layer of each of the lower stacked body T1, the middle stacked body T2, and the upper stacked body T3, the metal bridge MB may also electrically connect the word line WL1 and the word line WL2 instead of the bridging portion WLB. [Description of Reference Numerals]

[0063] 1 Semiconductor memory device, 10 Substrate, 10m Memory cell array, 10s Connection region, 20 Semiconductor layer, 30 Storage layer, 40 Insulating layer, 50 Core layer, 100 Stacked body.

Claims

1. A semiconductor memory device includes: A bit line; A first stack body disposed above the bit line, in which a plurality of first insulating layers and a plurality of first conductive layers are alternately stacked in a first direction. The first stack body has a first stepped region and a first bridging region. The first stepped region is at the center in a second direction intersecting the first direction, causing the ends of the plurality of first conductive layers to be stepped in the second direction. The first bridging region is adjacently disposed to the first stepped region in a third direction intersecting the first direction and the second direction. For each of the plurality of first conductive layers, the storage cell regions on both sides in the second direction are electrically connected to each other across the first stepped region; And A second stack body disposed above the first stack body, in which a plurality of second insulating layers and a plurality of second conductive layers are alternately stacked in the first direction. The second stack body has a second stepped region and a second bridging region. The second stepped region is at the center in the second direction, causing the ends of the plurality of second conductive layers to be stepped in the second direction. The second bridging region is adjacently disposed to the second stepped region in the third direction. For each of the plurality of second conductive layers, the storage cell regions on both sides in the second direction are electrically connected to each other across the second stepped region, The width of the first bridging region in the third direction related to the lowermost layer of the plurality of first conductive layers is greater than the width of the second bridging region in the third direction related to the lowermost layer of the plurality of second conductive layers.

2. The semiconductor memory device according to claim 1, wherein With respect to 100% of the width of the first bridging region in the third direction related to the lowermost layer of the plurality of first conductive layers, the width of the second bridging region in the third direction related to the lowermost layer of the plurality of second conductive layers is in the range of 40% or more and 80% or less.

3. The semiconductor memory device according to claim 1, wherein It further includes a third stack body disposed above the second stack body, in which a plurality of third insulating layers and a plurality of third conductive layers are alternately stacked in the first direction. The third stack body has a third stepped region and a third bridging region. The third stepped region is at the center in the second direction, causing the ends of the plurality of third conductive layers to be stepped in the second direction. The third bridging region is adjacently disposed to the third stepped region in the third direction. For each of the plurality of third conductive layers, the storage cell regions on both sides in the second direction are electrically connected to each other across the third stepped region, The width of the third bridging region in the third direction related to the lowermost layer of the plurality of third conductive layers is greater than the width of the second bridging region in the third direction related to the lowermost layer of the plurality of second conductive layers.

4. The semiconductor memory device according to claim 3, wherein The width in the third direction of the second bridging region associated with the lowermost layer among the plurality of second conductive layers is in the range of 40% or more and 80% or less with respect to 100% of the width in the third direction of the third bridging region associated with the lowermost layer among the plurality of third conductive layers.

5. The semiconductor memory device according to claim 3, wherein the width in the third direction of the first bridging region associated with the lowermost layer among the plurality of first conductive layers is greater than the width in the third direction of the third bridging region associated with the lowermost layer among the plurality of third conductive layers.

6. The semiconductor memory device according to claim 5, wherein the width in the third direction of the third bridging region associated with the lowermost layer among the plurality of third conductive layers is in the range of 50% or more and less than 100% with respect to 100% of the width in the third direction of the first bridging region associated with the lowermost layer among the plurality of first conductive layers.

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