Semiconductor device and forming method

Abstract

One or more support dielectric layers are included under and / or on a nanostructure channel of the nanostructure transistor. Nanostructure transistors may be formed by forming a stack of nanosheets that includes a stack of one or more channel layers sandwiched between sacrificial layers. The nanostructured channel layer stacks may each include a nanostructured channel layer and one or more dielectric support layers underlying and / or on the nanostructured channel layer. The nanosheet stack is etched to define a nanostructure channel of the nanostructure transistor. An inner spacer process is performed to form inner spacers on sidewalls of the sacrificial layer between the nanostructure channel layer stacks and then form source / drain contacts on sidewalls of the nanostructure channel layer stacks and on the inner spacers. The sacrificial layer is then removed in a nanosheet release process, and the sacrificial layer is replaced with a metal gate structure and an associated high-k dielectric layer.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a semiconductor device and a forming method thereof. Background Art

[0002] With the progress of semiconductor device manufacturing and the reduction of the size of technology processing nodes, transistors may be affected by short channel effects (SCEs) such as hot carrier degradation, barrier lowering, and quantum confinement. Additionally, as the gate length of transistors decreases to achieve smaller technology nodes, source / drain (S / D) electron tunneling increases, which increases the off current (the current flowing through the channel of the transistor when the transistor is in an off configuration). Silicon (Si) / silicon germanium (SiGe) nanostructure transistors such as nanowires, nanosheets, and gate-all-around (GAA) devices are potential candidates for overcoming SCEs at smaller technology nodes. Nanostructure transistors are efficient structures that can experience reduced SCEs and enhanced carrier mobility compared to other types of transistors. Summary of the Invention

[0003] Some embodiments described herein provide a method. The method includes forming a layer stack over a substrate of a semiconductor device, the layer stack including a plurality of sacrificial nanostructure layers and a plurality of nanostructure channel layer stacks, wherein the plurality of sacrificial nanostructure layers and the plurality of nanostructure channel layer stacks are arranged in a direction approximately perpendicular to the substrate, and wherein one of the plurality of nanostructure channel layer stacks includes a nanostructure channel layer and at least one support dielectric layer located between the nanostructure channel layer and one of the plurality of sacrificial nanostructure layers. The method includes etching the layer stack to form a fin structure including the plurality of sacrificial nanostructure layers and the plurality of nanostructure channel layer stacks. The method includes etching the plurality of sacrificial nanostructure layers to form cavities between the plurality of nanostructure channel layer stacks. The method includes forming an inner spacer layer in the cavities and on the exposed portions of the plurality of nanostructure channel layer stacks. The method includes performing a dry etching operation to etch the inner spacer layer to form inner spacers in the cavities, wherein the dry etching operation exposes the ends of the plurality of nanostructure channel layer stacks. The method includes forming a source / drain contact layer on the fin structure such that the source / drain contact layer contacts the ends of the plurality of nanostructure channel layer stacks.

[0004] Some embodiments described herein provide a method. The method includes forming a layer stack over a substrate of a semiconductor device, the layer stack including a plurality of sacrificial nanostructure layers and a plurality of nanostructure channel layer stacks, wherein the plurality of sacrificial nanostructure layers and the plurality of nanostructure channel layer stacks are arranged in a direction approximately perpendicular to the substrate, and wherein one of the plurality of nanostructure channel layer stacks includes a nanostructure channel layer and at least one support dielectric layer located between the nanostructure channel layer and one of the plurality of sacrificial nanostructure layers. The method includes etching the layer stack to form a fin structure including the plurality of sacrificial nanostructure layers and the plurality of nanostructure channel layer stacks. The method includes etching the plurality of sacrificial nanostructure layers to form cavities between the plurality of nanostructure channel layer stacks. The method includes forming an inner spacer layer in the cavities and on the exposed portions of the plurality of nanostructure channel layer stacks. The method includes etching the inner spacer layer to form inner spacers in the cavities, wherein etching the inner spacer layer exposes the ends of the plurality of nanostructure channel layer stacks, and wherein the inner spacers have a curved outer surface. The method includes forming a source / drain contact layer on the fin structure such that the source / drain contact layer contacts the ends of the plurality of nanostructure channel layer stacks.

[0005] Some embodiments described herein provide a semiconductor device. The semiconductor device includes a plurality of nanostructured channels arranged in a direction approximately perpendicular to a substrate. The plurality of nanostructured channels comprise a transition metal dichalcogenide (TMD) material. The semiconductor device includes a supporting dielectric layer vertically adjacent to a nanostructured channel among the plurality of nanostructured channels. A first end of the nanostructured channel extends laterally outward from the supporting dielectric layer, and a second end of the nanostructured channel opposite to the first end extends laterally outward from the supporting dielectric layer. The semiconductor device includes a first source / drain contact in contact with a plurality of surfaces of the first end. The semiconductor device includes a second source / drain contact in contact with a plurality of surfaces of the second end. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure will be understood by reading the following detailed description in conjunction with the accompanying drawings. It should be understood that the devices and / or structures shown in the figures are not necessarily drawn to scale. Thus, for clarity of discussion, the dimensions of various features may be arbitrarily increased and / or decreased.

[0007] Figure 1 is a diagram of an exemplary environment in which the systems and / or methods described herein may be implemented.

[0008] Figure 2A and Figure 2B is a diagram of an exemplary embodiment of a fin formation process described herein.

[0009] Figures 3A to 3D is a diagram of an exemplary embodiment of an inner spacer formation process described herein.

[0010] Figure 4 is a diagram of an exemplary embodiment of a source / drain contact layer formation process described herein.

[0011] Figure 5 is a diagram of an exemplary embodiment of a source / drain plug layer formation process described herein.

[0012] Figure 6 is a diagram of an exemplary embodiment of a nanosheet etching process described herein.

[0013] Figures 7A to 7C is a diagram of an exemplary embodiment of a replacement gate (RPG) process described herein.

[0014] Figures 8A to 8C is a diagram of an exemplary embodiment of an inner spacer formation process described herein.

[0015] Figures 9A to 9C It is a diagram of an exemplary implementation of the internal spacer formation process described herein.

[0016] Figures 10A to 10D It is a diagram of an exemplary implementation of the internal spacer formation process described herein.

[0017] Figure 11 It is a diagram of an exemplary component of the device described herein.

[0018] Figure 12 It is a flowchart of an exemplary process associated with forming the semiconductor device described herein.

[0019] Figure 13 It is a flowchart of an exemplary process associated with forming the semiconductor device described herein. Detailed Description

[0020] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the present disclosure may reuse reference numerals and / or letters in various examples. Such reuse is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one component or feature shown in the figures to another (other) component or feature. In addition to the orientation depicted in the figures, the spatially relative terms are also intended to encompass different orientations of the components in use or operation. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0022] In some cases, reducing the geometric and dimensional properties of a fin field-effect transistor (finFET) may degrade the performance of the finFET. As an example, as the finFET technology process node shrinks, the likelihood of short-channel effects such as drain-induced barrier lowering occurring in the finFET may increase. Additionally or alternatively, as the gate length of the finFET decreases, the likelihood of electron tunneling and leakage occurring in the finFET may increase.

[0023] Nanostructure transistors (e.g., nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors, and / or other types of nanostructure transistors) may overcome one or more of the above drawbacks of finFETs. However, nanostructure transistors face fabrication challenges that may lead to performance issues and / or device failures. For example, as the thickness of the nanostructure channel of a nanostructure transistor decreases, the material of the nanostructure channel may not provide sufficient mechanical strength to withstand sagging and / or other mechanical degradation. Although using transition metal dichalcogenide (TMD) materials to replace conventional nanostructure channel materials (such as silicon (Si)) may provide a larger Young's modulus for the nanostructure channel and thus greater mechanical strength at nanoscale thicknesses, the nanostructure channels of nanostructure transistors may still undergo mechanical failures due to exposure to external forces from subsequent semiconductor processing operations (such as film patterning and / or nanosheet release, etc.).

[0024] In some embodiments described herein, one or more support dielectric layers are included under and / or on the nanostructured channel of a nanostructured transistor. A nanostructured transistor can be formed by forming a nanosheet stack that includes one or more channel layer stacks sandwiched between respective sacrificial layers. Each nanostructured channel layer stack can include a nanostructured channel layer and one or more dielectric support layers under and / or on the nanostructured channel layer. The nanosheet stack is etched to define the nanostructured channel of the nanostructured transistor. An inner spacer process is performed to form inner spacers on the sidewalls of the sacrificial layers between each nanostructured channel layer stack, and then source / drain contacts are formed on the sidewalls of the nanostructured channel layer stack and on the inner spacers. Subsequently, the sacrificial layers are removed in a nanosheet release process, and the sacrificial layers are replaced with a metal gate structure and an associated high dielectric constant (high-k) dielectric layer.

[0025] The support dielectric layer can increase the mechanical strength of the nanostructured channel, which enables the use of advanced materials such as TMD materials in the nanostructured channel. This enables the achievement of two-dimensional nanostructured channels (e.g., nanostructured channels with a thickness of approximately one atom) in the nanostructured transistor. Additionally and / or alternatively, the support dielectric layer can reduce the likelihood and / or magnitude of mechanical degradation of the nanostructured channel, which can occur due to external forces from subsequent semiconductor processing operations (such as film patterning and / or nanosheet release, etc.). Thus, the support dielectric layer can provide a larger process window (e.g., a larger temperature range, a larger mechanical stress range) for forming the nanostructured channel. The support dielectric layer can also provide a substrate for the high-k dielectric layer on which the metal gate structure is deposited, which can reduce void formation and improve the thin film growth of the high-k dielectric layer relative to forming the high-k dielectric layer only on the two-dimensional nanostructured channel. The support dielectric layer can increase the structural strength of the vertical stack of nanostructured channels, thereby enabling a large number of nanostructured channels to be achieved on a single vertical stack. The support dielectric layer can also provide sufficient structural strength for the nanostructured channel such that the nanostructured channel can extend laterally outward from the support dielectric layer, which can enable a reduced contact resistance between the nanostructured channel and the source / drain contacts due to a larger contact area that can be achieved between the nanostructured channel and the source / drain contacts. Additionally, the process for forming the support dielectric layer can be integrated with silicon (Si) processing operations.

[0026] Figure 1 is a diagram of an exemplary environment 100 in which the systems and / or methods described herein can be implemented. As Figure 1As shown, the exemplary environment 100 may include a plurality of semiconductor processing tools 102 to 112 and a wafer / die transfer tool 114. The plurality of semiconductor processing tools 102 to 112 may include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, and / or another type of semiconductor processing tool. The tools included in the exemplary environment 100 may be included in semiconductor cleanrooms, semiconductor foundries, semiconductor processing facilities, and / or manufacturing facilities, as well as other facilities.

[0027] The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer on a substrate (e.g., a wafer). In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, a low-pressure CVD (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool (e.g., a sputtering tool or another type of PVD tool). In some embodiments, the deposition tool 102 includes an epitaxial tool configured to form layers and / or regions of a device by epitaxial growth. In some embodiments, the exemplary environment 100 includes multiple types of deposition tools 102.

[0028] The exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a radiation source, such as an ultraviolet (UV) light source (e.g., a deep UV light source, an extreme UV (EUV) light source, and / or a similar light source), an x-ray source, an electron beam (e-beam) source, and / or a similar radiation source. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern can include one or more semiconductor device layer patterns for forming one or more semiconductor devices, can include patterns for forming one or more structures of a semiconductor device, can include patterns for etching various parts of a semiconductor device, and / or similar patterns. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0029] The developing tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source to develop the pattern transferred from the exposure tool 104 to the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the unexposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the exposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by dissolving the exposed or unexposed portions of the photoresist layer using a chemical developer.

[0030] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, a wafer, or a semiconductor device. For example, the etching tool 108 can include a wet etching tool, a dry etching tool, and / or a similar tool. In some embodiments, the etching tool 108 includes a chamber that can be filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 uses plasma etching or plasma-assisted etching to etch one or more portions of the substrate, and the plasma etching or plasma-assisted etching can involve using an ionized gas to perform isotropic etching or directional etching on the one or more portions. In some embodiments, the etching tool 108 includes a plasma-based asher to remove photoresist material and / or another material.

[0031] The planarization tool 110 is a semiconductor processing tool capable of grinding or planarizing the various layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool for grinding or planarizing a layer or surface of a deposited material or a plated material and / or another type of planarization tool. The planarization tool 110 may utilize a combination of chemical forces and mechanical forces (e.g., chemical etching and free abrasive grinding) to grind or planarize the surface of a semiconductor device. The planarization tool 110 may combine a abrasive and corrosive chemical slurry with a polishing pad and a retainer ring (e.g., typically having a diameter larger than that of the semiconductor device). The polishing pad and the semiconductor device may be pressed together by a dynamic polishing head and held in position by the retainer ring. The dynamic polishing head may rotate using different axes of rotation to remove material and flatten any irregular topography of the semiconductor device, thereby flattening or planarizing the semiconductor device.

[0032] The plating tool 112 is a semiconductor processing tool capable of plating a substrate (e.g., a wafer, a semiconductor device, and / or a similar device) or a portion of a substrate with one or more metals. For example, the plating tool 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a compound material or alloy (e.g., tin-silver, tin-lead, and / or a similar material) electroplating device, and / or an electroplating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0033] The wafer / die transfer tool 114 includes a mobile robot, a robotic arm, a tram or a rail vehicle, an overhead hoist transport (OHT) system, an automated material handling system (AMHS), and / or another type of device configured to transfer substrates and / or semiconductor devices between the semiconductor processing tools 102 to 112, configured to transfer substrates and / or semiconductor devices between the various processing chambers of the same semiconductor processing tool, and / or configured to transfer substrates and / or semiconductor devices to other locations (e.g., a wafer cassette, a storage chamber, and / or a similar location) and from other locations (e.g., a wafer cassette, a storage chamber, and / or a similar location). In some embodiments, the wafer / die transfer tool 114 may be a programmed device configured to travel a specific path and / or may be semi-automatic or automatic in operation. In some embodiments, the exemplary environment 100 includes a plurality of wafer / die transfer tools 114.

[0034] For example, the wafer / die transporter 114 can be included in a cluster tool or another type of tool that includes multiple processing chambers, and can be configured to transport substrates and / or semiconductor devices between the multiple processing chambers, transport substrates and / or semiconductor devices between a processing chamber and a buffer region, transport substrates and / or semiconductor devices between a processing chamber and an interface tool (e.g., an equipment front end module (EFEM)), and / or transport substrates and / or semiconductor devices between a processing chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), etc. In some embodiments, the wafer / die transporter 114 can be included in a multi-chamber (or cluster) deposition tool 102, which can include a pre-cleaning processing chamber (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or by-products from a substrate and / or semiconductor device) and multiple types of deposition processing chambers (e.g., processing chambers for depositing different types of materials, processing chambers for performing different types of deposition operations). In these embodiments, the wafer / die transporter 114 is configured to transport substrates and / or semiconductor devices between the various processing chambers of the deposition tool 102 without breaking or removing the vacuum (or at least a partial vacuum) between the various processing chambers and / or between the various processing operations in the deposition tool 102 described herein.

[0035] The semiconductor processing tools 102 to 112 described herein can perform a combination of operations for forming one or more parts of a nanostructure transistor. For example, one or more of the semiconductor processing tools 102 to 112 can be used to perform the following operations: forming a layer stack above a substrate of a semiconductor device, the layer stack including a plurality of sacrificial nanostructure layers and a plurality of nanostructure channel layer stacks, wherein the plurality of sacrificial nanostructure layers and the plurality of nanostructure channel layer stacks are arranged in a direction approximately perpendicular to the substrate, and wherein one nanostructure channel layer stack of the plurality of nanostructure channel layer stacks includes a nanostructure channel layer and at least one support dielectric layer located between the nanostructure channel layer and one sacrificial nanostructure layer of the plurality of sacrificial nanostructure layers; etching the layer stack to form a fin structure including the plurality of sacrificial nanostructure layers and the plurality of nanostructure channel layer stacks; etching the plurality of sacrificial nanostructure layers to form cavities between the plurality of nanostructure channel layer stacks; forming an inner spacer layer in the cavities and on the exposed portions of the plurality of nanostructure channel layer stacks; performing a dry etching operation to etch the inner spacer layer, thereby forming inner spacers in the cavities, wherein the dry etching operation exposes the ends of the plurality of nanostructure channel layer stacks; and / or forming a source / drain contact layer on the fin structure such that the source / drain contact layer contacts the ends of the plurality of nanostructure channel layer stacks and so on.

[0036] As another example, one or more of the semiconductor processing tools 102 to 112 can be used to perform the following operations: forming a layer stack above a substrate of a semiconductor device, the layer stack including a plurality of sacrificial nanostructure layers and a plurality of nanostructure channel layer stacks, wherein the plurality of sacrificial nanostructure layers and the plurality of nanostructure channel layer stacks are arranged in a direction approximately perpendicular to the substrate, and wherein one nanostructure channel layer stack of the plurality of nanostructure channel layer stacks includes a nanostructure channel layer and at least one support dielectric layer located between the nanostructure channel layer and one sacrificial nanostructure layer of the plurality of sacrificial nanostructure layers; etching the layer stack to form a fin structure including the plurality of sacrificial nanostructure layers and the plurality of nanostructure channel layer stacks; etching the plurality of sacrificial nanostructure layers to form cavities between the plurality of nanostructure channel layer stacks; forming an inner spacer layer in the cavities and on the exposed portions of the plurality of nanostructure channel layer stacks; etching the inner spacer layer to form inner spacers in the cavities, wherein etching the inner spacer layer exposes the ends of the plurality of nanostructure channel layer stacks, and wherein the inner spacers have a curved outer surface; and / or forming a source / drain contact layer on the fin structure such that the source / drain contact layer contacts the ends of the plurality of nanostructure channel layer stacks and so on.

[0037] In some embodiments, one or more of semiconductor processing tools 102 to 112 may be used to implement the combination Figure 2A , Figure 2B , Figures 3A to 3D , Figure 4 , Figure 5 , Figure 6 , Figures 7A to 7C , Figures 8A to 8C , Figures 9A to 9C , Figures 10A to 10D , Figure 12 and / or Figure 13 and one or more of the semiconductor processing operations illustrated in other figures.

[0038] Figure 1 The number and arrangement of the devices shown in Figure 1 are provided as one or more examples. In practice, compared to the devices shown in Figure 1 there may be additional devices, fewer devices, different devices, or devices arranged in a different manner. Additionally, Figure 1 two or more of the devices shown in

[0039] Figure 2A and Figure 2B may be implemented within a single device, or Figure 2A and Figure 2B the single device shown in Figure 2A and Figure 2B may be implemented as multiple distributed devices. Additionally or alternatively, a set of devices (e.g., one or more devices) of the exemplary environment 100 may perform one or more functions described as being performed by another set of devices of the exemplary environment 100.

[0040] Figure 2A shows a perspective view of the semiconductor device 205. AsFigure 2A As shown, the processing of the semiconductor device 205 can be implemented in combination with the semiconductor substrate 210. The semiconductor substrate 210 can include a silicon (Si) substrate, a substrate formed of a silicon-containing material, a group III-V compound semiconductor material substrate (such as gallium arsenide (GaAs)), a silicon on insulator (SOI) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or another type of semiconductor substrate. The semiconductor substrate 210 can include various layers, and the various layers include a conductive layer or an insulating layer formed on the semiconductor substrate. The semiconductor substrate 210 can contain a compound semiconductor and / or an alloy semiconductor. The semiconductor substrate 210 can include various doping configurations to meet one or more design parameters. For example, different doping profiles (e.g., n-well, p-well) can be formed on the semiconductor substrate 210 in regions designed for different device types (e.g., p-type metal-oxide semiconductor (PMOS) nanostructure transistors, n-type metal-oxide semiconductor (NMOS) nanostructure transistors). Suitable doping can include ion implantation and / or diffusion processes of dopants. In addition, the semiconductor substrate 210 can include an epitaxial (epi) layer (epi layer), which can be strained to enhance performance, and / or can have other suitable enhancement features. The semiconductor substrate 210 can include a portion of a semiconductor wafer on which other semiconductor devices are formed.

[0041] As Figure 2A further shown, an isolation layer 215 is formed on the semiconductor substrate 210. The isolation layer 215 can provide electrical isolation between the transistors of the semiconductor device 205 and the semiconductor substrate 210, which can reduce the current leaking into the semiconductor substrate 210 and improve the operating efficiency of the transistors. The isolation layer 215 can contain one or more electrically insulating materials, such as one or more dielectric materials. For example, the isolation layer 215 can contain silicon oxide (SiO x , such as SiO2), silicon nitride (Si x N y , such as Si3N4), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), aluminum oxide (Al x O y , such as Al2O3), hafnium oxide (HfO x, such as HfO2), low dielectric constant (low-k) dielectric materials, high dielectric constant (high-k) dielectric materials, and / or another suitable insulating material. The deposition tool 102 can be used to deposit the isolation layer 215 using PVD technology, ALD technology, CVD technology, oxidation technology, combined with Figure 1 Another type of deposition technology described and / or another suitable deposition technology to deposit the isolation layer 215. The isolation layer 215 can be deposited in one or more deposition operations. In some embodiments, a planarization tool 110 can be used to planarize the isolation layer 215 after depositing the isolation layer 215.

[0042] Such as Figure 2A As further shown in, a layer stack 220 is formed on the isolation layer 215. The layer stack 220 includes a plurality of alternating layers arranged in a direction approximately perpendicular to the semiconductor substrate 210. For example, the layer stack 220 includes vertical alternating layers of a sacrificial nanostructure layer 225 and a channel layer stack 230 above the semiconductor substrate 210. Figure 2A The number of the sacrificial nanostructure layers 225 and the number of the channel layer stacks 230 shown in are only examples, and other numbers of the sacrificial nanostructure layers 225 and other numbers of the channel layer stacks 230 are also within the scope of this disclosure.

[0043] The sacrificial nanostructure layer 225 includes a first material composition, and the channel layer stack 230 includes a second material composition. In some embodiments, the first material composition and the second material composition are the same material composition. In some embodiments, the first material composition and the second material composition are different material compositions. As an example, the sacrificial nanostructure layer 225 can include silicon nitride (Si x N y ), and the channel layer stacks 230 can each include a combination of nanostructure layers that include silicon oxide (SiO x ), and / or one or more TMD materials. In some embodiments, the first material composition and the second material composition have different oxidation rates and / or etching selectivities, which enables the subsequent removal of the sacrificial nanostructure layer 225 during the nanosheet release operation while minimizing the removal of the materials of the channel layer stack 230 to the extent that they are not removed. Other examples of the materials of the sacrificial nanostructure layer 225 include silicon oxide (SiO x ), silicon carbonitride (SiCN), and / or silicon germanium (SiGe), etc.

[0044] Such as Figure 2AAs shown in the detailed view of the channel layer stack 230 in [description], each channel layer stack 230 may include a nanostructured channel layer 235 and at least one support dielectric layer, such as a bottom support dielectric layer 240 located below the nanostructured channel layer 235 and / or a top support dielectric layer 245 located on the nanostructured channel layer 235. In some embodiments, only the bottom support dielectric layer 240 is included between the nanostructured channel layer 235 and the underlying sacrificial nanostructure layer 225, and the top support dielectric layer 245 is omitted from the semiconductor device 205. In these embodiments, the top surface of the nanostructured channel layer 235 may be in direct physical contact with the sacrificial nanostructure layer 225 located above the nanostructured channel layer 235. In some embodiments, only the top support dielectric layer 245 is included between the nanostructured channel layer 235 and the sacrificial nanostructure layer 225 located above the nanostructured channel layer 235, and the bottom support dielectric layer 240 is omitted from the semiconductor device 205. In these embodiments, the bottom surface of the nanostructured channel layer 235 may be in direct physical contact with the sacrificial nanostructure layer 225 located below the nanostructured channel layer 235.

[0045] The support dielectric layer may provide increased mechanical strength to the nanostructured channel layer 235, which may enable the use of advanced materials such as TMDs in the nanostructured channel layer 235. This enables the achievement of two-dimensional nanostructured channels (e.g., nanostructured channels with a thickness of one atom) in the transistors of the semiconductor device 205. Additionally and / or alternatively, the support dielectric layer may reduce the likelihood and / or extent of mechanical degradation of the nanostructured channel layer 235, which may occur due to external forces from subsequent semiconductor processing operations (such as film patterning and / or nanosheet release for removing the sacrificial nanostructure layer 225, etc.).

[0046] The nanostructured channel layer 235 may comprise one or more semiconductor materials, such as silicon (Si), silicon germanium (SiGe), and / or germanium (Ge), etc. Additionally and / or alternatively, the nanostructured channel layer 235 may comprise one or more TMD materials, such as molybdenum disulfide (MoS2), tungsten disulfide (WS2), and / or tungsten selenide (WSe2), etc.

[0047] The bottom support dielectric layer 240 and / or the top support dielectric layer 245 may comprise one or more dielectric materials, such as silicon oxide (SiO x , such as SiO2), silicon nitride (Si x N y , such as Si3N4), silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), aluminum oxide (Al x O y , such as Al2O3), hafnium oxide (HfO x, such as HfO2), low dielectric constant (low-k) dielectric materials, high dielectric constant (high-k) dielectric materials, and / or another suitable insulating material. Additionally and / or alternatively, a nanostructured two-dimensional insulating material (e.g., an insulating material having a crystalline structure with an atomic thickness) (e.g., boron nitride (BN)) can be used for the bottom support dielectric layer 240 and / or the top support dielectric layer 245. In some embodiments, the bottom support dielectric layer 240 and the top support dielectric layer 245 comprise the same dielectric material and / or the same material composition. In some embodiments, the bottom support dielectric layer 240 and the top support dielectric layer 245 comprise different dielectric materials and / or different material compositions.

[0048] Various techniques can be used to form the channel layer stack 230 on the sacrificial nanostructure layer 225. For example, the bottom support dielectric layer 240 of the channel layer stack 230 can be deposited or transferred onto the sacrificial nanostructure layer 225, the nanostructured channel layer 235 of the channel layer stack 230 can be deposited or transferred onto the bottom support dielectric layer 240, and the top support dielectric layer 245 of the channel layer stack 230 can be deposited or transferred onto the nanostructured channel layer 235. Another sacrificial nanostructure layer 225 can be deposited on the top support dielectric layer 245.

[0049] As another example, the bottom support dielectric layer 240 can be omitted, and the nanostructured channel layer 235 can be deposited or transferred onto the underlying sacrificial nanostructure layer 225. The top support dielectric layer 245 of the channel layer stack 230 can be deposited or transferred onto the nanostructured channel layer 235, and another sacrificial nanostructure layer 225 can be deposited on the top support dielectric layer 245.

[0050] As another example, the bottom support dielectric layer 240 can be deposited or transferred onto the underlying sacrificial nanostructure layer 225, the nanostructured channel layer 235 can be deposited or transferred onto the bottom support dielectric layer 240, and another sacrificial nanostructure layer 225 can be deposited on the top support dielectric layer 245 (omitting the top support dielectric layer 245).

[0051] The deposition tool 102 can be used to deposit the sacrificial nanostructure layer 225 of the layer stack 220 using PVD techniques, ALD techniques, CVD techniques, oxidation techniques, another type of deposition technique described in combination Figure 1 with, and / or another suitable deposition technique. The sacrificial nanostructure layer 225 of the layer stack 220 can be deposited in one or more deposition operations respectively.

[0052] In some embodiments, the deposition tool 102 is used to deposit using PVD techniques, ALD techniques, CVD techniques, oxidation techniques, in combination Figure 1Another type of deposition technique described and / or another suitable deposition technique is used to deposit the bottom support dielectric layer 240 and / or the top support dielectric layer 245 of the layer stack 220. The bottom support dielectric layer 240 and / or the top support dielectric layer 245 of the layer stack 220 can be deposited in one or more deposition operations, respectively. In some embodiments, the bottom support dielectric layer 240 and / or the top support dielectric layer 245 of the layer stack 220 are grown on a sacrificial substrate to have a specific crystalline structure (e.g., in the case of two-dimensional boron nitride, for example) and then transferred to the semiconductor device 205 to form the layer stack 220.

[0053] In some embodiments, the deposition tool 102 is used to utilize PVD technology, ALD technology, CVD technology, oxidation technology, combined with Figure 1 Another type of deposition technique described and / or another suitable deposition technique is used to deposit the nanostructured channel layer 235 of the layer stack 220. The nanostructured channel layer 235 of the layer stack 220 can be deposited in one or more deposition operations, respectively. In some embodiments, the nanostructured channel layer 235 of the layer stack 220 is grown on a sacrificial substrate (e.g., a sapphire substrate or an alumina (Al2O3) substrate) to have a specific crystalline structure (e.g., in the case of a two-dimensional TMD nanostructured channel layer 235, for example) and then transferred to the semiconductor device 205 to form the layer stack 220. The nanostructured channel layer 235 can be grown to a thickness of one layer, which means that each of the nanostructured channel layers 235 is one atomic layer of a TMD material.

[0054] As further shown in the detailed view of the channel layer stack 230, the bottom support dielectric layer 240 can have a dimension D1 corresponding to the thickness of the bottom support dielectric layer 240. In some embodiments, the dimension D1 is in the range of approximately 1 nanometer to approximately 3 nanometers. If the dimension D1 is less than approximately 1 nanometer, the deposition uniformity of the bottom support dielectric layer 240 may be uncontrollable and voids and / or other discontinuities may occur in the bottom support dielectric layer 240. If the dimension D1 is greater than approximately 3 nanometers, the thickness of the bottom support dielectric layer 240 may be too large to form high-density transistors on the semiconductor device 205. If the dimension D1 is in the range of approximately 1 nanometer to approximately 3 nanometers, a continuous film with minimized voids or other discontinuities can be formed for the bottom support dielectric layer 240 while enabling the formation of high-density transistors on the semiconductor device 205. However, other values of the dimension D1 and ranges other than approximately 1 nanometer to approximately 3 nanometers are also within the scope of this disclosure.

[0055] As further shown in the detailed view of the channel layer stack 230, the top support dielectric layer 245 may have a dimension D2 corresponding to the thickness of the top support dielectric layer 245. In some embodiments, the dimension D2 ranges from approximately 1 nanometer to approximately 3 nanometers. If the dimension D2 is less than approximately 1 nanometer, the deposition uniformity of the top support dielectric layer 245 may be uncontrollable and voids and / or other discontinuities may occur in the top support dielectric layer 245. If the dimension D2 is greater than approximately 3 nanometers, the thickness of the top support dielectric layer 245 may be too large such that high-density transistors cannot be formed on the semiconductor device 205. If the dimension D2 ranges from approximately 1 nanometer to approximately 3 nanometers, a continuous film with minimized voids or other discontinuities can be formed for the top support dielectric layer 245 while enabling the formation of high-density transistors on the semiconductor device 205. However, other values of the dimension D2 and ranges other than approximately 1 nanometer to approximately 3 nanometers are also within the scope of this disclosure.

[0056] As further shown in the detailed view of the channel layer stack 230, the nanostructured channel layer 235 may have a dimension D3 corresponding to the thickness of the nanostructured channel layer 235. In some embodiments, the dimension D3 corresponds to the nanostructured channel layer 235 having a thickness of one layer (e.g., a layer of TMD material having an atomic thickness). In some embodiments, the dimension D3 is greater than or equal to approximately 0.5 nanometer and less than approximately 1 nanometer. However, other values and ranges of the dimension D3 are also within the scope of this disclosure.

[0057] As Figure 2A further shown, one or more additional layers may be formed on and / or over the layer stack 220. For example, a hard mask (HM) layer 250 may be formed on and / or over the layer stack 220 (e.g., on the topmost sacrificial nanostructure layer 225 of the layer stack 220). The hard mask layer 250 may comprise silicon nitride (Si x N y ), silicon oxide (SiO x ), and / or another dielectric material. The hard mask layer 250 may be deposited using the deposition tool 102 with PVD techniques, ALD techniques, CVD techniques, oxidation techniques, another type of deposition technique described in combination Figure 1 and / or another suitable deposition technique. The hard mask layer 250 may be deposited in one or more deposition operations. In some embodiments, the hard mask layer 250 may be planarized using the planarization tool 110 after depositing the hard mask layer 250.

[0058] As Figure 2BAs shown, another hard mask layer 255 can be formed over and / or on the hard mask layer 250. The hard mask layer 255 can include one or more metal materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), their alloys, and other metal examples. The hard mask layer 255 can be deposited using the deposition tool 102 and / or the plating tool 112 by PVD technology, ALD technology, CVD technology, electroplating technology, combined with Figure 1 the other type of deposition technology described and / or another suitable deposition technology to deposit the hard mask layer 255. The hard mask layer 255 can be deposited in one or more deposition operations. In some embodiments, a planarization tool 110 can be used to planarize the hard mask layer 255 after depositing the hard mask layer 255.

[0059] As Figure 2B further shown, the hard mask layers 250 and 255 are used to pattern the layer stack 220 to form fin structures 260 from the layer stack 220. For example, patterns can be formed in the hard mask layers 250 and 255, and the patterns in the hard mask layers 250 and 255 can be used to etch the layer stack 220 to form fin structures 260 above the isolation layer 215. The etching of the layer stack 220 can terminate on the isolation layer 215; however, a portion of the isolation layer 215 can be removed during the etching of the layer stack 220 (this is called over-etching) to ensure complete etching through the layer stack 220.

[0060] In some embodiments, the patterns in the photoresist layer are used to etch the hard mask layer 250 and / or 255 to transfer the patterns to the hard mask layer 250 and / or 255. In these embodiments, a photoresist layer can be formed on the hard mask layer 255 using the deposition tool 102. The photoresist layer can be exposed to a radiation source using the exposure tool 104 to pattern the photoresist layer. Some portions of the photoresist layer can be developed and removed using the development tool 106 to expose the patterns. The hard mask layer 250 and / or 255 can be etched based on the patterns using the etching tool 108 to transfer the patterns to the hard mask layer 250 and / or 255. In some embodiments, the patterns are transferred to the hard mask layer 255 using the photoresist layer, and the patterns are transferred from the hard mask layer 255 to the hard mask layer 250 using the etching tool 108. In some embodiments, the patterns are transferred to the hard mask layers 250 and 255 using the photoresist layer.

[0061] Etching tool 108 can be used to etch layer stack 220 based on the patterns in hard mask layers 250 and 255 to form fin structures 260 in one or more etching operations. In some embodiments, the etching operation includes a dry etching operation (e.g., a plasma etching operation). In some embodiments, the etching operation includes a wet chemical etching operation and / or another type of etching operation. In some embodiments, multiple etching operations are performed to cyclically etch layer stack 220 to obtain sidewalls of fin structures 260 that are approximately orthogonal to the surface of semiconductor substrate 210. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, as an alternative, a liftoff process can be used to pattern hard mask layers 250 and 255.

[0062] As Figure 2B shown, fin structures 260 extend above semiconductor substrate 210 and above isolation layer 215. Fin structures 260 include the remaining portion of layer stack 220 that is not removed during the etching of layer stack 220. The remaining portion includes some portions of sacrificial nanostructure layer 225 of layer stack 220 and some portions of channel layer stack 230 (including some portions of bottom support dielectric layer 240 and / or some portions of top support dielectric layer 245 and some portions of nanostructure channel layer 235).

[0063] As described above, Figure 2A and Figure 2B are provided as examples. Other examples may be different from the examples described for Figure 2A and Figure 2B Illustrative embodiments 200 may include additional operations, fewer operations, different operations, and / or operations in a different order compared to the operations described in connection with Figure 2A and Figure 2B Illustrated.

[0064] Figures 3A to 3D is a diagram of an exemplary embodiment 300 of the inner spacer formation process described herein. Exemplary embodiment 300 includes an example of forming inner spacers on fin structures 260. The inner spacers are formed to provide electrical isolation between the gate structure of a transistor in semiconductor device 205 and the source / drain contact layer of the transistor, which reduces the likelihood of an electrical short circuit occurring between the gate structure and the source / drain contact layer. The inner spacers can also reduce the parasitic capacitance in the transistor and can protect the source / drain contact layer from etching during the nanosheet release operation for removing sacrificial nanostructure layer 225. In some embodiments, in combination with Figure 2A andFigure 2B Perform the operations described in connection with Example Implementation 300 after the process described.

[0065] As Figure 3A shown, in the etching operation, the sacrificial nanostructure layer 225 of the fin structure 260 is etched laterally (e.g., in a direction approximately parallel to the top surface of the semiconductor substrate 210), thereby forming cavities 305 between portions of the channel layer stack 230. Specifically, the etching tool 108 is used to etch the ends of the sacrificial nanostructure layer 225 laterally to form cavities 305 between the ends of the channel layer stacks 230. In some embodiments, an etchant is used to etch the sacrificial nanostructure layer 225, and the etching rate of the etchant for the sacrificial nanostructure layer 225 can be greater than the etching rate of the etchant for the channel layer stack 230, such that etching of the channel layer stack 230 is minimized. Forming the cavities 305 causes the ends of the channel layer stack 230 to extend laterally outward from the sacrificial nanostructure layer 225.

[0066] As Figure 3B shown, an inner spacer layer 310 is conformally deposited along the sidewalls and the top of the fin structure 260. Specifically, the inner spacer layer 310 is conformal to the profile of the fin structure 260 such that the inner spacer layer 310 is formed as a thin film in the cavities 305 on the ends of the sacrificial nanostructure layer 225. The inner spacer layer 310 is also deposited on the exposed surfaces (e.g., top surface, bottom surface, side surfaces, end surfaces) of the channel layer stack 230 that extend laterally outward from the sacrificial nanostructure layer 225. The inner spacer layer 310 can be deposited using the deposition tool 102 by means of CVD techniques, PVD techniques, and ALD techniques and / or another deposition technique.

[0067] In some embodiments, the inner spacer layer 310 comprises silicon nitride (Si x N y ), silicon oxide (SiO x ), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and / or another dielectric material. In some embodiments, the inner spacer layer 310 comprises a metal oxide-based material, such as tungsten oxide (WO x ), molybdenum oxide (MoO x ), and / or another metal oxide-based material.

[0068] As Figure 3CAs shown, the inner spacer layer 310 is partially removed such that the remaining portion of the inner spacer layer 310 corresponds to the inner spacer 315 in the cavity 305. An etching operation to partially remove the inner spacer layer 310 to form the inner spacer 315 can be implemented using an etching tool 108. The etching operation 320 can include a highly directional etching to selectively remove the inner spacer layer 310 from the end of the channel layer stack 230 without removing (or minimizing the removal from) the inner spacer layer 310 from the cavity 305. Specifically, the highly directional etching operation 320 can include a vertical etching in which the inner spacer layer 310 is etched mainly in a direction approximately perpendicular to the surface of the semiconductor substrate 210. Dry etching techniques such as plasma-based etching techniques can be used to achieve the vertical etching. For example, the pressure in the etching tool 108, the bias voltage of the plasma, and / or another parameter of the etching tool 108 can be selected to achieve the vertical etching.

[0069] As Figure 3C shown in the detailed view of, since the end 325 of the inner spacer 315 is approximately in the same horizontal plane 330 as the end of the channel layer stack 230, the end 325 of the inner spacer 315 can be approximately coplanar with the end of the channel layer stack 230 (e.g., with the end of the nanostructured channel layer 235, the end of the bottom support dielectric layer 240, and / or the end of the top support dielectric layer 245). The end 325 of the inner spacer 315 can have an angle of approximately 90 degrees (e.g., approximately 85 degrees to 95 degrees) with respect to the nanostructured channel layer 235, the bottom support dielectric layer 240, and / or the top support dielectric layer 245 (indicated as dimension D4 in Figure 3C . However, other values of the angle are also within the scope of this disclosure.

[0070] As Figure 3D shown in the perspective view of the fin structure 260 in, the inner spacer 315 can have an approximately C-shaped cross-sectional profile. The inner spacer 315 can extend along the fin structure 260. The inner spacer 315 can include a section on the sidewall of the sacrificial nanostructure layer 225, a section on the top surface of the channel layer stack 230, and a section on the bottom surface of another channel layer stack 230.

[0071] As described above, Figures 3A to 3D is provided as an example. Other examples can be different from the example described for Figures 3A to 3D . Compared with the operations described in connection with Figures 3A to 3D , the exemplary implementation 300 can include additional operations, fewer operations, different operations, and / or operations in a different order.

[0072] Figure 4FIG. is a diagram of an exemplary implementation 400 of a source / drain contact layer formation process described herein. Exemplary implementation 400 includes an example of forming a source / drain contact layer on a fin structure 260 of a semiconductor device 205. In some implementations, the operations described in connection with exemplary implementation 400 are performed after the process described in connection with Figures 2A to 3D is described.

[0073] As shown in Figure 4 , a source / drain contact layer 405 is formed on the fin structure 260. The source / drain contact layer 405 fills the remaining region of the cavity 305 where the inner spacer 315 was previously formed. The source / drain contact layer 405 is also formed on the exposed ends of the channel layer stack 230 (including on the exposed ends of the nanostructured channel layer 235, on the exposed ends of the bottom support dielectric layer 240, and / or on the exposed ends of the top support dielectric layer 245).

[0074] The source / drain contact layer 405 can be deposited using a deposition tool 102 and / or a plating tool 112 with PVD technology, ALD technology, CVD technology, electroplating technology, another type of deposition technology described in connection with Figure 1 and / or another suitable deposition technology. The source / drain contact layer 405 can be deposited in one or more deposition operations. In some implementations, a deposition technology with high step coverage is used to deposit the source / drain contact layer 405. "Step coverage" refers to the uniformity of coverage on surfaces of different heights, angles, and / or shapes. A deposition technology with high step coverage is a deposition technology that can achieve a highly uniform deposition rate on surfaces of the fin structure 260 at different heights and / or angles and with various shapes. This enables the source / drain contact layer 405 to be formed in the cavity 305 and on the ends of the channel layer stack 230 while achieving a continuous layer in the source / drain contact layer 405 that is minimized to have no voids or other discontinuities.

[0075] In some implementations, the source / drain contact layer 405 includes one or more metal materials, one or more metal alloys, one or more semimetals, one or more semimetal TMD materials, combinations thereof, and / or another suitable material. For example, the source / drain contact layer 405 can include a nitrogen-rich transition metal nitride (such as Mo5N6). As another example, the source / drain contact layer 405 can include platinum selenide (PtSe2), titanium (Ti), titanium nitride (TiN), tungsten (W), cobalt (Co), bismuth (Bi), and / or antimony (Sb), etc.

[0076] As described above, Figure 4 is provided as an example. Other examples may be different from those described forFigure 4 The examples described. Compared with the operations combined Figure 4 with the operations described, the exemplary implementation 400 may include additional operations, fewer operations, different operations, and / or operations in a different order.

[0077] Figure 5 FIG. is an illustration of an exemplary implementation 500 of the source / drain plug layer formation process described herein. In some implementations, after the process combined Figures 2A to 4 with the operations described in the exemplary implementation 500 is performed.

[0078] As Figure 5 shown in, a source / drain plug layer 505 is formed on the source / drain contact layer 405. The source / drain plug layer 505 can be deposited using the deposition tool 102 and / or the plating tool 112 with PVD technology, ALD technology, CVD technology, electroplating technology, another type of deposition technology combined Figure 1 with the deposition technology described and / or another suitable deposition technology. The source / drain plug layer 505 can be deposited in one or more deposition operations. The source / drain plug layer 505 includes one or more metal materials, one or more metal alloys, one or more semimetals, one or more semimetal TMD materials, combinations thereof, and / or another suitable material. For example, the source / drain plug layer 505 can include tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), and / or ruthenium (Ru), etc.

[0079] In some implementations, one or more liners are deposited on the source / drain contact layer 405, and the source / drain plug layer 505 is deposited on the one or more liners. The one or more liners can include adhesion liners for promoting adhesion between the source / drain contact layer 405 and the source / drain plug layer 505, barrier layers for inhibiting material migration of the source / drain plug layer 505 into the surrounding layers, and / or another type of liner. Examples of materials for the one or more liners include nickel (Ni), titanium (Ti), titanium nitride (TiN), and / or tantalum nitride (TaN), etc.

[0080] As Figure 5As further shown, the hard mask layers 250 and 255 are removed from the fin structure 260 of the semiconductor device 205. The hard mask layers 250 and 255 can be removed from the fin structure 260 after the source / drain plug layer 505 is formed. Forming the source / drain plug layer 505 before removing the hard mask layers 250 and 255 enables the removal of the hard mask layers 250 and 255 to form separate source / drain contact layers 405 on opposite sides of the fin structure 260 and separate source / drain plug layers 505 on opposite sides of the fin structure 260 without using an additional shielding layer. In other words, removing the hard mask layers 250 and 255 divides the source / drain contact layer 405 into separate source / drain contact layers 405 and divides the source / drain plug layer 505 into separate source / drain plug layers 505 without using an additional shielding layer to pattern the source / drain contact layer 405 and the source / drain plug layer 505. Therefore, the formation of the source / drain contact layer 405 and the formation of the source / drain plug layer 505 are self-aligned. In this way, the source / drain contact layers 405 located on opposite sides of the fin structure 260 do not directly contact each other, and the source / drain plug layers 505 located on opposite sides of the fin structure 260 do not directly contact each other, which reduces the possibility of electrical short circuits.

[0081] A planarization tool 110 can be used to perform a planarization operation to remove the hard mask layers 250 and 255 and remove the excess material of the source / drain contact layer 405 and the excess material of the source / drain plug layer 505 to form separate source / drain contact layers 405 and separate source / drain plug layers 505. The planarization operation can terminate on the topmost sacrificial nanostructure layer 225 such that the top surface of the topmost sacrificial nanostructure layer 225 is exposed.

[0082] As described above, Figure 5 is provided as an example. Other examples may be different from the example described for Figure 5 elaborated. Compared with the operations described in connection with Figure 5 elaborated, the exemplary embodiment 500 may include additional operations, fewer operations, different operations, and / or operations in a different order.

[0083] Figure 6 is a diagram of an exemplary embodiment 600 of the nanosheet etching process described herein. The nanosheet etching process can be performed to etch the fin structure 260 and the associated source / drain contact layer 405 and source / drain plug layer 505 to define a plurality of nanostructure transistors 605. In some embodiments, the operations described in connection with the exemplary embodiment 600 are performed after the process described in connection with Figures 2A to 5 elaborated.

[0084] As Figure 6As shown, the fin structure 260 is etched to define the nanostructure transistor 605. The nanostructure transistor 605 extends over the semiconductor substrate 210 and over the isolation layer 215. The nanostructure transistor 605 includes portions of the fin structure 260, such as portions of the channel layer stack 230 (e.g., portions of the nanostructure channel layer 235, portions of the bottom support dielectric layer 240, portions of the top support dielectric layer 245), portions of the sacrificial nanostructure layer 225, and portions of the inner spacer 315. The portions of the nanostructure channel layer 235 correspond to the nanostructure channel 610 of the nanostructure transistor 605. The portions of the bottom support dielectric layer 240 correspond to the bottom support dielectric layer 615 of the nanostructure transistor 605. The portions of the top support dielectric layer 245 correspond to the top support dielectric layer 620 of the nanostructure transistor 605. The portions of the sacrificial nanostructure layer 225 correspond to the sacrificial structures 625 located between the nanostructure channels 610. The portions of the inner spacer 315 correspond to the inner spacers 630 located between the nanostructure channels 610.

[0085] The bottom support dielectric layer 615 and the top support dielectric layer 620 can be adjacent to the nanostructure channel 610 in the vertical direction such that the nanostructure channel 610 is located between the bottom support dielectric layer 615 and the top support dielectric layer 620 in the vertical direction. In some embodiments, the bottom support dielectric layer 615 and the top support dielectric layer 620 comprise the same dielectric material and / or the same material composition. In some embodiments, the bottom support dielectric layer 615 and the top support dielectric layer 620 comprise different dielectric materials and / or different material compositions.

[0086] In some embodiments, only the bottom support dielectric layer 615 is included between the nanostructure channel 610 and the underlying sacrificial structure 625, and the top support dielectric layer 620 is omitted from the semiconductor device 205. In these embodiments, the top surface of the nanostructure channel 610 can make direct physical contact with the sacrificial structure 625 located above the nanostructure channel 610. In some embodiments, only the top support dielectric layer 620 is included between the nanostructure channel 610 and the sacrificial structure 625 located above the nanostructure channel 610, and the bottom support dielectric layer 615 is omitted from the semiconductor device 205. In these embodiments, the bottom surface of the nanostructure channel 610 can make direct physical contact with the sacrificial structure 625 located below the nanostructure channel 610.

[0087] In the nanosheet etching process, the source / drain contact layer 405 and the source / drain plug layer 505 are also etched to define source / drain contacts 635 and 640 on opposite sides of the nanostructure channel 610 of the nanostructure transistor 605 and to define source / drain plugs 645 and 650 on opposite sides of the nanostructure channel 610 of the nanostructure transistor 605. "Source / drain" may refer to the source or the drain individually or jointly depending on the context. The source / drain contact 635 may be located on the first end of the nanostructure channel 610 of the nanostructure transistor 605 (and may be in contact with the first end), and the source / drain contact 640 may be located on the second end of the nanostructure channel 610 opposite the first end (and may be in contact with the second end). The source / drain contacts 635 and 640 may each have an approximately C-shaped cross-sectional profile. The source / drain plug 645 may be located on the source / drain contact 635, and the source / drain plug 650 may be located on the source / drain contact 640.

[0088] In some embodiments, one or more hard mask layers (e.g., using deposition tool 102) may be formed over and / or on the fin structure 260, the source / drain contact layer 405, and / or the source / drain plug layer 505. The one or more hard mask layers may be used to perform the nanosheet etching process to define the nanostructure transistor 605. For example, a dielectric hard mask layer and a metal hard mask layer similar to the hard mask layers 250 and 255 may be formed. A pattern may be formed in the metal hard mask layer (e.g., using etching tool 108 and / or a lift-off process) and then transferred to the dielectric hard mask layer (e.g., using etching tool 108). Dry etching techniques and / or another suitable etching technique may be used to etch the fin structure 260, the source / drain contact layer 405, and / or the source / drain plug layer 505 based on the pattern (e.g., using etching tool 108). In some embodiments, multiple etching operations are performed to cyclically etch the fin structure 260, the source / drain contact layer 405, and / or the source / drain plug layer 505 to obtain sidewalls of the nanostructure transistor 605 that are approximately orthogonal to the surface of the semiconductor substrate 210. The hard mask layer may then be removed.

[0089] As described above, Figure 6 is provided as an example. Other examples may be different from the example Figure 6 described. Compared to the operations Figure 6 described, the exemplary embodiment 600 may include additional operations, fewer operations, different operations, and / or operations in a different order.

[0090] Figures 7A to 7CThis is a diagram of an exemplary implementation 700 of a replacement gate (RPG) process described herein. Exemplary implementation 700 includes an example of a replacement gate process for replacing a sacrificial structure 625 using a gate structure (e.g., a replacement gate structure) of a nanostructure transistor 605 of a semiconductor device 205. In some implementations, the operations described in conjunction with exemplary implementation 700 are performed after the operations described in conjunction with Figures 3A to 6 are performed.

[0091] As Figure 7A shown, a nanosheet release operation of the RPG process is performed to remove the sacrificial structure 625 from the nanostructure transistor 605. This creates openings between and around the nanostructure channels 610. The nanostructure release operation may include performing an etching operation using an etching tool 108 to remove the sacrificial structure 625 based on an etching selectivity difference between the material of the sacrificial structure 625 and the material of the nanostructure channels 610 and an etching selectivity difference between the material of the sacrificial structure 625 and the material of the inner spacer 630. The inner spacer 630 may be used as an etch stop layer in the etching operation to protect the source / drain contacts 635 and 640 from etching.

[0092] The etching operation for removing the sacrificial structure 625 may include an isotropic etching technique for etching the sacrificial structure 625 in multiple directions to completely remove the sacrificial structure 625. As an example, a wet etching technique may be used to remove the sacrificial structure 625. As another example, a hydrofluoric acid (HF) vapor etching technique may be used to remove the sacrificial structure 625. As another example, a carbon fluoride-based plasma etching technique may be used to remove the sacrificial structure 625. The carbon fluoride-based plasma etching technique may include using a carbon tetrafluoride (CF4) etchant in which carbon tetrafluoride radicals are used to etch the sacrificial structure 625.

[0093] As Figure 7BAs shown, continue with the RPG operation, in which a gate structure (e.g., replacement gate structure) 705 of the nanostructure transistor 605 is formed between the nanostructure channels 610, in the openings between and around the nanostructure channels 610, and between the inner spacers 630. The gate structure 705 wraps around at least three sides of the nanostructure channel 610. Specifically, the gate structure 705 fills the regions between the nanostructure channels 610 and around the nanostructure channels 610 that were previously occupied by the sacrificial structure 625, such that the gate structure 705 completely wraps around the nanostructure channel 610 and surrounds the nanostructure channel 610. The gate structure 705 may include a metal gate structure that includes one or more metals, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), their alloys, and other metal examples. Additionally and / or alternatively, the gate structure 705 may include one or more p-type work function metals, one or more n-type work function metals, and / or another type of work function metal.

[0094] A gate dielectric layer 710 of the nanostructure transistor 605 may be formed in the opening around the nanostructure channel 610 before forming the gate structure 705. The gate structure 705 may be formed on the gate dielectric layer 710. The gate dielectric layer 710 includes one or more dielectric materials, such as silicon oxide (SiO x , such as SiO2), silicon nitride (Si x N y , such as Si3N4), aluminum oxide (Al x O y , such as Al2O3), hafnium oxide (HfO x , such as HfO2), zirconium oxide (ZrO x , such as ZrO2), hafnium zirconium oxide (Hf x Zr y O z ), aluminum nitride (AlN), hafnium nitride (HfN), high-k dielectric materials, and / or another suitable dielectric material.

[0095] In some embodiments, an interface layer (not shown) is also deposited before forming the gate structure 705 (the interface layer is deposited on the gate dielectric layer 710 before forming the gate structure 705). The interface layer may include one or more dielectric materials, such as silicon oxide (SiO x , such as SiO2), silicon nitride (Si x N y , such as Si3N4), silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), aluminum oxide (Al x O y , such as Al2O3), hafnium oxide (HfO x, such as HfO2), aluminum nitride (AlN), hafnium nitride (HfN), low-k dielectric materials, high-k dielectric materials, and / or another suitable insulating material. Additionally and / or alternatively, a nanostructured two-dimensional insulating material (e.g., an insulating material having a crystalline structure with an atomic thickness) (e.g., boron nitride (BN)) can be used for the interface layer.

[0096] The deposition tool 102 can be used to deposit the gate dielectric layer 710 using CVD techniques, PVD techniques, ALD techniques, another deposition technique described above Figure 1 and / or another suitable deposition technique. The deposition tool 102 can be used to deposit the interface layer using CVD techniques, PVD techniques, ALD techniques, another deposition technique described above Figure 1 and / or another suitable deposition technique. The deposition tool 102 can be used to deposit the gate structure 705 using CVD techniques, PVD techniques, ALD techniques, another deposition technique described above Figure 1 and / or another suitable deposition technique.

[0097] In some embodiments, only a bottom support dielectric layer 615 is included between the nanostructured channel 610 and the underlying gate structure 705, and the top support dielectric layer 620 is omitted from the semiconductor device 205. In these embodiments, the top surface of the nanostructured channel 610 can make direct physical contact with the gate dielectric layer 710 located between the nanostructured channel 610 and the gate structure 705 above the nanostructured channel 610. In some embodiments, only a top support dielectric layer 620 is included between the nanostructured channel 610 and the gate structure 705 located above the nanostructured channel 610, and the bottom support dielectric layer 615 is omitted from the semiconductor device 205. In these embodiments, the bottom surface of the nanostructured channel 610 can make direct physical contact with the gate dielectric layer 710 located between the nanostructured channel 610 and the gate structure 705 below the nanostructured channel 610.

[0098] As Figure 7C shown, a planarization operation can be performed to planarize the gate structure 705 and / or remove excess material from the gate structure 705. The planarization tool 110 can be used to perform the planarization operation.

[0099] As Figure 7C further shown, exemplary dimensions of the nanostructured transistor 605 can include the channel length of the nanostructured channel 610 (corresponding to Figure 7C(in the dimension D5). The "channel length" refers to the length of the nanostructure channel 610 located between the source / drain contact 635 and the source / drain contact 640. In some embodiments, the channel length ranges from approximately 5 nanometers to approximately 20 nanometers. If the channel length is less than approximately 5 nanometers, the nanostructure transistor 605 may experience high current leakage and may not be turned off. If the channel length is greater than approximately 20 nanometers, the size of the nanostructure transistor 605 may be such that a high density of transistors cannot be formed on the semiconductor device 205. If the channel length ranges from approximately 5 nanometers to approximately 20 nanometers, low current leakage can be achieved for the nanostructure transistor 605 while enabling the formation of a high density of transistors on the semiconductor device 205. However, other values of the channel length and ranges other than approximately 5 nanometers to approximately 20 nanometers are also within the scope of this disclosure.

[0100] As Figure 7C further shown therein, another exemplary dimension of the nanostructure transistor 605 may include the thickness of the source / drain contact (e.g., source / drain contact 635, source / drain contact 640), corresponding to Figure 7C the dimension D6 in). In some embodiments, the thickness ranges from approximately 5 nanometers to approximately 20 nanometers. If the thickness is less than approximately 5 nanometers, the nanostructure transistor 605 may experience high contact resistance, which can reduce the performance of the nanostructure transistor 605. If the thickness is greater than approximately 20 nanometers, the size of the nanostructure transistor 605 may be such that a high density of transistors cannot be formed on the semiconductor device 205. If the thickness ranges from approximately 5 nanometers to approximately 20 nanometers, low contact resistance can be achieved for the nanostructure transistor 605 while enabling the formation of a high density of transistors on the semiconductor device 205. However, other values of the thickness and ranges other than approximately 5 nanometers to approximately 20 nanometers are also within the scope of this disclosure.

[0101] As described above, Figures 7A to 7C is provided as an example. Other examples may be different from the examples described for Figures 7A to 7C Compared to the operations described in connection with Figures 7A to 7C the exemplary embodiment 700 may include additional operations, fewer operations, different operations, and / or operations in a different order.

[0102] Figures 8A to 8C is a diagram of an exemplary embodiment 800 of the inner spacer formation process described herein. In some embodiments, the operations described in connection with the exemplary embodiment 800 are performed after the processes described in connection with Figure 2A and Figure 2B are described.

[0103] Go toFigure 8A , can be formed by ways similar to those described in connection with Figure 3A and Figure 3B to form cavity 305 and inner spacer layer 310. As Figure 8A shown, part of the inner spacer layer 310 is removed such that the remaining portion of the inner spacer layer 310 corresponds to the inner spacer 315 in the cavity 305. Etching operation 805 can be performed using an etching tool 108 to partially remove the inner spacer layer 310, thereby forming the inner spacer 315.

[0104] Etching operation 805 can include performing an etching that is less directional compared to the etching operation 320 performed in connection with exemplary embodiment 300. This rounds the ends of the inner spacer 315. In some embodiments, dry etching techniques (e.g., plasma-based etching techniques) are used, in which the pressure, bias voltage, and / or another parameter of the etching tool 108 are selected to achieve rounding of the ends of the inner spacer 315. In some embodiments, another etching technique is used, such as a wet etching technique (e.g., using a wet chemical etchant).

[0105] As Figure 8B shown, operations similar to those described in connection with Figures 4 to 6 shown and described can be performed to form additional structures and / or layers of the nanostructure transistor 605 after forming the inner spacer 315.

[0106] As Figure 8B further shown in the detailed view in, the less directional etching causes the inner spacer 315 to have a rounded or curved outer surface 810 (and thus causes the inner spacer 630 to have a rounded or curved outer surface). The outer surface 810 of the inner spacer 630 can have an angle less than approximately 90 degrees and in some embodiments less than approximately 85 degrees (indicated as dimension D4 in Figure 8B ). However, other values of the angle are also within the scope of this disclosure. Additionally, the inner spacer 630 can be concave with respect to the end surface 815 of the nanostructure channel 610 of the nanostructure transistor 605.

[0107] As Figure 8C shown, operations similar to those described in connection with Figures 7A to 7C shown and described can be performed to form additional structures and / or layers of the nanostructure transistor 605.

[0108] In some embodiments, only a bottom support dielectric layer 615 is included between the nanostructure channel 610 and the underlying gate structure 705, and the top support dielectric layer 620 is omitted from the semiconductor device 205. In these embodiments, the top surface of the nanostructure channel 610 can make direct physical contact with the gate dielectric layer 710 located between the nanostructure channel 610 and the gate structure 705 above the nanostructure channel 610. In some embodiments, only a top support dielectric layer 620 is included between the nanostructure channel 610 and the gate structure 705 located above the nanostructure channel 610, and the bottom support dielectric layer 615 is omitted from the semiconductor device 205. In these embodiments, the bottom surface of the nanostructure channel 610 can make direct physical contact with the gate dielectric layer 710 located between the nanostructure channel 610 and the gate structure 705 below the nanostructure channel 610.

[0109] As described above, Figures 8A to 8C is provided as an example. Other examples may be different from the example(s) given for Figures 8A to 8C described. Compared to the operations described in connection with Figures 8A to 8C described, the exemplary embodiment 800 may include additional operations, fewer operations, different operations, and / or operations in a different order.

[0110] Figures 9A to 9C is a diagram of an exemplary embodiment 900 of the inner spacer formation process described herein. In some embodiments, the operations described in connection with the exemplary embodiment 900 are performed after the processes described in connection with Figure 2A and Figure 2B described.

[0111] Turning to Figure 9A , the cavity 305 and the inner spacer layer 310 can be formed in a manner similar to the manner described in connection with Figure 3A and Figure 3B described, respectively. As shown in Figure 9A , a portion of the inner spacer layer 310 is removed such that the remaining portion of the inner spacer layer 310 corresponds to the inner spacer 315 in the cavity 305. The etching operation 905 to partially remove the inner spacer layer 310 and thereby form the inner spacer 315 can be performed using the etching tool 108. The etching operation 905 can include using a lateral etching technique (e.g., as opposed to the vertical etching technique used in the etching operation 320). In the etching operation 905, a plasma, hydrofluoric acid (HF) vapor, and / or another type of etchant is used to etch the inner spacer layer 310 laterally. One or more parameters of the etching tool 108 (e.g., pressure, plasma bias voltage, and / or another parameter) are selected to achieve the lateral etching of the inner spacer 315.

[0112] As in Figure 9AAs further shown in, the lateral etching of the inner spacer layer 310 also enables the lateral etching of the bottom support dielectric layer 240 and / or the top support dielectric layer 245. The lateral etching of the bottom support dielectric layer 240 and / or the top support dielectric layer 245 causes the ends of the nanostructure channel layer 235 to extend laterally outward beyond the bottom support dielectric layer 240 and / or the top support dielectric layer 245. In some embodiments, the etchant used for the etching operation 905 has a lower selectivity for etching the bottom support dielectric layer 240 and the top support dielectric layer 245, such that the bottom support dielectric layer 240 and the top support dielectric layer 245 are etched.

[0113] As Figure 9B shown in, operations similar to those described in connection with Figures 4 to 6 shown and described may be performed after forming the inner spacer 315 to form additional structures and / or layers of the nanostructure transistor 605.

[0114] As Figure 9B further shown in the detailed view in, the lateral etching of the etching operation 905 causes the inner spacer 315 to have a rounded or curved outer surface 810 (and thus causes the inner spacer 630 to have a rounded or curved outer surface). The outer surface 810 of the inner spacer 630 may have an angle less than approximately 90 degrees, and in some embodiments less than approximately 85 degrees (indicated as dimension D4 in Figure 9B ). However, other values of the angle are also within the scope of this disclosure. Additionally, the inner spacer 630 may be recessed relative to the end surface 815 of the nanostructure channel 610 of the nanostructure transistor 605. The ends of the bottom support dielectric layer 615 and the top support dielectric layer 620 may also be curved, and the inner spacer 630 may be recessed relative to the ends of the bottom support dielectric layer 615 and the top support dielectric layer 620.

[0115] Additionally, the ends 910 of the nanostructure channel 610 extend laterally outward beyond the bottom support dielectric layer 615 and the top support dielectric layer 620. The distance between the end surface 815 of the nanostructure channel 610 and the bottom support dielectric layer 615 or the top support dielectric layer 620 (corresponding to Figure 9BThe dimension D7) therein may be included within a range of approximately 2 nanometers to approximately 10 nanometers. The end 910 of the nanostructure channel 610 may laterally protrude outwardly beyond the bottom support dielectric layer 615 and the top support dielectric layer 620 by such a distance that the source / drain contact 635 or the source / drain contact 640 can wrap around the end 910. This increases the physical contact between the end 910 of the nanostructure channel 610 and the source / drain contact 635 or the source / drain contact 640, which can reduce the contact resistance between the nanostructure channel 610 and the source / drain contact 635 or the source / drain contact 640. However, other values of the range are also within the scope of this disclosure.

[0116] As Figure 9C shown, operations similar to those associated with Figures 7A to 7C shown and described can be performed to form additional structures and / or layers of the nanostructure transistor 605.

[0117] In some embodiments, only the bottom support dielectric layer 615 is included between the nanostructure channel 610 and the underlying gate structure 705, and the top support dielectric layer 620 is omitted from the semiconductor device 205. In these embodiments, the top surface of the nanostructure channel 610 can make direct physical contact with the gate dielectric layer 710 located between the nanostructure channel 610 and the gate structure 705 above the nanostructure channel 610. In some embodiments, only the top support dielectric layer 620 is included between the nanostructure channel 610 and the gate structure 705 located above the nanostructure channel 610, and the bottom support dielectric layer 615 is omitted from the semiconductor device 205. In these embodiments, the bottom surface of the nanostructure channel 610 can make direct physical contact with the gate dielectric layer 710 located between the nanostructure channel 610 and the gate structure 705 below the nanostructure channel 610.

[0118] As described above, Figures 9A to 9C is provided as an example. Other examples may be different from the example for Figures 9A to 9C described. Compared to the operations associated with Figures 9A to 9C described, the exemplary embodiment 900 may include additional operations, fewer operations, different operations, and / or operations in a different order.

[0119] Figures 10A to 10D is a diagram of an exemplary embodiment 1000 of the inner spacer formation process described herein. In some embodiments, the operations associated with the exemplary embodiment 1000 are performed after the processes associated with Figure 2A and Figure 2B described.

[0120] Turning to Figure 10A , it can be respectively by means of the combination withFigure 3A and Figure 3B form the cavity 305 and the inner spacer layer 310 in a similar manner as described. As Figure 10A shown, the inner spacer layer 310 is partially removed such that the remaining portion of the inner spacer layer 310 corresponds to the inner spacer 315 in the cavity 305. An etching operation 1005 can be performed using an etching tool 108 to partially remove the inner spacer layer 310, thereby forming the inner spacer 315. The etching operation 1005 can include using a vertical etching technique similar to the etching operation 320 described in connection with Figures 3A to 3D the description.

[0121] As Figure 10A shown in the detailed view of, since the end 325 of the inner spacer 315 is approximately in the same horizontal plane 330 as the end of the channel layer stack 230, the end 325 of the inner spacer 315 can be approximately coplanar with the end of the channel layer stack 230 (e.g., with the end of the nanostructured channel layer 235, the end of the bottom support dielectric layer 240, and / or the end of the top support dielectric layer 245). The end 325 of the inner spacer 315 can have an angle of approximately 90 degrees (e.g., approximately 85 degrees to 95 degrees) with respect to the nanostructured channel layer 235, the bottom support dielectric layer 240, and / or the top support dielectric layer 245 (indicated as dimension D4 in Figure 10A ). However, other values of the angle are also within the scope of this disclosure.

[0122] As Figure 10B shown, another etching operation 1010 can be performed using an etching tool 108 to etch the ends 1015 of the bottom support dielectric layer 240 and the top support dielectric layer 245. The etching operation 1010 can include using a lateral etching technique (e.g., opposite to the vertical etching technique used in the etching operation 1005). In the etching operation 1010, a plasma, hydrofluoric acid (HF) vapor, a wet etchant, and / or another type of etchant is used to etch the ends 1015 of the bottom support dielectric layer 240 and the top support dielectric layer 245 laterally. The etchant used in the etching operation 1010 can have a high etching rate for the bottom support dielectric layer 240 and the top support dielectric layer 245 and a low etching rate for the inner spacer 315 and the nanostructured channel layer 235.

[0123] As Figure 10BAs further shown in, the lateral etching of the ends 1015 of the bottom support dielectric layer 240 and the top support dielectric layer 245 causes the ends of the nanostructure channel layer 235 to extend laterally outward beyond the bottom support dielectric layer 240 and / or the top support dielectric layer 245. Due to the etching selectivity of the etchant used in the etching operation 1010, the ends 325 of the inner spacer 315 and the ends of the nanostructure channel layer 235 can be approximately maintained in the same horizontal plane 330.

[0124] As Figure 10C shown in, operations similar to those shown and described in connection with Figures 4 to 6 can be performed after forming the inner spacer 315 to form additional structures and / or layers of the nanostructure transistor 605.

[0125] As Figure 10C further shown in the detailed view in, the vertical etching of the etching operation 1005 causes the inner spacer 315 to have approximately straight and approximately right-angled ends 325 (and thus causes the inner spacer 630 to have approximately straight and approximately right-angled ends). Additionally, the lateral etching of the etching operation 1010 causes the ends 910 of the nanostructure channel 610 to extend laterally outward beyond the bottom support dielectric layer 615 and the top support dielectric layer 620. The distance between the end surface 815 of the nanostructure channel 610 and the bottom support dielectric layer 615 or the top support dielectric layer 620 (corresponding to Figure 9B dimension D8 in) can be in the range of approximately 2 nanometers to approximately 10 nanometers. The ends 910 of the nanostructure channel 610 can project laterally outward beyond the bottom support dielectric layer 615 and the top support dielectric layer 620 by this distance so that the source / drain contact 635 or the source / drain contact 640 can wrap around the ends 910. This increases the physical contact between the ends 910 of the nanostructure channel 610 and the source / drain contact 635 or the source / drain contact 640, which can reduce the contact resistance between the nanostructure channel 610 and the source / drain contact 635 or the source / drain contact 640. However, other values within this range are also within the scope of this disclosure.

[0126] As Figure 10D shown in, operations similar to those shown and described in connection with Figures 7A to 7C can be performed to form additional structures and / or layers of the nanostructure transistor 605.

[0127] In some embodiments, only a bottom support dielectric layer 615 is included between the nanostructure channel 610 and the underlying gate structure 705, and the top support dielectric layer 620 is omitted from the semiconductor device 205. In these embodiments, the top surface of the nanostructure channel 610 may make direct physical contact with the gate dielectric layer 710 located between the nanostructure channel 610 and the gate structure 705 above the nanostructure channel 610. In some embodiments, only a top support dielectric layer 620 is included between the nanostructure channel 610 and the gate structure 705 located above the nanostructure channel 610, and the bottom support dielectric layer 615 is omitted from the semiconductor device 205. In these embodiments, the bottom surface of the nanostructure channel 610 may make direct physical contact with the gate dielectric layer 710 located between the nanostructure channel 610 and the gate structure 705 below the nanostructure channel 610.

[0128] As described above, Figures 10A to 10D is provided as an example. Other examples may be different from those Figures 10A to 10D described. Compared to the operations Figures 10A to 10D described, the exemplary embodiment 1000 may include additional operations, fewer operations, different operations, and / or operations in a different order.

[0129] Figure 11 is a diagram of exemplary components of the apparatus 1100 described herein. In some embodiments, one or more of the semiconductor processing tools 102 to 112 and / or the wafer / die transfer tool 114 may include one or more apparatuses 1100 and / or one or more components of the apparatus 1100. As Figure 11 shown, the apparatus 1100 may include a bus 1110, a processor 1120, a memory 1130, an input component 1140, an output component 1150, and / or a communication component 1160.

[0130] The bus 1110 may include one or more components enabling wired communication and / or wireless communication between the components of the apparatus 1100. The bus 1110 may couple, for example, via operative coupling, communicative coupling, electrical coupling, and / or electro - coupling Figure 11The two or more components shown are coupled together. For example, bus 1110 may include electrical connectors (e.g., wiring, traces, and / or leads) and / or a wireless bus. Processor 1120 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, an application specific integrated circuit, and / or another type of processing component. Processor 1120 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 1120 may include one or more processors that can be programmed to perform one or more operations or processes described elsewhere herein.

[0131] Memory 1130 may include volatile memory and / or non-volatile memory. For example, memory 1130 may include random access memory (RAM), read only memory (ROM), a hard disk drive, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory). Memory 1130 may include internal memory (e.g., RAM, ROM, or a hard disk drive) and / or removable memory (e.g., removable via a universal serial bus connector). Memory 1130 may be a non-transitory computer-readable medium. Memory 1130 may store information related to the operation of device 1100, one or more instructions, and / or software (e.g., one or more software applications). In some embodiments, memory 1130 may include one or more memories that are coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 1120) via bus 1110. The communicative coupling between processor 1120 and memory 1130 may enable processor 1120 to read and / or process information stored in memory 1130 and / or store information in memory 1130.

[0132] Input component 1140 may enable device 1100 to receive input, such as user input and / or sensed input. For example, input component 1140 may include a touch screen, a keyboard, a keypad, a mouse, buttons, a microphone, switches, sensors, a global positioning system sensor, a global navigation satellite system sensor, an accelerometer, a gyroscope, and / or an actuator. Output component 1150 may enable device 1100 to provide output, such as via a display, a speaker, and / or a light emitting diode. Communication component 1160 may enable device 1100 to communicate with other devices via a wired connector and / or a wireless connector. For example, communication component 1160 may include a receiver, a transmitter, a transceiver, a modem, a network adapter, and / or an antenna.

[0133] Device 1100 may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 1130) may store a set of instructions (e.g., one or more instructions or codes) for execution by processor 1120. Processor 1120 may execute the set of instructions to perform one or more operations or processes described herein. In some embodiments, execution of the set of instructions by one or more processors 1120 causes the one or more processors 1120 and / or device 1100 to perform one or more operations or processes described herein. In some embodiments, hardwired circuitry may be used instead of or in combination with the instructions to perform one or more operations or processes described herein. Additionally or alternatively, processor 1120 may be configured to perform one or more operations or processes described herein. Thus, the embodiments described herein are not limited to any particular combination of hardwired circuitry and software.

[0134] Figure 11 The number and arrangement of components shown are provided as an example. Compared to Figure 11 the components shown, device 1100 may include additional components, fewer components, different components, or components arranged in a different manner. Additionally or alternatively, a set of components (e.g., one or more components) of device 1100 may perform one or more functions described as being performed by another set of components of device 1100.

[0135] Figure 12 is a flowchart of an exemplary process 1200 associated with forming a semiconductor device described herein. In some embodiments, one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102 to 112) are used to perform Figure 12 one or more of the process operations shown. Additionally or alternatively, one or more components of device 1100 (e.g., processor 1120, memory 1130, input component 1140, output component 1150, and / or communication component 1160) may be used to perform Figure 12 one or more of the process operations shown.

[0136] As Figure 12As shown, process 1200 may include forming a layer stack over a substrate of a semiconductor device, the layer stack including a plurality of sacrificial nanostructure layers and a plurality of nanostructure channel layer stacks (operation 1210). For example, as described herein, a layer stack 220 including a plurality of sacrificial nanostructure layers 225 and a plurality of channel layer stacks 230 may be formed over a semiconductor substrate 210 of a semiconductor device 205 using one or more of semiconductor processing tools 102 to 112. In some embodiments, the plurality of sacrificial nanostructure layers 225 and the plurality of channel layer stacks 230 are arranged in a direction approximately perpendicular to the semiconductor substrate 210. In some embodiments, one channel layer stack 230 of the plurality of channel layer stacks 230 includes a nanostructure channel layer 235 and at least one support dielectric layer (e.g., bottom support dielectric layer 240, top support dielectric layer 245) between the nanostructure channel layer 235 and one sacrificial nanostructure layer 225 of the plurality of sacrificial nanostructure layers 225.

[0137] As Figure 12 Further shown, process 1200 may include etching the layer stack to form fin structures including the plurality of sacrificial nanostructure layers and the plurality of nanostructure channel layer stacks (operation 1220). For example, as described herein, one or more of semiconductor processing tools 102 to 112 may be used to etch the layer stack 220 to form fin structures 260 including the plurality of sacrificial nanostructure layers 225 and the plurality of channel layer stacks 230.

[0138] As Figure 12 Further shown, process 1200 may include etching the plurality of sacrificial nanostructure layers to form cavities between the plurality of nanostructure channel layer stacks (operation 1230). For example, as described herein, one or more of semiconductor processing tools 102 to 112 may be used to etch the plurality of sacrificial nanostructure layers 225 to form cavities 305 between the plurality of channel layer stacks 230.

[0139] As Figure 12 Further shown, process 1200 may include forming an inner spacer layer in the cavities and on the exposed portions of the plurality of nanostructure channel layer stacks (operation 1240). For example, as described herein, one or more of semiconductor processing tools 102 to 112 may be used to form an inner spacer layer 310 in the cavities 305 and on the exposed portions of the plurality of channel layer stacks 230.

[0140] As Figure 12As further shown, process 1200 may include performing a dry etching operation to etch the inner spacer layer, thereby forming an inner spacer in the cavity (operation 1250). For example, as described herein, one or more of semiconductor processing tools 102 to 112 may be used to perform a dry etching operation (e.g., etching operation 320, etching operation 1005) to etch the inner spacer layer 310, thereby forming an inner spacer 315 in the cavity 305. In some embodiments, the dry etching operation exposes the ends of the plurality of channel layer stacks 230.

[0141] As Figure 12 As further shown, process 1200 may include forming a source / drain contact layer on the fin structure such that the source / drain contact layer contacts the ends of the plurality of nanostructure channel layer stacks (operation 1260). For example, as described herein, one or more of semiconductor processing tools 102 to 112 may be used to form a source / drain contact layer 405 on the fin structure 260 such that the source / drain contact layer 405 contacts the ends of the plurality of channel layer stacks 230.

[0142] Process 1200 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0143] In a first embodiment, the ends of the nanostructure channel layer 235, the ends of the at least one support dielectric layer (e.g., the ends of the bottom support dielectric layer 240, the ends of the top support dielectric layer 245), and the ends 325 of a subset of the inner spacers 315 adjacent to the channel layer stack 230 are approximately coplanar.

[0144] In a second embodiment, separate or in combination with the first embodiment, process 1200 includes performing a wet etching operation (e.g., etching operation 1010) using a wet etchant after the dry etching operation to etch the at least one support dielectric layer.

[0145] In a third embodiment, separate or in combination with one or more of the first and second embodiments, the ends 1015 of the at least one support dielectric layer (e.g., the ends 1015 of the bottom support dielectric layer 240, the ends 1015 of the top support dielectric layer 245) are concave with respect to the ends of the nanostructure channel layer 235, and the ends 325 of a subset of the inner spacers 315 adjacent to the channel layer stack 230 are approximately coplanar.

[0146] In a fourth embodiment, separate or in combination with one or more of the first to third embodiments, the ends of the at least one support dielectric layer are curved.

[0147] In a fifth embodiment, either alone or in combination with one or more of the first through fourth embodiments, the ends of the nanostructured channel layer are approximately coplanar with the ends of a subset of the inner spacers adjacent to the stack of the nanostructured channel layer.

[0148] In a sixth embodiment, either alone or in combination with one or more of the first through fifth embodiments, the etch rate of the support dielectric layer is greater than the etch rate of the wet etchant for the nanostructured channel layer and the etch rate of the wet etchant for the subset of the inner spacers adjacent to the stack of the nanostructured channel layer.

[0149] Although Figure 12 illustrates exemplary operations of process 1200, in some embodiments, process 1200 includes additional operations, fewer operations, different operations, or operations arranged in a different manner compared to the operations depicted in Figure 12 In addition or alternatively, two or more of the operations of process 1200 may be performed in parallel.

[0150] Figure 13 is a flowchart of an exemplary process 1300 associated with forming the semiconductor devices described herein. In some embodiments, one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102 to 112) are used to perform Figure 13 the one or more process operations shown. In addition or alternatively, one or more components of device 1100 (e.g., processor 1120, memory 1130, input component 1140, output component 1150, and / or communication component 1160) may be used to perform Figure 13 the one or more process operations shown.

[0151] As Figure 13As shown in, process 1300 may include forming a layer stack above a substrate of a semiconductor device, the layer stack including a plurality of sacrificial nanostructure layers and a plurality of nanostructure channel layer stacks (operation 1310). For example, as described herein, a layer stack 220 including a plurality of sacrificial nanostructure layers 225 and a plurality of channel layer stacks 230 may be formed above a semiconductor substrate 210 of a semiconductor device 205 using one or more of semiconductor processing tools 102 to 112. In some embodiments, the plurality of sacrificial nanostructure layers 225 and the plurality of channel layer stacks 230 are arranged in a direction approximately perpendicular to the semiconductor substrate 210. In some embodiments, one channel layer stack 230 of the plurality of channel layer stacks 230 includes a nanostructure channel layer 235 and at least one support dielectric layer (e.g., bottom support dielectric layer 240, top support dielectric layer 245) located between the nanostructure channel layer 235 and one of the plurality of sacrificial nanostructure layers 225.

[0152] As Figure 13 As further shown in, process 1300 may include etching the layer stack to form a fin structure including the plurality of sacrificial nanostructure layers and the plurality of nanostructure channel layer stacks (operation 1320). For example, as described herein, one or more of semiconductor processing tools 102 to 112 may be used to etch the layer stack 220 to form a fin structure 260 including the plurality of sacrificial nanostructure layers 225 and the plurality of channel layer stacks 230.

[0153] As Figure 13 As further shown in, process 1300 may include etching the plurality of sacrificial nanostructure layers to form cavities between the plurality of nanostructure channel layer stacks (operation 1330). For example, as described herein, one or more of semiconductor processing tools 102 to 112 may be used to etch the plurality of sacrificial nanostructure layers 225 to form cavities 305 between the plurality of channel layer stacks 230.

[0154] As Figure 13 As further shown in, process 1300 may include forming an inner spacer layer in the cavities and on exposed portions of the plurality of nanostructure channel layer stacks (operation 1340). For example, as described herein, one or more of semiconductor processing tools 102 to 112 may be used to form an inner spacer layer 310 in the cavities 305 and on exposed portions of the plurality of channel layer stacks 230.

[0155] As Figure 13As further shown, process 1300 may include etching an inner spacer layer to form an inner spacer in the cavity (operation 1350). For example, as described herein, one or more of semiconductor processing tools 102 to 112 may be used to etch inner spacer layer 310 to form inner spacer 315 in cavity 305. In some embodiments, etching inner spacer layer 310 exposes the ends of the plurality of channel layer stacks 230. In some embodiments, inner spacer 315 has a curved outer surface 810.

[0156] As Figure 13 As further shown, process 1300 may include forming a source / drain contact layer on the fin structure such that the source / drain contact layer contacts the ends of the plurality of nanostructure channel layer stacks (operation 1360). For example, as described herein, one or more of semiconductor processing tools 102 to 112 may be used to form source / drain contact layer 405 on fin structure 260 such that source / drain contact layer 405 contacts the ends of the plurality of channel layer stacks 230.

[0157] Process 1300 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0158] In a first embodiment, the ends of the at least one support dielectric layer (e.g., the ends of bottom support dielectric layer 240, top support dielectric layer 245) are curved.

[0159] In a second embodiment, separate or in combination with the first embodiment, the ends of the at least one support dielectric layer (e.g., the ends of bottom support dielectric layer 240, top support dielectric layer 245) are approximately coplanar with the ends of nanostructure channel layer 235.

[0160] In a third embodiment, separate or in combination with one or more of the first and second embodiments, the ends of nanostructure channel layer 235 extend laterally outward from the ends of the at least one support dielectric layer (e.g., the ends of bottom support dielectric layer 240, top support dielectric layer 245).

[0161] In a fourth embodiment, separate or in combination with one or more of the first to third embodiments, etching inner spacer layer 310 includes performing a wet etching operation to etch inner spacer layer 310.

[0162] In a fifth embodiment, either alone or in combination with one or more of the first through fourth embodiments, etching the inner spacer layer 310 includes performing a lateral plasma etching operation to etch the inner spacer layer 310.

[0163] In a sixth embodiment, either alone or in combination with one or more of the first through fifth embodiments, etching the inner spacer layer 310 includes performing a lateral hydrofluoric acid etching operation to etch the inner spacer layer 310.

[0164] Although Figure 13 illustrative operations of process 1300 are shown, in some embodiments, compared to Figure 13 the operations depicted in, process 1300 includes additional operations, fewer operations, different operations, or operations arranged in a different manner. Additionally or alternatively, two or more of the operations of process 1300 may be performed in parallel.

[0165] In this way, one or more support dielectric layers are included under and / or on the nanostructure channel of the nanostructure transistor. The nanostructure transistor can be formed by forming a nanosheet stack that includes one or more channel layer stacks sandwiched between respective sacrificial layers. Each nanostructure channel layer stack can include a nanostructure channel layer and one or more dielectric support layers under and / or on the nanostructure channel layer. The nanosheet stack is etched to define the nanostructure channel of the nanostructure transistor. An inner spacer process is performed to form inner spacers on the sidewalls of the sacrificial layers between each nanostructure channel layer stack, and then source / drain contacts are formed on the sidewalls of the nanostructure channel layer stacks and on the inner spacers. Subsequently, the sacrificial layers are removed in a nanosheet release process, and the sacrificial layers are replaced with a metal gate structure and an associated high-k dielectric layer.

[0166] The supporting dielectric layer can increase the mechanical strength of the nanostructured channel, which enables the use of advanced materials such as TMD materials in the nanostructured channel. This enables the achievement of two-dimensional nanostructured channels (e.g., nanostructured channels with a thickness of approximately one atom) in nanostructured transistors. Additionally and / or alternatively, the supporting dielectric layer can reduce the likelihood and / or magnitude of mechanical degradation of the nanostructured channel, which can occur due to external forces from subsequent semiconductor processing operations (such as film patterning and / or nanosheet release, etc.). Therefore, the supporting dielectric layer can provide a larger process window (e.g., a larger temperature range, a larger mechanical stress range) for forming the nanostructured channel. The supporting dielectric layer can also provide a substrate for the high-k dielectric layer on which the metal gate structure is deposited, which can reduce void formation and improve the thin film growth of the high-k dielectric layer compared to forming the high-k dielectric layer only on the two-dimensional nanostructured channel. The supporting dielectric layer can increase the structural strength of the vertical stacking of nanostructured channels, thereby enabling a large number of nanostructured channels to be achieved on a single vertical stack. The supporting dielectric layer can also provide sufficient structural strength for the nanostructured channel such that the nanostructured channel can extend laterally outward from the supporting dielectric layer, which can enable a reduced contact resistance between the nanostructured channel and the source / drain contact due to a larger contact area that can be achieved between the nanostructured channel and the source / drain contact. Additionally, the process for forming the supporting dielectric layer can be integrated with silicon (Si) processing operations.

[0167] As elaborated in more detail above, some embodiments set forth herein provide a method. The method includes forming a layer stack above a substrate of a semiconductor device, the layer stack including a plurality of sacrificial nanostructure layers and a plurality of nanostructure channel layer stacks, wherein the plurality of sacrificial nanostructure layers and the plurality of nanostructure channel layer stacks are arranged in a direction approximately perpendicular to the substrate, and wherein a nanostructure channel layer stack of the plurality of nanostructure channel layer stacks includes a nanostructure channel layer and at least one support dielectric layer located between the nanostructure channel layer and a sacrificial nanostructure layer of the plurality of sacrificial nanostructure layers. The method includes etching the layer stack to form a fin structure including the plurality of sacrificial nanostructure layers and the plurality of nanostructure channel layer stacks. The method includes etching the plurality of sacrificial nanostructure layers to form cavities between the plurality of nanostructure channel layer stacks. The method includes forming an inner spacer layer in the cavities and on exposed portions of the plurality of nanostructure channel layer stacks. The method includes performing a dry etching operation to etch the inner spacer layer to form inner spacers in the cavities, wherein the dry etching operation exposes ends of the plurality of nanostructure channel layer stacks. The method includes forming a source / drain contact layer on the fin structure such that the source / drain contact layer contacts the ends of the plurality of nanostructure channel layer stacks.

[0168] In some embodiments, ends of the nanostructure channel layer, ends of the at least one support dielectric layer, and ends of a subset of the plurality of inner spacers adjacent to the one nanostructure channel layer stack are approximately coplanar. In some embodiments, the method of forming a semiconductor device further includes: performing a wet etching operation using a wet etchant to etch the at least one support dielectric layer after the dry etching operation. In some embodiments, ends of the at least one support dielectric layer are recessed relative to ends of the nanostructure channel layer, and ends of a subset of the plurality of inner spacers adjacent to the one nanostructure channel layer stack are approximately coplanar. In some embodiments, the ends of the at least one support dielectric layer have a curved outer surface. In some embodiments, the ends of the nanostructure channel layer and the ends of the subset of the inner spacers adjacent to the one nanostructure channel layer stack are approximately coplanar. In some embodiments, the wet etchant has a higher etching rate for the at least one support dielectric layer than for the nanostructure channel layer and for the subset of the inner spacers adjacent to the one nanostructure channel layer stack.

[0169] As elaborated in more detail above, some embodiments set forth herein provide a method. The method includes forming a layer stack above a substrate of a semiconductor device, the layer stack including a plurality of sacrificial nanostructure layers and a plurality of nanostructure channel layer stacks, wherein the plurality of sacrificial nanostructure layers and the plurality of nanostructure channel layer stacks are arranged in a direction approximately perpendicular to the substrate, and wherein one of the nanostructure channel layer stacks of the plurality of nanostructure channel layer stacks includes a nanostructure channel layer and at least one support dielectric layer located between the nanostructure channel layer and one of the plurality of sacrificial nanostructure layers. The method includes etching the layer stack to form a fin structure including the plurality of sacrificial nanostructure layers and the plurality of nanostructure channel layer stacks. The method includes etching the plurality of sacrificial nanostructure layers to form cavities between the plurality of nanostructure channel layer stacks. The method includes forming an inner spacer layer in the cavities and on exposed portions of the plurality of nanostructure channel layer stacks. The method includes etching the inner spacer layer to form inner spacers in the cavities, wherein etching the inner spacer layer exposes ends of the plurality of nanostructure channel layer stacks, and wherein the inner spacers have a curved outer surface. The method includes forming a source / drain contact layer on the fin structure such that the source / drain contact layer contacts the ends of the plurality of nanostructure channel layer stacks.

[0170] In some embodiments, ends of the at least one support dielectric layer have a curved outer surface. In some embodiments, ends of the at least one support dielectric layer are approximately coplanar with ends of the nanostructure channel layer. In some embodiments, ends of the nanostructure channel layer extend laterally outward from ends of the at least one support dielectric layer. In some embodiments, etching the inner spacer layer includes performing a wet etching operation to etch the inner spacer layer. In some embodiments, etching the inner spacer layer includes performing a lateral plasma etching operation to etch the inner spacer layer. In some embodiments, etching the inner spacer layer includes performing a lateral hydrofluoric acid etching operation to etch the inner spacer layer.

[0171] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a plurality of nanostructured channels arranged in a direction approximately perpendicular to a substrate. The plurality of nanostructured channels includes a transition metal dichalcogenide (TMD) material. The semiconductor device includes a supporting dielectric layer vertically adjacent to a nanostructured channel among the plurality of nanostructured channels. A first end of the one nanostructured channel extends laterally outward from the supporting dielectric layer, and a second end of the one nanostructured channel opposite to the first end extends laterally outward from the supporting dielectric layer. The semiconductor device includes a first source / drain contact in contact with a plurality of surfaces of the first end. The semiconductor device includes a second source / drain contact in contact with a plurality of surfaces of the second end.

[0172] In some embodiments, a distance between the first end of the one nanostructured channel and an end of the supporting dielectric layer is in a range of approximately 2 nanometers to approximately 10 nanometers. In some embodiments, the semiconductor device further includes: a gate structure surrounding the plurality of nanostructured channels on at least three sides of the plurality of nanostructured channels; and a plurality of inner spacers located between the gate structure and the first source / drain contact and between the gate structure and the second source / drain contact. In some embodiments, the plurality of inner spacers has a curved outer surface. In some embodiments, an inner spacer among the plurality of inner spacers and a nanostructured channel among the plurality of nanostructured channels have approximately coplanar ends. In some embodiments, the supporting dielectric layer is located under the one nanostructured channel.

[0173] As used herein, "meeting a threshold value" may depend on the context and refer to a value greater than the threshold value, greater than or equal to the threshold value, less than the threshold value, less than or equal to the threshold value, equal to the threshold value, not equal to the threshold value, or a similar value.

[0174] The terms "approximately" and "substantially" may indicate a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are only examples and are not intended to be limiting. It should be understood that according to the present disclosure, the terms "approximately" and "substantially" may refer to a percentage of a value of a given quantity.

[0175] The foregoing has outlined features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, characterized in that, Comprising: Forming a layer stack above a substrate of a semiconductor device, the layer stack including a plurality of sacrificial nanostructure layers and a plurality of nanostructure channel layer stacks, wherein the plurality of sacrificial nanostructure layers and the plurality of nanostructure channel layer stacks are arranged in a direction approximately perpendicular to the substrate, and wherein one nanostructure channel layer stack among the plurality of nanostructure channel layer stacks includes a nanostructure channel layer and at least one support dielectric layer located between the nanostructure channel layer and one sacrificial nanostructure layer among the plurality of sacrificial nanostructure layers; Etching the layer stack to form a fin structure including the plurality of sacrificial nanostructure layers and the plurality of nanostructure channel layer stacks; Etching the plurality of sacrificial nanostructure layers to form a plurality of cavities between the plurality of nanostructure channel layer stacks; Forming an inner spacer layer in the plurality of cavities and on the exposed portions of the plurality of nanostructure channel layer stacks; Performing a dry etching operation to etch the inner spacer layer, thereby forming a plurality of inner spacers in the plurality of cavities, wherein the dry etching operation exposes the ends of the plurality of nanostructure channel layer stacks; And Forming a source / drain contact layer on the fin structure such that the source / drain contact layer contacts the ends of the plurality of nanostructure channel layer stacks.

2. The method for forming a semiconductor device according to claim 1, wherein The ends of the nanostructure channel layer, the ends of the at least one support dielectric layer, and the ends of a subset of the plurality of inner spacers adjacent to one nanostructure channel layer stack are approximately coplanar.

3. The method for forming a semiconductor device according to claim 1, wherein Further comprising: After the dry etching operation, performing a wet etching operation using a wet etchant to etch the at least one support dielectric layer.

4. The method for forming a semiconductor device according to claim 3, wherein, Wherein the ends of the at least one support dielectric layer are recessed relative to the ends of the nanostructure channel layer, and the ends of a subset of the plurality of inner spacers adjacent to one nanostructure channel layer stack are approximately coplanar.

5. The method for forming a semiconductor device according to claim 4, wherein, The ends of the at least one support dielectric layer have a curved outer surface.

6. The method for forming a semiconductor device according to claim 4, wherein, The ends of the nanostructure channel layer and the ends of the subset of the inner spacers adjacent to one nanostructure channel layer stack are approximately coplanar.

7. The method for forming a semiconductor device according to claim 4, wherein, The wet etchant has a higher etching rate for the at least one support dielectric layer than for the nanostructure channel layer and for the subset of the inner spacers adjacent to one nanostructure channel layer stack.

8. A method for forming a semiconductor device, characterized in that Comprising: Forming a layer stack above a substrate of a semiconductor device, the layer stack including a plurality of sacrificial nanostructure layers and a plurality of nanostructure channel layer stacks, wherein the plurality of sacrificial nanostructure layers and the plurality of nanostructure channel layer stacks are arranged in a direction approximately perpendicular to the substrate, and wherein one nanostructure channel layer stack among the plurality of nanostructure channel layer stacks includes a nanostructure channel layer and at least one support dielectric layer located between the nanostructure channel layer and one sacrificial nanostructure layer among the plurality of sacrificial nanostructure layers; Etch the layer stack to form a fin structure including the plurality of sacrificial nanostructure layers and the stacked plurality of nanostructure channel layers; Etch the plurality of sacrificial nanostructure layers to form a plurality of cavities between the stacked plurality of nanostructure channel layers; Form an inner spacer layer in the plurality of cavities and on the exposed portions of the stacked plurality of nanostructure channel layers; Etch the inner spacer layer to form a plurality of inner spacers in the plurality of cavities, wherein etching the inner spacer layer exposes the ends of the stacked plurality of nanostructure channel layers, and wherein the plurality of inner spacers have curved outer surfaces; and Form a source / drain contact layer on the fin structure such that the source / drain contact layer contacts the ends of the stacked plurality of nanostructure channel layers.

9. The method for forming a semiconductor device according to claim 8, wherein, The ends of the nanostructure channel layers extend laterally outward from the ends of the at least one support dielectric layer.

10. A semiconductor device, characterized in that, Comprising: A plurality of nanostructure channels arranged in a direction approximately perpendicular to the substrate, wherein the plurality of nanostructure channels comprise a transition metal dichalcogenide material; A support dielectric layer vertically adjacent to a nanostructure channel among the plurality of nanostructure channels, wherein a first end of the one nanostructure channel extends laterally outward from the support dielectric layer, and wherein a second end of the one nanostructure channel opposite to the first end extends laterally outward from the support dielectric layer; A first source / drain contact in contact with a plurality of surfaces of the first end; and A second source / drain contact in contact with a plurality of surfaces of the second end.

11. The semiconductor device according to claim 10, wherein, Further comprising: A gate structure surrounding the plurality of nanostructure channels on at least three sides of the plurality of nanostructure channels; and A plurality of inner spacers located between the gate structure and the first source / drain contact and between the gate structure and the second source / drain contact.

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