Groove type HEMT device and manufacturing method thereof

Abstract

The invention discloses a groove type HEMT (High Electron Mobility Transistor) device and a manufacturing method thereof, relates to a power device based on a nitride semiconductor material, and aims to solve the problems that in the conduction process of the device, high-concentration two-dimensional electron gas can sink to the upper surface of an upper semiconductor, a lower buffer layer and other areas, so that the dynamic resistance of the device is increased, and the reliability of the device is improved. And the reliability is reduced after long-time use. According to the invention, by designing multiple sections of parallel two-dimensional electron gas, the on-resistance of the nitride semiconductor material high electron mobility transistor device can be further reduced, and by adjusting the structures of the uppermost layer and the lowermost layer of the stacked channel layer and the thickness of the structure layer, the on-resistance of the device can be further reduced. And the shortest distance from the two-dimensional electron gas to the upper surface of the semiconductor and the buffer layer is changed so as to adjust the compromise between the on resistance of the device and the dynamic resistance caused by electron collapse.

Description

Technical Field

[0001] The present invention relates to a power device based on a nitride semiconductor material, in particular to a structure and a manufacturing method of a HEMT device. Background Art

[0002] A high electron mobility transistor (HEMT) based on a nitride semiconductor material is a high-performance electronic device based on wide-bandgap semiconductor materials such as gallium nitride (GaN) and aluminum nitride (AlN). Compared with traditional silicon-based devices, it has significant advantages in on-resistance and power density, switching speed and loss. An existing enhanced nitride semiconductor material high electron mobility transistor structure is as Figure 1 shown. In this device, a two-dimensional electron gas is formed at the interface between the first nitride semiconductor layer 102 and the barrier layer 103 as the current path of the device, which affects the on-resistance of the device. Generally, a higher concentration of two-dimensional electron gas is beneficial to reducing the on-resistance of the device. However, increasing the concentration of the two-dimensional electron gas is often restricted by many processes and device designs. For example, Figure 1 in a normally-off HEMT, due to the limitation of the minimum turn-on voltage, the energy band height of the barrier layer 103 should not be set too high, thus restricting the further increase of the concentration of the two-dimensional electron gas and limiting the reduction of the on-resistance of the device. Another example is that during the device conduction process, a high concentration of two-dimensional electron gas will fall into regions such as the upper semiconductor surface and the lower buffer layer, resulting in problems such as an increase in the dynamic resistance of the device and a decrease in reliability under long-term use. Summary of the Invention

[0003] To solve the above-mentioned problems, the present invention provides a technical solution as follows: A trench-type HEMT device, the device includes a substrate layer at the bottom, a buffer layer above the substrate layer, a first nitride semiconductor layer above the buffer layer, a passivation layer above the device, and source metal and drain metal connected to the semiconductor through the passivation layer. A semiconductor trench and a stacked channel layer are provided above the first nitride semiconductor layer. The semiconductor trench is filled with a first barrier layer and gate metal from bottom to top. The stacked channel layer includes at least one layer of stacked barrier layers and stacked nitride semiconductor layers arranged alternately up and down. A two-dimensional electron gas is formed at the interface between the stacked barrier layer and the stacked nitride semiconductor layer; a thin-film nitride semiconductor layer is further provided between the first barrier layer on the side wall of the semiconductor trench and the stacked channel layer, and two-dimensional electron gases can be respectively formed at the interfaces between the thin-film nitride semiconductor layer and the first barrier layer and the stacked barrier layer on its two sides.

[0004] Further, the semiconductor trench includes an insulating layer provided on the trench wall and a gate metal provided in the trench, and the top of the insulating layer extends outward to cover the stacked channel layer; Alternatively, the semiconductor trench includes a first barrier layer provided on the trench wall and a gate metal provided in the trench, and the top of the first barrier layer extends outward to cover the stacked channel layer; Alternatively, the semiconductor trench includes a first barrier layer provided on the trench wall, a gate metal provided in the trench, and a second nitride semiconductor layer provided between the first barrier layer and the gate metal, and the top of the first barrier layer extends outward to cover the stacked channel layer.

[0005] Further, two or more parallel two-dimensional electron gases are formed at the interfaces between the first nitride semiconductor layer and the stacked barrier layer above it and between the first barrier layer and the first nitride semiconductor layer, and the concentrations of the multiple two-dimensional electron gases formed in the device decrease sequentially from the center in the up and down directions.

[0006] Further, the thin film nitride semiconductor layer overlaps with the two-dimensional electron gases formed by the first barrier layer and the stacked barrier layer on both sides of it to form a single thickened channel.

[0007] Further, the gate metal extends upward and outward to the outside of the trench to serve as a field plate structure of the device.

[0008] Further, a source field plate structure connected to the source is provided above the upper surface of the semiconductor to reduce the surface electric field when the device is reverse biased.

[0009] Further, a P-type nitride semiconductor region is provided below the semiconductor trench.

[0010] The present invention also provides a manufacturing method for a trench-type HEMT device, and the manufacturing method includes the following steps: In the first step, a buffer layer is formed on the substrate layer, and then a first nitride semiconductor layer is formed on the buffer layer; In the second step, a stacked channel layer, a semiconductor trench, and a thin film nitride semiconductor layer are formed on the first nitride semiconductor layer; In the third step, a gate structure is formed in the semiconductor trench; In the fourth step, a passivation layer and an upper surface metal are formed, and finally the device is formed.

[0011] Further, the specific steps in the second step are as follows: First, a stacked barrier layer and a stacked nitride semiconductor layer are formed on the first nitride semiconductor layer by an epitaxial method, and then, by a photolithography method, a semiconductor trench is etched on the stacked channel layer; then a thin film nitride semiconductor layer is deposited on the semiconductor trench and the stacked nitride semiconductor layer, Alternatively, The specific steps in the second step are as follows: First, form a patterned sacrificial mask layer on the first nitride semiconductor layer; then, form a stacked channel layer on the nitride semiconductor layer by an epitaxial method, and then form a filling layer thereon; next, perform chemical mechanical polishing using the sacrificial mask layer as a polishing stop layer; then, remove the sacrificial mask layer; finally, use the filling layer as an etching mask layer to etch and form a semiconductor trench; then, remove the etching mask layer, and deposit a thin film nitride semiconductor layer on the semiconductor trench and the stacked nitride semiconductor layer; or deposit a stacked nitride semiconductor layer on the semiconductor trench and the stacked barrier layer, and reduce the thickness of the stacked nitride semiconductor layer in the semiconductor trench by photolithography to form a thin film nitride semiconductor layer.

[0012] Further, the specific steps in the third step are as follows: First, form a first barrier layer on the upper surface of the semiconductor, and then form a P-type second nitride semiconductor layer; then, fill the semiconductor trench with metal and perform back-etching to form a gate metal; next, under the protection of the gate metal, etch the P-type second nitride semiconductor layer located on the upper surface by a self-aligned method to make it retract into the trench.

[0013] The present invention is beneficial to further reduce the on-resistance of a nitride semiconductor material high electron mobility transistor device by designing a two-dimensional electron gas in multiple parallel segments, and by adjusting the structures of the uppermost and lowermost layers of the stacked channel layer and the thickness of this structural layer, change the shortest distance from the two-dimensional electron gas to the upper surface of the semiconductor and the buffer layer, so as to adjust the compromise between the on-resistance of the device and the dynamic resistance caused by electron trapping. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic structural diagram of an existing enhanced nitride semiconductor material high electron mobility transistor.

[0015] Figure 2 It is a schematic structural diagram of an enhanced nitride semiconductor material high electron mobility transistor according to an embodiment of the present invention.

[0016] Figure 3 It is a schematic structural diagram of an enhanced nitride semiconductor material high electron mobility transistor according to another embodiment of the present invention.

[0017] Figure 4 It is a schematic structural diagram of a depletion-type nitride semiconductor material high electron mobility transistor according to another embodiment of the present invention.

[0018] Figure 5 It is a schematic structural diagram of a nitride semiconductor material high electron mobility transistor according to another embodiment of the present invention.

[0019] Figures 6 - 8 Schematic diagram of an implementation method for the second step in the key steps of manufacturing the device of the present invention.

[0020] Figures 9 - 14 Schematic diagram of another implementation method for the second step in the key steps of manufacturing the device of the present invention.

[0021] Figures 15 - 16 Schematic diagram of a third implementation method for the second step in the key steps of manufacturing the device of the present invention.

[0022] Figures 17 - 19 Schematic diagram of an implementation method for the third step in the key steps of manufacturing the device of the present invention.

[0023] Figure 20 Schematic diagram of an implementation method for the fourth step in the key steps of manufacturing the device of the present invention. Detailed implementation manners Detailed implementation manners

[0024] It should be noted that the corresponding position words described in this document, such as "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "upright", are relative positions corresponding to the reference diagrams. The specific implementation does not limit the fixed direction. It should be noted that the devices in the drawings are not necessarily drawn to scale. The straight lines shown for the doping regions, trenches, and boundaries of the material layers in the drawings, as well as the sharp corners formed by these boundaries, are generally not straight lines and precise angles in actual applications.

[0025] The present invention will be described in detail below with reference to the drawings and embodiments.

[0026] An embodiment of a nitride semiconductor material high electron mobility transistor device of the present invention is as Figure 2 shown, which includes: A substrate layer 100 at the bottom, a buffer layer 101 located above the substrate layer, and a nitride semiconductor layer 102 located above the buffer layer.

[0027] It further includes a stacked channel layer 209 located on the nitride semiconductor layer 102.

[0028] There are semiconductor trenches 208 between the stacked channel layers 209.

[0029] The sidewalls of the semiconductor trenches 208 are thin film nitride semiconductor layers 214.

[0030] The semiconductor trenches 208 are filled from bottom to top with a first barrier layer 206, a P-type nitride semiconductor layer 210, and a gate metal 220.

[0031] In addition, it further includes: source metal 222 and drain metal 221 located above the device and connected to the semiconductor through the passivation layer 215.

[0032] The stacked channel layer 209 described above includes at least one stacked barrier layer 203 and at least one stacked nitride semiconductor layer 204 that alternate. A multi-segment two-dimensional electron gas is formed at the alternating interfaces of the multiple stacked barrier layers and stacked nitride semiconductor layers.

[0033] In the above device, due to the multi-segment parallel two-dimensional electron gas, the on-resistance is smaller compared to existing devices.

[0034] In addition, the gate metal 220, P-type nitride semiconductor layer 210 inside the trench, and the first barrier layer 206 at the bottom of the trench form the gate structure of the enhancement-mode high electron mobility transistor device. Under the gate bias, the two-dimensional electron gas in the first barrier layer 206, thin film nitride semiconductor layer 214, and nitride semiconductor layer 102 at the bottom of the semiconductor trench 208 is controlled. Generally, the energy band height difference between the first barrier layer 206 and the nitride semiconductor layer 102 is set to be larger than the energy band height difference between the stacked barrier layer 203 and the stacked nitride semiconductor layer 204, and the turn-on voltage of the device is regulated by this energy band height difference. This approach is beneficial for increasing the turn-on voltage of the device without reducing the on-resistance of the device.

[0035] It should be noted that when the lowermost structure in the stacked channel layer 209 is the stacked barrier layer 203, a two-dimensional electron gas will be formed at the interface with the underlying nitride semiconductor layer 102. When the uppermost structure in the stacked channel layer 209 is the stacked nitride semiconductor layer 204, a two-dimensional electron gas will also be formed at the interface with the upper first barrier layer 206.

[0036] Those skilled in the art can adjust the structures of the uppermost and lowermost layers of the stacked channel layer 209 and the thickness of these structural layers to change the shortest distance from the two-dimensional electron gas to the upper surface of the semiconductor and the buffer layer 101, so as to adjust the trade-off between the on-resistance of the device and the dynamic resistance caused by electron trapping.

[0037] According to the actual device design and process limitations, the multiple stacked barrier layers 203 and stacked nitride semiconductor layers 204 in the stacked channel layer 209 may have different thicknesses, material composition ratios, and energy band structures to adjust the concentration of the formed multi-segment two-dimensional electron gas. The first barrier layer 206 in the trench and the thin film nitride semiconductor layer 214 can form a two-dimensional electron gas, and the stacked barrier layer 203 on the other side and the thin film nitride semiconductor layer 214 also form a two-dimensional electron gas. By adjusting the thickness of the thin film nitride semiconductor layer 214 to change the two-dimensional electron gas on both sides, the two-dimensional electron gas on both sides is made to overlap, forming a single thickened channel, ensuring that the current of the multi-segment two-dimensional electron gas in the stacked channel layer 209 can flow between the drain and source through the single thickened channel in the thin film nitride semiconductor layer 214.

[0038] In a practical embodiment, there are multiple segments of two-dimensional electron gas in the stacked channel layer 209, and its concentration decreases successively from the center in the up and down directions. The concentration of the two-dimensional electron gas at the very center of the stacked channel layer 209 is the highest, and the concentrations of the two-dimensional electron gases at the uppermost and lowermost positions are the lowest. This approach is beneficial for reducing device reliability problems caused by electrons falling into the passivation layer and the buffer layer.

[0039] In some embodiments, there may be an alternating combination of more layers of passivation layer and through metal layer on the upper surface. For example, the design scheme in Chinese Patent CN222106722U. This method is beneficial for forming a uniform current path on the upper surface of the device and reducing the on-resistance.

[0040] In a practical embodiment, the substrate layer 100 is composed of silicon, and the nitride semiconductor layer 102 is gallium nitride. The buffer layer 101 may be composed of multiple layers of aluminum gallium nitride or may include a superlattice material layer, and is beneficial for forming a high-quality gallium nitride epitaxial layer.

[0041] In a practical embodiment of a 600V enhancement-mode high electron mobility transistor device, the depth of the semiconductor trench 208 is between 0.1um and 0.8um, and the width of the semiconductor trench is between 0.3um and 2um. The thickness of the stacked channel layer 209 is between 0.01um and 0.6um, where the thickness of the stacked barrier layer 203 is between 50A and 2000A, the thickness of the stacked nitride semiconductor layer 204 is between 200A and 4000A. The thickness of the thin film nitride semiconductor layer 214 is between 5A and 50A. The thickness of the P-type nitride semiconductor layer 210 is between 200A and 1500A. The thickness of the passivation layer 215 is between 0.3um and 2um.

[0042] Figure 3 For Figure 2 a variant embodiment based on the device, in which several different embodiments of the device of the present invention are listed.

[0043] In some device embodiments of the present invention, the gate metal 220 may not only be in the trench but also have a structure extending outside the trench, serving as the field plate structure of the device, as Figure 3 shown.

[0044] In some device embodiments of the present invention, a source field plate structure 223 connected to the source may also be provided above the upper surface of the semiconductor to reduce the surface electric field when the device is reverse-biased, as Figure 3 shown.

[0045] In some device embodiments of the present invention, a P-type nitride semiconductor region 240 may also be provided below the semiconductor trench, as Figure 3As shown. This approach is beneficial for reducing the electric field strength near the trench during the reverse bias process and can also reduce the impact of electron trapping on the turn-on voltage.

[0046] In addition, in some variant embodiments, in addition to the gate structure in the above device, different gate structure implementation schemes may also be adopted to obtain different types of trench-type power device structures, such as Figure 4 , Figure 5 shown in the device embodiments in

[0047] For example, based on the Figure 2 structure, omitting the P-type nitride semiconductor layer 210 in the trench can form a depletion-type high electron mobility transistor device structure, such as Figure 4 shown.

[0048] Another example is that based on the Figure 2 structure, omitting the P-type nitride semiconductor layer 210 and the first barrier layer 206 in the trench and forming a gate structure of insulating layer 216 - gate metal 220 at the bottom of the trench, a trench-type high electron mobility transistor device structure combined with a field effect transistor can be formed, such as Figure 5 shown.

[0049] The following are the key manufacturing steps of the above device of the present invention: The first step is to form a buffer layer 101 on the substrate layer 100, and then form a nitride semiconductor layer 102 on the buffer layer 101.

[0050] The second step is to form a stacked channel layer 209, a semiconductor trench 208, and a thin film nitride semiconductor layer 214 on the nitride semiconductor layer 102.

[0051] The third step is to form a gate structure in the semiconductor trench 208.

[0052] The fourth step is to form a passivation layer 215 and an upper surface metal, and finally form the device.

[0053] In the first step, the substrate layer 100 may be composed of materials such as silicon, gallium nitride, silicon carbide, aluminum nitride, etc. The buffer layer 101 and the nitride semiconductor layer 102 may be formed by MOCVD or MOVPE.

[0054] In the second step, the stacked barrier layer 203 in the stacked channel layer 209 may be aluminum gallium nitride, and the stacked nitride semiconductor layer 204 and the thin film nitride semiconductor layer 214 are gallium nitride. The formation sequence of the stacked channel layer 209 and the semiconductor trench 208 may be different, and those skilled in the art can achieve it through different means.

[0055] For example, in one embodiment, first form the stacked channel layer 209, and then form the semiconductor trench 208: First, a stacked channel layer 209 is formed on the nitride semiconductor layer 102 by an epitaxial method, as Figure 6 shown.

[0056] Then, by a photolithography method, a semiconductor trench 208 is etched in the stacked channel layer 209, as Figure 7 shown.

[0057] Then, an MOCVD deposition of a thin film nitride semiconductor layer 214 is performed on the semiconductor trench 208 and the stacked nitride semiconductor layer 204, as Figure 8 shown.

[0058] For another example, in another embodiment, the semiconductor trench 208 is first formed and then the stacked channel layer 209 is formed: First, a patterned sacrificial mask layer 233 is formed on the nitride semiconductor layer 102 by a photolithography method, as Figure 9 shown; Then, a stacked channel layer 209 is formed on the nitride semiconductor layer 102 by an epitaxial method, and a filling layer 234 is formed thereon, as Figure 10 shown; Next, chemical mechanical polishing is performed using the sacrificial mask layer 233 as a polishing stop layer, as Figure 11 shown.

[0059] Then, the sacrificial mask layer 233 is removed, as Figure 12 shown; Finally, using 234 as an etching mask layer, the semiconductor trench 208 is etched and formed, as Figure 13 shown.

[0060] Then, the etching mask layer 234 is removed, and an MOCVD deposition of a thin film nitride semiconductor layer 214 is performed on the semiconductor trench 208 and the stacked nitride semiconductor layer 204, as Figure 14 shown.

[0061] For another example, in another embodiment, when the uppermost layer of the stacked channel layer 209 is a stacked barrier layer 203, the above Figures 9 to 13 steps are repeated to form the semiconductor trench 208, as Figure 15 shown.

[0062] Then, the etching mask layer 234 is removed, and an MOCVD deposition of a stacked nitride semiconductor layer 204 is performed on the semiconductor trench 208 and the stacked barrier layer 203, as Figure 16 shown.

[0063] Finally, by a photolithography method, the thickness of the stacked nitride semiconductor layer 204 in the semiconductor trench 208 is reduced to form a thin film nitride semiconductor layer 214, which can also achieve the same effect asFigure 14 The same structure.

[0064] In the third step, the method for forming the gate structure may be as follows: First, a first barrier layer 206 is formed on the upper surface of the semiconductor, and then a P-type nitride semiconductor layer 210 is formed, as Figure 17 shown. Among them, the first barrier layer 206 may be aluminum gallium nitride, and the P-type nitride semiconductor layer 210 may be magnesium-doped gallium nitride.

[0065] Then, the semiconductor trench is filled with metal and etched back to form the gate metal, as Figure 18 shown. The filling metal may be a single layer or a metal combination layer formed by titanium, titanium nitride, aluminum, nickel, gold, silver, etc.

[0066] Next, under the protection of the gate metal, the P-type nitride semiconductor layer 210 located on the upper surface is etched by a self-alignment method, as Figure 19 shown. During this etching process, the first barrier layer 206 located on the upper surface may be partially or completely removed.

[0067] At this time, a gate structure of gate metal 220 - P-type nitride semiconductor layer 210 - first barrier layer 206 is formed in the semiconductor trench. The above method is beneficial to accurately control the thickness of the P-type nitride semiconductor layer 210 in the trench and is beneficial to the stability of the turn-on voltage of the device.

[0068] In the fourth step, generally, a passivation layer 215 is first formed, then a patterned contact hole is formed on the passivation layer, and then a patterned upper surface metal layer is formed on it. Among them, the patterned source metal 222 and drain metal 221 are respectively connected to the left and right ends of the semiconductor trench, and the patterned upper surface gate metal 224 is connected to the gate metal 220 through the contact hole, as Figure 20 shown.

[0069] In addition, those skilled in the art should know that the structural features and process steps mentioned in each of the above-mentioned embodiments of the present invention can be combined with each other to form more device structures and manufacturing processes of the embodiments of the present invention.

[0070] Those skilled in the art should know that the above manufacturing steps only list the key steps and do not show the complete steps of forming the device. The specific detailed manufacturing steps can be obtained according to the common manufacturing process steps in the art and common sense knowledge, and appropriate additions, subtractions, and changes can be made to them.

Claims

1. A trench-type HEMT device, the device comprising a substrate layer at the bottom, a buffer layer above the substrate layer, a first nitride semiconductor layer above the buffer layer, a passivation layer above the device, and source metal and drain metal connected to the semiconductor through the passivation layer, characterized in that, Above the first nitride semiconductor layer, there are semiconductor trenches and a stacked channel layer. Inside the semiconductor trenches, a first blocking layer and a gate metal are filled from bottom to top. The stacked channel layer includes at least one stacked blocking layer and a stacked nitride semiconductor layer that are alternately arranged up and down. A two-dimensional electron gas is formed at the interface between the stacked blocking layer and the stacked nitride semiconductor layer. A thin-film nitride semiconductor layer is also provided between the first blocking layer on the sidewall of the semiconductor trench and the stacked channel layer. The thin-film nitride semiconductor layer can respectively form a two-dimensional electron gas at the interfaces with the first blocking layer and the stacked blocking layer on its two sides.

2. The trench-type HEMT device according to claim 1, characterized in that, The semiconductor trench includes an insulating layer provided on the trench wall and a gate metal provided inside the trench. The top of the insulating layer extends outward to cover the stacked channel layer. Alternatively, the semiconductor trench includes a first blocking layer provided on the trench wall and a gate metal provided inside the trench. The top of the first blocking layer extends outward to cover the stacked channel layer. Alternatively, the semiconductor trench includes a first blocking layer provided on the trench wall, a gate metal provided inside the trench, and a second nitride semiconductor layer provided between the first blocking layer and the gate metal. The top of the first blocking layer extends outward to cover the stacked channel layer.

3. The trench-type HEMT device according to claim 1, characterized in that, Two or more parallel two-dimensional electron gases are formed at the interfaces between the first nitride semiconductor layer and the stacked blocking layer above it, and between the first blocking layer and the first nitride semiconductor layer. The concentration of the multi-segment two-dimensional electron gas formed in the device decreases successively from the center in the up and down directions.

4. The grooved HEMT device according to claim 1, wherein The two-dimensional electron gases formed by the thin-film nitride semiconductor layer respectively with the first blocking layer and the stacked blocking layer on its two sides overlap to form a single thickened channel.

5. The trench-type HEMT device according to claim 1, characterized in that, The gate metal extends upward and outward to the outside of the trench to serve as a field plate structure of the device.

6. The grooved HEMT device according to claim 1, characterized in that, Above the upper surface of the semiconductor, a source field plate structure connected to the source is provided to reduce the surface electric field when the device is reverse-biased.

7. The trench-type HEMT device according to claim 1, wherein, A P-type nitride semiconductor region is provided below the semiconductor trench.

8. A manufacturing method of a trench-type HEMT device, characterized in that, The manufacturing method includes the following steps: First step, form a buffer layer on the substrate layer, and then form a first nitride semiconductor layer on the buffer layer. Second step, form a stacked channel layer, a semiconductor trench, and a thin-film nitride semiconductor layer on the first nitride semiconductor layer. Third step, form a gate structure inside the semiconductor trench. Fourth step, form a passivation layer and an upper surface metal, and finally form the device.

9. The manufacturing method of the trench-type HEMT device according to claim 8, wherein, The specific steps in the second step are: First, form a stacked blocking layer and a stacked nitride semiconductor layer on the first nitride semiconductor layer by an epitaxial method, and then, by a photolithography method, etch out a semiconductor trench on the stacked channel layer; then deposit a thin-film nitride semiconductor layer on the semiconductor trench and the stacked nitride semiconductor layer. Alternatively, The specific steps in the second step are as follows: First, a patterned sacrificial mask layer is formed on the first nitride semiconductor layer; then, a stacked channel layer is formed on the nitride semiconductor layer by an epitaxial method, and a filling layer is formed thereon; then, chemical mechanical polishing is performed with the sacrificial mask layer as a polishing stop layer; then, the sacrificial mask layer is removed; finally, the semiconductor trench is etched with the filling layer as an etching mask layer. Then, the etching mask layer is removed, and a thin film nitride semiconductor layer is deposited on the semiconductor trench and the stacked nitride semiconductor layer; alternatively, a stacked nitride semiconductor layer is deposited on the semiconductor trench and the stacked barrier layer, and the thickness of the stacked nitride semiconductor layer in the semiconductor trench is reduced by photolithography to form a thin film nitride semiconductor layer.

10. The manufacturing method of the trench-type HEMT device according to claim 8, characterized in that, The specific steps in the third step are as follows: First, a first barrier layer is formed on the upper surface of the semiconductor, and then a P-type second nitride semiconductor layer is formed; then, the semiconductor trench is filled with metal and etched back to form a gate metal; then, under the protection of the gate metal, the P-type second nitride semiconductor layer located on the upper surface is etched by a self-aligned method so that it retracts into the trench.

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