Method of forming semiconductor device and integrated circuit

Abstract

The method for forming the transistor comprises the following steps: forming a plurality of stacked channels of the transistor; forming a plurality of semiconductor structures staggered with the channels; and forming a semiconductor seed layer in the end of the channel and in the source / drain trench on the semiconductor structure. A source / drain region of the transistor is then epitaxially grown from the seed layer in the source / drain trench. The semiconductor structure is then replaced with a dielectric internal spacer. A gate metal is then formed that encases the channel and is separated from the source / drain regions by dielectric internal spacers. The embodiment of the invention also relates to a method of forming the semiconductor device and an integrated circuit.

Description

Technical Field

[0001] Embodiments of the present application relate to methods of forming semiconductor devices and integrated circuits. Background Art

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advances in integrated circuit materials and design have produced multiple generations of integrated circuits, each having smaller and more complex circuits than the previous generation. During the development of integrated circuits, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometric size (i.e., the smallest components (or lines) that can be created using a manufacturing process) has decreased. Such scaling generally provides benefits by increasing production efficiency and reducing related costs. Such scaling also increases the complexity of processing and manufacturing integrated circuits. Summary of the Invention

[0003] Some embodiments of the present application provide a method of forming a semiconductor device, including: forming a plurality of stacked channels; forming a semiconductor seed layer on an end of the stacked channels; forming source / drain regions of the transistor by performing epitaxial growth from the seed layer; after forming the source / drain regions, forming a plurality of dielectric inner spacers that are interleaved with the channels and separated from the source / drain regions by the semiconductor seed layer; and forming a gate metal of the transistor that wraps the channels and is separated from the source / drain regions by the dielectric inner spacers.

[0004] Some other embodiments of the present application provide an integrated circuit, including: a transistor, including: a plurality of stacked channels; a gate metal that wraps the channels; a gate dielectric located between the channels and the gate metal; a plurality of dielectric inner spacers that are interleaved with the channels; source / drain regions; and a semiconductor seed layer located between the inner spacers and the source / drain regions.

[0005] Some further embodiments of the present application provide a method of forming a semiconductor device, including: forming a plurality of stacked channels; forming source / drain regions adjacent to the stacked channels; forming a plurality of dielectric inner spacers of the transistor by oxidizing a plurality of semiconductor structures that are interleaved with the channels; forming a gate dielectric on the channels; and forming a gate metal that wraps the channels and is separated from the source / drain regions by the dielectric inner spacers. Brief Description of the Drawings

[0006] When read in conjunction with the drawings, various aspects of the embodiments of the present disclosure can be best understood. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0007] Figures 1 to 19B are perspective views and cross-sectional views of an integrated circuit at various processing stages according to some embodiments.

[0008] Figures 20A to 22B are perspective views and cross-sectional views of an integrated circuit at various processing stages according to some embodiments.

[0009] Figure 23 is a cross-sectional view of an integrated circuit according to some embodiments.

[0010] Figure 24 is a cross-sectional view of an integrated circuit according to some embodiments.

[0011] Figure 25 is a flowchart of a method for forming an integrated circuit according to some embodiments.

[0012] Figure 26 is a flowchart of a method for forming an integrated circuit according to some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. In addition, the embodiments of the present disclosure may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity, and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] In addition, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as shown in the figures. Except for the orientation depicted in the figures, spatially relative terms are intended to include different orientations of the device during use or operation. The device may be oriented otherwise (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0015] Terms indicating relative degree, such as "about", "substantially", etc., should be interpreted as would be considered by a person of ordinary skill in the art in view of the current technical specifications.

[0016] Embodiments of the present disclosure generally relate to semiconductor devices and, more particularly, to field effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructure devices. Examples of nanostructure devices include gate-all-around (GAA) devices, nanosheet FETs (NSFETs), nanowire FETs (NWFETs), etc. In advanced technology nodes, the active region spacing between nanostructure devices is typically uniform, the source / drain epitaxial structure is symmetric, and the metal gate surrounds the four sides of the nanostructure (e.g., nanosheet). The gate-drain capacitance (“Cgd”) increases due to the larger metal gate caps and the increased source / drain epitaxial dimensions.

[0017] Embodiments of the present disclosure provide a gate-all-around transistor that includes a first source / drain region and a second source / drain region, a plurality of stacked channels each extending between the first source / drain region and the second source / drain region, a gate metal that wraps around the channels, and a low-k internal spacer located between adjacent channels and electrically isolating the gate metal from the source / drain regions. Embodiments of the present disclosure advantageously form the internal spacer after forming the source / drain regions. More particularly, embodiments of the present disclosure form a dielectric nanostructure between the channels, recess the dielectric nanostructure, form a semiconductor structure in the recess, and form a semiconductor seed layer on the ends of the channels and on the outer surface of the semiconductor structure. The source / drain regions grow epitaxially from the semiconductor seed layer, and the dielectric nanostructure is removed. After removing the dielectric nanostructure, a low-k dielectric internal spacer is formed to replace the sacrificial semiconductor nanostructure. The dielectric internal spacer can include an oxide or an air gap. The gate metal is then formed. The result is a reduced capacitance between the gate metal and the source / drain regions, an increased switching speed of the transistor, a higher quality source / drain region, enhanced strain for improved device performance, and a reduced time in forming the source / drain regions.

[0018] The transistor can be referred to as a “nanostructure transistor,” and the channels can be referred to as “semiconductor nanostructures.” The nanostructure transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more lithography processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine lithography and self-alignment processes, thus allowing the creation of patterns having, for example, a pitch smaller than that achievable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. A spacer is formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer can then be used to pattern the nanostructure transistor structure.

[0019] Figures 1 to 19BIs a perspective view and a side cross-sectional view of a portion of integrated circuit 100 at various processing stages. The manufacturing process produces a plurality of transistors 101, which will be described in further detail below.

[0020] Figure 1 Is a perspective view of integrated circuit 100 in an intermediate processing state according to some embodiments. Integrated circuit 100 includes a substrate 102. Substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. In an exemplary embodiment, the substrate includes silicon. Optionally, substrate 102 may include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium phosphoarsenide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, indium gallium phosphide, and / or gallium indium phosphoarsenide; or combinations thereof. Other substrates may be used, such as single-layer, multi-layer, or graded substrates.

[0021] Integrated circuit 100 includes a semiconductor stack 103, and semiconductor stack 103 includes a plurality of semiconductor layers 104 and sacrificial semiconductor layers 106 that alternate with each other. As will be elaborated in further detail below, semiconductor layer 104 will be patterned to form the stacked channels of a plurality of transistors. As will be elaborated in more detail below, sacrificial semiconductor layer 106 will ultimately be completely removed and is used to enable the formation of gate metals and other structures around the channels. In Figure 1 is shown three semiconductor layers 104 and three sacrificial semiconductor layers 106. In some embodiments, multi-layer stack 103 may include fewer or more layers than shown in Figure 1 shown.

[0022] In some embodiments, semiconductor layer 104 may be formed of a first semiconductor material suitable for n-type semiconductor nanostructure transistors, such as silicon, silicon carbide, etc., and sacrificial semiconductor layer 106 may be formed of a second semiconductor material suitable for p-type semiconductor nanostructure transistors, such as silicon germanium, etc. Each of the layers of multi-layer stack 103 may be epitaxially grown using processes such as vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.

[0023] As Figure 1As shown, integrated circuit 100 includes a hard mask layer 108 formed over a top sacrificial semiconductor layer 106. A thin dielectric layer 111 is located on stack 103 below the hard mask layer 108. In some embodiments, the hard mask layer 108 includes a dielectric material. The dielectric material may include SiN, SiCN, SiOCN, SiOC, or other suitable dielectric materials. The hard mask layer 108 may have a thickness between 3 nm and 20 nm. In some embodiments, the dielectric layer 111 includes SiO, SiN, SiCN, SiOCN, SiOC, or other suitable dielectric materials. The dielectric layer 111 may have a thickness between 1 nm and 10 nm. Other materials and thicknesses may be used for the hard mask layer 108 and the dielectric layer 111 without departing from the scope of the embodiments of the present disclosure.

[0024] Due to the high etch selectivity between the materials of the semiconductor layer 104 and the sacrificial semiconductor layer 106, the sacrificial semiconductor layer 106 of the second semiconductor material can be removed without significantly removing the semiconductor layer 104 of the first semiconductor material, thereby allowing the semiconductor layer 104 to be released to form the stacked channel region of the transistor.

[0025] In Figure 2 , the hard mask layer 108 has been patterned according to a lithography process. After patterning the hard mask layer 108, trenches 110 have been formed in stack 103 and substrate 102. The trenches 110 can be formed by an anisotropic etching process that etches in a downward direction. The etching process defines semiconductor fins 112 by forming trenches 110 that pass through the hard mask layer 108, the dielectric layer 111, the sacrificial semiconductor layer 106, the semiconductor layer 104, and the substrate 102. The result of the etching process is the formation of multiple semiconductor fins 112 by stack 103. The semiconductor fins 112 extend in the X direction.

[0026] In Figure 3 , shallow trench isolation regions 116 have been formed by depositing a dielectric material in the trenches 110 between the fins 112. The dielectric material can be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes. In an exemplary embodiment, the dielectric material includes silicon oxide. However, without departing from the scope of the embodiments of the present disclosure, the dielectric material may include SiN, SiCN, SiOC, SiOCN, or other dielectric materials. A chemical mechanical planarization (CMP) process has been implemented to remove excess material of the shallow trench isolation regions 116 from the top surface of the hard mask layer 108.

[0027] In Figure 4In [description], the hard mask layer 108 and the dielectric layer 111 have been removed. As a result, the top semiconductor layer 104 is exposed and has a top surface that is lower than the top surface of the shallow trench isolation region 116. The hard mask layer 108 and the dielectric layer 111 can be removed using one or more etching processes. The etching process can include wet etching, dry etching, or other suitable etching processes.

[0028] In Figure 5 In [description], according to some embodiments, an etch-back process has been implemented to recess the top of the shallow trench isolation region 116. The etch-back process causes the shallow trench isolation region 116 to be completed. The top surface of the shallow trench isolation region 116 is lower than the lowermost sacrificial semiconductor layer 106 of each stack 112.

[0029] In Figure 6 In [description], a sacrificial gate structure 118 has been formed above the fins 112. The sacrificial gate structure 118 extends in the Y direction and is perpendicular to the fins 112. Each sacrificial gate structure 118 spans multiple fins 112. The sacrificial gate structure 118 is also formed in the trench 110. Figure 6 Only a single sacrificial gate structure 118 is shown. However, in practice, multiple sacrificial gate structures 118 are formed to extend parallel to each other in the Y direction.

[0030] The sacrificial gate structure 118 includes a dielectric layer 126. In an exemplary embodiment, the dielectric layer 126 includes silicon oxide and can be referred to as a dummy gate oxide layer. However, optionally, without departing from the scope of the embodiments of the present disclosure, the dielectric layer 126 can include SiN, SiCN, SiOC, SiOCN, or other dielectric materials. In some embodiments, the dielectric layer 126 has a low-k dielectric material. The dielectric layer 126 can be deposited by CVD, ALD, or PVD.

[0031] The sacrificial gate structure 118 includes a sacrificial gate layer 128 on the dielectric layer 126. The sacrificial gate layer 128 can include a material having a high etch selectivity relative to the shallow trench isolation region 116. In an exemplary embodiment, the sacrificial gate layer 128 includes polysilicon. However, the sacrificial gate layer 128 can be a conductive, semi-conductive, or non-conductive material and can be or include amorphous silicon, poly-silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The sacrificial gate layer 128 can be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material.

[0032] The sacrificial gate structure 118 includes a dielectric layer 130 on the sacrificial gate layer 128 and a dielectric layer 132 on the dielectric layer 130. The dielectric layers 130 and 132 can correspond to a first mask layer and a second mask layer. The dielectric layer 130 can include silicon nitride, silicon oxynitride, or other suitable dielectric materials. The dielectric layer 130 can include silicon nitride, silicon oxynitride, or other suitable dielectric materials. The dielectric layers 130 and 132 are different materials from each other and can be deposited using CVD, ALD, PVD, or other suitable deposition processes. Without departing from the scope of the embodiments of the present disclosure, other materials and deposition processes can be used for the dielectric layers 130 and 132.

[0033] A gate spacer layer 134 has been formed on the sidewalls of the layers 126, 128, 130, and 132. The gate spacer layer 134 can also be formed on other exposed surfaces of the integrated circuit. For example, portions of the gate spacer layer 134 are formed on the top surface of the fin 112, on the sidewalls of the fin 112, and on the top surface of the shallow trench isolation region 116. The gate spacer layer 134 can include one or more of SiO, SiN, SiON, SiCN, SiOCN, SiOC, or other suitable dielectric materials. The gate spacer layer 134 can be formed by PVD, CVD, ALD, or other suitable deposition processes.

[0034] In Figure 7 the horizontal portions (e.g., in the X-Y plane) of the gate spacer layer 134 have been removed. In other words, the portions of the gate spacer layer located on the top surface of the stack 112 and on the top surface of the shallow trench isolation region 116 have been removed. The vertically thicker portions of the gate spacer layer 134 remain on the sidewalls of the fin 112. The removal of the portions of the gate spacer layer 134 can be accomplished via an anisotropic etching process to expose the upper surfaces of the fin 112 and the trench isolation region 116. After patterning the gate spacer layer, the vertically thicker portions of the gate spacer layer 134 remain, such as Figure 7 the portions shown in

[0035] In Figure 7In , after removing a portion of the gate spacer layer 134, source / drain trenches 120 are formed in the fin 112. The sacrificial gate structure 118 and the gate spacer layer 134 act as masks for forming the source / drain trenches 120 in the fin 112. In particular, one or more etching processes are implemented to form the source / drain trenches 120 in the fin 112. Forming the source / drain trenches 120 includes etching through each of the semiconductor layer 104 and the sacrificial semiconductor layer 106 and a portion of the substrate 102. Accordingly, the removal operation may include suitable etching operations for removing the materials of the semiconductor layer 104, the sacrificial semiconductor layer 106, and the substrate 102. The etching process may include reactive ion etching (RIE), neutral beam etching (NBE), atomic layer etching (ALE), etc.

[0036] The formation of the source / drain trenches 120 causes a stack 122 for forming the channel 105 to be formed. Each stack 122 of the channel 105 corresponds to a stacked channel of the transistor. The formation of the source / drain trenches 120 also causes a plurality of sacrificial semiconductor nanostructures 107 to be formed from the sacrificial semiconductor layer 106. After forming the source / drain trenches 120, the channel 105 and the sacrificial semiconductor nanostructures 107 may have substantially similar lateral dimensions.

[0037] Figure 8A is a perspective view of an integrated circuit 100 according to some embodiments. Figure 8B is according to some embodiments of the integrated circuit 100 along Figure 8A and taken along a cut line X and at the same processing stage as Figure 8A a cross-sectional view.

[0038] In Figure 8A and Figure 8B the sacrificial semiconductor nanostructures 107 have been removed. The sacrificial semiconductor nanostructures 107 may be removed by implementing an etching process that selectively etches the material of the sacrificial semiconductor nanostructures 107 with respect to the material of the channel 105. As previously described, in one exemplary embodiment, the channel 105 is silicon and the sacrificial semiconductor nanostructures 107 are silicon germanium. The etching process selectively etches the silicon germanium of the sacrificial semiconductor nanostructures 107 with respect to the silicon of the channel 105. The result is that the sacrificial semiconductor nanostructures 107 are completely removed and the channel 105 remains. As previously described, other materials may be used for the channel 105 and the sacrificial semiconductor nanostructures 107 without departing from the scope of the embodiments of the present disclosure.

[0039] Figure 8A and Figure 8B The views of also show that the source / drain trenches 120 extend into the substrate 102. In particular, the etching process for forming the source / drain trenches 120 also forms grooves in the substrate 102. As Figure 8BAs shown, the groove can be concave.

[0040] Figure 9A is a perspective view of an integrated circuit 100 according to some embodiments. Figure 9B is a cross-sectional view of the integrated circuit 100 according to some embodiments at the Figure 9A same processing stage.

[0041] In Figure 9A and Figure 9B a sacrificial dielectric nanostructure 135 has been formed to replace the sacrificial semiconductor nanostructure 107. Accordingly, the sacrificial dielectric nanostructure 135 is formed between adjacent channels 105. The lowermost sacrificial dielectric nanostructure 135 of each stack 122 is located between the substrate 102 and the lowermost channel 105 of each stack 122. In an exemplary embodiment, the sacrificial dielectric nanostructure 135 comprises silicon oxide. Optionally, the sacrificial dielectric nanostructure 125 may comprise SiON, SiCN, SiOCN, SiOC, or other suitable dielectric materials.

[0042] In some embodiments, the sacrificial dielectric nanostructure 135 is formed by depositing a dielectric material in the source / drain trenches 120. The dielectric material also fills the spaces left between the channels 105 by removing the sacrificial semiconductor nanostructure 107. The dielectric material may be deposited by CVD, ALD, PVD, or other suitable deposition processes. After depositing the dielectric material, an etching process is performed using the gate spacer layer 134 as a mask. The etching process is an anisotropic etching process that selectively etches in a downward direction. As a result, the dielectric material is removed from the source / drain trenches 120, and only the dielectric nanostructure 135 between the channels 105 remains.

[0043] Figure 10A is a perspective view of an integrated circuit 100 according to some embodiments. Figure 10B is a cross-sectional view of the integrated circuit 100 according to some embodiments at the Figure 10A same processing stage.

[0044] In Figure 10A and Figure 10B an etching process has been performed to form grooves 133 in the dielectric nanostructure 135. In particular, an isotropic etching process is performed that selectively etches the material of the dielectric nanostructure 135 relative to other exposed materials. The etching process is timed to remove the end portions of the dielectric nanostructure 135 without completely removing the dielectric nanostructure 135. As a result, grooves 133 are formed in the dielectric nanostructure 135 between adjacent channels 105. In other words, the ends of the dielectric nanostructure 135 are recessed relative to the ends of the channels 105.

[0045] Figure 11A Is a perspective view of an integrated circuit 100 according to some embodiments. Figure 11B Is a cross-sectional view of the integrated circuit 100 according to some embodiments at the Figure 11A Same processing stage.

[0046] In Figure 11A And Figure 11B A semiconductor structure 137 has been formed in the groove 133. In particular, an epitaxial growth process has been implemented to grow the semiconductor structure 137 from the channel 105. In an exemplary embodiment, the semiconductor structure 137 includes silicon germanium. However, other semiconductor materials may be utilized without departing from the scope of the embodiments of the present disclosure. The semiconductor structure may be referred to as a sacrificial semiconductor inner spacer because a dielectric inner spacer will be formed to replace the sacrificial semiconductor inner spacer.

[0047] In fact, after the epitaxial growth process of forming the semiconductor structure 137, the semiconductor material extends into the source / drain trench 120. Therefore, an anisotropic etching process is implemented, which selectively removes the semiconductor material of the semiconductor structure 137 in the vertical direction such that only the portion covered by the channel 105 remains.

[0048] Figure 12A Is a perspective view of an integrated circuit 100 according to some embodiments. Figure 12B Is a cross-sectional view of the integrated circuit 100 according to some embodiments at the Figure 12A Same processing stage.

[0049] In Figure 12A And Figure 12B A groove 139 has been formed in the channel 105. In particular, an etching process has been implemented to form the groove 139 in the channel 105. In particular, an isotropic etching process is implemented, which selectively etches the material of the channel 105 with respect to other exposed materials. The etching process is timed to remove the end portion of the channel 105 without completely removing the channel 105. As a result, a groove 139 is formed in the channel 105. In other words, the end of the channel 105 is recessed with respect to the end of the semiconductor structure 137. In some embodiments, the groove 139 is not formed, resulting in straight vertical sidewalls of the channel 105 and the semiconductor structure 137.

[0050] In Figure 12A And Figure 12B A bottom semiconductor layer 141 has been formed in the bottom of the trench 120 formed in the recessed groove in the substrate 102. The bottom semiconductor layer may include an intrinsic semiconductor material such as undoped silicon, undoped silicon germanium, or other semiconductor materials.

[0051] Figure 13AIs a perspective view of an integrated circuit 100 according to some embodiments. Figure 13B Is the integrated circuit 100 according to some embodiments at the Figure 13A Same processing stage cross-sectional view.

[0052] In Figure 13A And Figure 13B A continuous semiconductor seed layer 143 has been formed in the source / drain trench 120 and the recess 139. The semiconductor seed layer 143 can be formed on the exposed surfaces of the channel 105, the semiconductor structure 137, and the bottom semiconductor layer 141. In some embodiments, the semiconductor seed layer includes silicon. The silicon can be doped with boron, gallium, or other dopant materials. In some embodiments, the semiconductor seed layer 143 can include silicon germanium. The silicon germanium can include germanium between 10% and 30%, and can be doped with boron, gallium, or other dopant materials. The semiconductor seed layer 143 can have a thickness between 0.5 nm and 10 nm. Other materials and thicknesses can be used for the semiconductor seed layer without departing from the scope of the embodiments of the present disclosure.

[0053] In some embodiments, a seam 145 is formed in the semiconductor seed layer 143. The seam 145 may be generated due to the presence of the recess 139 and the channel 105. The seam 145 can correspond to a slot or gap formed adjacent to the recess 139. In some embodiments, the recess 139 is not formed. This may result in the absence of the seam 139 in the semiconductor seed layer 143.

[0054] Figure 14A Is a perspective view of an integrated circuit 100 according to some embodiments. Figure 14B Is the integrated circuit 100 according to some embodiments at the Figure 14A Same processing stage cross-sectional view.

[0055] In Figure 14A And Figure 14B The source / drain regions 140 have been formed. In the illustrated embodiment, the source / drain regions 140 grow epitaxially from the semiconductor seed layer 143. The source / drain regions 140 fill the source / drain trenches 120. For each stack 122 of the channel 105, there are two source / drain regions 140. Each channel 105 of the stack 122 extends between adjacent source / drain regions 140. The semiconductor seed layer 143 can be considered part of the source / drain regions 140. Some stacks 122 of the channel 105 can share the source / drain regions 140 with stacks 122 of the channel 105 adjacent in the X direction.

[0056] As in Figure 14AAs can be seen, source / drain regions 140 are grown over portions of the gate spacer layer 134. A lower portion of the source / drain regions 140 is formed by remnants of the gate spacer layer 134 on the surface of the trench isolation region 116 in the Y direction.

[0057] In some embodiments, the source / drain regions 140 apply beneficial stress on the corresponding channels 105, thereby improving performance. Additionally, since the source / drain regions 140 are grown from a continuous semiconductor seed layer 143, the source / drain regions 140 have high quality and fewer defects. Further, epitaxial growth can completely cover the channel ends with a smaller epitaxial volume. In some embodiments, the width of the laterally grown source / drain regions 140 can be between 0 nm and 15 nm. In some embodiments, the reduced volume of the source / drain regions 140 can result in a narrower oxide diffusion (OD) spacer that defines the active region. For example, an OD spacer according to some embodiments of the present disclosure can be narrower by between 0 nm and 15 nm than other solutions that can have an OD range between 20 nm and 50 nm. In some embodiments, the continuous semiconductor seed layer 143 is silicon.

[0058] The source / drain regions 140 can include any acceptable material, such as suitable for n-type or p-type devices. In some embodiments, for n-type devices, the source / drain regions 140 include materials that apply tensile strain in the channel region, such as silicon, SiC, SiCP, SiP, etc. According to certain embodiments, when forming p-type devices, the source / drain regions 140 include materials that apply compressive strain in the channel region, such as SiGe, SiGeB, Ge, GeSn, etc. The source / drain regions 140 can have a surface that protrudes from the corresponding surfaces of the fins and can have facets. Adjacent source / drain regions 140 can be merged in some embodiments to form a single source / drain region 140 over two adjacent fins of the fin 112.

[0059] The source / drain regions 140 can be implanted with dopants, followed by an annealing process. The source / drain regions 140 can have an impurity concentration between about 10 19 cm -3 and about 10 21 cm -3 . The n-type and / or p-type impurities for the source / drain regions 140 can be any of the impurities discussed previously. In some embodiments, the source / drain regions 140 are doped in-situ during growth.

[0060] Figure 15 is a perspective view of an integrated circuit 100 according to some embodiments. In Figure 15In [the structure], a contact etch stop layer (CESL) 144 and an interlayer dielectric (ILD) 146 have been formed. The CESL layer 144 may include a thin dielectric layer conformally deposited on the exposed surfaces of the source / drain regions 140, the trench isolation regions 116, the gate spacer layer 134, and other exposed surfaces. The CESL layer 144 may include SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. The CESL 144 may be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0061] The dielectric layer 146 covers the CESL 144. The dielectric layer 146 may include SiO, SiON, SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. The dielectric layer 146 may be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0062] In some embodiments, the presence of the semiconductor seed layer 143 results in a better U% of growth of the source / drain regions 140 that can completely cover the channel ends. In other words, the source / drain regions 140 occupy a lower lateral volume, which is beneficial for reducing parasitic capacitance and OD pitch scaling. Additionally, this may lead to a shorter epitaxial growth process to reduce the cost of the epitaxial growth process. Due to the completion of the oxide inner spacers in the device, this may also result in a reduced gate-to-drain capacitance. This can be mainly seen Figure 14A in [the structure] where the source / drain regions 140 do not protrude beyond the outer edge of the lower portion of the gate spacer layer 134. This results in a reduced gate-to-source / drain capacitance and a reduced active region pitch scaling, as will be described in more detail below. In some embodiments, the use of the seed layer 143 results in high-quality source / drain regions with fewer defects and high beneficial strain to enhance the performance of P-type transistors.

[0063] In Figure 15 [the structure], a CMP process has been implemented to reduce the height of the sacrificial gate structure 118. The result of the CMP process is the complete removal of the dielectric layers 130 and 132. The heights of the sacrificial gate layer 128, the gate spacer layer 134, the CESL layer 144, and the dielectric layer 146 have been reduced, and the top surface has been planarized. In some embodiments, the process for forming the source / drain regions 140 results in a narrower OD size. The dimension in the Y direction of the trench isolation regions 116 corresponding to the upper protruding portions of the substrate 102. This can be achieved because the lateral width of the source / drain regions is restricted, as previously described. This reduces the risk of bridging between the source / drain regions adjacent to each other in the Y direction. The reduced risk of bridging allows for a smaller OD size. Additionally, as Figure 15As shown, the outer edge of the source / drain region 140 protrudes only a small distance in the Y direction beyond the inner edge of the adjacent lower portion of the gate spacer layer 134. In some embodiments, the outer edge of the source / drain region 140 does not protrude beyond the outer edge of the lower portion of the gate spacer layer 134.

[0064] Figure 16 is a perspective view of an integrated circuit 100 according to some embodiments along Figure 15 the cut line 16. In Figure 16 it, the sacrificial gate structure 118 has been removed from between the gate spacer layers 134. In particular, the dielectric layer 126 and the sacrificial gate layer 128 have been completely removed from between the gate spacer layers 134.

[0065] In some embodiments, the sacrificial gate layer 128 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the sacrificial gate layer 128 without etching the spacer layer 134. When etching the sacrificial gate layer 128, the dielectric layer 126 (when present) can be used as an etch stop layer. Then, after removing the sacrificial gate layer 128, the dielectric layer 126 can be removed.

[0066] The removal of the sacrificial gate layer 128 and the dielectric layer 126 creates a void between the gate spacer layers 134 above the channel 105. As will be elaborated in more detail below, the upper portion of the gate metal or gate electrode will be formed in the void. Thus, the sacrificial gate layer 128 is sacrificial in the sense that the upper portion of the gate metal will ultimately be formed in its place.

[0067] Figure 17A is a perspective view of an integrated circuit 100 according to some embodiments. Figure 17B is a cross-sectional view of an integrated circuit 100 according to some embodiments at the Figure 17A same processing stage. Figure 17A The view of Figure 16 is taken along the same cut line as

[0068] In Figure 17A and Figure 17B the channel 105 is released by removing the dielectric nanostructures 135. The dielectric nanostructures 135 can be removed by a selective etching process using an etchant that is selective to the material of the dielectric nanostructures 135, such that the dielectric nanostructures 135 are removed with substantially no etching of the channel 105 or the semiconductor structure 137. The removal of the dielectric nanostructures 135 creates a void 148 between the channels 105.

[0069] Figure 18A is a perspective view of an integrated circuit 100 according to some embodiments.Figure 18B is a cross-sectional view of integrated circuit 100 according to some embodiments at the Figure 18A same processing stage. Figure 18A The view of Figure 16 is taken along the same cut line as

[0070] In Figure 18A and Figure 18B , according to some embodiments, the dielectric inner spacer 136 is formed from the semiconductor structure 137. In particular, the semiconductor structure 137 is transformed into the dielectric inner spacer 136. In one example, an oxidation process is performed to oxidize the semiconductor structures 137 to transform them into the dielectric inner spacers 136.

[0071] In some embodiments, the oxidation process includes generating and performing furnace oxidation in the presence of a plasma. In some embodiments, the plasma is generated between 500 °C and 800 °C. Furnace oxidation is performed in the presence of a plasma to transform or replace the semiconductor structures into the dielectric inner spacers 136. In some embodiments, the semiconductor structures 137 include silicon germanium. The oxidation process transforms the silicon germanium into silicon germanium oxide. In some embodiments, the concentration of germanium is greater than or equal to 0% and less than or equal to 50%. In some embodiments, the semiconductor structures 137 include silicon, and the oxidation process produces silicon oxide dielectric inner spacers 136. Other types of semiconductors may be utilized without departing from the scope of the embodiments of the present disclosure. In some embodiments, the furnace oxidation process utilizes H2 / O2 gas. In some embodiments, the inner spacer 136 includes SiO because Ge can be removed as a gaseous byproduct through the furnace oxidation process or through a subsequent H2 annealing process. In some embodiments, the annealing process is not performed.

[0072] In some embodiments, due to the use of high-energy plasma, the oxidation process produces porous dielectric inner spacers 136. This can further reduce the dielectric constant of the dielectric inner spacers. This further reduces the gate-to-source / drain capacitance and results in a higher switching speed of the transistor 101.

[0073] In some embodiments, the dielectric inner spacer 136 has a width between 1 nm and 15 nm in the X direction. In some embodiments, the dielectric inner spacer 136 has a height dimension between 1 nm and 15 nm in the Z direction. In some embodiments, the dielectric inner spacer has a flat outer surface. In some embodiments, the dielectric inner spacer 136 protrudes outwardly towards the source / drain region 140. The protruding portion may extend between 1 nm and 10 nm. In some embodiments, the dielectric inner spacer 136 has a flat inner surface. In some embodiments, the dielectric inner spacer 136 protrudes into the gap 148, where the protruding depth is between 1 nm and 10 nm.

[0074] In some embodiments, the dielectric inner spacer 136 also causes an interfacial dielectric layer 162 to be formed on the exposed surface of the channel 105. The interfacial dielectric layer 162 is part of the gate dielectric, as will be explained in more detail below.

[0075] Figure 19A is a perspective view of an integrated circuit 100 according to some embodiments. Figure 19B is an integrated circuit 100 according to some embodiments in and Figure 19A is a cross-sectional view of the same processing stage. Figure 19A The view of is in and Figure 16 is taken along the same cut line.

[0076] In Figure 19A and Figure 19B According to some embodiments, an interfacial dielectric layer 162, a high-k dielectric layer 164, and a gate metal 166 have been formed. The interfacial gate dielectric layer 162 may be formed as described with respect to Figure 18A and Figure 18B or may be formed in a different process.

[0077] The interfacial gate dielectric layer 162 is deposited on all exposed surfaces of the channel 105. The interfacial gate dielectric layer 162 wraps around the channel 105. The interfacial gate dielectric layer 162 may include a dielectric material such as silicon oxide, silicon nitride, or other suitable dielectric material. The interfacial gate dielectric layer 162 may include a dielectric that is relatively low-k relative to a high-k dielectric such as hafnium oxide or other high-k dielectric materials that may be used in the gate dielectric of a transistor. The high-k dielectric may include a dielectric material having a dielectric constant higher than that of silicon oxide. The interfacial gate dielectric layer 162 may be formed by a thermal oxidation process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. The interfacial gate dielectric layer 162 may have a thickness between 0.5 nm and 2 nm. Other materials, deposition processes, and thicknesses may be used for the interfacial gate dielectric layer 162 without departing from the scope of the embodiments of the present disclosure.

[0078] The high-k dielectric layer 164 is deposited in a conformal deposition process. The conformal deposition process deposits the high-k dielectric layer 164 on the interfacial gate dielectric layer 162, on the substrate 102, on the trench isolation region 116, and on the gate spacer layer 134. The high-k gate dielectric layer 164 wraps around the channel 105. The high-k gate dielectric layer 164 has a thickness between 1 nm and 3 nm. The high-k dielectric layer includes one or more dielectric material layers, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, titanium oxide, hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The high-k dielectric layer 164 can be formed by CVD, ALD, or any suitable method. Other thicknesses, deposition processes, and materials can be used for the high-k dielectric layer 164 without departing from the scope of the embodiments of the present disclosure. The high-k dielectric layer 164 is a gate dielectric layer.

[0079] The gate metal 166 is deposited on all exposed surfaces of the high-k dielectric layer 164. The gate metal 166 wraps around the channel 105. Although the gate metal 166 is shown as a single layer in Figure 19A and Figure 19B , in reality, the gate metal 166 can include one or more conductive liner layers, work function layers, and gate fill layers that together constitute the gate metal. The gate metal can include one or more of Ti, TiN, Ta, TaN, Al, Cu, Co, Ru, W, Au, or other suitable conductive materials. The gate metal 166 can be deposited by PVD, ALD, or CVD. Other configurations, materials, and deposition processes can be used for the gate metal 166 without departing from the scope of the embodiments of the present disclosure.

[0080] At Figure 19A and Figure 19B in the processing stage shown, the transistor 101 is substantially completed. Each transistor 101 includes a stack 122 of channels 105 that extend between the source / drain regions 140 and serve as the stacked channel of the transistor 101. The gate metal 166 serves as a gate electrode surrounding the channel 105.

[0081] At Figure 19A , there are no breaks in the gate metal 166, such that the gate electrodes of adjacent transistors 101 are all shorted together. Although Figure 19B is not shown, in a further processing step, a gate cutting process can be implemented to electrically isolate portions of the gate metal 166 to form electrically isolated gate electrodes for the transistors 101.

[0082] Although Figure 19A and Figure 19BNot shown, source / drain contact members may also be formed. Trenches may be formed in the CESL layer 144 and the dielectric layer 146 to expose the top surface of the source / drain regions 140. Silicide may be formed on the exposed portions of the source / drain regions 140. Conductive vias or plugs may be formed to contact the silicide. Voltage may be applied to the source / drain regions 140, or current may be conducted through the source / drain contact members.

[0083] Figures 20A to 22B A process for forming a transistor 101 of an integrated circuit 100 according to some embodiments is shown. Figures 20A to 22B The process may be substantially similar to the process regarding Figures 1 to 17B shown and described.

[0084] Figure 20A is a perspective view of an integrated circuit 100 according to some embodiments. Figure 20B is a cross-sectional view of an integrated circuit 100 according to some embodiments at the same processing stage as Figure 20A the same.

[0085] In Figure 20A and Figure 20B multiple porous dielectric films 168 have been formed from the inner end portions of the semiconductor structure 137. The porous dielectric films 168 are formed by performing an oxidation process in the presence of the semiconductor structure 137. The oxidation process may include generating a plasma in the presence of the semiconductor structure 137. Generating the plasma may include raising the temperature to between 200 °C and 400 °C, but other temperature ranges may be utilized without departing from the scope of the embodiments of the present disclosure. An oxidizing agent is introduced to assist the oxidation process in combination with the plasma. The result of this process is that the inner ends of the semiconductor structure 137 become dielectric material. In some embodiments, the plasma is generated using a combination of a magnetic field and microwave radiation to ionize the gas. In some embodiments, the plasma may be generated using an electron cyclotron resonance tool, a plasma enhanced CVD tool, or other suitable tool. In some embodiments, oxygen is used to form the plasma.

[0086] In addition, holes are formed through the dielectric material. The holes are sized to be able to remove the remaining portion of the semiconductor structure 137 in a subsequent etching process. The holes are small enough to ensure that the material for forming the high-K dielectric 164 does not pass through the porous dielectric film 137. In some embodiments, the hole size is between 0.5 nm and 1.5 nm, but other sizes may be utilized without departing from the scope of the embodiments of the present disclosure. In some embodiments, for thin oxide layers, there will be pinholes through which the etching gas can pass to remove the semiconductor structure 137.

[0087] In some embodiments, the porous dielectric film 168 may be referred to as a semi-permeable dielectric layer or a semi-permeable dielectric structure. In some embodiments, the porous dielectric film 168 may comprise silicon oxide. In these instances, the semiconductor structure 137 is silicon. In some embodiments, the porous dielectric film 168 may comprise silicon germanium oxide having a germanium concentration between 0% and 60%. In these instances, the structure 130 is silicon germanium. In some embodiments, the thickness of the porous dielectric film 168 in the X direction is between 1 nm and 5 nm. Without departing from the scope of the embodiments of the present disclosure, other materials, dimensions, and processes may be utilized in forming the porous dielectric film 168.

[0088] In Figure 20A and Figure 20B an interface dielectric layer 162 is also formed over the channel 105. The interface dielectric layer 162 may be created due to an oxidation process or due to other processes. The interface dielectric layer 162 may have the materials and characteristics previously described.

[0089] Figure 21A is a perspective view of an integrated circuit 100 according to some embodiments. Figure 21B is a cross-sectional view of an integrated circuit 100 according to some embodiments at the same processing stage as Figure 21A the same.

[0090] In Figure 21A and Figure 21B dielectric inner spacers 170 have been formed. The dielectric inner spacers 170 are formed by performing an etching process in the presence of the porous dielectric film 168. The etching process selectively etches the material of the remaining portion of the semiconductor structure 137. As previously described, the inner end portion of the semiconductor structure 137 has been transformed into the porous dielectric film 168. However, the remaining portion of the semiconductor structure 137 remains semiconductor material. In Figure 21A and Figure 21B the etching process selectively etches the material of the semiconductor structure 137 with respect to the semiconductor material of the channel 105 and the seed layer 143 to completely remove the remaining portion of the semiconductor structure 137.

[0091] In some embodiments, the porous dielectric film 168 enables an etchant material to pass through the porous dielectric film 168 to contact the semiconductor structure 137. The etchant material etches the semiconductor structure 137. The resulting material is removed through the pores of the porous dielectric film 168 through the porous dielectric film 168.

[0092] The result of the etching process is the formation of a gap to replace the semiconductor structure 137. The gap is formed between the porous dielectric film 168 and the semiconductor seed layer 143. In some embodiments, the gap is filled with a fluid that produces a low dielectric constant, such as air or another fluid or gas. Thus, the dielectric inner spacer 170 is a gap having a very low dielectric constant. In embodiments where the dielectric inner spacer 170 is filled with air, the dielectric constant of the dielectric inner spacer 170 is close to 1. In particular, the dielectric constant of air at room temperature is about 1.0006, which is much lower than that of typical solid dielectric materials. In some embodiments, the dielectric inner spacer 170 may be referred to as a gas dielectric inner spacer, a fluid dielectric inner spacer, a hollow inner spacer, or an air dielectric inner spacer.

[0093] In some embodiments, the dielectric inner spacer 170 may occupy a portion of the source / drain region 140. In some embodiments, the width of the dielectric inner spacer 170 in the X direction may be between 1 nm and 15 nm, and the width in the Y direction may be between 1 nm and 15 nm. The shape of the dielectric inner spacer 170 may be flat, or may protrude toward the source / drain region 140, where the depth of the protruding portion is between 1 nm and 10 nm. The shape of the dielectric inner spacer 170 on the inside may be flat, or may protrude toward the gate metal 166 (formed subsequently), where the depth of the protruding portion is between 1 nm and 10 nm. In some embodiments, due to the very low dielectric constant of the dielectric inner spacer 170, the gate-to-source / drain capacitance is very low. This results in a higher switching speed in the overall better performance of the transistor 101. In some embodiments, the reduced volume of the source / drain region 140 may result in a narrower OD spacing. For example, the OD spacing according to some embodiments of the present disclosure may be narrower by between 0 nm and 15 nm than other solutions that may have an OD range between 20 nm and 50 nm.

[0094] Figure 22A is a perspective view of an integrated circuit 100 according to some embodiments. Figure 22B is an integrated circuit 100 according to some embodiments at the Figure 22A same processing stage.

[0095] In Figure 22A and Figure 22BIn [the structure], an interfacial dielectric layer 162, a high-k dielectric layer 164, and a gate metal 166 have been formed. The interfacial dielectric layer 162, the high-k dielectric layer 164, and the gate metal 166 can be formed as previously described. The high-k dielectric layer 164 lines the inner surface of the channel 105, the porous dielectric film 168, and the gate spacer layer 134. As previously described, the pores of the porous dielectric film 168 do not allow the material or precursor of the high-k dielectric layer 164 to enter the dielectric inner spacer 170. Thus, as previously described, the porous dielectric film 168 is a semi-permeable dielectric structure.

[0096] The gate metal 166 wraps around the channel 105. The gate metal is separated from the source / drain regions 140 by the porous dielectric film 168 and the dielectric inner spacer 170. Due to the low dielectric constant of the porous dielectric film 168 and the dielectric inner spacer 170, there is a low gate-to-source / drain capacitance. In some embodiments, the porous dielectric film 168 can be considered as part of the dielectric inner spacer 170.

[0097] Figure 23 is a cross-sectional view of an integrated circuit 100 according to some embodiments. In Figure 23 [the structure], the semiconductor seed layer 143 does not include a seam 145. Instead, the sidewalls of the semiconductor seed layer 143 are vertically straight without ridges or seams. Thus, the source / drain regions 140 do not include protrusions into the seam. Instead, except for the steps at the top channel 105 of each stack, the source / drain regions 140 have substantially vertical sidewalls.

[0098] Figure 24 is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 24 [The figure] shows a processing stage in which the semiconductor seed layer 143 has been formed. In some embodiments, the semiconductor seed layer preferentially grows on the channel 105. As a result, the semiconductor seed layer 143 grows thicker at the ends of the channel 105 than at the ends of the semiconductor structure 137. Thus, the semiconductor seed layer 143 has a stepped structure with thinner and thicker portions, as shown in Figure 24 [the figure]. In some embodiments, the semiconductor seed layer 143 has a thickness between 2 nm and 6 nm at the ends of the channel 105. In some embodiments, the semiconductor seed layer 143 has a thickness between 0.5 nm and 3 nm at the ends of the semiconductor structure 137 and at the outer ends of the dielectric inner spacer 136 / 170 that will be formed to replace the semiconductor structure 137.

[0099] In some embodiments, the operations as described with respect to Figure 12A and Figure 12BThe recesses of the channel 105 shown and described. Thus, the surface of the channel 105 and the semiconductor structure 137 can be substantially coplanar with each other. If the semiconductor seed layer 143 preferentially grows faster on the channel 105 or the semiconductor structure 137, this can cause the semiconductor seed layer 143 to have substantially vertical sidewalls or to have a stepped structure.

[0100] Figure 25 is a flowchart of a method 2500 for forming an integrated circuit according to some embodiments. The method 2500 can utilize the structures, processes, and systems described with respect to Figures 1 to 24 In 2502, the method 2500 includes forming a plurality of stacked channels of a transistor. An example of a transistor is Figure 19B the transistor 101. An example of a stacked channel is Figure 19B the stacked channel 105. In 2504, the method 2500 includes forming a semiconductor seed layer on the ends of the stacked channels. An example of a seed layer is Figure 19B the seed layer 143. In 2506, the method 2500 includes forming source / drain regions of the transistor by performing epitaxial growth from the seed layer. An example of a source / drain region is Figure 19B the source / drain region 140. In 2508, the method 2500 includes, after forming the source / drain regions, forming a plurality of dielectric inner spacers that are interleaved with the channels and separated from the source / drain regions by the semiconductor seed layer. An example of a dielectric inner spacer is Figure 19B the dielectric inner spacer. In 2510, the method 2500 includes forming a gate metal of the transistor that wraps the channels and is separated from the source / drain regions by the dielectric inner spacers. An example of a gate metal is Figure 19B the gate metal 166.

[0101] Figure 26 is a flowchart of a method 2600 for forming an integrated circuit according to some embodiments. The method 2600 can utilize the structures, processes, and systems described with respect to Figures 1 to 24 In 2602, the method 2600 includes forming a plurality of stacked channels of a transistor. An example of a transistor is Figure 19B the transistor 101. An example of a stacked channel is Figure 19B the stacked channel 105. In 2604, the method 2600 includes forming source / drain regions of the transistor adjacent to the stacked channels. An example of a source / drain region is Figure 19B the source / drain region 140. In 2606, the method 2600 includes forming a plurality of dielectric inner spacers of the transistor by oxidizing a plurality of semiconductor structures that are interleaved with the channels. An example of a semiconductor structure is Figure 17Bsemiconductor structure 137. An example of a dielectric inner spacer is Figure 19B dielectric inner spacer 136 of Figure 19B . In 2608, method 2600 includes forming a gate dielectric over the channel. An example of a gate dielectric is Figure 19B gate dielectric 164 of Figure 19B . In 2610, method 2600 includes forming a gate metal that wraps around the channel and is separated from the source / drain regions by a dielectric inner spacer. An example of a gate metal is Figure 19B gate metal 166 of Figure 19B .

[0102] Embodiments of the present disclosure provide a gate-all-around transistor that includes a first source / drain region and a second source / drain region, a plurality of stacked channels each extending between the first source / drain region and the second source / drain region, a gate metal that wraps around the channels, and a low-k inner spacer located between adjacent channels and electrically isolating the gate metal from the source / drain regions. Embodiments of the present disclosure advantageously form the inner spacer after forming the source / drain regions. More particularly, embodiments of the present disclosure form a dielectric nanostructure between the channels, recess the dielectric nanostructure, form a semiconductor structure in the recess, and form a semiconductor seed layer on the ends of the channels and on the outer surface of the semiconductor structure. The source / drain regions grow epitaxially from the semiconductor seed layer, and the dielectric nanostructure is removed. After removing the dielectric nanostructure, a low-k dielectric inner spacer is formed to replace the sacrificial semiconductor nanostructure. The dielectric inner spacer may include an oxide or an air gap. Then the gate metal is formed. The result is a reduced capacitance between the gate metal and the source / drain regions, an increased switching speed of the transistor, a higher quality source / drain region, enhanced strain for improved device performance, and a reduced time in forming the source / drain regions.

[0103] In some embodiments, the method includes: forming a plurality of stacked channels of a transistor; forming a semiconductor seed layer on the ends of the stacked channels; and forming the source / drain regions of the transistor by performing epitaxial growth from the seed layer. The method includes: after forming the source / drain regions, forming a plurality of dielectric inner spacers that are interleaved with the channels and separated from the source / drain regions by the semiconductor seed layer; and forming a gate metal of the transistor that wraps around the channels and is separated from the source / drain regions by the dielectric inner spacers.

[0104] In some embodiments, an integrated circuit includes a transistor. The transistor includes: a plurality of stacked channels; a gate metal that wraps around the channels; and a gate dielectric located between the channels and the gate metal. The transistor includes: a plurality of dielectric inner spacers that are interleaved with the channels; source / drain regions; and a semiconductor seed layer located between the inner spacers and the source / drain regions.

[0105] In some embodiments, the method includes: forming a plurality of stacked channels of a transistor; forming source / drain regions of the transistor adjacent to the stacked channels; and forming a plurality of dielectric inner spacers of the transistor by oxidizing a plurality of semiconductor structures interleaved with the channels. The method includes: forming a gate dielectric over the channels; and forming a gate metal that wraps the channels and is separated from the source / drain regions by the dielectric inner spacers.

[0106] Some embodiments of the present application provide a method of forming a semiconductor device, including: forming a plurality of stacked channels; forming a semiconductor seed layer on ends of the stacked channels; forming the source / drain regions of the transistor by performing epitaxial growth from the seed layer; after forming the source / drain regions, forming a plurality of dielectric inner spacers interleaved with the channels and separated from the source / drain regions by the semiconductor seed layer; and forming a gate metal of the transistor that wraps the channels and is separated from the source / drain regions by the dielectric inner spacers.

[0107] In some embodiments, the dielectric inner spacers are fluid-filled gaps. In some embodiments, the method includes: forming semiconductor structures interleaved with the channels; and forming the semiconductor seed layer by epitaxial growth from ends of the stacked channels and from ends of the semiconductor structures. In some embodiments, the method includes forming the dielectric inner spacers in place of the semiconductor structures. In some embodiments, forming the dielectric inner spacers includes converting the semiconductor structures into dielectric inner spacers by oxidizing the semiconductor structures. In some embodiments, forming the dielectric inner spacers includes: generating a plasma in the presence of the semiconductor structures; and oxidizing the semiconductor structures. In some embodiments, forming the dielectric inner spacers includes: forming a plurality of porous dielectric films interleaved with the channels; and removing the semiconductor structures via the porous dielectric films, wherein the dielectric inner spacers are fluid-filled gaps; and forming the gate metal adjacent to the porous dielectric films. In some embodiments, the method includes: forming a gate dielectric layer in contact with the porous dielectric films; and forming the gate metal in contact with the gate dielectric layer and separated from the porous dielectric films by the gate dielectric layer. In some embodiments, the method includes: forming dielectric nanostructures interleaved with the channels; forming grooves by indenting end portions of the dielectric nanostructures; after indenting the end portions of the dielectric nanostructures, forming the semiconductor structures in the grooves; and removing the dielectric nanostructures after forming the semiconductor structures. In some embodiments, the dielectric inner spacers include silicon oxide or silicon germanium oxide.

[0108] Some other embodiments of the present application provide an integrated circuit, including: a transistor, including: a plurality of stacked channels; gate metal that wraps the channels; a gate dielectric located between the channels and the gate metal; a plurality of dielectric inner spacers that are interleaved with the channels; source / drain regions; and a semiconductor seed layer located between the inner spacers and the source / drain regions.

[0109] In some embodiments, the dielectric inner spacers include silicon oxide or silicon germanium oxide. In some embodiments, the outer ends of the channels are laterally offset relative to the inner spacers. In some embodiments, the semiconductor seed layer includes a plurality of seams filled with the source / drain regions. In some embodiments, the transistor includes a plurality of porous dielectric films that are interleaved with the channels and each located between the gate metal and a corresponding inner spacer. In some embodiments, the gate dielectric contacts the porous dielectric films. In some embodiments, the dielectric inner spacers are gaps filled with a fluid.

[0110] Some other embodiments of the present application provide a method for forming a semiconductor device, including: forming a plurality of stacked channels; forming source / drain regions adjacent to the stacked channels; forming a plurality of dielectric inner spacers of the transistor by oxidizing a plurality of semiconductor structures that are interleaved with the channels; forming a gate dielectric on the channels; and forming gate metal that wraps the channels and is separated from the source / drain regions by the dielectric inner spacers.

[0111] In some embodiments, forming the dielectric inner spacers includes: generating a porous dielectric film from each semiconductor structure by oxidizing an inner end of the semiconductor structure; and removing a remaining portion of each semiconductor structure via the porous dielectric film, wherein after forming the gate metal, each porous dielectric film is located between the gate metal and the source / drain regions. In some embodiments, forming the dielectric inner spacers includes converting each semiconductor structure into a corresponding dielectric inner spacer of the plurality of dielectric inner spacers by oxidizing the semiconductor structure.

[0112] The features of several embodiments are outlined above so that those skilled in the art can better understand various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the embodiments of the present disclosure, and various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method of forming a semiconductor device, comprising: Forming a plurality of stacked channels; Forming a semiconductor seed layer on an end portion of the stacked channels; Forming source / drain regions of the transistor by performing epitaxial growth from the seed layer; After forming the source / drain regions, forming a plurality of dielectric inner spacers that are interleaved with the channels and separated from the source / drain regions by the semiconductor seed layer; And Forming a gate metal of the transistor that wraps the channels and is separated from the source / drain regions by the dielectric inner spacers.

2. The method according to claim 1, wherein, The dielectric inner spacers are fluid-filled gaps.

3. The method according to claim 1, comprising: Forming a semiconductor structure that is interleaved with the channels; And Forming the semiconductor seed layer by epitaxial growth from an end portion of the stacked channels and from an end portion of the semiconductor structure.

4. The method according to claim 3, comprising forming the dielectric inner spacers in place of the semiconductor structure.

5. The method according to claim 4, wherein, Forming the dielectric inner spacers includes converting the semiconductor structure into dielectric inner spacers by oxidizing the semiconductor structure.

6. The method according to claim 5, wherein, Forming the dielectric inner spacers includes: Generating a plasma in the presence of the semiconductor structure; and Oxidizing the semiconductor structure.

7. The method according to claim 5, wherein, Forming the dielectric inner spacers includes: Forming a plurality of porous dielectric films that are interleaved with the channels; and Removing the semiconductor structure via the porous dielectric films, wherein the dielectric inner spacers are fluid-filled gaps; and Forming the gate metal adjacent to the porous dielectric films.

8. The method according to claim 7, comprising: Forming a gate dielectric layer that contacts the porous dielectric films; And Forming the gate metal that contacts the gate dielectric layer and is separated from the porous dielectric films by the gate dielectric layer.

9. An integrated circuit, comprising: A transistor, comprising: A plurality of stacked channels; A gate metal that wraps the channels; A gate dielectric located between the channels and the gate metal; A plurality of dielectric inner spacers that are interleaved with the channels; Source / drain regions; and A semiconductor seed layer located between the inner spacers and the source / drain regions.

10. A method of forming a semiconductor device, comprising: Forming a plurality of stacked channels; Forming source / drain regions adjacent to the stacked channels; Forming a plurality of dielectric inner spacers of the transistor by oxidizing a plurality of semiconductor structures that are interleaved with the channels; Forming a gate dielectric on the channels; And Forming a gate metal that wraps the channels and is separated from the source / drain regions by the dielectric inner spacers.

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