Battery structure, battery cell, and photovoltaic system

Abstract

The application discloses a battery structure, a battery monomer and a photovoltaic system, and belongs to the technical field of batteries. The battery structure comprises a silicon base body having a front surface and a back surface oppositely arranged along a first direction; a first intrinsic amorphous silicon layer, a crystalline silicon layer and a first microcrystalline silicon layer are sequentially stacked on the front surface of the silicon base body in a direction away from the silicon base body, the crystalline silicon layer and the first microcrystalline silicon layer have a first doping type, and the crystalline silicon layer contains hydrogen elements and oxygen elements; a second intrinsic amorphous silicon layer and a second microcrystalline silicon layer are sequentially stacked on the back surface of the silicon base body in a direction away from the silicon base body, and the second microcrystalline silicon layer has a second doping type; wherein the thickness of the crystalline silicon layer is smaller than the thickness of the first microcrystalline silicon layer, and the first doping type is opposite to the second doping type. By depositing the crystalline silicon layer between the amorphous silicon layer and the microcrystalline silicon layer, the microcrystalline silicon layer has higher crystallization rate and light transmittance, the process time is shortened, and the etching effect on the amorphous silicon layer is avoided.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of batteries, and particularly relates to a battery structure, a battery monomer and a photovoltaic system. BACKGROUND

[0002] A silicon heterojunction solar cell (Heterojunction with Back Contact, referred to as HJT) is a kind of high-efficiency photovoltaic device, which realizes excellent surface passivation effect by forming a high-quality heterojunction, thereby obtaining significant advantages such as high conversion efficiency. However, the process time of the film layer structure of the HJT is long, the preparation difficulty is high, and the final efficiency of the battery needs to be improved. SUMMARY

[0003] The present application aims to at least solve one of the technical problems existing in the prior art. To this end, the present application provides a battery structure, a battery monomer and a photovoltaic system, which deposits a crystalline silicon layer between the amorphous silicon layer and the microcrystalline silicon layer, so that the microcrystalline silicon layer has a higher crystallization rate and light transmittance, and at the same time, the process time is shortened, and the amorphous silicon layer is not etched.

[0004] In a first aspect, the present application provides a battery structure, comprising:

[0005] A silicon substrate having a front surface and a back surface oppositely arranged along a first direction;

[0006] A first intrinsic amorphous silicon layer, a crystalline silicon layer and a first microcrystalline silicon layer are sequentially stacked on the front surface of the silicon substrate in a direction away from the silicon substrate, the crystalline silicon layer and the first microcrystalline silicon layer have a first doping type, and the crystalline silicon layer contains hydrogen and oxygen elements;

[0007] A second intrinsic amorphous silicon layer and a second microcrystalline silicon layer are sequentially stacked on the back surface of the silicon substrate in a direction away from the silicon substrate, and the second microcrystalline silicon layer has a second doping type;

[0008] The thickness of the crystalline silicon layer is less than the thickness of the first microcrystalline silicon layer, and the first doping type and the second doping type are opposite.

[0009] According to the battery structure of the present application, amorphous silicon and microcrystalline silicon are deposited on both sides of the silicon substrate to form a high-quality heterojunction, and a crystalline silicon layer is further deposited on the front surface, which can promote the high-quality growth of the microcrystalline silicon layer, improve the crystallization rate and light transmittance of the microcrystalline silicon, optimize the energy band structure of the heterojunction interface, reduce the loss of recombination, enhance the collection efficiency of carriers, and significantly improve the current. At the same time, the deposition time of the crystalline silicon layer is short, the process time is shortened, and the amorphous silicon layer is not etched.

[0010] According to some embodiments of the present application, the thickness of the crystalline silicon layer is 0.5nm-1nm.

[0011] According to some embodiments of the present application, the total thickness of the crystalline silicon layer and the first microcrystalline silicon layer is 18-20 nm.

[0012] According to some embodiments of the present application, the thickness ratio of the crystalline silicon layer and the first microcrystalline silicon layer is 1: (17-40).

[0013] According to some embodiments of the present application, the oxygen doping concentration of the crystalline silicon layer is 1*10 21 cm -3 -1*10 23 cm -3 , and the oxygen doping concentration of the first microcrystalline silicon layer is 1*10 17 cm -3 -1*10 18 cm -3 .

[0014] According to some embodiments of the present application, the crystalline silicon layer is a phosphorus-doped crystalline silicon layer, the first microcrystalline silicon layer is a phosphorus-doped microcrystalline silicon layer, and the second microcrystalline silicon layer is a boron-doped microcrystalline silicon layer.

[0015] According to some embodiments of the present application, the thickness of the first intrinsic amorphous silicon layer is 5-7 nm, the thickness of the phosphorus-doped crystalline silicon layer is 0.5-1 nm, the thickness of the phosphorus-doped microcrystalline silicon layer is 18-22 nm, the thickness of the second intrinsic amorphous silicon layer is 5-8 nm, and the thickness of the boron-doped microcrystalline silicon layer is 25-30 nm.

[0016] According to some embodiments of the present application, the phosphorus doping concentration of the phosphorus-doped crystalline silicon layer is 1*10 17 cm -3 -1*10 18 cm -3 , and the phosphorus doping concentration of the phosphorus-doped microcrystalline silicon layer is 1*10 18 cm -3 -1*10 20 cm -3 .

[0017] According to some embodiments of the present application, the surface of the silicon substrate in the second direction is formed with the second intrinsic amorphous silicon layer, the first intrinsic amorphous silicon layer, the crystalline silicon layer, the first microcrystalline silicon layer, and the second microcrystalline silicon layer stacked in sequence, the second intrinsic amorphous silicon layer is arranged close to the silicon substrate, and the first direction is perpendicular to the second direction.

[0018] In a second aspect, the present application provides a battery cell, comprising a first conductive structure, a second conductive structure, and a battery structure according to the foregoing, the first conductive structure is arranged on the surface of the first microcrystalline silicon layer of the battery structure away from the silicon substrate, and the second conductive structure is arranged on the surface of the second microcrystalline silicon layer of the battery structure away from the silicon substrate.

[0019] The battery cell according to the application has good electrochemical performance, high short-circuit current and conversion efficiency.

[0020] In a third aspect, the application provides a photovoltaic system comprising the battery cell according to the foregoing.

[0021] The photovoltaic system according to the application has higher system efficiency and total output power.

[0022] Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or can be learned by practice of the application. BRIEF DESCRIPTION OF DRAWINGS

[0023] The above and / or additional aspects and advantages of the application will become apparent and be readily understood by considering the following detailed description, including the accompanying drawings, in which:

[0024] Figure 1 is a structural schematic diagram of a battery structure provided by the embodiments of the application;

[0025] Figure 2 is a structural schematic diagram of a battery cell provided by the embodiments of the application.

[0026] REFERENCE NUMERALS

[0027] Battery structure 100, battery cell 200, silicon substrate 10, first intrinsic amorphous silicon layer 21, crystalline silicon layer 30, first microcrystalline silicon layer 41, second intrinsic amorphous silicon layer 22, second microcrystalline silicon layer 42, first transparent conductive film layer 51, second transparent conductive film layer 52, first electrode 61, second electrode 62. DETAILED DESCRIPTION

[0028] Embodiments of the application are described in detail below, examples of which are shown in the accompanying drawings. In the drawings, the size and relative sizes of layers, regions, elements and the like can be exaggerated for clarity. Identical or similar component elements throughout the drawings are denoted by the same or similar reference numerals. The embodiments described below by reference to the drawings are exemplary only, are for the purpose of explanation only, and are not to be construed as limiting the application.

[0029] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0030] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Also, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0031] In the related art, the structure of a silicon heterojunction (HJT) solar cell is based on crystalline silicon (c-Si) as a substrate, and intrinsic amorphous silicon and microcrystalline silicon layers are deposited on both sides to form a heterojunction. For example, the back surface of the cell structure adopts P-type boron-doped microcrystalline silicon to form an emitter. The front surface of the cell structure adopts an N-type phosphorus-doped microcrystalline silicon layer. However, the contact interface between the intrinsic amorphous silicon layer and the microcrystalline silicon layer on the front surface of the heterojunction cell based on the conventional structure has a serious parasitic absorption effect. In view of this, the present application proposes a cell structure, which forms a high-quality heterojunction by depositing amorphous silicon and microcrystalline silicon on both sides of a silicon substrate, wherein an oxygen-containing crystalline silicon layer is further deposited between the intrinsic amorphous silicon layer and the microcrystalline silicon layer on the front surface, which serves as a seed layer before the formation of a dense microcrystalline silicon layer. The oxygen-containing crystalline silicon layer can promote the high-quality growth of the microcrystalline silicon layer, improve the crystallization rate and light transmittance of the microcrystalline silicon, optimize the energy band structure of the heterojunction interface, reduce the recombination loss, enhance the collection efficiency of the carriers, and significantly improve the current. At the same time, the deposition time of the crystalline silicon layer is short, which shortens the process time and does not cause etching effect on the amorphous silicon layer. At the same time, the introduction of the oxygen-containing crystalline silicon layer can reduce the overall thickness of the doped microcrystalline silicon layer on the front surface.

[0032] Referring to Figure 1 , Figure 1 A battery structure is shown, and one embodiment of the present application proposes a battery structure. In the present embodiment, the battery structure 100 comprises a silicon substrate 10, a first intrinsic amorphous silicon layer 21, a second intrinsic amorphous silicon layer 22, a crystalline silicon layer 30, a first microcrystalline silicon layer 41 and a second microcrystalline silicon layer 42. The silicon substrate 10 has a front surface and a back surface oppositely arranged along a first direction; the first intrinsic amorphous silicon layer 21, the crystalline silicon layer 30 and the first microcrystalline silicon layer 41 are sequentially laminated on the front surface of the silicon substrate, the second intrinsic amorphous silicon layer 22 and the second microcrystalline silicon layer 42 are sequentially laminated on the back surface of the silicon substrate, the crystalline silicon layer 30 and the first microcrystalline silicon layer 41 have a first doping type, the second microcrystalline silicon layer 42 has a second doping type, the crystalline silicon layer contains hydrogen and oxygen elements; wherein the thickness of the crystalline silicon layer 30 is less than the thickness of the first microcrystalline silicon layer 41, and the first doping type and the second doping type are opposite.

[0033] The silicon substrate can be an N-type single crystal silicon wafer, and the thickness can be 50 μm-200 μm (specifically, such as 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm, 180 μm, 190 μm, 200 μm, etc.).

[0034] The first direction is the thickness direction of the silicon substrate 10, and the two large-area surfaces of the silicon substrate 10 are oppositely arranged as the front surface and the back surface. For example, the upper surface of the silicon substrate 10 is taken as the front surface, and the lower surface is taken as the back surface, the first intrinsic amorphous silicon layer 21 is formed on the upper surface of the silicon substrate 10, the crystalline silicon layer 30 is formed on the surface of the first intrinsic amorphous silicon layer 21 away from the silicon substrate 10, the first microcrystalline silicon layer 41 is formed on the surface of the crystalline silicon layer 30 away from the silicon substrate 10, the second intrinsic amorphous silicon layer 22 is formed on the lower surface of the silicon substrate 10, and the second microcrystalline silicon layer 42 is formed on the surface of the second intrinsic amorphous silicon layer 22 away from the silicon substrate 10.

[0035] It should be noted that the first microcrystalline silicon layer 41 and the second microcrystalline silicon layer 42 in the present embodiment are fully microcrystallized film layers, or partially microcrystallized and contain amorphous silicon film layers. In terms of process, the raw materials for preparing microcrystalline silicon and amorphous silicon are roughly the same, so in actual preparation, the film layer prepared by microcrystalline silicon may contain part of amorphous silicon.

[0036] The first doping type can be N-type, and the second doping type can be P-type. Alternatively, the first doping type can be P-type, and the second doping type can be N-type. Wherein, N-type doping can be phosphorus doping, arsenic doping or antimony doping, etc., and P-type doping can be boron doping, gallium doping or indium doping, etc.

[0037] As an example, the crystalline silicon layer 30 and the first microcrystalline silicon layer 41 can be phosphorus-doped microcrystalline silicon layers, and the second microcrystalline silicon layer 42 can be boron-doped.

[0038] The crystalline silicon layer 30 is a transition film layer between amorphous silicon and microcrystalline silicon, which is mainly used to promote uniform nucleation and high-quality growth of the subsequent first microcrystalline silicon layer 41. The hydrogen-oxygen-containing crystalline silicon layer 30 is used as a seed layer in the embodiment, and the oxygen element can quickly promote crystallization, so that the first microcrystalline silicon layer 41 has a higher nucleation effect, a higher crystallization rate, and higher light transmittance. At the same time, the thickness of the crystalline silicon layer 30 can be thinned, and the deposition time can be shortened.

[0039] In some embodiments, the thickness of the crystalline silicon layer 30 is 0.5 nm to 1 nm. For example, the thickness of the crystalline silicon layer can be 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, or 1 nm. Since the crystalline silicon layer can promote crystallization more quickly, the required deposition time can be further shortened.

[0040] In some embodiments, the total thickness of the crystalline silicon layer 30 and the first microcrystalline silicon layer 41 is 18 nm to 20 nm. For example, the total thickness can be 18 nm, 18.5 nm, 19 nm, 19.5 nm, or 20 nm.

[0041] The crystallization rate of the microcrystalline silicon gradually increases as the film thickness increases, but increasing the film thickness inevitably increases the parasitic absorption of the microcrystalline silicon and increases the electron tunneling contact problem. The hydrogen-oxygen-containing crystalline silicon layer 30 is used as a seed layer in the embodiment, so that the first microcrystalline silicon layer 41 has a higher crystallization rate and light transmittance. Therefore, the thickness of the first microcrystalline silicon layer 41 can be thinned, and on the premise of guaranteeing the original advantages, a lower front parasitic absorption and a low electron tunneling contact resistivity can be achieved through a low total film thickness.

[0042] In some embodiments, the thickness of the first microcrystalline silicon layer 41 is 17 nm to 19.5 nm. For example, the thickness of the first microcrystalline silicon layer 41 can be 17 nm, 17.5 nm, 18 nm, 18.5 nm, 19 nm, or 19.5 nm.

[0043] In other embodiments, the thickness ratio of the crystalline silicon layer 30 to the first microcrystalline silicon layer 41 is 1:(17-40). For example, 1:17, 1:20, 1:25, 1:30, 1:35, or 1:40. The crystalline silicon layer 30 is beneficial to promote the growth quality of the first microcrystalline silicon layer 41, and can promote the growth of the microcrystalline silicon layer to be more dense. Controlling the thickness ratio between the two can balance or tend to select between the crystallization rate and light transmittance of the first microcrystalline silicon layer 41 and the parasitic absorption and contact resistance of the total film thickness, and can guarantee the conversion efficiency of the battery structure 100.

[0044] In some embodiments, the oxygen doping concentration of the crystalline silicon layer 30 is 1*10 21 cm -3 -1*10 23 cm -3 The oxygen doping concentration of the first microcrystalline silicon layer is 1*10 17 cm -3 -1*10 18 cm -3 For example, the oxygen doping concentration of the crystalline silicon layer 30 can be 1*10 21 cm -3 , 1*10 22 cm -3 , or 1*10 23 cm -3 The crystalline silicon layer with high oxygen content can widen the band gap, enhance the absorption of short-wavelength light, and significantly improve the current.

[0045] As an example, the crystalline silicon layer 30 is a phosphorus-doped crystalline silicon layer, the first microcrystalline silicon layer 41 is a phosphorus-doped microcrystalline silicon layer, and the second microcrystalline silicon layer 42 is a boron-doped microcrystalline silicon layer. The front surface of the silicon substrate 10 adopts a stacked structure of an intrinsic layer, an N-type microcrystalline silicon layer, and an intrinsic layer, and the back surface forms a stacked structure of an intrinsic layer and a P-type microcrystalline silicon layer, thereby forming a high-quality heterojunction, especially a high front surface crystallization rate and better light transmittance with low parasitic absorption at a super-thin thickness.

[0046] In some embodiments, the thickness of the first intrinsic amorphous silicon layer 21 is 5nm-7nm, the thickness of the phosphorus-doped crystalline silicon layer is 0.5nm-1nm, the thickness of the phosphorus-doped microcrystalline silicon layer is 18nm-22nm, the thickness of the second intrinsic amorphous silicon layer 22 is 5nm-8nm, and the thickness of the boron-doped microcrystalline silicon layer is 25nm-30nm.

[0047] The thickness of the first intrinsic amorphous silicon layer 21 can be 5nm, 5.5nm, 6nm, 6.5nm, or 7nm, which has a higher transmittance and better passivation effect, is conducive to reducing light absorption loss, and improves the conversion efficiency of the solar cell.

[0048] The thickness of the second intrinsic amorphous silicon layer 22 can be 5nm, 5.5nm, 6nm, 6.5nm, 7nm, 7.5nm, or 8nm, which has a better passivation effect, can reduce the recombination rate of the solar cell back surface, and improves the conversion efficiency of the solar cell.

[0049] The thickness of the boron-doped microcrystalline silicon layer can be 25nm, 26nm, 27nm, 28nm, 29nm, or 30nm, which can ensure the carrier transport path and provide more carrier transport channels, thereby improving the conversion efficiency of the cell. The boron doping concentration of the boron-doped microcrystalline silicon layer can be 1*10 19 cm -3-1*10 20 cm -3 In the boron-doped microcrystalline silicon layer, moderate boron doping can establish a hole conduction network, thereby improving the short-circuit current and conversion efficiency of the cell.

[0050] The thickness of the phosphorus-doped crystalline silicon layer and the thickness of the phosphorus-doped microcrystalline silicon layer can refer to the foregoing description of the crystalline silicon layer 30 and the first microcrystalline silicon layer 41, which also has the same technical effects, and the present embodiment will not be described here.

[0051] The phosphorus doping concentration of the phosphorus-doped crystalline silicon layer is 1*10 17 cm -3 -1*10 18 cm -3 , such as 1*10 17 cm -3 or 1*10 18 cm -3 The doping of phosphorus elements can improve the band structure of the seed layer, reduce the band gap, be beneficial to the photoelectron transition, improve the absorption and utilization efficiency of the cell to photons, increase the number of photo-generated carriers, and thereby improve the short-circuit current and conversion efficiency of the solar cell.

[0052] The phosphorus doping concentration of the phosphorus-doped microcrystalline silicon layer is 1*10 18 cm -3 -1*10 20 cm -3 . Such as 1*10 18 cm -3 , 1*10 19 cm -3 or 1*10 20 cm -3 , improve the absorption and utilization efficiency of the cell to photons, increase the number of photo-generated carriers, and thereby improve the short-circuit current and conversion efficiency of the solar cell.

[0053] In the related art, the phosphorus doping concentration of the hydrogen-containing seed layer and the phosphorus-doped microcrystalline silicon layer is basically the same, and the phosphorus doping concentration of the crystalline silicon layer 30 in the present embodiment is lower, which improves passivation and potentially improves the open-circuit voltage.

[0054] One embodiment of the present application also proposes a preparation process of each film layer of the cell structure 100, as follows:

[0055] Silicon substrate 10: The silicon substrate 10 can be a double-side polished and clean silicon substrate 10 obtained after completing double-side cleaning and polishing, removing surface organic matter, metal impurities and surface damage layer, etc.

[0056] The process for cleaning the silicon substrate is not limited in the present application, and can be any cleaning process, such as standard clean 1 or standard clean 2. The standard clean 1 can include a mixture of ammonium hydroxide, hydrogen peroxide and water, and the standard clean 2 can include a mixture of hydrochloric acid, hydrogen peroxide and water.

[0057] In some embodiments, the double-side polished and cleaned silicon substrate can be textured. Specifically, texturing refers to forming a micro-textured structure on the surface of the silicon substrate by chemical etching or physical methods. Such structure can increase the residence time of light on the silicon surface, reduce the reflection of light, and thus improve the light absorption efficiency.

[0058] In some embodiments, the texturing can be performed by chemical etching using an alkaline solution, such as sodium hydroxide or potassium hydroxide. By utilizing the anisotropic etching characteristics of silicon in the alkaline solution, a pyramid-shaped textured structure is formed.

[0059] In some embodiments, the first intrinsic amorphous silicon layer 21, the crystalline silicon layer 30, the first microcrystalline silicon layer 41, the second intrinsic amorphous silicon layer 22 and the second microcrystalline silicon layer 42 can be prepared by plasma enhanced chemical vapor deposition, hot-wire chemical vapor deposition or low pressure chemical vapor deposition. The thickness of each film layer can be controlled as described above, and other related process parameters are as follows:

[0060] The first intrinsic amorphous silicon layer 21: under the conditions of 180-210℃, 0.4-0.7 Torr and a deposition power of 200-500 W, hydrogen is passed at a flow rate of 500-2000 sccm and silane is passed at a flow rate of 500-1000 sccm; the flow rate ratio of hydrogen to silane is controlled to be (1-3):1.

[0061] The crystalline silicon layer 30: under the conditions of 170-190℃, 4-5 Torr and a deposition power of 2000-4000 W, hydrogen is passed at a flow rate of 5000-8000 sccm, silane is passed at a flow rate of 50-100 sccm, phosphorus source is passed at a flow rate of 50-200 sccm, and oxygen source is passed at a flow rate of 300-800 sccm; the flow rate ratio of oxygen source to silane is controlled to be (5-10):1.

[0062] First microcrystalline silicon layer 41: Under the conditions of 170℃-190℃, 0.4 Torr-1 Torr and coating power of 3000W-5000W, hydrogen is introduced at a flow rate of 10000sccm-20000sccm, silane at a flow rate of 500sccm-1000sccm, phosphorus source at a flow rate of 100sccm-300sccm, and oxygen source at a flow rate of 10sccm-100sccm; the flow ratio of hydrogen to silane is controlled to be (200-300):1.

[0063] Second intrinsic amorphous silicon layer 22: Under the conditions of 180℃-220℃, 0.4Torr-0.7Torr and coating power of 100W-400W, hydrogen is introduced at a flow rate of 1000sccm-3000sccm and silane is introduced at a flow rate of 500sccm-1000sccm; the flow rate ratio of hydrogen to silane is controlled as (1-3):1.

[0064] Second microcrystalline silicon layer 42: Under the conditions of 140℃-170℃, 3Torr-5Torr and coating power of 5000W-7000W, hydrogen is introduced at a flow rate of 18000sccm-25000sccm, silane at a flow rate of 50sccm-80sccm, boron source at a flow rate of 20sccm-100sccm and oxygen source at a flow rate of 10sccm-30sccm; the flow ratio of hydrogen to silane is controlled as (250-350):1.

[0065] In some embodiments, the silane used in the above preparation processes may include one or more of SiH4, Si2H6, and Si3H8. The oxygen source may include one or more of CO2, O2, and N2O. The phosphorus source may include one or more of PH3 and P2H4. The boron source may include BH3, B3H6, and B4H4. 10 One or more of them.

[0066] The following describes in detail an embodiment of the battery structure 100 in this application, in conjunction with the manufacturing process.

[0067] Example 1

[0068] (1) Cleaning and velveting

[0069] N-type monocrystalline silicon wafers with a thickness of 150μm are selected. The front and back sides of the silicon wafers are cleaned using a tank cleaning and texturing machine. Then, the silicon wafers are texturized with sodium hydroxide solution to form a textured surface on the front and back sides of the silicon wafers to provide silicon substrate 10.

[0070] (2) Preparation of the second intrinsic amorphous silicon layer 22

[0071] The second intrinsic amorphous silicon layer 22 is prepared by a plasma enhanced chemical (PECVD) vapor chemical deposition method. The second intrinsic amorphous silicon layer 22 is prepared on the silicon substrate 10 obtained in step (1). The specific parameters are as follows: hydrogen and silane are introduced, the thickness is controlled to be 5-7 nm, the hydrogen flow rate is 1500 sccm, the silane flow rate is 750 sccm, the temperature is 200°C, the pressure is 0.5 Torr, and the plating power is 200 W.

[0072] (3) Preparation of the first intrinsic amorphous silicon layer 21

[0073] The second intrinsic amorphous silicon layer 22 remaining on the front side of the silicon substrate 10 is cleaned based on step (2), and the first intrinsic amorphous silicon layer 21 is prepared on the front side of the silicon substrate 10 by a plasma enhanced chemical (PECVD) vapor chemical deposition method. The specific parameters are as follows: hydrogen and silane are introduced, the thickness is controlled to be 5-8 nm, the hydrogen flow rate is 1500 sccm, the silane flow rate is 750 sccm, the temperature is 200°C, the pressure is 0.5 Torr, and the plating power is 200 W.

[0074] (4) Preparation of the crystalline silicon layer 30

[0075] The crystalline silicon layer 30 is continuously prepared on the front side of the silicon substrate 10 obtained in step (4) by a plasma enhanced chemical (PECVD) vapor chemical deposition method, and the crystalline silicon layer 30 is formed on the surface of the first intrinsic amorphous silicon layer 21. The specific parameters are as follows: hydrogen, silane, CO2, and phosphine are introduced, the thickness is controlled to be 0.5-1 nm, the hydrogen flow rate is 6000 sccm, the silane flow rate is 75 sccm, the CO2 flow rate is 500 sccm, the phosphine flow rate is 100 sccm, the temperature is 180°C, the pressure is 4.5 Torr, and the plating power is 3000 W.

[0076] (5) Preparation of the first microcrystalline silicon layer 41

[0077] The first microcrystalline silicon layer 41 is continuously prepared on the front side of the silicon substrate 10 obtained in step (5) by a plasma enhanced chemical (PECVD) vapor chemical deposition method, and the first microcrystalline silicon layer 41 is formed on the surface of the crystalline silicon layer 30. The specific parameters are as follows: hydrogen, silane, CO2, and phosphine are introduced, the thickness is controlled to be 20-22 nm, the plating time is 60 s, the hydrogen flow rate is 15000 sccm, the silane flow rate is 700 sccm, the phosphine flow rate is 200 sccm, the CO2 flow rate is 50 sccm, the temperature is 180°C, the pressure is 0.5 Torr, and the plating power is 4000 W.

[0078] (6) Preparation of the second microcrystalline silicon layer 42

[0079] The front surface film layer remaining on the back surface of the silicon substrate 10 in step (5) is cleaned, and a second microcrystalline silicon layer 42 is continuously prepared on the back surface of the silicon substrate 10 by a plasma enhanced chemical (PECVD) vapor chemical deposition method. The second microcrystalline silicon layer 42 is formed on the surface of the second intrinsic amorphous silicon layer 22. The specific parameters are as follows: hydrogen and silane, CO2 are introduced, and the thickness is controlled to be 25 nm to 30 nm under the conditions of 150°C, 4 Torr, and a film plating power of 6000 W, with a hydrogen flow range of 20000 sccm, a silane flow range of 70 sccm, a CO2 flow range of 20 sccm, and borane of 50 sccm.

[0080] In Example 1, the surface of the silicon substrate 10 in the second direction forms a stacked structure, the first direction is perpendicular to the second direction, and the second direction is the lateral direction of the silicon substrate 10. The stacked structure is formed on the side surface of the silicon substrate 10 and includes the second intrinsic amorphous silicon layer 22, the first intrinsic amorphous silicon layer 21, the crystalline silicon layer 30, the first microcrystalline silicon layer 41, and the second microcrystalline silicon layer 42 which are sequentially stacked; wherein the second intrinsic amorphous silicon layer 22 is arranged close to the silicon substrate 10 and in contact with the side surface of the silicon substrate 10.

[0081] It should be noted that the stacked structure of the side surface will cause the front surface and the back surface of the battery structure 100 to be short-circuited, so subsequent cutting removal or trench isolation is required to expose the side surface of the silicon substrate 10 again and restore the electrical performance of the battery structure 100.

[0082] Example 2

[0083] The difference between the battery structure 100 preparation process in this example and Example 1 is only that the preparation parameters of the N-type doped layer in step (5) are adjusted in this example: the film plating time is shortened to 40 s, and the thickness of the first microcrystalline silicon layer 41 is adjusted to 18 nm.

[0084] The remaining steps are performed according to the method in Example 1.

[0085] Comparative Example 1

[0086] The difference between the battery structure 100 preparation process in this example and Example 1 is only that the preparation process in step (4) is adjusted to prepare a high hydrogen seed layer in this comparative example. The specific parameters are as follows: hydrogen and silane, phosphine are introduced, and the thickness is controlled to be 4 nm under the conditions of 180°C, 4.5 Torr, and a film plating power of 3000 W, with a hydrogen flow range of 25000 sccm, a silane flow range of 75 sccm, and phosphine of 100 sccm.

[0087] The remaining steps are performed according to the method in Example 1.

[0088] The performance comparison of the above-mentioned Example 1, Example 2, and Comparative Example 2 is shown in Table 1.

[0089] Table 1

[0090]

[0091] As can be seen from Table 1, according to the comparison between Example 1 and Comparative Example 1, it can be concluded that the introduction of the ultra-thin oxygen-containing silicon-based layer on the front side of the solar cell improves the crystallization rate of the solar cell and the light transmittance is better, the high oxygen content of the crystalline silicon layer 30 widens the band gap and enhances the absorption of short-wavelength light, and the short-circuit current and conversion efficiency are significantly improved.

[0092] According to the comparison between Example 1 and Example 2, it can be concluded that Example 2 reduces the thickness of the N-type doped layer by 2 nm on the basis of Example 1, thereby reducing the front-side electron tunneling contact resistivity, and the fill factor (FF) is improved; at the same time, due to the reduction in the thickness of the N-type doped layer, the parasitic absorption is reduced, and the short-circuit current and conversion efficiency are improved.

[0093] Referring to Figure 2 , Figure 2 A structure of a battery monomer is shown, and one embodiment of the present application further provides a battery monomer. In the present embodiment, the battery monomer 200 includes a first conductive structure, a second conductive structure, and the battery structure 100 according to the foregoing, the first conductive structure is arranged on the surface of the first microcrystalline silicon layer 41 of the battery structure 100 away from the silicon substrate 10, and the second conductive structure is arranged on the surface of the second microcrystalline silicon layer 42 of the battery structure 100 away from the silicon substrate 10.

[0094] The first conductive structure includes a first transparent conductive film layer 51 and a first electrode 61. The first transparent conductive film layer 51 is arranged on the surface of the first microcrystalline silicon layer 41 away from the crystalline silicon layer 30, and the first electrode 61 is arranged on the surface of the first transparent conductive film layer 51 away from the first microcrystalline silicon layer 41.

[0095] The first conductive structure includes a second transparent conductive film layer 52 and a second electrode 62. The second transparent conductive film layer 52 is arranged on the surface of the second microcrystalline silicon layer 42 away from the second intrinsic amorphous silicon layer 22, and the second electrode 62 is arranged on the surface of the second transparent conductive film layer 52 away from the second microcrystalline silicon layer 42.

[0096] The first transparent conductive film layer 51 and the second transparent conductive film layer 52 can include one or more of indium tin oxide (ITO), lanthanide metal-doped indium oxide, fluorine-doped tin oxide (FTO), antimony-doped tin oxide, boron-doped zinc oxide (BZO), aluminum zinc oxide (AZO), indium zinc oxide (IZO), gallium zinc oxide (GZO), and indium tungsten oxide (IWO). The above oxides have good light transmittance, good electrical conductivity, and chemical stability, and can collect the current generated by the photoelectric effect in the solar cell.

[0097] The thickness of the first transparent conductive film layer 51 and the second transparent conductive film layer 52 can be 50-150 nm, such as 50 nm, 75 nm, 100 nm, 125 nm or 150 nm. The thickness of the first transparent conductive film layer 51 and the second transparent conductive film layer 52 can be the same or different.

[0098] The first transparent conductive film layer 51 and the second transparent conductive film layer 52 can be prepared by atmospheric pressure chemical vapor deposition (APCVD), radio frequency magnetron sputtering (PVD) or reactive plasma deposition (RPD).

[0099] The first electrode 61 and the second electrode 62 can include one or more of Al, Ti, Ni, Co, Ag, Cu and Sn.

[0100] The first electrode 61 and the second electrode 62 can be prepared by low-temperature copper paste or silver-coated copper paste. Alternatively, the first electrode 61 and the second electrode 62 can be prepared by electroplating one or more of Al, Ti, Ni, Co, Ag, Cu and Sn.

[0101] The battery cell according to the present application has good electrochemical performance, and has a high short-circuit current and conversion efficiency.

[0102] One embodiment of the present application provides a photovoltaic system, which includes the battery cell 200 according to the foregoing.

[0103] The photovoltaic system according to the present application has higher system efficiency and total output power.

[0104] Although embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that various changes, modifications, substitutions and alterations can be made thereto without departing from the principles and spirit of the present application, the scope of which is defined by the following claims and their equivalents.

Claims

1. A battery structure, characterized in that, include: A silicon substrate having a front side and a back side disposed opposite to each other along a first direction; In a direction away from the silicon substrate, a first intrinsic amorphous silicon layer, a crystalline silicon layer, and a first microcrystalline silicon layer are sequentially stacked on the front side of the silicon substrate. The crystalline silicon layer and the first microcrystalline silicon layer have a first doping type. The crystalline silicon layer contains hydrogen and oxygen elements, and the oxygen doping concentration in the crystalline silicon layer is greater than the hydrogen doping concentration. The oxygen doping concentration of the crystalline silicon layer is 1*10⁻⁶. 21 cm -3 -1*10 23 cm -3 The thickness of the crystalline silicon layer is 0.5 nm to 1 nm, and the oxygen doping concentration of the first microcrystalline silicon layer is 1*10⁻⁶. 17 cm -3 -1*10 18 cm -3 ; In a direction away from the silicon substrate, a second intrinsic amorphous silicon layer and a second microcrystalline silicon layer are sequentially stacked on the back side of the silicon substrate, the second microcrystalline silicon layer having a second doping type; The thickness of the crystalline silicon layer is less than the thickness of the first microcrystalline silicon layer, and the first doping type and the second doping type are opposite.

2. The battery structure according to claim 1, characterized in that, The total thickness of the crystalline silicon layer and the first microcrystalline silicon layer is 18nm~20nm.

3. The battery structure according to claim 1, characterized in that, The thickness ratio of the crystalline silicon layer to the first microcrystalline silicon layer is 1:(17-40).

4. The battery structure according to any one of claims 1-3, characterized in that, The crystalline silicon layer is a phosphorus-doped crystalline silicon layer, the first microcrystalline silicon layer is a phosphorus-doped microcrystalline silicon layer, and the second microcrystalline silicon layer is a boron-doped microcrystalline silicon layer.

5. The battery structure according to claim 4, characterized in that, The thickness of the first intrinsic amorphous silicon layer is 5nm~7nm, the thickness of the phosphorus-doped crystalline silicon layer is 0.5nm~1nm, the thickness of the phosphorus-doped microcrystalline silicon layer is 18nm~22nm, the thickness of the second intrinsic amorphous silicon layer is 5nm~8nm, and the thickness of the boron-doped microcrystalline silicon layer is 25nm~30nm.

6. The battery structure according to claim 5, characterized in that, The phosphorus doping concentration of the phosphorus-doped silicon layer is 1*10. 17 cm -3 -1*10 18 cm -3 The phosphorus doping concentration of the phosphorus-doped microcrystalline silicon layer is 1*10. 18 cm -3 -1*10 20 cm -3 .

7. The battery structure according to any one of claims 1-3, characterized in that, The silicon substrate has a second intrinsic amorphous silicon layer, a first intrinsic amorphous silicon layer, a crystalline silicon layer, a first microcrystalline silicon layer, and a second microcrystalline silicon layer stacked sequentially on its surface in the second direction. The second intrinsic amorphous silicon layer is disposed close to the silicon substrate, and the first direction is perpendicular to the second direction.

8. A single battery cell, characterized in that, The battery structure includes a first conductive structure, a second conductive structure, and a battery structure according to any one of claims 1-7, wherein the first conductive structure is disposed on the surface of the first microcrystalline silicon layer of the battery structure on the side away from the silicon substrate, and the second conductive structure is disposed on the surface of the second microcrystalline silicon layer of the battery structure on the side away from the silicon substrate.

9. A photovoltaic system, characterized in that, Includes the battery cell according to claim 8.

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