Electronic device

Abstract

An electronic device is provided. The electronic device comprises a first substrate, a second substrate, a plurality of electronic units, an optical layer, a first sealing layer and a second sealing layer. The second substrate is arranged opposite to the first substrate. The plurality of electronic units are arranged between the first substrate and the second substrate. The optical layer is disposed between a portion of the plurality of electronic units and the second substrate. The first sealing layer is arranged between the other part of the electronic units and the second substrate, and the first sealing layer surrounds the optical layer. The second sealing layer is arranged between the first substrate and the second substrate, and the second sealing layer surrounds the first sealing layer. Wherein, relative to visible light, the difference between the penetration rate of the first sealing layer and the penetration rate of the optical layer is less than 5%.

Description

Technical Field

[0001] The present invention relates to an electronic device, and more particularly to an electronic device including a sealing layer. Background Art

[0002] Electronic devices including electronic units, such as displays, smartphones, tablet computers, laptop computers, and televisions, have become indispensable necessities in modern society. With the booming development of such electronic devices, consumers have high expectations for the quality, functions, or prices of these electronic devices.

[0003] Generally, in the process of manufacturing an electronic device, various bonding elements are often required to perform a bonding process, so that different substrates are bonded to each other to obtain an electronic device. Therefore, once the reliability of the bonding element is insufficient, problems such as reducing the visual effect, resolution, reliability, yield, and / or process margin of the electronic component may occur. In addition, it may also cause problems that the electronic device is not easily applied to a narrow bezel device.

[0004] Therefore, these electronic devices do not meet consumers' expectations in all aspects, and there are still some problems with the electronic devices. Developing improved electronic devices is still one of the current goals. Summary of the Invention

[0005] In some embodiments, an electronic device is provided. The electronic device may include a first substrate, a second substrate, a plurality of electronic units, an optical layer, a first sealing layer, and a second sealing layer. The second substrate may be disposed opposite to the first substrate. The plurality of electronic units may be disposed between the first substrate and the second substrate. The optical layer may be disposed between a portion of these electronic units and the second substrate. The first sealing layer may be disposed between another portion of these electronic units and the second substrate, and the first sealing layer may surround the optical layer. The second sealing layer may be disposed between the first substrate and the second substrate, and the second sealing layer may surround the first sealing layer. Wherein, with respect to visible light, the difference between the transmittance of the first sealing layer and the transmittance of the optical layer may be less than 5%.

[0006] In some embodiments, an electronic device is provided. The electronic device may include a first substrate, a second substrate, a plurality of electronic units, an optical layer, a sealing layer, and spacers. The first substrate may have an active region and a peripheral region, and the peripheral region may surround the active region. The second substrate may be disposed opposite to the first substrate. The plurality of electronic units may be disposed between the active region and the second substrate. The optical layer may be disposed between a portion of these electronic units and the second substrate. The sealing layer may be disposed between another portion of these electronic units and the second substrate and between the peripheral region and the second substrate. The spacers may be disposed between the peripheral region and the second substrate, and the spacers may be embedded in the sealing layer. Wherein, with respect to visible light, the difference between the transmittance of the sealing layer and the transmittance of the optical layer may be less than 5%.

[0007] The electronic device of the present disclosure can be applied to various types of electronic devices. To make the features and advantages of the present disclosure more obvious and understandable, various embodiments are specifically described below in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Through the following detailed description in conjunction with the accompanying drawings, we can better understand the viewpoints of the embodiments of the present disclosure. It should be noted that, according to industrial standard practices, some features may not be drawn to scale. In fact, for the sake of clear discussion, the dimensions of different components may be increased or decreased.

[0009] Figure 1 is a top view schematic diagram of an electronic device according to some embodiments of the present disclosure.

[0010] Figure 2 is a top view schematic diagram of a region of an electronic device according to some embodiments of the present disclosure.

[0011] Figure 3 is a cross-sectional schematic diagram of an electronic device according to some embodiments of the present disclosure.

[0012] Figure 4 is a cross-sectional schematic diagram of an electronic device according to some embodiments of the present disclosure.

[0013] Figure 5 is a top view schematic diagram of an electronic device according to some embodiments of the present disclosure.

[0014] Figure 6 is a cross-sectional schematic diagram of an electronic device according to some embodiments of the present disclosure.

[0015] Figure 7 is a cross-sectional schematic diagram of an electronic device according to some embodiments of the present disclosure.

[0016] Figure 8 It is a top view schematic diagram of an electronic device according to some embodiments of the present disclosure.

[0017] Figure 9 It is a cross-sectional schematic diagram of an electronic device according to some embodiments of the present disclosure.

[0018] Figure 10 It is a cross-sectional schematic diagram of an electronic device according to some embodiments of the present disclosure.

[0019] Figure 11 It is a top view schematic diagram of an electronic device according to some embodiments of the present disclosure.

[0020] Figure 12 It is a cross-sectional schematic diagram of an electronic device according to some embodiments of the present disclosure.

[0021] Figure 13 It is a cross-sectional schematic diagram of an electronic device according to some embodiments of the present disclosure.

[0022] Figure 14 It is a cross-sectional schematic diagram of an electronic device according to some embodiments of the present disclosure.

[0023] Figure 15 It is a cross-sectional schematic diagram of an electronic device according to some embodiments of the present disclosure.

[0024]

Symbol Explanation

[0025] 1, 2, 3, 4, 5, 6, 7, 8, 9, 10: Electronic device

[0026] 10: First substrate

[0027] 12: Conductive layer

[0028] 14: Pixel definition layer

[0029] 14TS: Top surface

[0030] 16, 16B, 16G, 16R: Electronic unit

[0031] 20: Second substrate

[0032] 22: Light-shielding layer

[0033] 24, 24B, 24R, 24G: Filter layer

[0034] 26: Planarization layer

[0035] 27, 27R, 27G: Color conversion layer

[0036] 28: Separation layer

[0037] 30: Optical layer

[0038] 40: First sealing layer

[0039] 42: Spacer

[0040] 42a: First spacer component

[0041] 42b: Second spacer component

[0042] 42b1, 42b2: Gap elements

[0043] 44: Retaining wall

[0044] 44BS: Bottom surface

[0045] 50: Second sealing layer

[0046] 52: Gap particles

[0047] 60: Air gap

[0048] AA: Active area

[0049] CL: Cutting line

[0050] D1: First direction

[0051] D2: Second direction

[0052] D3: Third direction

[0053] H: Height

[0054] I-I’, II-II’, III-III’, IV-IV’: Sections

[0055] L1: First virtual center line

[0056] L2: Second virtual center line

[0057] G1, G2, G3, G4, G5: Gaps

[0058] PA: Peripheral area

[0059] R1: Region

[0060] W1, W40, W42a, W44, W50: Widths Detailed implementation manner

[0061] The following provides a detailed description of the electronic devices in the embodiments of the present disclosure. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present disclosure. The specific components and arrangements described below are only for simply and clearly describing some embodiments of the present disclosure. Of course, these are only for illustration and not for limiting the present disclosure. In addition, similar and / or corresponding component symbols may be used in different embodiments to indicate similar and / or corresponding components to clearly describe the present disclosure. However, the use of these similar and / or corresponding component symbols is only for simply and clearly describing some embodiments of the present disclosure, and does not represent any association between the different embodiments and / or structures discussed.

[0062] It should be understood that in each embodiment, relative terms may be used, for example, "lower" or "bottom" or "higher" or "top", to describe the relative relationship of one component in the figure to another component. It can be understood that if the device in the figure is flipped upside down, the component described on the "lower" side will become the component on the "higher" side. The embodiments of the present disclosure can be combined with the attached Figure 1 And it is understood that the drawings of the present disclosure are also regarded as part of the disclosure description.

[0063] Furthermore, when it is mentioned that a first material layer is on or over a second material layer, it may include the case where the first material layer is in direct contact with the second material layer, or the first material layer and the second material layer may not be in direct contact, that is, there may be one or more other material layers between the first material layer and the second material layer. However, when the first material layer is directly on the second material layer, it means that the first material layer is in direct contact with the second material layer.

[0064] In addition, it should be understood that the ordinal numbers such as "first", "second", etc. used in the specification and the claims are used to modify components, and they do not themselves intend to imply that the component (or these components) has any previous ordinal number, nor do they represent the order of one component and another component, or the order in the manufacturing method. The use of these ordinal numbers is only to clearly distinguish a component with a certain name from another component with the same name. The claims and the specification may not use the same terms. For example, the first component in the specification may be the second component in the claims.

[0065] In some embodiments of the present disclosure, terms related to joining and connection, such as "connect", "interconnect", "bond", etc., unless otherwise defined, may mean that two structures are in direct contact, or may also mean that two structures are not in direct contact, with other structures disposed therebetween. And these terms related to connection and joining may also include the cases where both structures are movable, or both structures are fixed. In addition, the term "electrically connected" or "electrically coupled" includes any means of direct and indirect electrical connection.

[0066] In the text, terms such as "approximate", "about", "substantially" generally mean within 10%, or 5%, or 3%, or 2%, or 1%, or 0.5% of a given value or range. The given quantity is an approximate quantity, that is, the meanings of "approximate", "about", "substantially" may still be implied even without specific mention of "approximate", "about", "substantially". The phrase "in the range from the first value to the second value", "between the first value and the second value" or "the first value to the second value" means that the range includes the first value, the second value and other values therebetween. Moreover, there may be a certain error between any two values or directions being compared. If the first value is equal to the second value, it implies that there may be an error of about 10%, or 5%, or 3%, or 2%, or 1%, or 0.5% between the first value and the second value. If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees. If the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0067] Throughout the specification and claims of the present disclosure, certain terms are used to refer to specific components. Those skilled in the art should understand that electronic device manufacturers may use different names to refer to the same component. This document is not intended to distinguish components that have the same function but different names. In the following specification and claims, words such as "comprise", "include", "have" are open-ended words, and thus should be interpreted as meaning "including but not limited to...". Therefore, when the description of the present disclosure uses the terms "comprise", "include" and / or "have", it specifies the existence of the corresponding components, regions, steps, operations and / or assemblies, but does not exclude the existence of one or more corresponding components, regions, steps, operations and / or assemblies.

[0068] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It is understood that such terms, if defined in a commonly used dictionary, should be interpreted as having a meaning consistent with the relevant art and the background or context of the present disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of the present disclosure.

[0069] In the present disclosure, each direction is not limited to the three axes of the rectangular coordinate system, such as the X-axis, Y-axis, and Z-axis, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For the convenience of description, hereinafter, the X-axis direction is the first direction (width direction) D1, the Y-axis direction is the second direction (length direction) D2, and the Z-axis direction is the third direction (height / thickness direction) D3. In some embodiments, the top view schematic diagram described herein is a cross-sectional schematic diagram of the XY plane, and the cross-sectional schematic diagram described herein is a cross-sectional schematic diagram of the XZ plane. In some embodiments, the normal direction of the first substrate and / or the second substrate may be the third direction D3.

[0070] In some embodiments, according to the embodiments of the present disclosure, an optical microscope (OM), a scanning electron microscope (SEM), an α-step, an ellipsometer, or other suitable means may be used to measure the relative setting relationship, depth, thickness, width or height of each component, or the spacing or distance between components. According to some embodiments, a scanning electron microscope may be used to obtain a cross-sectional structure image of the component to be measured, and measure the depth, thickness, width or height of each component, or the spacing or distance between components.

[0071] In some embodiments, according to the embodiments of the present disclosure, an ultraviolet-visible spectrometer or other suitable means may be used to measure the transmittance (unit: %) of each component. In some embodiments, according to the embodiments of the present disclosure, a thin film analyzer or other suitable means may be used to measure the refractive index (n value) (unit: dimensionless) of each component. Among them, the refractive index may represent the ratio of the speed of light in a vacuum (c) to the phase velocity (v) of light after entering the medium (n = c / v).

[0072] In the present disclosure, the electronic device may include, but is not limited to, a display module, a backlight module, an antenna module, a sensing module, or a splicing module. The electronic device may be a bendable or flexible electronic device. The display module may be a non-self-emitting display module or a self-emitting display module. The antenna module may be a liquid crystal type antenna module or a non-liquid crystal type antenna module. The sensing module may be a sensing module for sensing capacitance, light, heat, or ultrasonic waves, but is not limited thereto. The electronic unit may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light emitting diode or a photodiode. The light emitting diode may include, for example, an organic light emitting diode (OLED), a mini light emitting diode (mini LED), a micro light emitting diode (micro LED), or a quantum dot light emitting diode (quantum dot LED), but is not limited thereto. The splicing module may be, for example, a display splicing module or an antenna splicing module, but is not limited thereto.

[0073] In addition, the shape of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may have peripheral systems such as a processing system, a driving system, a control system, a light source system, a shelf system, etc. to support the display module or the splicing module.

[0074] It should be understood that, for clarity of illustration, some components of the electronic device may be omitted in the drawings, and only some components are schematically shown. In some embodiments, additional components may be added to the electronic device described below. In other embodiments, some components of the electronic device described below may be replaced or omitted.

[0075] Referring to Figure 1 , which is a top view schematic diagram of an electronic device 1 according to some embodiments of the present disclosure. In some embodiments, the electronic device 1 may include a first substrate 10, a second substrate 20, and a bonding member. In some embodiments, the second substrate 20 may be disposed opposite to the first substrate 10, and the bonding member may be disposed between the second substrate 20 and the first substrate 10. In some embodiments, the first substrate 10 and the second substrate 20 may be arranged along a third direction D3. In some embodiments, the first substrate 10 may include an active area AA and a peripheral area PA. In some embodiments, the peripheral area PA may surround the active area AA. In some embodiments, the peripheral area PA may completely surround the active area AA, or the peripheral area PA may surround a part of the active area AA and expose another part of the active area AA. In some embodiments, other components such as pads may be further disposed in the peripheral area PA of the first substrate 10.

[0076] In some embodiments, the bonding member may include an optical layer 30, a first sealing layer 40, and / or a second sealing layer 50, but the present disclosure is not limited thereto. In some embodiments, as Figure 1 shown, the first sealing layer 40 may be disposed in both the active region AA and the peripheral region PA. In some embodiments, as Figure 1 shown, the second sealing layer 50 may be disposed in the peripheral region PA and may be spaced apart from the active region AA by a distance. In some embodiments, the second sealing layer 50 may surround the first sealing layer 40. In some embodiments, when viewed from a top view, the first sealing layer 40 and / or the second sealing layer 50 may have a frame shape, but the present disclosure is not limited thereto. In some embodiments, the first sealing layer 40 may be interposed between the optical layer 30 and the second sealing layer 50.

[0077] Referring to Figure 2 , which is a top view schematic diagram of the region R1 of the electronic device 1 according to some embodiments of the present disclosure. In some embodiments, the cutting line CL may extend along the second direction D2, and a subsequent cutting process may be performed along the cutting line CL. In some embodiments, in the third direction D3, the cutting line CL may overlap with the edge of the second substrate 20. In some embodiments, the cutting process may include a laser cutting process, a blade cutting process, other suitable cutting processes, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, in the first direction D1, the cutting line CL and the active region AA of the first substrate 10 may be spaced apart from each other by a width W1. In some embodiments, the width W1 may be between 1200 um and 2000 um. For example, the width W1 may be 1200 um, 1400 um, 1600 um, 1800 um, 2000 um, or any value between the foregoing values or any value range composed of any values, but the present disclosure is not limited thereto.

[0078] In some embodiments, as Figure 2 shown, in the first direction D1, the first sealing layer 40 may have a width W40. In some embodiments, the width W40 of the first sealing layer 40 may be between 800 um and 1200 um. For example, the width W40 may be 800 um, 900 um, 1000 um, 1100 um, 1200 um, or any value between the foregoing values or any value range composed of any values, but the present disclosure is not limited thereto. In some embodiments, a first virtual center line L1 of the first sealing layer 40 is shown, wherein in the first direction D1, the first virtual center line L1 may bisect the width W40 of the first sealing layer 40. Therefore, the material of the first sealing layer 40 may be coated along the first virtual center line L1 of the first sealing layer 40. In some embodiments, the first virtual center line L1 may overlap with the edge of the active region AA.

[0079] In some embodiments, as Figure 2As shown, in the first direction D1, the second sealing layer 50 may have a width W50. In some embodiments, the width W50 of the second sealing layer 50 may be between 550um and 950um. For example, the width W50 may be 550um, 650um, 750um, 850um, 950um, or any value or range of values between the foregoing values, but the present disclosure is not limited thereto. In some embodiments, a second virtual center line L2 of the second sealing layer 50 is shown, wherein in the first direction D1, the second virtual center line L2 may bisect the width W50 of the second sealing layer 50. Therefore, the material of the second sealing layer 50 can be coated along the second virtual center line L2 of the second sealing layer 50.

[0080] Referring to Figure 3 , which is a cross-sectional schematic view of an electronic device 1 according to some embodiments of the present disclosure. Among them, Figure 3 is a cross-sectional schematic view taken along the Figure 1 section I-I' shown. In some embodiments, the first substrate 10 and / or the second substrate 20 may include glass, quartz, sapphire, ceramics, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polypropylene (PP), liquid crystal polymer (LCP), other suitable materials, or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the substrate 100 may include a light-transmitting substrate, a semi-light-transmitting substrate, or an opaque substrate. For example, the first substrate 10 and the second substrate 20 may include glass.

[0081] In some embodiments, the conductive layer 12 may be disposed on the first substrate 10. In some embodiments, the material of the conductive layer 12 may include metals, metal nitrides, semiconductor materials, other suitable conductive materials, or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the material of the conductive layer 12 may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), silver (Ag), magnesium (Mg), their alloys, their compounds, or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the material of the conductive layer 12 may include a transparent conductive oxide (TCO). For example, the transparent conductive oxide may include indium tin oxide (ITO), antimony zinc oxide (AZO), tin oxide (SnO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), antimony tin oxide (ATO), other suitable transparent conductive materials, or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the pixel definition layer 14 may be disposed on the conductive layer 12. In some embodiments, the pixel definition layer 14 may have openings, and the openings may be used to expose the subsequently formed electronic units.

[0082] In some embodiments, a plurality of electronic units 16 may be disposed on the first substrate 10 and in the openings of the pixel definition layer 14. In some embodiments, the plurality of electronic units 16 may be disposed between the first substrate 10 and the second substrate 20. In some embodiments, the plurality of electronic units 16 may be disposed in the active region AA of the first substrate 10. In other words, the region of the first substrate 10 where the plurality of electronic units 16 are disposed may serve as the active region AA of the first substrate 10. In some embodiments, the plurality of electronic units 16 may be disposed between the active region AA of the first substrate 10 and the second substrate 20.

[0083] In some embodiments, the electronic unit 16 may be a component with a light-emitting function. In some embodiments, the electronic unit may include an organic light emitting diode (OLED), a mini light emitting diode (mini LED), a micro light emitting diode (micro LED), a quantum dot light emitting diode (quantum dot LED), other suitable light-emitting components, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, since the electronic unit 16 may be a small-sized light-emitting component, the conductive layer 12 and the pixel definition layer 14 corresponding to the electronic unit 16 have a small pitch. In some embodiments, the electronic unit 16 may include electronic units that emit light of different colors. In some embodiments, the electronic unit 16 may include an electronic unit 16B that emits blue light, an electronic unit 16R that emits red light, and an electronic unit 16G that emits green light. In some embodiments, the first substrate 10, the conductive layer 12, the pixel definition layer 14, and the electronic unit 16 may be collectively referred to as a transistor module.

[0084] In some embodiments, the light-shielding layer 22 may be disposed on the second substrate 20. In some embodiments, the light-shielding layer 22 may be a black matrix, a black glue, or a black photoresist material. In some embodiments, with respect to visible light, the transmittance of the light-shielding layer 22 may be less than 30%. For example, the transmittance of the light-shielding layer 22 for visible light is less than 30%, 25%, 20%, 15%, 10%, 5%, 3%, 1%, or any value between the foregoing values, but the present disclosure is not limited thereto. Therefore, in the case where the light-shielding layer 22 has a low transmittance, the external ambient light irradiated onto the conductive layer 12 can be reduced. In some embodiments, the light-shielding layer 22 may have an opening, and the opening may be used to expose a subsequent formed color filter layer.

[0085] In some embodiments, the color filter layer 24 may be disposed on the second substrate 20 and may be disposed in the opening of the light-shielding layer 22. In some embodiments, the color filter layer 24 may include a blue color filter layer 24B, a red color filter layer 24R, and a green color filter layer 24G corresponding to blue light, red light, and green light, respectively. In some embodiments, the planarization layer 26 may be disposed on the color filter layer 24 and the light-shielding layer 22 to make the second substrate 20 have a flat surface. In some embodiments, the planarization layer 26 may include an optically transparent material. In some embodiments, the second substrate 20, the light-shielding layer 22, the color filter layer 24, and the planarization layer 26 may be collectively referred to as a color filter module.

[0086] In some embodiments, as Figure 3As shown, the optical layer 30 may be disposed between a part of the electronic unit 16 and the second substrate 20. In some embodiments, the optical layer 30 may cover a part of the electronic unit 16 and may expose a part of the electronic unit 16. In some embodiments, the optical layer 30 may include an optical clear adhesive (OCA), an optical clear resin (OCR), a pressure sensitive adhesive (PSA), but the present disclosure is not limited thereto.

[0087] In some embodiments, with respect to visible light, the transmittance of the optical layer 30 may be greater than or equal to 95% and less than or equal to 100% (95% ≤ transmittance of the optical layer 30 ≤ 100%). For example, the transmittance of the optical layer 30 may be 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or any value between the foregoing values or any value range composed of any values, but the present disclosure is not limited thereto. In some embodiments, visible light may be light having a wavelength between 380 nm and 780 nm. For example, the wavelength of visible light may be 380 nm, 400 nm, 500 nm, 550 nm, 600 nm, 700 nm, 780 nm, or any value between the foregoing values or any value range composed of any values, but the present disclosure is not limited thereto. In some embodiments, the refractive index (n value) of the optical layer 30 may be between 1.3 and 1.6. For example, the n value of the optical layer 30 may be 1.3, 1.35, 1.4, 1.45, 1.5, 1.51, 1.52, 1.53, 1.54, 1.55, 1.56, 1.57, 1.58, 1.59, 1.6, or any value between the foregoing values or any value range composed of any values, but the present disclosure is not limited thereto.

[0088] In some embodiments, as Figure 3 shown, the first sealing layer 40 may be disposed between another part of the electronic unit 16 and the second substrate 20. In some embodiments, the first sealing layer 40 may be disposed on the electronic unit 16 exposed by the optical layer 30. In some embodiments, the optical layer 30 may cover a part of the electronic unit 16, and the first sealing layer 40 may cover the remaining part of the electronic unit 16. In some embodiments, the first sealing layer 40 may surround the optical layer 30.

[0089] In some embodiments, the transmittance of the first sealing layer 40 may be greater than or equal to 95% and less than or equal to 100% relative to visible light. For example, the transmittance of the first sealing layer 40 may be 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or any value or range of values between the foregoing values, but the present disclosure is not limited thereto. In some embodiments, the first sealing layer 40 may include silicone resin, epoxy resin, acrylic resin, other suitable materials, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the refractive index (n value) of the first sealing layer 40 may be between 1.3 and 1.6. For example, the n value of the first sealing layer 40 may be 1.3, 1.35, 1.4, 1.45, 1.5, 1.51, 1.52, 1.53, 1.54, 1.55, 1.56, 1.57, 1.58, 1.59, 1.6, or any value or range of values between the foregoing values, but the present disclosure is not limited thereto.

[0090] In some embodiments, the difference in the transmittance between the first sealing layer 40 and the optical layer 30 may be less than 5% (|transmittance of the first sealing layer 40 - transmittance of the optical layer 30| < 5%) relative to visible light, so as to avoid a seam when light passes through the adjacent first sealing layer 40 and optical layer 30 respectively, thereby improving the visual effect of the user observing the electronic device 1. For example, the difference in the transmittance between the first sealing layer 40 and the optical layer 30 may be less than 5%, 4%, 3%, 2%, 1%, 0.5% or less, or any value or range of values between the foregoing values, but the present disclosure is not limited thereto. In some embodiments, the transmittance of the first sealing layer 40 may be less than the transmittance of the optical layer 30 relative to visible light. In some embodiments, the transmittance of the first sealing layer 40 may be less than the transmittance of the optical layer 30 by a difference of 5% relative to visible light.

[0091] In some embodiments, the difference in the refractive index between the first sealing layer 40 and the optical layer 30 may be less than 0.1 (|refractive index of the first sealing layer 40 - refractive index of the optical layer 30| < 0.1), so as to avoid a seam when light passes through the adjacent first sealing layer 40 and optical layer 30 respectively, thereby improving the visual effect. For example, the difference in the refractive index between the first sealing layer 40 and the optical layer 30 may be less than 0.1, 0.09, 0.08, 0.07, 0.06, 0.05, 0.04, 0.03 or less, or any value or range of values between the foregoing values, but the present disclosure is not limited thereto.

[0092] In some embodiments, as Figure 3 shown, the second sealing layer 50 may be disposed between the first substrate 10 and the second substrate 20, and the second sealing layer 50 may surround the first sealing layer 40. In some embodiments, the second sealing layer 50 may be disposed on the peripheral region PA of the first substrate 10. In some embodiments, in the third direction D3, the junction of the first sealing layer 40 and the second sealing layer 50 does not overlap with the electronic unit 16. In some embodiments, the projection position of the junction of the first sealing layer 40 and the second sealing layer 50 on the first substrate 10 is spaced apart from the projection position of the electronic unit 16 on the first substrate 10 by a distance. In some embodiments, since the first sealing layer 40 may be between the optical layer 30 and the second sealing layer 50, the optical layer 30 and the second sealing layer 50 are spaced apart by a distance.

[0093] In some embodiments, the material of the second sealing layer 50 may be the same as or different from the material of the first sealing layer 40. In some embodiments, the second sealing layer 50 may include silicone resin, epoxy resin, acrylic resin, other suitable materials, or a combination thereof, but the present disclosure is not limited thereto. In other embodiments, the second sealing layer 50 may further include a filler to enhance the structural strength of the second sealing layer 50. Therefore, the structural strength of the second sealing layer 50 may be greater than the structural strength of the first sealing layer 40. In some embodiments, the filler may include silica-based materials. For example, the filler may include silica particles. In this embodiment, since the first sealing layer 40 does not include a filler, the transmittance of the first sealing layer 40 may be greater than the transmittance of the second sealing layer 50.

[0094] In some embodiments, the second sealing layer 50 may further include a plurality of interstitial particles 52, and the plurality of interstitial particles 52 may be dispersed in the second sealing layer 50 to enhance the structural strength and support of the second sealing layer 50. In some embodiments, the volume of the interstitial particles 52 may account for 3% or less of the volume of the second sealing layer 50. For example, the volume of the interstitial particles 52 may account for 3%, 2.5%, 2%, 1.5%, 1%, 0.75%, 0.5%, 0.1%, or any value or range of values between the foregoing values of the volume of the second sealing layer 50, but the present disclosure is not limited thereto. In some embodiments, the interstitial particles 52 may include silica-based materials. For example, the interstitial particles 52 may include silica balls. In some embodiments, the size of the interstitial particles 52 may be significantly larger than the size of the filler. In some embodiments, the size of the interstitial particles 52 may depend on the height H (i.e., the cell gap) between the planarization layer 26 and the electronic unit 16. In some embodiments, the diameter of the interstitial particles 52 may be 0.5 to 0.95 times the height H. For example, the diameter of the interstitial particles 52 may be 0.5 times, 0.6 times, 0.7 times, 0.8 times, 0.9 times, 0.95 times the height H, or any value or range of values between the foregoing values, but the present disclosure is not limited thereto.

[0095] In some embodiments, as Figure 3 shown, the electronic device 1 may include a separator 42 surrounding the optical layer 30, and the separator 42 may include a first spacer element 42a. In some embodiments, the first spacer element 42a may be disposed between the active region AA of the first substrate 10 and the second substrate 20. In some embodiments, the first spacer element 42a may provide support and structural strength between the first substrate 10 and the second substrate 20. In some embodiments, the first spacer element 42a may include polyimide (PI), benzocyclobutene, polymethylmethacrylate (PMMA), polyamide, acrylic acid, phenolic resin, other suitable materials, or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, as Figure 3 shown, when observed in a cross-sectional view, the shape of the first spacer element 42a may include a rectangle, a regular trapezoid, an inverted trapezoid, a semicircle, other suitable shapes, or combinations thereof, but the present disclosure is not limited thereto.

[0096] In some embodiments, a transistor module and a light filtering module may be formed separately. In some embodiments, spacers 42 may be formed on the light filtering module. For example, the spacers 42 may be formed on the surface of the planarization layer 26 in the light filtering module away from the second substrate 20 by a photolithography process. In some embodiments, after the spacers 42 are formed on the light filtering module, materials for the bonding members (e.g., materials for the optical layer 30, the first sealing layer 40, and the second sealing layer 50) are provided on the light filtering module. For example, the materials for the bonding members may be provided on the light filtering module by coating, injection, other suitable processes, or a combination thereof. In some embodiments, a bonding process is performed to bond the transistor module to the light filtering module. For example, the transistor module is flipped so that the electronic unit 16 of the transistor module faces the light filtering module for bonding with the light filtering module. In some embodiments, a photo-curing process is performed on the bonded transistor module and light filtering module. In some embodiments, after the photo-curing process is performed, a thermal-curing process is further performed. In some embodiments, a cutting process (as Figure 2 shown) may be performed on the cured transistor module and light filtering module to obtain a plurality of electronic devices.

[0097] It should be noted in particular that since the opening rate in the peripheral area PA is smaller than that in the active area AA, the conductive layer 12 and the pixel defining layer 14 in the peripheral area PA will block the light emitted during the photo-curing process, making it difficult for the bonding member between the conductive layer 12 and the pixel defining layer 14 in the peripheral area PA to be photo-cured. Additionally, when the electronic device includes a small-sized light-emitting component, the opening rate in the active area AA will be further reduced, resulting in even more difficulty in photo-curing the bonding member between the conductive layer 12 and the pixel defining layer 14 in the peripheral area PA. Therefore, if the bonding member is difficult to be photo-cured, the different materials in the bonding member will dissolve into each other, leading to the problem of dissolution (dissolve). Furthermore, since the bonding process may be performed under a pressure lower than normal pressure (e.g., less than 1 atm), the materials of the bonding member will spill over to the cutting line (such as the cutting line CL shown in Figure 2 ), interfering with the subsequent cutting process. This further leads to the deterioration of the performance of the electronic device.

[0098] In a comparative example, the optical layer 30 is disposed in the active area AA and the peripheral area PA of the first substrate 10, the second sealing layer 50 is disposed in the peripheral area PA of the first substrate 10, the optical layer 30 is in direct contact with the second sealing layer 50, and the first sealing layer 40 is omitted. Since the light emitted during the photo-curing process is blocked, it is difficult for the second sealing layer 50 to be effectively photo-cured. Therefore, dissolution (dissolve) will occur between the optical layer 30 and the second sealing layer 50 and / or cause the optical layer 30 and the second sealing layer 50 to spill over to the cutting line (such asFigure 2 on the cutting line CL shown.

[0099] However, in the present disclosure, by disposing the first sealing layer 40 between the optical layer 30 and the second sealing layer 50 and in the active region AA, the first sealing layer 40 is located in the active region AA with a higher aperture ratio. Therefore, the first sealing layer 40 can be irradiated by the light emitted during the photo-curing process, and the first sealing layer 40 can be effectively photo-cured, thereby separating the optical layer 30 and the second sealing layer 50 from each other. Then, a thermal curing process is performed to thermally cure the optical layer 30 and the second sealing layer 50 and ensure the curing of the first sealing layer 40. Accordingly, the present disclosure can avoid the problems of penetration and / or overflow caused by the direct contact between the optical layer 30 and the second sealing layer 50.

[0100] In the following, the same or similar component symbols and descriptions are omitted.

[0101] Referring to Figure 4 , which is a cross-sectional schematic view of the electronic device 2 according to some embodiments of the present disclosure. Among them, Figure 4 is a cross-sectional schematic view taken along the cross-section I-I' shown in Figure 1 . In some embodiments, as shown in Figure 4 , the electronic device 2 may include a color conversion layer 27 and a separation layer 28. In some embodiments, the separation layer 28 may be disposed on the light-shielding layer 22 to define a space for accommodating the color conversion layer 27. In some embodiments, the separation layer 28 may include a black resin, a gray resin, a white resin, a metal, other suitable materials, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the color conversion layer 27 may be disposed on the light-filtering layer 24. In some embodiments, the color conversion layer 27 may include a red color conversion layer 27R and a green color conversion layer 27G. In some embodiments, the red color conversion layer 27R may be disposed on the red light-filtering layer 24R and may include red quantum dots. In some embodiments, the green color conversion layer 27G may be disposed on the green light-filtering layer 24G and may include green quantum dots. Therefore, the blue light emitted from the electronic unit 16B can convert the wavelength and color of the light through the color conversion layer 27. Optionally, a light diffusion layer may be disposed on the blue light-filtering layer 24B, and the light diffusion layer may include diffusion particles, such as titanium dioxide particles.

[0102] Referring to Figure 5 , which is a top view schematic of the electronic device 3 according to some embodiments of the present disclosure. For ease of illustration, in Figure 5Some components may be omitted. In some embodiments, the first sealing layer 40 may be disposed in both the active region AA and the peripheral region PA, and the second sealing layer 50 may be omitted. In some embodiments, the optical layer 30 may be disposed in the active region AA. Accordingly, the present disclosure can avoid the problems of penetration and / or overflow caused by the direct contact between the optical layer 30 and the second sealing layer. For example, a part of the first sealing layer 40 in the active region AA may be first photocured in the photocuring process, and then the remaining part of the first sealing layer 40 in the peripheral region PA (and the optical layer 30) may be thermally cured in the thermal curing process.

[0103] Referring to Figure 6 , which is a cross-sectional schematic view of the electronic device 3 according to some embodiments of the present disclosure. Among them, Figure 6 is a cross-sectional schematic view taken along the Figure 5 section II-II' shown. In some embodiments, as Figure 6 shown, the optical layer 30 may be disposed between a part of the electronic unit 16 and the second substrate 20. In some embodiments, the first sealing layer 40 may be disposed between another part of the electronic unit 16 and the second substrate 20, and may be disposed between the peripheral region PA of the first substrate 10 and the second substrate 20. In some embodiments, the first sealing layer 40 may be disposed on the electronic unit 16 exposed by the optical layer 30.

[0104] In some embodiments, as Figure 6 shown, the electronic device 3 may include a spacer 42 surrounding the optical layer 30. In some embodiments, the spacer 42 may include a first spacer component 42a and a second spacer component 42b, and the second spacer component 42b may surround the first spacer component 42a. In some embodiments, a part of the spacer 42 (i.e., the first spacer component 42a) may be disposed between the active region AA of the first substrate 10 and the second substrate 20, and may be embedded in the first sealing layer 40. In some embodiments, a part of the spacer 42 (i.e., the second spacer component 42b) may be disposed between the peripheral region PA of the first substrate 10 and the second substrate 20, and may be embedded in the first sealing layer 40. In some embodiments, the materials and formation methods of the first spacer component 42a and the second spacer component 42b may be the same or different. In some embodiments, the first spacer component 42a and the second spacer component 42b may include the same material and be formed in the same process.

[0105] In some embodiments, the second spacer assembly 42b may include a plurality of spacers 42b1, 42b2, and the plurality of spacers 42b1, 42b2 may be arranged on the periphery of the first sealing layer 40. In some embodiments, the spacers 42b1, 42b2 may be disposed on a side of the first sealing layer 40 away from the optical layer 30. In some embodiments, the spacer 42b1 may be closer to the optical layer 30 than the spacer 42b2.

[0106] In some embodiments, as Figure 6 shown, after performing the bonding process and before performing the light curing process, the second spacer assembly 42b can be used to prevent the material of the first sealing layer 40 from overflowing. Since the second spacer assembly 42b may include a plurality of spacers 42b1, 42b2, the process margin can be further improved. In some embodiments, the first sealing layer 40 may fill the gaps G1 and G2. In other embodiments, the first sealing layer 40 may not fill the gap G1, or the first sealing layer 40 may not be filled into the gap G1. In other embodiments, the first sealing layer 40 may not fill the gap G1, and the first sealing layer 40 may not be filled into the gap G2. Therefore, the process margin for providing the material of the first sealing layer 40 on the filter module and / or the process margin for performing the cutting process can be improved.

[0107] Referring to Figure 7 , which is a cross-sectional schematic diagram of the electronic device 4 according to some embodiments of the present disclosure. Among them, Figure 7 is a cross-sectional schematic diagram taken along the cross-section II-II' shown in Figure 5 . In some embodiments, as Figure 7 shown, the electronic device 4 may include a spacer 42 surrounding the optical layer 30. In some embodiments, the first sealing layer 40 may completely fill, partially fill, or not fill the gaps G1 and / or G2.

[0108] Referring to Figure 8 , which is a top view schematic diagram of the electronic device 5 according to some embodiments of the present disclosure. For the sake of convenience of description, in Figure 8Some components may be omitted. In some embodiments, the electronic device 5 may further include a dam wall 44 disposed in the optical layer 30, and the first sealing layer 40 and the second sealing layer 50 may be omitted. In some embodiments, the dam wall 44 may be disposed in the peripheral area PA of the first substrate 10. In some embodiments, the material and formation method of the dam wall 44 may be the same as or different from those of the first spacer component 42a. In some embodiments, the dam wall 44 and the first spacer component 42a may include the same material and be formed in the same process. In some embodiments, when viewed from a top view, the dam wall 44 may have a frame shape, but the present disclosure is not limited thereto. Accordingly, the present disclosure can avoid the problems of penetration and / or overflow caused by the direct contact between the optical layer 30 and the second sealing layer. For example, since the first sealing layer 40 and the second sealing layer 50 are omitted, penetration and / or overflow will not occur. In addition, the photo-curing process may be omitted, and the optical layer 30 may be thermally cured by a thermal curing process.

[0109] Refer to Figure 9 , which is a cross-sectional schematic view of the electronic device 5 according to some embodiments of the present disclosure. Among them, Figure 9 is a cross-sectional schematic view taken along the Figure 8 section III-III' shown. In some embodiments, the optical layer 30 may be disposed in the active area AA and the peripheral area PA of the first substrate 10. In some embodiments, the dam wall 44 may surround the first spacer component 42a. In some embodiments, in the first direction D1, the first spacer component 42a may have a width W42a, the dam wall 44 may have a width W44, and the ratio of the width W44 to the width W42a (width W44 / width W42a) may be between 1 and 100. For example, the ratio of the width W44 to the width W42a may be 1, 5, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, or any value or value range composed of any of the foregoing values, but the present disclosure is not limited thereto. In some embodiments, the bottom surface 44BS of the dam wall 44 may be flush with the top surface 14TS of the pixel defining layer 14. In some embodiments, the optical layer 30 may completely fill, partially fill, or not fill the gap G3.

[0110] Refer to Figure 10 , which is a cross-sectional schematic view of the electronic device 6 according to some embodiments of the present disclosure. Among them, Figure 10 is along Figure 8A schematic cross-sectional view taken along the cross-section III-III'. In some embodiments, the bottom surface 44BS of the retaining wall 44 may be lower than the top surface 14TS of the pixel definition layer 14, so that a part of the retaining wall 44 is embedded in the pixel definition layer 14. In some embodiments, an etching process may be performed on the pixel definition layer 14 to form a recess (not shown), and then the retaining wall 44 is formed in the recess. In some embodiments, since the pixel definition layer 14 may cover a part of the side surface of the retaining wall 44, the structural strength of the electronic device can be improved. In some embodiments, the optical layer 30 may completely fill, partially fill, or not fill the gap G3.

[0111] Referring to Figure 11 , which is a top view schematic diagram of the electronic device 7 according to some embodiments of the present disclosure. In some embodiments, the electronic device 7 may include a second sealing layer 50 disposed in the peripheral area PA of the first substrate 10, and the optical layer 30 and the first sealing layer 40 are omitted. In some embodiments, since the optical layer 30 and the first sealing layer 40 are omitted, there is an air gap 60 between the active area AA of the first substrate 10 and the second substrate 20. Accordingly, the present disclosure can avoid the problems of penetration and / or overflow caused by the direct contact between the optical layer 30 and the second sealing layer 50. For example, since the optical layer 30 is omitted, penetration and / or overflow do not occur. In the present disclosure, sufficient structural strength of the electronic device can be provided by the first spacer assembly 42a, the second sealing layer 50, and the gap particles 52.

[0112] Referring to Figure 12 , which is a cross-sectional schematic diagram of the electronic device 7 according to some embodiments of the present disclosure. Among them, Figure 12 is a cross-sectional schematic diagram taken along the cross-section IV-IV' shown in Figure 11 . In some embodiments, the air gap 60 may be between the electronic unit 16 and the planarization layer 26. In this embodiment, the electronic device 7 may include a second sealing layer 50 disposed in the peripheral area PA of the first substrate 10, and the optical layer 30 and the first sealing layer 40 are omitted.

[0113] Referring to Figure 13 , which is a cross-sectional schematic diagram of the electronic device 8 according to some embodiments of the present disclosure. Among them, Figure 13 is a cross-sectional schematic diagram taken along the cross-section IV-IV' shown in Figure 11 . In some embodiments, the air gap 60 may be between the electronic unit 16 and the separation layer 28. In this embodiment, the electronic device 8 may include a second sealing layer 50 disposed in the peripheral area PA of the first substrate 10, and the optical layer 30 and the first sealing layer 40 are omitted.

[0114] Referring to Figure 14 and Figure 15, which is a cross-sectional schematic diagram of electronic devices 9 and 10 according to some embodiments of the present disclosure. Among them, Figure 14 and Figure 15 are respectively cross-sectional schematic diagrams taken along the Figure 11 shown cross-section IV-IV'. In some embodiments, as Figure 14 and Figure 15 shown, the gap particles 42b1 and 42b2 can replace the gap particles 52.

[0115] Accordingly, the present disclosure adjusts the corresponding relationships such as the material type, setting position, size, etc. of the bonding members (for example, the optical layer, the first sealing layer, the second sealing layer) between the first substrate and the second substrate to improve the reliability of the bonding members and / or the visual effect, resolution, reliability, yield and / or process margin of the electronic device.

[0116] For example, the present disclosure can select an optical layer and a first sealing layer with specific transmittance differences (for example, <5%) and / or specific refractive index (n value) differences (for example, <0.1) to avoid the problem of seams when light passes through adjacent optical layers and sealing layers respectively. For example, the present disclosure can avoid the problems of penetration and / or overflow caused by the direct contact between the optical layer and the second sealing layer by setting the first sealing layer between the optical layer and the second sealing layer; by setting the optical layer and the first sealing layer and omitting the second sealing layer; by setting the optical layer and omitting the first sealing layer and the second sealing layer; and / or by setting an air gap and the second sealing layer. For example, the electronic device of the present disclosure can include gap particles and spacers (for example, spacer components, gap elements) to improve the structural strength of the electronic device. For example, since the bonding members of the present disclosure can have a high transmittance, the electronic device of the present disclosure can be applied to narrow bezel products.

[0117] The features between the embodiments of the present disclosure can be arbitrarily mixed and used as long as they do not violate the inventive spirit or conflict with each other. In addition, the protection scope of the present disclosure is not limited to the processes, machines, manufactures, compositions of matter, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the processes, machines, manufactures, compositions of matter, devices, methods and steps developed currently or in the future from the disclosure of the present disclosure. As long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can be used according to the present disclosure. Therefore, the protection scope of the present disclosure includes the above-mentioned processes, machines, manufactures, compositions of matter, devices, methods and steps. The protection scope of the present disclosure shall be determined by the scope defined in the patent application scope. Any embodiment or claim of the present disclosure does not have to achieve all the purposes, advantages and / or features disclosed in the present disclosure.

[0118] The foregoing outlines several embodiments so that those skilled in the art may better understand the perspective of the embodiments of the present disclosure. Those skilled in the art should understand that they can, based on the embodiments of the present disclosure, design or modify other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present disclosure.

Claims

1. An electronic device, characterized in that, Comprising: A first substrate; A second substrate, disposed opposite to the first substrate; A plurality of electronic units, disposed between the first substrate and the second substrate; An optical layer, disposed between a part of the plurality of electronic units and the second substrate; A first sealing layer, disposed between another part of the plurality of electronic units and the second substrate, and the first sealing layer surrounds the optical layer; And A second sealing layer, disposed between the first substrate and the second substrate, and the second sealing layer surrounds the first sealing layer; Wherein, with respect to visible light, the difference between the transmittance of the first sealing layer and the transmittance of the optical layer is less than 5%.

2. The electronic device according to claim 1, characterized in that, The second sealing layer includes a plurality of interstitial particles.

3. The electronic device according to claim 1, characterized in that, The junction of the first sealing layer and the second sealing layer does not overlap with the plurality of electronic units.

4. The electronic device according to claim 1, wherein With respect to visible light, the transmittance of the first sealing layer is less than the transmittance of the optical layer.

5. The electronic device according to claim 1, characterized in that, With respect to visible light, the transmittance of the first sealing layer and the optical layer is greater than or equal to 95% and less than or equal to 100%.

6. The electronic device according to claim 1, wherein The difference in the n value between the first sealing layer and the optical layer is less than 0.

1.

7. The electronic device according to claim 1, wherein The n values of the first sealing layer and the optical layer are between 1.3 and 1.

6.

8. The electronic device according to claim 1, wherein The width of the first sealing layer is between 800um and 1200um.

9. An electronic device, characterized in that, Comprising: A first substrate, having an active region and a peripheral region, the peripheral region surrounding the active region; A second substrate, disposed opposite to the first substrate; A plurality of electronic units, disposed between the active region and the second substrate; An optical layer, disposed between a part of the plurality of electronic units and the second substrate; A sealing layer, disposed between another part of the plurality of electronic units and the second substrate and between the peripheral region and the second substrate; And Spacers, disposed between the peripheral region and the second substrate, and the spacers are embedded in the sealing layer; Wherein, with respect to visible light, the difference between the transmittance of the sealing layer and the transmittance of the optical layer is less than 5%.

10. The electronic device according to claim 9, wherein The spacers surround the optical layer.

11. The electronic device according to claim 10, wherein, The spacers include a first spacer component and a second spacer component, and the second spacer component surrounds the first spacer component.

12. The electronic device according to claim 9, wherein, The spacers include a plurality of interstitial elements, and the plurality of interstitial elements are arranged on the periphery of the sealing layer.

13. The electronic device according to claim 9, characterized in that, With respect to visible light, the transmittance of the sealing layer is less than the transmittance of the optical layer.

14. The electronic device according to claim 9, wherein With respect to visible light, the transmittance of the sealing layer and the optical layer is greater than or equal to 95% and less than or equal to 100%.

15. The electronic device according to claim 9, wherein The difference in the n value between the sealing layer and the optical layer is less than 0.

1.

16. The electronic device according to claim 9, wherein The n values of the sealing layer and the optical layer are between 1.3 and 1.6.

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