A test screening method and system for enhancing chip resistance to electrical interference

Abstract

The present invention provides a test screening method and system for enhancing chip anti-electric interference, which relates to the field of semiconductor chip anti-electric interference technology. The method comprises extracting a characteristic frequency set and its corresponding spatial electric field distribution by finite element analysis to generate an excitation signal library; regulating the electron spin quantum state of the NV color center by microwave pulses to lock the characteristic resonant frequency point set corresponding to the microcrack; constructing a Vietoris-Rips complex based on the characteristic resonant frequency point set to screen out high-risk chips with a defect risk index greater than 0.15; applying dynamic bias temperature stress to high-risk chips to screen out chips that meet the standards; optimizing the excitation combination weight, frequency band priority and stress loading timing through interactive training, and finally outputting an adaptive test strategy. The beneficial effect of the present invention is to achieve full-process closed-loop control from signal generation, defect location to strategy adaptation, thereby ensuring the long-term stability of the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chip anti-electrical interference, and in particular to a test screening method and system for enhancing chip anti-electrical interference. Background Art

[0002] Currently, anti-interference testing of high-density integrated circuits in complex electromagnetic environments primarily relies on fixed-band scanning and statistical threshold determination using automated test equipment (ATE). This traditional approach has significant drawbacks: First, ATE test bandwidth is typically limited to less than 200 MHz, making it incapable of capturing hidden defects caused by GHz-level transient interference; second, test parameter setting relies on manual experience, resulting in a false positive rate as high as 15%-20%, and the approach is unable to dynamically adapt to process fluctuations.

[0003] Existing technologies attempt to alleviate interference by adding shielding covers or improving filtering algorithms, but the former is limited by packaging space, and the latter is difficult to cope with multi-physical field coupling effects due to algorithm rigidity. Neither method fundamentally solves the problem of high-frequency defect detection and reliability assessment. Summary of the Invention

[0004] The purpose of the present invention is to provide a test screening method and system for enhancing chip resistance to electrical interference, so as to improve the above-mentioned problem. To achieve the above-mentioned purpose, the technical solution adopted by the present invention is as follows:

[0005] In a first aspect, the present application provides a test and screening method for enhancing chip resistance to electrical interference, comprising:

[0006] Based on the failure frequency distribution data of historically failed chips on the production line, the eigenmodes of Maxwell's equations are solved using the three-dimensional finite-difference time-domain method. The finite element analysis method is then used to extract the set of eigenfrequencies and their corresponding spatial electric field distributions. This generates an excitation signal library, which includes swept-frequency signals, pulse-modulated signals, and field-distributed coupled signals.

[0007] The diamond NV color center array is used to detect the response of the excitation signal in the excitation signal library. The electron spin quantum state of the NV color center is controlled by microwave pulses, the ground state transition probability is measured and the time domain magnetic field signal is inverted. The time domain magnetic field signal is short-time Fourier transformed to generate the magnetic field fluctuation spectrum, and the characteristic resonant frequency point set corresponding to the microcrack is locked.

[0008] A Vietoris-Rips complex is constructed based on the characteristic resonant frequency set, and the persistent coherence characteristics are calculated to generate a lifecycle distribution graph. The defect risk index is calculated based on the Betti number of the lifecycle distribution graph, and high-risk chips with a defect risk index greater than 0.15 are screened out.

[0009] Traverse the list of high-risk chips, apply dynamic bias temperature stress to the high-risk chips, calculate the gate oxide trap density change rate through the electrothermal coupling effect, and screen out chips that meet the standards;

[0010] The excitation signal library, characteristic resonant frequency set, high-risk chips and standard-compliant chips are input into the deep deterministic policy gradient model for training. The test coverage and false positive rate are used as reward functions. The excitation combination weights, frequency band priorities and stress loading timing are optimized through interactive training, and the adaptive test strategy is finally output.

[0011] Preferably, the failure frequency distribution data of historically failed chips on the production line is used to solve the characteristic modes of Maxwell's equations using a three-dimensional finite-difference time-domain method, and the characteristic frequency set and its corresponding spatial electric field distribution are extracted by a finite element analysis method to generate an excitation signal library, which includes:

[0012] Obtain the frequency distribution data of failed chips from historical failure analysis reports on the production line. Based on electromagnetic field theory, establish the Maxwell eigenvalue equation for the transient electromagnetic field and obtain the electromagnetic field eigenmode of the chip under transient interference.

[0013] Based on the electromagnetic field eigenmode, finite element analysis was used to mesh the chip packaging structure, extracting multiple resonant frequency points of the chip in the range of 1MHz–3GHz, as well as the three-dimensional spatial field distribution corresponding to each resonant frequency point;

[0014] The characteristic frequency of the resonant frequency point is converted into a time domain signal, and combined with the three-dimensional spatial field distribution to generate a signal type, which is used as an excitation signal library. The excitation signal library includes swept frequency signal coverage of 1MHz-3GHz, spatial coupling methods based on three-dimensional spatial field distribution to adjust the signal, and various signal forms including single frequency, swept frequency, and pulse modulation.

[0015] Preferably, the diamond NV color center array is used to respond to and detect the excitation signal in the excitation signal library, the electron spin quantum state of the NV color center is regulated by microwave pulses, the ground state transition probability is measured and the time domain magnetic field signal is inverted, the time domain magnetic field signal is subjected to short-time Fourier transform to generate a magnetic field fluctuation spectrum, and the characteristic resonant frequency point set corresponding to the microcrack is locked, which includes:

[0016] Based on the excitation signal library, the quantum spin properties of diamond nitrogen vacancy color centers are utilized. By applying microwave pulses with a frequency of 12.5–18.5 GHz, the electron spin quantum state of the NV color center is controlled, driving its spin state to transition from the ground state to the excited state, forming a coherent superposition state of the NV color center array.

[0017] The fluorescence detection device is used to measure the proportion of NV color centers in the ground state in the array, calculate the ground state transition probability, and invert the time domain magnetic field signal based on the preset inversion formula;

[0018] The time-frequency analysis of the time-domain magnetic field signal was performed. The short-time Fourier transform was used to divide it into 50ns time windows and generate time-frequency spectrograms segment by segment. The time-frequency spectrograms were denoised by the Daubechies wavelet function to obtain the denoised time-frequency spectrograms.

[0019] The peak frequency point set that persists in the time-frequency spectrum after noise reduction is identified and output as the criterion for defect location, recorded as the characteristic resonance frequency point set, where the peak frequency points in the peak frequency point set correspond to the local resonance characteristics caused by chip microcracks.

[0020] Preferably, the steps of constructing a Vietoris-Rips complex based on a set of characteristic resonant frequency points, calculating the persistent coherence characteristics and generating a life cycle distribution graph, calculating a defect risk index based on the Betti number of the life cycle distribution graph, and screening out high-risk chips with a defect risk index greater than 0.15 include:

[0021] Based on a set of characteristic resonant frequency points, the frequency points are mapped to points in a high-dimensional space. Based on a preset point spacing threshold, adjacent points are connected to form a complex, thereby obtaining a topological structure model of the frequency point spatial correlation. By incrementally expanding the scale parameter in the topological structure model, the persistent homology characteristics of the complex in the one-dimensional homology group are calculated. At the same time, the generation and disappearance process of the ring topological structure is recorded, generating a raw data set containing the life cycle of each ring structure.

[0022] The generated raw data set is analyzed to extract the lifecycle distribution diagram of the one-dimensional ring topology characteristics associated with the defect frequency band in the characteristic resonant frequency point set. In the lifecycle distribution diagram, the horizontal axis represents the frequency point spacing scale parameter, and the vertical axis represents the persistence length of the ring structure. By quantifying the correlation between the persistence length and the frequency point density, a defect risk space mapping relationship is generated;

[0023] Based on the defect risk space mapping relationship, the number of Betti number rings in each frequency band is counted to obtain statistical results, and the defect risk index is calculated. High-risk chips with a defect risk index greater than 0.15 are screened and the corresponding list is output.

[0024] Preferably, the traversing the list of high-risk chips, applying dynamic bias temperature stress to the high-risk chips, calculating the gate oxide trap density change rate through the electrothermal coupling effect, and screening out chips that meet the standards, includes:

[0025] For a list of high-risk chips, dynamic bias temperature stress is applied, which involves alternating a drain-source voltage of 1200 V and a junction temperature of 175°C to simulate the electrothermal coupling effect under extreme working conditions and obtain electrothermal response data.

[0026] Based on the electrothermal response data, the electrothermal coupling effect is analyzed, and the key parameters related to the electrothermal coupling effect are extracted. Using the key parameters, the gate oxide trap density change rate is calculated through a preset model;

[0027] A threshold for the rate of change of gate oxide trap density is set, and failed chips whose rate of change exceeds the threshold are eliminated. Finally, a list of chips that have passed the reliability test is output to complete the final verification of the anti-electrical interference performance.

[0028] In a second aspect, the present application also provides a test and screening system for enhancing chip resistance to electrical interference, comprising:

[0029] Solution module: This module uses the three-dimensional finite-difference time-domain method to solve the characteristic modes of Maxwell's equations based on the failure frequency distribution data of historically failed chips on the production line. Finite element analysis is used to extract the characteristic frequency set and its corresponding spatial electric field distribution, generating an excitation signal library. The excitation signal library includes swept frequency signals, pulse modulation signals, and field distribution coupling signals.

[0030] Inversion calculation module: used to detect the response of the excitation signal in the excitation signal library using the diamond NV color center array, control the electron spin quantum state of the NV color center through microwave pulses, measure the ground state transition probability and invert the time domain magnetic field signal, perform short-time Fourier transform on the time domain magnetic field signal to generate the magnetic field fluctuation spectrum, and lock the characteristic resonant frequency point set corresponding to the microcrack;

[0031] The first calculation and screening module is used to construct a Vietoris-Rips complex based on the characteristic resonant frequency set, calculate the persistent coherence characteristics and generate a life cycle distribution diagram, calculate the defect risk index based on the Betti number of the life cycle distribution diagram, and screen out high-risk chips with a defect risk index greater than 0.15;

[0032] The second calculation and screening module is used to traverse the list of high-risk chips, apply dynamic bias temperature stress to the high-risk chips, calculate the gate oxide trap density change rate through the electrothermal coupling effect, and screen out chips that meet the standards;

[0033] Training module: This module is used to input the stimulus signal library, characteristic resonant frequency set, high-risk chips, and standard-compliant chips into the deep deterministic policy gradient model for training. The model uses test coverage and false positive rate as reward functions. Through interactive training, it optimizes the stimulus combination weights, frequency band priorities, and stress loading timing, ultimately outputting an adaptive test strategy.

[0034] In a third aspect, the present application further provides a test and screening device for enhancing chip resistance to electrical interference, comprising:

[0035] Memory for storing computer programs;

[0036] A processor is used to implement the steps of the test and screening method for enhancing chip resistance to electrical interference when executing the computer program.

[0037] In a fourth aspect, the present application further provides a readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the above-mentioned test screening method based on enhancing chip resistance to electrical interference are implemented.

[0038] The beneficial effects of the present invention are:

[0039] This paper proposes a chip testing method that integrates quantum sensing, topological data analysis and reinforcement learning. By constructing a multimodal excitation signal library to simulate the real electromagnetic environment, using a diamond NV color center array to realize magnetic field detection, combined with continuous coherence to quantify defect risks, and using a deep deterministic policy gradient model to dynamically optimize the test strategy, it breaks through the bandwidth and accuracy limitations of traditional technologies and realizes closed-loop control of the entire process from signal generation, defect location to strategy adaptation.

[0040] The quantum sensing technology of this invention breaks through the bandwidth limitation of traditional ATE, improves the frequency positioning accuracy, and enhances the micro-crack detection rate; the defect risk index based on topological data analysis reduces the misjudgment rate and solves the subjective bias problem of manual experience; the reinforcement learning model realizes adaptive adjustment of test parameters, shortens the test cycle, and supports real-time response to process fluctuations; the electrothermal coupling stress model accurately predicts the gate oxide trap density to ensure the long-term stability of the chip.

[0041] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the embodiments of the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0043] Figure 1 Schematic diagram of the process of the test and screening method for enhancing chip resistance to electrical interference according to an embodiment of the present invention;

[0044] Figure 2 Schematic diagram of the structure of a test and screening system for enhancing chip resistance to electrical interference according to an embodiment of the present invention;

[0045] Figure 3 Schematic diagram of the structure of the test and screening equipment for enhancing chip resistance to electrical interference described in an embodiment of the present invention.

[0046] In the figure: 701, solution module; 702, inversion calculation module; 703, first calculation and screening module; 704, second calculation and screening module; 705, training module; 800, test and screening equipment for enhancing chip resistance to electrical interference; 801, processor; 802, memory; 803, multimedia component; 804, I / O interface; 805, communication component. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0048] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are used only to distinguish the description and should not be understood as indicating or implying relative importance.

[0049] Embodiment 1:

[0050] This embodiment provides a test and screening method for enhancing a chip's resistance to electrical interference.

[0051] See also Figure 1 , the figure shows that the method includes step S100, step S200, step S300, step S400 and step S500.

[0052] S100. Based on the failure frequency distribution data of historically failed chips on the production line, the three-dimensional time-domain finite difference method is used to solve the characteristic modes of Maxwell's equations. The characteristic frequency set and its corresponding spatial electric field distribution are extracted through the finite element analysis method to generate an excitation signal library, which includes swept frequency signals, pulse modulation signals, and field distribution coupling signals.

[0053] It can be understood that step S100 includes steps S101, S102, and S103, wherein:

[0054] S101. Obtain the frequency distribution data of the failed chips from the historical failure analysis report of the production line. Based on electromagnetic field theory, establish the Maxwell eigenvalue equation of the transient electromagnetic field to obtain the electromagnetic field eigenmode of the chip under transient interference. The calculation formula is as follows:

[0055]

[0056] Where, is the curl operator, μ is the magnetic permeability, E n is the electric field distribution vector, is the characteristic angular frequency, is the dielectric constant;

[0057] S102. Based on the electromagnetic field eigenmode, use finite element analysis to mesh the chip packaging structure, extract multiple resonant frequency points of the chip in the range of 1 MHz to 3 GHz, and the three-dimensional spatial field distribution corresponding to each resonant frequency point;

[0058] S103. Convert the characteristic frequency of the resonant frequency point into a time domain signal, and combine it with the three-dimensional spatial field distribution to generate a signal type, and use the signal type as an excitation signal library, where the excitation signal library includes a swept frequency signal coverage of 1MHz-3GHz, a spatial coupling method for adjusting the signal based on the three-dimensional spatial field distribution, and a variety of signal forms including single frequency, swept frequency, and pulse modulation.

[0059] It should be noted that the data source is based on the frequency distribution data of at least 300 groups of failed chips extracted from the historical failure analysis report (FA Report) of the production line (such as the 300-500MHz range), and the three-dimensional time-domain finite difference method (3D-FDTD) is used to solve the Maxwell eigenvalue equation. The Yee grid algorithm sets a 10μm spatial resolution (matching a 3GHz wavelength) and a 0.1-1ps time step. The spatial grid resolution needs to match the minimum wavelength (such as 3GHz corresponds to a 10μm grid); and a perfectly matched layer (PML) absorption boundary is set to avoid reflection interference, and then the characteristic frequency is extracted by the Arnoldi iteration method. and electric field distribution E n; Perform finite element analysis using adaptive mesh encryption technology (chip edge encryption to 5μm); Use frequency response analysis to screen 1MHz-3GHz resonance peaks with Q factors greater than or equal to 50, that is, exclude pseudo modes with Q factors less than 50; and normalize the E n The field distribution is used to set the excitation signal parameters; the final generation includes 1MHz step frequency sweep (dwell 10μs), rise time less than 1ns rise pulse (simulating ESD) and ESD-based n A multi-modal excitation signal library for spatially coupled signals with field distribution. This step not only breaks through the 200MHz bandwidth limitation of traditional ATE and supports 3GHz transient interference simulation, but also optimizes signal coupling efficiency through electromagnetic field eigenvalue solutions, improving test sensitivity and compatibility with chip testing at different process nodes.

[0060] S200. Use the diamond NV color center array to respond to and detect the excitation signals in the excitation signal library, control the electron spin quantum state of the NV color center through microwave pulses, measure the ground state transition probability and invert the time domain magnetic field signal, perform short-time Fourier transform on the time domain magnetic field signal to generate a magnetic field fluctuation spectrum, and lock the characteristic resonant frequency point set corresponding to the microcrack.

[0061] It can be understood that step S200 includes steps S201, S202, S203, and S204, wherein:

[0062] S201. Based on the excitation signal library, the quantum spin properties of diamond nitrogen vacancy color centers are utilized to control the electron spin quantum state of the NV color center by applying microwave pulses with a frequency of 12.5–18.5 GHz, driving its spin state to transition from the ground state to the excited state, forming a coherent superposition state NV color center array;

[0063] It should be noted that chemical vapor deposition diamond is used to form NV color center density of 10¹ by ion implantation. 7 cm⁻³, and the spin state is controlled by a 12.5-18.5GHz Hahn echo sequence. These pulses can precisely control the electron spin quantum state of the NV color center, and use 532nm laser excitation and APD to detect the fluorescence intensity. Through the action of microwave pulses, the electron spin of the NV color center is driven to transition from the ground state (|0>) to the excited state (|1>), forming a coherent superposition state. This coherent superposition state is a key state in quantum computing and quantum sensing, and can be used for highly sensitive magnetic field detection. Diamond is prepared by chemical vapor deposition and ion implantation to form a high-density NV color center array in the diamond. This array structure can improve the intensity and uniformity of the signal, thereby improving the sensitivity of detection.

[0064] S202. Measure the ratio of the color centers in the ground state in the NV color center array by a fluorescence detection device, calculate the ground state transition probability, and invert the time domain magnetic field signal based on a preset inversion formula. The calculation formula of the preset inversion formula is as follows:

[0065]

[0066] Where B rf (t) is the inverted time domain magnetic field signal is the electron gyromagnetic ratio, is the integration time, is the ground state transition probability;

[0067] It should be noted that the fluorescence detection device is used to measure the proportion of NV color centers in the ground state (|0>). The NV color centers emit fluorescence of a specific wavelength when in the ground state. The proportion of ground state color centers can be determined by detecting the fluorescence intensity, and the ground state transition probability can be calculated based on the fluorescence detection results. , which reflects the probability of the NV color center transitioning from the ground state to the excited state under the action of the microwave pulse. Based on the inversion formula Acquire time domain magnetic field signals and be able to invert time domain magnetic field signals with high precision.

[0068] S203, performing time-frequency analysis on the time-domain magnetic field signal, dividing it into 50 ns time windows using short-time Fourier transform and generating time-frequency spectrograms segment by segment, and performing noise reduction processing on the time-frequency spectrogram using Daubechies wavelet function to obtain a noise-reduced time-frequency spectrogram;

[0069] It should be noted that after noise reduction using a Blackman-Harris window STFT (50ns window length) and Daubechies6 wavelet, a set of defect characteristic frequency points with an accuracy of ±1MHz is extracted, providing accurate data for subsequent spectrum analysis and enabling dynamic monitoring of the magnetic field signal. In this step, time-frequency analysis is performed on the inverted time-domain magnetic field signal. The short-time Fourier transform (STFT) is used to segment the signal into 50ns time windows, generating a time-frequency spectrum for each segment. This allows for simultaneous analysis of the signal's time and frequency domain characteristics, providing more comprehensive signal information. The Daubechies wavelet function is then used to perform noise reduction on the time-frequency spectrum, effectively removing noise from the signal while preserving its key characteristics.

[0070] S204, identifying a set of peak frequency points that persist in the time-frequency spectrum after noise reduction, and outputting the set of peak frequency points as a criterion for defect location, recorded as a characteristic resonance frequency point set, wherein the peak frequency points in the peak frequency point set correspond to the local resonance characteristics caused by chip microcracks.

[0071] It should be noted that in the denoised time-frequency spectrum, the identification of persistent peak frequency sets is intended to reflect the primary frequency components in the signal, which are closely related to the local resonance characteristics of the chip. The identified peak frequency sets are used as the criterion for defect location. These peak frequencies correspond to the local resonance characteristics caused by chip microcracks and can be used to accurately identify the location of defects in the chip. Finally, these peak frequencies are recorded as characteristic resonance frequency sets, which serve as the basis for subsequent defect location and analysis. This step can accurately locate defects such as microcracks in the chip, improve the accuracy of defect detection, and facilitate further research into the nature and impact of defects.

[0072] S300: Construct a Vietoris-Rips complex based on the characteristic resonant frequency set, calculate the persistent coherence characteristics and generate a life cycle distribution diagram, calculate the defect risk index based on the Betti number of the life cycle distribution diagram, and screen out high-risk chips with a defect risk index greater than 0.15.

[0073] It can be understood that step S300 includes S301, S302 and S303, wherein:

[0074] S301. Based on a set of characteristic resonant frequency points, the frequency points are mapped to points in a high-dimensional space. Adjacent points are connected according to a preset point spacing threshold to form a complex, thereby obtaining a topological structure model of the spatial correlation of the frequency points. By incrementally expanding the scale parameter in the topological structure model, the persistent homology characteristics of the complex in the one-dimensional homology group are calculated. The generation and disappearance processes of the ring topological structures are simultaneously recorded to generate a raw data set containing the life cycle of each ring structure.

[0075] It should be noted that the frequency point set is mapped to the metric space, and the distance function is defined as the frequency point spacing , where d is the distance function, f i is the first data point, f j For the second data point, calculate f i and f jThe absolute value of the difference between the two frequencies is used to obtain a non-negative distance metric. The initial value is set to 1MHz and gradually increased to the maximum frequency spacing (e.g., 500MHz), thereby constructing 1-simplexes (edges) and 2-simplexes (triangles), excluding isolated points. The generation and disappearance thresholds of each ring structure are recorded, and the persistence length is defined as the disappearance threshold minus the generation threshold. It can be understood that according to the preset point spacing threshold, adjacent points are connected to form a complex. The complex is a topological structure used to describe the connection relationship between points. The selection of the point spacing threshold is critical, as it determines which points are considered "adjacent." This threshold can be determined based on experimental data or theoretical analysis. By connecting adjacent points, a topological structure model of the spatial correlation of frequency points is formed, where the topological structure model describes the spatial relationship and interaction between frequency points.

[0076] S302. Analyze the generated raw data set to extract a lifecycle distribution diagram of the one-dimensional ring topology features associated with the defect frequency band in the characteristic resonant frequency set. In the lifecycle distribution diagram, the horizontal axis represents the frequency spacing scale parameter, and the vertical axis represents the persistence length of the ring structure. By quantifying the correlation between the persistence length and the frequency density, a defect risk space mapping relationship is generated.

[0077] It should be noted that in the defect frequency band, high-density areas (such as 300–400 MHz) usually correspond to short-persistence ring structures (transient interference), and low-density areas correspond to long-persistence structures (stable defects). Then, the Python Persim library can be used to generate a life cycle distribution diagram, where the life cycle distribution diagram intuitively reveals the defect stability and supports quick decision-making.

[0078] It can be understood that this step generates a spatial mapping of defect risk by quantifying the correlation between persistence length and frequency density. This mapping can link the topological characteristics of the frequency points with defect risk. The longer the persistence length, the more stable the ring structure and the more severe the defect. When analyzing the topological structure model, the scale parameter in the model is first incrementally expanded. This process is to gradually adjust the resolution of the model to observe the topological characteristics of the data set in more detail. On this basis, the persistent homology characteristics of the complex in the one-dimensional homology group are calculated. Among them, persistent homology is used to analyze the topological structure of the data set, which can accurately capture the ring structure in the data. The appearance and disappearance of these ring structures are recorded in detail, and then a raw data set containing the life cycle of each ring structure is generated. The so-called life cycle refers to the time span from the generation to the final disappearance of the ring structure.

[0079] S303: Based on the defect risk space mapping relationship, the number of Betti number rings in each frequency band is counted to obtain statistical results, and the defect risk index is calculated. High-risk chips with a defect risk index greater than 0.15 are screened out and a corresponding list is output. The calculation formula is as follows:

[0080]

[0081] Where, is the defect risk index, is the persistent sum of the topological characteristics of the one-dimensional homology group ring, card(f d ) is the number of frequency points in the characteristic resonant frequency point set.

[0082] It should be noted that the characteristic frequency points were mapped to the metric space, the Vietoris-Rips complex (ε=1-500MHz) was constructed, the continuous coherence was calculated to generate the life cycle distribution diagram, the Betti number was counted in the 50MHz frequency band, and the ROC curve was used to determine the risk threshold of η>0.15 (AUC=0.92) to screen high-risk chips.

[0083] It can be understood that based on the defect risk space mapping relationship, the number of rings of the Betti numbers in each frequency band is counted. By counting the Betti numbers, the number of ring structures in each frequency band can be quantified, thereby evaluating the defect risk; high-risk chips with a defect risk index greater than 0.15 are screened out, and the corresponding list is output. This threshold can be adjusted according to the needs of actual applications to ensure the accuracy and reliability of the screening results.

[0084] S400, traverse the list of high-risk chips, apply dynamic bias temperature stress to the high-risk chips, calculate the gate oxide trap density change rate through the electrothermal coupling effect, and screen out chips that meet the standards.

[0085] It can be understood that step S400 includes S401, S402 and S403, wherein:

[0086] S401. Apply dynamic bias temperature stress to the high-risk chips, including alternating 1200 V drain-source voltage and 175°C junction temperature to simulate the electrothermal coupling effect under extreme working conditions and obtain electrothermal response data.

[0087] It's important to note that using 1200V / 10μs (rise time <1ns) stimulates the gate oxide tunneling effect, simulating chip operation at high voltage. This high voltage can induce a strong electric field effect, potentially leading to electrical breakdown or trap state formation. Using 175°C / 1ms (controlled via a closed-loop thermocouple) accelerates ion mobility, simulating chip operation at high temperatures. This also accelerates material degradation and trap state formation, impacting chip performance. By alternating high voltage and high temperature, we simulate the dynamic stress conditions that chips may encounter in real-world applications, more realistically reflecting chip performance changes under complex environments. In this step, applying dynamic bias temperature stress simulates these complex electrothermal coupling effects, thereby acquiring electrothermal response data.

[0088] S402: Analyze the electrothermal coupling effect based on the electrothermal response data, extract key parameters related to the electrothermal coupling effect, and calculate the gate oxide trap density change rate using a preset model using the key parameters. The calculation formula is as follows:

[0089]

[0090] in, is the gate oxide trap density change rate, A is the material constant, E a is the activation energy of trap generation, m is the voltage index, T j is the junction temperature, k is the Boltzmann constant, V GS To quantize the voltage bias, V th is the threshold voltage;

[0091] S403 , setting a threshold value for the rate of change of gate oxide trap density, eliminating failed chips whose rate of change exceeds the threshold, and finally outputting a list of chips that have passed the reliability test, thus completing the final verification of the anti-electrical interference performance.

[0092] It should be noted that the acquired electrothermal response data is analyzed in detail to extract key parameters related to the electrothermal coupling effect. These parameters may include electric field strength, temperature distribution, current density, etc. The extracted key parameters are used to describe the characteristics of the electrothermal coupling effect. They set the threshold of the gate oxide trap density change rate to determine whether the chip meets the reliability requirements. The selection of the threshold should be based on the needs of the actual application and the reliability standard. For example, the threshold can be set to 0.15, indicating that when the gate oxide trap density change rate exceeds 15%, the chip is considered to have a high risk of failure. In this step, based on the calculated gate oxide trap density change rate, failed chips with a change rate exceeding the threshold are eliminated. Eliminating failed chips can ensure that the chips in the final output chip list have high reliability. The final output is a list of chips that have passed the reliability test, completing the final verification of the anti-electrical interference performance. These chips can work normally under extreme working conditions, that is, they meet the reliability requirements.

[0093] S500: Input the excitation signal library, characteristic resonant frequency set, high-risk chips and standard-compliant chips into the deep deterministic policy gradient model for training. With test coverage and false positive rate as reward functions, the model optimizes the excitation combination weights, frequency band priority and stress loading timing through interactive training, and finally outputs an adaptive test strategy.

[0094] It can be understood that the excitation signal library parameters generated in step S100, the characteristic resonant frequency point set output in step S200, the high-risk chip list screened in step 300, and the reliability test results in step S400 are input into the deep deterministic policy gradient model to construct a multidimensional state space including frequency weights, field distribution coupling coefficients, and stress time series; with test coverage and false positive rate False_Rate as optimization targets, the reward function is defined R =0.7⋅Coverage−0.3⋅False_Rate, and update the policy parameters through interactive training of the Actor-Critic network, where:

[0095]

[0096] Among them, Coverage is the test coverage, False - Rate is the misjudgment rate.

[0097] Based on the converged strategy network, the optimal test parameter combination is output, including the stimulus signal weight distribution { wk}( k =1,2,..., n ), defective frequency band priority sequence ( i =1,2,..., m ) and dynamic stress loading sequence , to achieve closed-loop optimization of the testing process.

[0098] Example 2:

[0099] like Figure 2 As shown, this embodiment provides a test and screening system for enhancing chip resistance to electrical interference, see Figure 2 The system comprises:

[0100] Solution module 701: Used to solve the characteristic modes of Maxwell's equations using the three-dimensional finite-difference time-domain method based on the failure frequency distribution data of historically failed chips on the production line. Finite element analysis is used to extract the characteristic frequency set and its corresponding spatial electric field distribution to generate an excitation signal library. The excitation signal library includes swept frequency signals, pulse modulation signals, and field distribution coupling signals.

[0101] Inversion calculation module 702: used to detect the response of the excitation signal in the excitation signal library using the diamond NV color center array, control the electron spin quantum state of the NV color center through microwave pulses, measure the ground state transition probability and invert the time domain magnetic field signal, perform short-time Fourier transform on the time domain magnetic field signal to generate the magnetic field fluctuation spectrum, and locate the characteristic resonant frequency point set corresponding to the microcrack;

[0102] The first calculation and screening module 703 is used to construct a Vietoris-Rips complex based on the characteristic resonant frequency set, calculate the persistent coherence characteristics and generate a life cycle distribution diagram, calculate the defect risk index based on the Betti number of the life cycle distribution diagram, and screen out high-risk chips with a defect risk index greater than 0.15;

[0103] The second calculation and screening module 704 is used to traverse the list of high-risk chips, apply dynamic bias temperature stress to the high-risk chips, calculate the gate oxide trap density change rate through the electrothermal coupling effect, and screen out chips that meet the standards;

[0104] Training module 705: used to input the excitation signal library, characteristic resonant frequency set, high-risk chips and standard-compliant chips into the deep deterministic policy gradient model for training, using test coverage and false positive rate as reward functions, and optimizing the excitation combination weights, frequency band priorities and stress loading timing through interactive training, and finally outputting an adaptive test strategy.

[0105] Specifically, the solution module 701 includes:

[0106] Establishment unit: This unit is used to obtain the frequency distribution data of failed chips in the historical failure analysis report of the production line. Based on electromagnetic field theory, the Maxwell eigenvalue equation of the transient electromagnetic field is established to obtain the electromagnetic field eigenmode of the chip under transient interference. The calculation formula is as follows:

[0107]

[0108] Where, is the curl operator, μ is the magnetic permeability, E n is the electric field distribution vector, is the characteristic angular frequency, is the dielectric constant;

[0109] The first extraction unit is used to mesh the chip packaging structure using finite element analysis based on the electromagnetic field eigenmode, extract multiple resonance frequency points of the chip in the range of 1MHz-3GHz, and the three-dimensional spatial field distribution corresponding to each resonance frequency point;

[0110] Generation unit: used to convert the characteristic frequency of the resonant frequency point into a time domain signal, and generate a signal type based on the three-dimensional spatial field distribution, and use the signal type as an excitation signal library. The excitation signal library includes a swept frequency signal coverage of 1MHz-3GHz, a spatial coupling method for adjusting the signal based on the three-dimensional spatial field distribution, and a variety of signal forms including single frequency, swept frequency, and pulse modulation.

[0111] Specifically, the inversion calculation module 702 includes:

[0112] Control drive unit: Based on the excitation signal library, it uses the quantum spin properties of diamond nitrogen vacancy color centers to control the electron spin quantum state of the NV color center by applying microwave pulses with a frequency of 12.5–18.5 GHz, driving its spin state to transition from the ground state to the excited state, forming a coherent superposition state NV color center array;

[0113] The calculation inversion unit is used to measure the ratio of the NV color center array in the ground state through the fluorescence detection device, calculate the ground state transition probability, and invert the time domain magnetic field signal based on the preset inversion formula. The calculation formula of the preset inversion formula is as follows:

[0114]

[0115] Where B rf (t) is the inverted time domain magnetic field signal, is the electron gyromagnetic ratio, is the integration time, is the ground state transition probability;

[0116] The first analysis unit is used to perform time-frequency analysis on the time-domain magnetic field signal, divide it into 50ns time windows using short-time Fourier transform and generate time-frequency spectrograms segment by segment, and perform noise reduction processing on the time-frequency spectrogram using Daubechies wavelet function to obtain the noise-reduced time-frequency spectrogram;

[0117] Identification unit: It is used to identify the peak frequency point set that persists in the time-frequency spectrum after noise reduction, and output the peak frequency point set as the judgment standard for defect location, recorded as the characteristic resonance frequency point set, where the peak frequency points in the peak frequency point set correspond to the local resonance characteristics caused by chip microcracks.

[0118] Specifically, the first calculation and screening module 703 includes:

[0119] A first obtaining unit is configured to map the frequency points into points in a high-dimensional space based on a set of characteristic resonant frequency points, connect adjacent points to form a complex according to a preset point spacing threshold, and thereby obtain a topological structure model of the spatial correlation of the frequency points. By incrementally expanding the scale parameter in the topological structure model, the persistent homology characteristics of the complex in the one-dimensional homology group are calculated, and the generation and disappearance process of the ring topological structure is recorded to generate a raw data set containing the life cycle of each ring structure.

[0120] The second extraction unit is used to analyze the generated raw data set and extract the life cycle distribution diagram of the one-dimensional ring topology characteristics associated with the defect frequency band in the characteristic resonant frequency point set. In the life cycle distribution diagram, the horizontal axis represents the frequency point spacing scale parameter, and the vertical axis represents the persistence length of the ring structure. By quantifying the correlation between the persistence length and the frequency point density, a defect risk space mapping relationship is generated;

[0121] Statistics unit: Based on the defect risk space mapping relationship, it counts the number of Betti number rings in each frequency band, obtains statistical results, calculates the defect risk index, screens out high-risk chips with a defect risk index greater than 0.15, and outputs the corresponding list. The calculation formula is as follows:

[0122]

[0123] Where, is the defect risk index, is the persistent sum of the topological characteristics of the one-dimensional homology group ring, card(f d ) is the number of frequency points in the characteristic resonant frequency point set.

[0124] Specifically, the second calculation and screening module 704 includes:

[0125] The second acquisition unit is used to apply dynamic bias temperature stress to a list of high-risk chips. This includes alternating between a drain-source voltage of 1200 V and a junction temperature of 175°C to simulate the electrothermal coupling effect under extreme working conditions, thereby obtaining electrothermal response data.

[0126] The second analysis unit is used to analyze the electrothermal coupling effect based on the electrothermal response data, extract key parameters related to the electrothermal coupling effect, and use the key parameters to calculate the gate oxide trap density change rate through a preset model. The calculation formula is as follows:

[0127]

[0128] in, is the gate oxide trap density change rate, A is the material constant, E a is the activation energy of trap generation, m is the voltage index, Tj is the junction temperature, k is the Boltzmann constant, V GS To quantize the voltage bias, V th is the threshold voltage;

[0129] Rejection unit: used to set the threshold of the change rate of gate oxide trap density, remove failed chips whose change rate exceeds the threshold, and finally output a list of chips that have passed the reliability test to complete the final verification of the anti-electrical interference performance.

[0130] It should be noted that, regarding the system in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated on here.

[0131] Example 3:

[0132] Corresponding to the above method embodiment, this embodiment also provides a test screening device for enhancing the chip's resistance to electrical interference. The test screening device for enhancing the chip's resistance to electrical interference described below and the test screening method for enhancing the chip's resistance to electrical interference described above can be referenced to each other.

[0133] Figure 3 FIG. 8 is a block diagram of a test and screening device 800 for enhancing chip resistance to electrical interference according to an exemplary embodiment. Figure 3 As shown, the test and screening device 800 for enhancing chip electrical interference resistance includes: a processor 801 and a memory 802. The test and screening device 800 for enhancing chip electrical interference resistance also includes one or more of a multimedia component 803, an I / O interface 804, and a communication component 805.

[0134] The processor 801 is used to control the overall operation of the test and screening device 800 for enhancing chip resistance to electrical interference, so as to complete all or part of the steps in the above-mentioned test and screening method for enhancing chip resistance to electrical interference. The memory 802 is used to store various types of data to support the operation of the test and screening device 800 for enhancing chip resistance to electrical interference. Such data may include, for example, instructions for any application or method operating on the test and screening device 800 for enhancing chip resistance to electrical interference, as well as application-related data, such as contact data, sent and received messages, pictures, audio, video, etc. The memory 802 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The multimedia component 803 may include a screen and an audio component. The screen may be, for example, a touch screen, and the audio component is used to output and / or input audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signal may be further stored in the memory 802 or transmitted via the communication component 805. The audio component also includes at least one speaker for outputting audio signals. The I / O interface 804 provides an interface between the processor 801 and other interface modules, and the above-mentioned other interface modules can be a keyboard, a mouse or buttons, etc. These buttons can be virtual buttons or physical buttons. The communication component 805 is used for wired or wireless communication between the test screening device 800 for enhancing the anti-electrical interference of the chip and other devices. Wireless communication, such as Wi-Fi, Bluetooth, near field communication (NFC), 2G, 3G or 4G, or a combination of one or more of them, so the corresponding communication component 805 may include: a Wi-Fi module, a Bluetooth module or an NFC module.

[0135] In an exemplary embodiment, the test and screening device 800 for enhancing the chip's resistance to electrical interference can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components to perform the above-mentioned test and screening method for enhancing the chip's resistance to electrical interference.

[0136] In another exemplary embodiment, a computer-readable storage medium including program instructions is further provided. When executed by a processor, the program instructions implement the steps of the aforementioned method for testing and screening enhanced chip electrical interference resistance. For example, the computer-readable storage medium may be the aforementioned memory 802 including the program instructions. The program instructions may be executed by the processor 801 of the device 800 for testing and screening enhanced chip electrical interference resistance to perform the aforementioned method for testing and screening enhanced chip electrical interference resistance.

[0137] Example 4:

[0138] Corresponding to the above method embodiment, this embodiment further provides a readable storage medium. The readable storage medium described below and the test screening method for enhancing chip resistance to electrical interference described above can refer to each other.

[0139] A computer program is stored on the readable storage medium. When the computer program is executed by the processor, the steps of the test and screening method for enhancing chip resistance to electrical interference of the above method embodiment are implemented.

[0140] The readable storage medium may specifically be any readable storage medium that can store program code, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0141] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

[0142] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A test and screening method for enhancing chip resistance to electrical interference, characterized in that: include: Based on the failure frequency distribution data of historically failed chips on the production line, the eigenmodes of Maxwell's equations are solved using the three-dimensional finite-difference time-domain method. The finite element analysis method is then used to extract the set of eigenfrequencies and their corresponding spatial electric field distributions. This generates an excitation signal library, which includes swept-frequency signals, pulse-modulated signals, and field-distributed coupled signals. The diamond NV color center array is used to detect the response of the excitation signal in the excitation signal library. The electron spin quantum state of the NV color center is controlled by microwave pulses, the ground state transition probability is measured and the time domain magnetic field signal is inverted. The time domain magnetic field signal is short-time Fourier transformed to generate the magnetic field fluctuation spectrum, and the characteristic resonant frequency point set corresponding to the microcrack is locked. A Vietoris-Rips complex is constructed based on the characteristic resonant frequency set, and the persistent coherence characteristics are calculated to generate a lifecycle distribution graph. The defect risk index is calculated based on the Betti number of the lifecycle distribution graph, and high-risk chips with a defect risk index greater than 0.15 are screened out. Traverse the list of high-risk chips, apply dynamic bias temperature stress to the high-risk chips, calculate the gate oxide trap density change rate through the electrothermal coupling effect, and screen out chips that meet the standards; The stimulus signal library, characteristic resonant frequency set, high-risk chips, and standard-compliant chips are input into a deep deterministic policy gradient model for training. Using test coverage and false positive rate as reward functions, the model optimizes stimulus combination weights, frequency band priorities, and stress loading timing through interactive training, ultimately outputting an adaptive test strategy. The steps of constructing a Vietoris-Rips complex based on a set of characteristic resonant frequency points, calculating the persistent coherence characteristics and generating a lifecycle distribution graph, calculating a defect risk index based on the Betti number of the lifecycle distribution graph, and screening out high-risk chips with a defect risk index greater than 0.15 include: Based on a set of characteristic resonant frequency points, the frequency points are mapped to points in a high-dimensional space. Based on a preset point spacing threshold, adjacent points are connected to form a complex, thereby obtaining a topological structure model of the frequency point spatial correlation. By incrementally expanding the scale parameter in the topological structure model, the persistent homology characteristics of the complex in the one-dimensional homology group are calculated. At the same time, the generation and disappearance process of the ring topological structure is recorded, generating a raw data set containing the life cycle of each ring structure. The generated raw data set is analyzed to extract the lifecycle distribution diagram of the one-dimensional ring topology characteristics associated with the defect frequency band in the characteristic resonant frequency point set. In the lifecycle distribution diagram, the horizontal axis represents the frequency point spacing scale parameter, and the vertical axis represents the persistence length of the ring structure. By quantifying the correlation between the persistence length and the frequency point density, a defect risk space mapping relationship is generated; Based on the defect risk space mapping relationship, the number of Betti number rings in each frequency band is counted to obtain the statistical results, and the defect risk index is calculated. High-risk chips with a defect risk index greater than 0.15 are screened out and the corresponding list is output. The calculation formula is as follows: Where, is the defect risk index, is the persistent sum of the topological characteristics of the one-dimensional homology group ring, card(f d ) is the number of frequency points in the characteristic resonant frequency point set.

2. The method for testing and screening chips to enhance their electrical interference resistance according to claim 1, characterized in that: Based on the failure frequency distribution data of historically failed chips on the production line, the three-dimensional finite-difference time-domain method is used to solve the characteristic modes of Maxwell's equations. The finite element analysis method is used to extract the characteristic frequency set and its corresponding spatial electric field distribution to generate an excitation signal library, which includes: Obtain the frequency distribution data of failed chips from the historical failure analysis report of the production line. Based on electromagnetic field theory, establish the Maxwell eigenvalue equation of the transient electromagnetic field and obtain the electromagnetic field eigenmode of the chip under transient interference. The calculation formula is as follows: Where, is the curl operator, μ is the magnetic permeability, E n is the electric field distribution vector, is the characteristic angular frequency, is the dielectric constant; Based on the electromagnetic field eigenmode, finite element analysis was used to mesh the chip packaging structure, extracting multiple resonant frequency points of the chip in the range of 1MHz–3GHz, as well as the three-dimensional spatial field distribution corresponding to each resonant frequency point; The characteristic frequency of the resonant frequency point is converted into a time domain signal, and combined with the three-dimensional spatial field distribution to generate a signal type, which is used as an excitation signal library. The excitation signal library includes swept frequency signal coverage of 1MHz-3GHz, spatial coupling methods based on three-dimensional spatial field distribution to adjust the signal, and various signal forms including single frequency, swept frequency, and pulse modulation.

3. The method for testing and screening chips to enhance their electrical interference resistance according to claim 1, wherein: The diamond NV color center array is used to respond to and detect the excitation signal in the excitation signal library, and the electron spin quantum state of the NV color center is controlled by microwave pulses. The ground state transition probability is measured and the time domain magnetic field signal is inverted. The time domain magnetic field signal is subjected to short-time Fourier transform to generate a magnetic field fluctuation spectrum, and the characteristic resonant frequency point set corresponding to the microcrack is locked, which includes: Based on the excitation signal library, the quantum spin properties of diamond nitrogen vacancy color centers are utilized. By applying microwave pulses with a frequency of 12.5–18.5 GHz, the electron spin quantum state of the NV color center is controlled, driving its spin state to transition from the ground state to the excited state, forming a coherent superposition state of the NV color center array. The ratio of the color centers in the ground state in the NV color center array is measured by a fluorescence detection device, the ground state transition probability is calculated, and the time domain magnetic field signal is inverted based on a preset inversion formula. The calculation formula of the preset inversion formula is as follows: Where B rf (t) is the inverted time domain magnetic field signal is the electron gyromagnetic ratio, is the integration time, is the ground state transition probability; The time-frequency analysis of the time-domain magnetic field signal was performed. The short-time Fourier transform was used to divide it into 50ns time windows and generate time-frequency spectrograms segment by segment. The time-frequency spectrograms were denoised by the Daubechies wavelet function to obtain the denoised time-frequency spectrograms. The peak frequency point set that persists in the time-frequency spectrum after noise reduction is identified and output as the criterion for defect location, recorded as the characteristic resonance frequency point set, where the peak frequency points in the peak frequency point set correspond to the local resonance characteristics caused by chip microcracks.

4. The method for testing and screening chips to enhance their electrical interference resistance according to claim 1, wherein: The method traverses the list of high-risk chips, applies dynamic bias temperature stress to the high-risk chips, calculates the gate oxide trap density change rate through the electrothermal coupling effect, and screens out chips that meet the standards, including: For a list of high-risk chips, dynamic bias temperature stress is applied, which involves alternating a drain-source voltage of 1200 V and a junction temperature of 175°C to simulate the electrothermal coupling effect under extreme working conditions and obtain electrothermal response data. Based on the electrothermal response data, the electrothermal coupling effect is analyzed, and the key parameters related to the electrothermal coupling effect are extracted. Using the key parameters, the gate oxide trap density change rate is calculated through a preset model. The calculation formula is as follows: in, is the gate oxide trap density change rate, A is the material constant, E a is the activation energy of trap generation, m is the voltage index, T j is the junction temperature, k is the Boltzmann constant, V GS To quantize the voltage bias, V th is the threshold voltage; A threshold for the rate of change of gate oxide trap density is set, and failed chips whose rate of change exceeds the threshold are eliminated. Finally, a list of chips that have passed the reliability test is output to complete the final verification of the anti-electrical interference performance.

5. A test and screening system for enhancing chip resistance to electrical interference, based on the test and screening method for enhancing chip resistance to electrical interference according to claim 1, characterized in that: include: Solution module: This module uses the three-dimensional finite-difference time-domain method to solve the characteristic modes of Maxwell's equations based on the failure frequency distribution data of historically failed chips on the production line. Finite element analysis is used to extract the characteristic frequency set and its corresponding spatial electric field distribution, generating an excitation signal library. The excitation signal library includes swept frequency signals, pulse modulation signals, and field distribution coupling signals. Inversion calculation module: used to detect the response of the excitation signal in the excitation signal library using the diamond NV color center array, control the electron spin quantum state of the NV color center through microwave pulses, measure the ground state transition probability and invert the time domain magnetic field signal, perform short-time Fourier transform on the time domain magnetic field signal to generate the magnetic field fluctuation spectrum, and lock the characteristic resonant frequency point set corresponding to the microcrack; The first calculation and screening module is used to construct a Vietoris-Rips complex based on the characteristic resonant frequency set, calculate the persistent coherence characteristics and generate a life cycle distribution diagram, calculate the defect risk index based on the Betti number of the life cycle distribution diagram, and screen out high-risk chips with a defect risk index greater than 0.15; The second calculation and screening module is used to traverse the list of high-risk chips, apply dynamic bias temperature stress to the high-risk chips, calculate the gate oxide trap density change rate through the electrothermal coupling effect, and screen out chips that meet the standards; Training module: This module inputs the stimulus signal library, characteristic resonant frequency set, high-risk chips, and standard-compliant chips into a deep deterministic policy gradient model for training. Using test coverage and false positive rate as reward functions, the model optimizes stimulus combination weights, frequency band priorities, and stress loading timing through interactive training, ultimately outputting an adaptive test strategy. Wherein, the first calculation and screening module includes: A first obtaining unit is configured to map the frequency points into points in a high-dimensional space based on a set of characteristic resonant frequency points, connect adjacent points to form a complex according to a preset point spacing threshold, and thereby obtain a topological structure model of the spatial correlation of the frequency points. By incrementally expanding the scale parameter in the topological structure model, the persistent homology characteristics of the complex in the one-dimensional homology group are calculated, and the generation and disappearance process of the ring topological structure is recorded to generate a raw data set containing the life cycle of each ring structure. The second extraction unit is used to analyze the generated raw data set and extract the life cycle distribution diagram of the one-dimensional ring topology characteristics associated with the defect frequency band in the characteristic resonant frequency point set. In the life cycle distribution diagram, the horizontal axis represents the frequency point spacing scale parameter, and the vertical axis represents the persistence length of the ring structure. By quantifying the correlation between the persistence length and the frequency point density, a defect risk space mapping relationship is generated; Statistics unit: Based on the defect risk space mapping relationship, it counts the number of Betti number rings in each frequency band, obtains statistical results, calculates the defect risk index, screens out high-risk chips with a defect risk index greater than 0.15, and outputs the corresponding list. The calculation formula is as follows: Where, is the defect risk index, is the persistent sum of the topological characteristics of the one-dimensional homology group ring, card(f d ) is the number of frequency points in the characteristic resonant frequency point set.

6. The test and screening system for enhancing chip resistance to electrical interference according to claim 5, characterized in that: The solution module includes: Establishment unit: This unit is used to obtain the frequency distribution data of failed chips in the historical failure analysis report of the production line. Based on electromagnetic field theory, the Maxwell eigenvalue equation of the transient electromagnetic field is established to obtain the electromagnetic field eigenmode of the chip under transient interference. The calculation formula is as follows: Where, is the curl operator, μ is the magnetic permeability, E n is the electric field distribution vector, is the characteristic angular frequency, is the dielectric constant; The first extraction unit is used to mesh the chip packaging structure using finite element analysis based on the electromagnetic field eigenmode, extract multiple resonance frequency points of the chip in the range of 1MHz-3GHz, and the three-dimensional spatial field distribution corresponding to each resonance frequency point; Generation unit: used to convert the characteristic frequency of the resonant frequency point into a time domain signal, and generate a signal type based on the three-dimensional spatial field distribution, and use the signal type as an excitation signal library. The excitation signal library includes a swept frequency signal coverage of 1MHz-3GHz, a spatial coupling method for adjusting the signal based on the three-dimensional spatial field distribution, and a variety of signal forms including single frequency, swept frequency, and pulse modulation.

7. The test and screening system for enhancing chip resistance to electrical interference according to claim 5, characterized in that: The inversion calculation module includes: Control drive unit: Based on the excitation signal library, it uses the quantum spin properties of diamond nitrogen vacancy color centers to control the electron spin quantum state of the NV color center by applying microwave pulses with a frequency of 12.5–18.5 GHz, driving its spin state to transition from the ground state to the excited state, forming a coherent superposition state NV color center array; The calculation inversion unit is used to measure the ratio of the NV color center array in the ground state through the fluorescence detection device, calculate the ground state transition probability, and invert the time domain magnetic field signal based on the preset inversion formula. The calculation formula of the preset inversion formula is as follows: Where B rf (t) is the inverted time domain magnetic field signal, is the electron gyromagnetic ratio, is the integration time, is the ground state transition probability; The first analysis unit is used to perform time-frequency analysis on the time-domain magnetic field signal, divide it into 50ns time windows using short-time Fourier transform and generate time-frequency spectrograms segment by segment, and perform noise reduction processing on the time-frequency spectrogram using Daubechies wavelet function to obtain the noise-reduced time-frequency spectrogram; Identification unit: It is used to identify the peak frequency point set that persists in the time-frequency spectrum after noise reduction, and output the peak frequency point set as the judgment standard for defect location, recorded as the characteristic resonance frequency point set, where the peak frequency points in the peak frequency point set correspond to the local resonance characteristics caused by chip microcracks.

8. The test and screening system for enhancing chip resistance to electrical interference according to claim 5, characterized in that: The second calculation and screening module includes: The second acquisition unit is used to apply dynamic bias temperature stress to a list of high-risk chips. This includes alternating between a drain-source voltage of 1200 V and a junction temperature of 175°C to simulate the electrothermal coupling effect under extreme working conditions, thereby obtaining electrothermal response data. The second analysis unit is used to analyze the electrothermal coupling effect based on the electrothermal response data, extract key parameters related to the electrothermal coupling effect, and use the key parameters to calculate the gate oxide trap density change rate through a preset model. The calculation formula is as follows: in, is the gate oxide trap density change rate, A is the material constant, E a is the activation energy of trap generation, m is the voltage index, T j is the junction temperature, k is the Boltzmann constant, V GS To quantize the voltage bias, V th is the threshold voltage; Rejection unit: used to set the threshold of the change rate of gate oxide trap density, remove failed chips whose change rate exceeds the threshold, and finally output a list of chips that have passed the reliability test to complete the final verification of the anti-electrical interference performance.

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