Electrophoretic display

Abstract

The invention provides an electrophoretic display. The electrophoretic display comprises a pixel control array comprising a plurality of pixel units; a gate control circuit is electrically connected to the pixel control array. The grid control circuit comprises a plurality of grid driving circuit groups, and one grid driving circuit group comprises a plurality of grid driving circuits. The gate driving circuit comprises a gate thin film transistor, and the output end of the gate driving circuit is connected to a gate line of the pixel control array; a plurality of control signal lines, wherein one control signal line is connected to the input end of one gate drive circuit of one gate drive circuit group; and a plurality of gate driving circuit group enabling lines, wherein one gate driving circuit group enabling line is connected to the enabling control points of the plurality of gate driving circuits of one gate driving circuit group.

Description

Technical Field

[0001] The present invention relates to an electrophoretic display, and more particularly to an electrophoretic display with a narrow border. Background Art

[0002] An ideal electronic paper is thin, light, easy to carry, low power consumption, and can be curled; moreover, the electronic paper has the characteristic of retaining the image after the power is turned off, so the electronic paper industry has been widely used in books, labels, posters, bulletin boards and other applications. In the past, various electronic paper technologies that can achieve this goal have been proposed, such as: quick response liquid powder display, cholesteric liquid crystal display, etc. However, based on the system integration practice considerations such as the display quality of the image, the design complexity of the electronic drive system, and the mass production stability, the electrophoretic display (EPD) is still the mainstream at present.

[0003] Most of the electronic paper products sold on the market now are basically based on electrophoretic materials as the display medium, and are combined with a thin-film transistor (TFT) substrate to form a display matrix panel. Since the electrophoretic material film itself is flexible, if it can be combined with a flexible TFT substrate, the flexible electronic paper can achieve the goal of free curling.

[0004] See Figure 1A and 1B , to illustrate the control architecture of the display signal of the existing electrophoretic display. As Figure 1A shown, the existing electrophoretic display 10A includes a substrate 20A and a pixel control array 30A. According to the required display resolution, the pixel control array 30A has a plurality of pixel units, such as X*Y (300*400) pixel units. This existing electrophoretic display 10A also includes a gate control circuit board 40A and a data control circuit board 50A. The gate control circuit board 40A includes, for example, N driving modules 42A, and each driving module 42A includes a gate driving IC 42B. Each gate driving IC (gate driving integrated circuit) 42B can output M gate driving signals so that the N driving modules 42A can provide all the gate driving signals, that is, M*N = Y. Furthermore, the data control circuit board 50A includes a plurality of data driving modules 51A, and each data driving module 51A includes a data driving IC (data driving integrated circuit) 52A. The sum of all the data driving ICs 52A can output X data signals to control the display data on the X*Y pixel units of the pixel control array 30A.

[0005] See alsoFigure 1B , due to the cumbersome driver program of electronic paper, which is not conducive to the traditional thin-film transistor circuit design, gate driver ICs are generally used for control. Usually, the chip on film (COF) packaging method is used to adhere the driver IC to the flexible substrate, increasing the cost of the driver IC. Moreover, the COF process of multiple driver ICs and the thermocompression bonding process between the driver module and the electrophoretic display will affect the overall yield performance and significantly increase the cost. The gate driver IC 42B on each gate driver module 42A includes a shift register 43A, a latch register 44A, a level shift 45A, and an output signal selection switch group (Switch) 46A to convert the input signal into M gate driving signals. Summary of the Invention

[0006] The present invention provides an electrophoretic display to save the gate driver IC, eliminate the yield loss caused by the thermocompression bonding process between the driver IC module and the electrophoretic display, and facilitate the production of a narrow-bezel electrophoretic display.

[0007] To achieve the above object, the present invention provides an electrophoretic display, comprising:

[0008] a substrate having a first surface and a second surface;

[0009] a pixel control array disposed on the second surface and comprising:

[0010] a plurality of pixel units, at least one of the pixel units comprising a pixel thin-film transistor, a storage capacitor, and a pixel electrode;

[0011] a plurality of gate lines, at least one of the gate lines connected to the gates of the pixel thin-film transistors of the plurality of pixel units;

[0012] a plurality of data lines, at least one of the data lines connected to the sources or drains of the pixel thin-film transistors of the plurality of pixel units;

[0013] a gate control circuit electrically connected to the pixel control array and comprising:

[0014] a plurality of gate driver circuit groups, one of the gate driver circuit groups comprising a plurality of gate driver circuits, one of the gate driver circuits comprising a gate thin-film transistor, wherein at least one of the gate thin-film transistors is a thin-film transistor with a low on-resistance, and the output end of one of the gate driver circuits is connected to one of the gate lines of the pixel control array;

[0015] a plurality of control signal lines, one of the control signal lines connected to the input end of one of the gate driver circuits of one of the gate driver circuit groups;

[0016] Multiple gate driver circuit group enable lines, and one of the gate driver circuit group enable lines is connected to the enable control points of multiple gate driver circuits of one of the gate driver circuit groups. Description of the Drawings

[0017] Figure 1A Is a block diagram of an existing electrophoretic display.

[0018] Figure 1B Is a driver block diagram of the gate driver circuit of an existing electrophoretic display.

[0019] Figure 2A Is a block diagram of an electrophoretic display according to an embodiment of the present invention.

[0020] Figure 2B Is a schematic diagram for explaining a pixel control array.

[0021] Figure 2C Is a schematic diagram for explaining a pixel thin film transistor and related components.

[0022] Figure 2D Is a schematic diagram for explaining a gate thin film transistor and related components.

[0023] Figure 3A Is a schematic diagram of a gate control circuit according to an embodiment of the present invention.

[0024] Figure 3B Is a schematic diagram of a gate driver circuit group according to an embodiment of the present invention.

[0025] Figure 4 Is a timing diagram of operation signals of an electrophoretic display according to an embodiment of the present invention.

[0026] Figure 5A Is a circuit diagram of a gate driver circuit group according to an embodiment of the present invention.

[0027] Figure 5B Is a circuit diagram of a gate driver circuit group according to another embodiment of the present invention.

[0028] Figure 5C Is a circuit diagram of a gate driver circuit group according to another embodiment of the present invention.

[0029] Figure 5D Is a circuit diagram of a gate driver circuit group according to another embodiment of the present invention.

[0030] Figure 6A Is a schematic diagram of the equivalent capacitance of the output equivalent capacitance in parallel with the data line and the gate line.

[0031] Figure 6B Is a schematic diagram of the equivalent capacitance of the output equivalent capacitance in parallel with the data line and the gate line.

[0032] Figure 6C It is a schematic diagram of a sampling gate line.

[0033] Figure 6D It is a circuit diagram of an output equivalent capacitance and a variable potential terminal.

[0034] Figure 6E It is a tracking compensation circuit diagram according to an embodiment of the present invention. Detailed implementation manners

[0035] For a detailed description and technical content of the present invention, please refer to the following detailed description and accompanying drawings as follows. The accompanying drawings and the detailed description are only for illustrative purposes and are not used to limit the present invention.

[0036] The driving method used for an electronic paper is much more complex than that of an LCD. Therefore, more requirements are imposed on the driving function. For example, the gate driving of an LCD is very simple. It only needs to sequentially turn on each scanning line, so the timing control is very simple. However, for the driving of an electronic paper, initialization, regional update, and post-update processing need to be considered, and there are many steps. Therefore, the gate driving control part must include multiple functions, such as all gate line output TFTs conducting potential, all gate line output TFTs cutting off potential, some gate line output TFTs conducting potential, some gate line output TFTs cutting off potential, the gate lines sequentially outputting TFT conducting potential, and maintaining the TFT cut-off potential after the power is turned off, etc.

[0037] See Figure 2A , which is a schematic diagram of an electrophoretic display according to an embodiment of the present invention. This electrophoretic display 10 includes a substrate 20 and a pixel control array 30. According to the required display resolution, the pixel control array 30 has a plurality of pixel units, such as X*Y (300*400) pixel units 32 (see Figure 2B ). The electrophoretic display 10 further includes a gate control circuit 40 and a data driving circuit 50. See Figure 2B, each pixel unit 32 of the present invention includes at least one pixel thin film transistor Tp, a storage capacitor Cs, and a pixel electrode PE. The pixel control array 30 further includes Y gate lines GL (illustrated as partial gate lines GL1 to GL3) and X data lines DL (illustrated as partial data lines DL1 to DL3), where the Y gate lines GL are respectively electrically connected to the gates of the pixel thin film transistors Tp and the outputs of the gate control circuit 40, and the X data lines DL are respectively electrically connected to the sources or drains of the pixel thin film transistors Tp and the outputs of the data driving circuit 50. When the pixel control array 30 needs to write data at a position, for example, corresponding to the position (GL1, DL1), the electrophoretic display 10 will set the level of the GL1-th gate line to logical high through the gate control circuit 40 to turn on the first gate line, and set the levels of the remaining gate lines to logical low. Furthermore, the electrophoretic display 10 will write data to the pixel electrode PE corresponding to the position (GL1, DL1) through the data driving circuit 50 from the DL1-th data line, and charge or discharge the storage capacitor Cs to set the data displayed at the position corresponding to (GL1, DL1).

[0038] Furthermore, referring to Figure 2A , a flexible circuit board 80 is attached to the substrate 20, and a control integrated circuit 82 is located on the flexible circuit board 80 and electrically connected to the gate control circuit 40 and the data driving circuit 50 to control the gate control circuit 40 and the data driving circuit 50.

[0039] With reference to Figure 2C , the pixel control array 30 is disposed on a substrate 20, and this substrate 20 has a first surface 21 and a second surface 22. More specifically, the pixel control array 30 is disposed on the second surface 22 of the substrate 20. Since this illustration is to show an embodiment of the main components constituting the pixel unit 32: the pixel thin film transistor Tp, the storage capacitor Cs, and the pixel electrode PE. And the pixel control array 30 includes a plurality of pixel units 32, so from Figure 2C it can be seen that in the present invention, the pixel control array 30 is disposed on the second surface 22 of the substrate 20.

[0040] Referring to Figure 2D , it is a schematic diagram for illustrating the gate thin film transistor Tg and related components. The gate thin film transistor Tg of the gate driving circuit group 42 of the present invention can be disposed on the second surface 22 of the substrate 20 and is electrically connected to the output equivalent capacitor Cg. The output equivalent capacitance value of the output equivalent capacitor Cg is provided by a capacitor formed by sandwiching an insulating layer CI between two conductive layers M1, M2 (such as metal 1 and metal 2 in the thin film transistor process) of the thin film transistor process.

[0041] According to an embodiment of the present invention, the gate thin film transistor Tg of the gate driving circuit group 42 can be a thin film transistor with a low on-resistance, and its on-resistance is not greater than 1 MΩ. According to an embodiment of the present invention, the on-resistance of the gate thin film transistor Tg is not greater than 100 KΩ. According to an embodiment of the present invention, the W / L ratio value of the gate thin film transistor Tg is greater than 50 / 1, so as to provide the required low on-resistance.

[0042] See Figure 3A and 3B , according to an embodiment of the present invention, the gate control circuit 40 includes a plurality of gate driving circuit groups 42_1..42_P, for example, including P gate driving circuit groups. Each gate driving circuit group 42 includes a plurality of gate driving circuits 43. Each gate driving circuit group 42 can receive Q control signals T1~TQ and output Q gate driving signals. For example, for the first gate driving circuit group 42_1, it can receive Q control signals T1~TQ and output Q gate driving signals G1~GQ. For the second gate driving circuit group 42_2, it can receive Q control signals T1~TQ and output Q gate driving signals G(Q + 1)~G(2Q)... For the Pth gate driving circuit group 42_P, it can receive Q control signals T1~TQ and output Q gate driving signals G((P - 1)Q + 1)~GPQ. Through the gate control circuit 40 of the present invention, P*Q gate driving signals can be provided under the condition of only receiving Q control signals T1~TQ. In other words, in the present invention, Y = P*Q. Furthermore, in conjunction with reference to Figure 5A , according to an embodiment of the present invention, a gate driving circuit group 42 can include Q gate thin film transistors Tg, that is, each gate driving circuit 43 includes a gate thin film transistor Tg. The gate of each gate thin film transistor Tg (that is, the enable control point EN of the gate driving circuit 43) is connected to the corresponding gate driving circuit enable line SL, and the source or drain of each gate thin film transistor Tg is electrically connected to an output equivalent capacitor Cg.

[0043] See Figure 5B , which is a circuit diagram of a gate driving circuit group according to another embodiment of the present invention. A gate driving circuit group 42 includes Q gate driving circuits 43. Each gate driving circuit 43 includes a pre-stage thin film transistor Tg1 and a post-stage thin film transistor Tg2 with a low on-resistance. The enable control point EN of the gate driving circuit 43 is the gate of the pre-stage thin film transistor Tg1. The source or drain of each post-stage thin film transistor Tg2 is electrically connected to an output equivalent capacitor Cg.

[0044] According to an embodiment of the present invention, in Figure 5BThe subsequent thin film transistor Tg2 of the middle gate driving circuit group 42 can be a thin film transistor with a low on-resistance, and its on-resistance is not greater than 1 MΩ. According to an embodiment of the present invention, the on-resistance of the subsequent thin film transistor Tg2 is not greater than 100 KΩ. According to an embodiment of the present invention, the W / L ratio value of the subsequent thin film transistor Tg2 is greater than 50 / 1, so as to provide the required low on-resistance.

[0045] See Figure 5C and Figure 5D , which are circuit diagrams of the gate driving circuit group according to a preferred embodiment of the present invention. The difference between it and Figure 5A and Figure 5B is that the source or drain of each gate thin film transistor Tg is electrically connected to an output equivalent capacitor Cg, and the other end of the output equivalent capacitor Cg is connected to a positive voltage, such as the positive power supply terminal Vhigh. The capacitor Cg accumulates negative charges at the drain or source terminal connecting the thin film transistor (Tg, Tg2), so as to ensure that the thin film transistor is completely in an open circuit state when the power is turned off.

[0046] In the following description, the logic high state potential is a high voltage that can turn on the thin film transistor, and the logic low state potential is a low voltage that can turn off the thin film transistor.

[0047] As described above, in combination with referring to Figure 2A , Figure 3A and Figure 4 , the electrophoretic display 10 can output the gate driving circuit group enabling signals S1 - SP through the gate driving circuit group enabling line SL to sequentially select and enable the first gate driving circuit group 42_1, the second gate driving circuit group 42_2... the Pth gate driving circuit group 42_P. In combination with referring to Figure 3A , when the gate driving circuit group enabling signal S1 is in the logic high state, the first gate driving circuit group 42_1 can receive Q control signals T1 to TQ and output Q gate driving signals G1 to GQ. For example, when the gate driving circuit group enabling signal S1 is in the logic high state, if the control signals T1, T2, T3 are 1, 0, 0 respectively, then the gate driving signals G1, G2, G3 are 1, 0, 0 respectively.

[0048] When the enable signal S2 of the gate drive circuit group is at a logic high level, the second gate drive circuit group 42_2 can receive Q control signals T1 to TQ and output Q gate drive signals G(Q + 1) to G(2Q). For example, when the enable signal S2 of the gate drive circuit group is at a logic high level, if the control signals T1, T2, T3 are 1, 0, 0 respectively, then the gate drive signals G(Q + 1), G(Q + 2), G(Q + 3) are 1, 0, 0 respectively. When the enable signal SP of the P-th gate drive circuit group is at a logic high level, the P-th gate drive circuit group 42_P can receive Q control signals T1 to TQ and output Q gate drive signals G((P - 1)*Q + 1), G((P - 1)*Q + 2). For example, when the enable signal SP of the gate drive circuit group is at a logic high level, if the control signals T1, T2 are 1, 0 respectively, then the gate drive signals G((P - 1)*Q + 1), G((P - 1)*Q + 2) are 1, 0 respectively, and so on. When other enable signals are at a logic low level, the output of the gate drive circuit group electrically connected to this enable signal is in a high impedance state, and the potential of the gate line connected to this high impedance output is Figure 5A , 5B , 5C and the voltage of the capacitor Cg in 5D. Therefore, the output states of the gate drive circuit group are three modes: logic high level, logic low level and high impedance output. When the output is at a logic high level, Cg will store the potential of the logic high level. When the output is at a logic low level, Cg will store the potential of the logic low level. When the output is at a high impedance, Cg will present the potential it stores.

[0049] Through the above gate control signal mechanism, the number of connection lines required to be connected to the gate control circuit 40 can be significantly reduced. Taking the pixel control array 30 having 300 * 400 pixel units (i.e., 120,000 pixel units 32) as an example, the prior art requires 300 gate lines to perform gate drive control. According to the present invention, using 15 input control signal lines (Q = 15) and 20 gate drive circuit group enable lines (P = 20), that is, P * Q = 300, only P + Q = 35 signal lines are required.

[0050] In addition, for electrophoretic displays, most display modes are static, that is, many pixels do not need to change the display content. For example, for the blank part of an e-book display or the picture display in a handwriting mode, many pixels do not need to change the display content. According to the above embodiments of the present invention, the enable signals S1 to SP of the gate drive circuit group and the input control signals T1 to TQ can be adjusted according to the positions and written values of the pixels that need to be changed, rather than performing a writing operation on all pixel units comprehensively, so as to more effectively control the display content of the electrophoretic display.

[0051] For example, if the user writes a straight line segment, assuming that the electrophoretic display 10 needs to write a total of 100 pixels (20x5 pixels, and signals relative to 20 gate lines and 5 data lines need to be output), and 4 frames are required to complete the required writing values. Furthermore, assume that 20 gate lines are distributed between the gate driving circuit group 42_m (which can receive 15 input control signal lines) and the gate driving circuit group 42_m+1 (which can receive 15 input control signal lines), and the first gate line to be controlled is the 4th input of the gate driving circuit group 42_m. Therefore, the input terminal T4 of the gate driving circuit group 42_m is in a logic high state and the remaining input terminals are in a logic low state. The enable line Sm of the gate driving circuit group 42_m is in a logic high state, and the remaining enable lines are in a logic low state. The data driving IC outputs the write data on the data lines that need to be changed, and the data lines of the remaining pixels that do not need to change state output a high impedance. Repeating this 20 times completes the writing of one frame. After repeating 4 frames, the local image update is completed. According to the above writing method, at most only 20*4 = 80 data line writing operations are required, compared with the prior art that requires 300*4 = 1200 writing operations for all gate writes, which can greatly reduce the number and time of writing operations.

[0052] Although the above example is a simplified example of the display operation of the general electrophoretic display 10, it can be seen from this example that for the locally changed display screen, the architecture of the present invention can greatly simplify the number and time of writing.

[0053] With reference to Figure 5C and Figure 5D , before performing the screen update, the gate driving initialization must be done first. The method is that all the enable lines SL of the gate driving circuits output a logic high potential, and all the input terminals of the gate driving circuit groups 42 input a logic low potential. At this time, all the equivalent capacitors Cg will be charged to the logic low potential. In order to have more negative charges at one end of the equivalent capacitor Cg connected to the gate line, the other end of the equivalent capacitor Cg is preferably connected to the highest positive power supply terminal Vhigh, or connected to a potential not less than zero volts or a variable potential. Referring again to Figure 6D , in another embodiment of the present invention, the variable potential is a programmable potential Vp.

[0054] Referring to Figure 6A , Figure 6B and Figure 6C , at the intersection of any gate line GL and multiple data lines DL, a capacitor (Cgd1, Cgd2... Cgdn) is formed respectively. These capacitors will superimpose the voltage change parts VD1, VD2~VDn on each data line onto the gate line, and its total influence (i.e., the total capacitance Cgdt) can be marked as Figure 6BThe equivalent circuit is such that the average voltage change part VDa of each data line will be superimposed on the gate line GL via the total capacitance Cgdt. When the signals superimposed on the gate line GL are large enough to turn on the thin film transistor that should be off, it will cause incorrect display of the electrophoretic display. To solve the above problems, as Figure 6E shown in a preferred embodiment of the present invention, a tracking compensation circuit 60 is provided between a sampling gate line GLs and the output equivalent capacitance Cg of each gate driver circuit group 42. The tracking compensation circuit includes a comparison circuit 62, a selection circuit 64, and an integration circuit 66. The output voltage VA of the tracking compensation circuit will vary with the change of the potential of a gate line. When the gate line sampling signal VG_ref output by the sampling gate line GLs is greater than a default critical voltage value (the first critical voltage value) Vth_H, the amplifier A1 turns on the switch SW1 and conducts the current of a weighted voltage (the first weighted voltage) V_H into the capacitor C of the integration circuit 66 to reduce the output voltage VA. When the voltage of the output voltage VA decreases, it will pull down the potential of all gate lines with high output impedance until the sampling signal (VG_ref) is less than the critical voltage value Vth_H. When the gate line sampling signal VG_ref output by the sampling gate line GLs is less than another default critical voltage value (the second critical voltage value) Vth_L, the amplifier A2 turns on the switch SW2 and conducts the current of a weighted voltage (the second weighted voltage) V_L into the capacitor C of the integration circuit 66 to increase the output voltage VA. When the voltage of the output voltage VA rises, it will pull up the potential of all gate lines with high output impedance until the sampling signal VG_ref is greater than the critical voltage value Vth_L. As Figure 6E shown, the output voltage of the integration circuit 66 changes complementarily with the change of the potential of the sampling gate line (VG_ref), and limits the voltage on the output equivalent capacitance of all gate lines with high output impedance between the weighted voltage Vth_H and the weighted voltage Vth_L. Therefore, the potentials of the weighted voltage Vth_H and the weighted voltage Vth_L are set at the potentials that do not turn on the gate thin film transistor Tg, and the potential of the weighted voltage Vth_H is higher than the potential of the weighted voltage Vth_L. The potential of the weighted voltage V_H must be a positive potential greater than 0, and the potential of the weighted voltage V_L must be a negative potential less than 0.

[0055] Refer back to Figure 6D , in another embodiment of the present invention, the other end of the equivalent capacitance Cg is connected to a programmable potential Vp, and the programmable potential is a preferred compensation potential planned according to the compensation parameters calculated by integrating the control parameters of each data line and gate line of the display at that time.

[0056] During the frame update period, after driving each gate line and completing the data line writing operation, the state of the input terminal of the gate driver circuit group 42 that is at a logic high level must be changed to a logic low level until the corresponding equivalent capacitor is charged to the logic low level potential. The gate driver initialization program can also be executed again to charge all the equivalent capacitors Cg to the logic low level potential to avoid the memory effect of the equivalent capacitor Cg, that is, when the next group of gate lines is turned on, the previous gate lines are also turned on synchronously and incorrect data is written.

[0057] During the above-mentioned image update period, the output terminals of multiple gate driver circuit groups 42 can output three types of states, namely high voltage, low voltage, and high output impedance. More specifically, according to one embodiment, at least one output of these gate driver circuit groups 42 is at a high impedance during the image update period. According to another embodiment, 50% of the gate driver circuit groups 42 output at a high impedance at least once during the image update period. According to another embodiment, 50% of the output terminals of these gate driver circuit groups 42 are at a low voltage at least once during the image update period. According to another embodiment, at least one output of these gate driver circuit groups 42 is at a high voltage at least once during the image update period. According to another embodiment, all the gate outputs of these gate driver circuit groups 42 are at a low voltage at least once during the image update period to initialize the storage capacitor.

[0058] Furthermore, when actuating at least one of the gate lines GL in the pixel control array 30, the gate address value of the pixel unit 32 is used multiple times to control the multiple gate driver circuit groups 42 to ensure the correct level of the gate line GL, and the interval time is not greater than 90% of the RC constant formed by the output impedance of the gate driver 43 and the output equivalent capacitor Cg.

[0059] In the above embodiment, these pixel thin film transistors and these gate thin film transistors are all amorphous silicon thin film transistors or organic thin film transistors or indium gallium zinc oxide (IGZO) thin film transistors. The substrate is a glass substrate or a flexible polymer material substrate.

[0060] In summary, the present invention can achieve the following effects:

[0061] Save the cost of using the gate driver module and the loss of yield caused by the thermal lamination process.

[0062] Through the gate control signal mechanism of the present invention, the number of connection lines to be connected to the gate control circuit 40 can be greatly reduced, that is, the number of control signal connection endpoints is reduced. The number of control signal connection endpoints is less than half of the number of these gate lines in the pixel control array, which can be used for a narrow border design.

[0063] Control the multiple gate driving circuit groups 42 to ensure that the interval time is not greater than 90% of the RC constant formed by the output impedance of the gate driving circuit 43 and the output equivalent capacitance Cg, which can ensure the correct level of the gate line GL.

[0064] The components of several embodiments are outlined above, enabling those with ordinary knowledge in the technical field to which the present invention pertains to better understand the concepts of the embodiments of the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains should understand that they can use the embodiments of the present invention as a basis to design or modify other processes and structures to achieve the same purpose and / or obtain the same benefits as the embodiments introduced herein. Those with ordinary knowledge in the technical field to which the present invention pertains should also understand that these equivalent structures do not deviate from the spirit and scope of the present invention, and various changes, substitutions, and other options can be made without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the appended patent application scope.

[0065]

Symbol Description

[0066] 10A: Electrophoretic display

[0067] 20A: Substrate

[0068] 30A: Pixel control array

[0069] 40A: Gate driving circuit board

[0070] 42A: Driving module

[0071] 42B: Gate driving IC

[0072] 50A: Data control circuit board

[0073] 51A: Data driving module

[0074] 52A: Data driving IC

[0075] 10: Electrophoretic display

[0076] 20: Substrate

[0077] 30: Pixel control array

[0078] 40: Gate control circuit

[0079] 50: Data driving circuit

[0080] 80: Flexible circuit board

[0081] 82: Control integrated circuit

[0082] DL1~DL3, DL: Data line

[0083] GL1 to GL3, GL: Gate line

[0084] 32: Pixel unit

[0085] Tp: Pixel thin film transistor

[0086] PE: Pixel electrode

[0087] Cs: Storage capacitor

[0088] S: Source

[0089] G: Gate

[0090] D: Drain

[0091] 21: First surface

[0092] 22: Second surface

[0093] M1: Conductive layer (metal one)

[0094] M2: Conductive layer (metal two)

[0095] Tg: Gate thin film transistor

[0096] Tg1: Pre-stage thin film transistor

[0097] Tg2: Post-stage thin film transistor

[0098] EN: Enable control point

[0099] Vhigh: Positive power supply terminal

[0100] Cg: Output equivalent capacitor

[0101] CI: Insulating layer

[0102] T1 to TQ: Control signal

[0103] G1 to GQ: Gate drive signal

[0104] 42_1, 42_2 to 42_P: Gate drive circuit group

[0105] 43: Gate drive circuit

[0106] S1 to Sp: Gate drive circuit group enable signal

[0107] SL, Sm: Gate drive circuit enable line

[0108] TL, Tn: Control signal line

[0109] Cgd1, Cgd2 to Cgdn: Capacitor

[0110] Cgdt: Total capacitance

[0111] VD1, VD2~VDn: Voltage change part

[0112] VDa: Average voltage change part

[0113] GLs: Sampling gate line

[0114] VA: Output voltage

[0115] Vp: Programmable potential

[0116] 60: Tracking compensation circuit

[0117] 62: Comparison circuit

[0118] 64: Selection circuit

[0119] 66: Integral circuit

[0120] Vth_H, Vth_L: Threshold voltage value

[0121] VG_ref: Sampling signals A1, A2, A3: Amplifier

[0122] V_H, V_L: Weighted voltage

[0123] SW1, SW2, SW3: Switch

[0124] R: Resistor

[0125] C: Capacitor

[0126] Vr: Reset voltage

Claims

1. An electrophoretic display, comprising: a substrate having a first surface and a second surface; a pixel control array disposed on the second surface and comprising: a plurality of pixel units, at least one of the pixel units comprising a pixel thin film transistor, a storage capacitor, and a pixel electrode; a plurality of gate lines, at least one of the gate lines being connected to the gates of the pixel thin film transistors of the plurality of pixel units; a plurality of data lines, at least one of the data lines being connected to the sources or drains of the pixel thin film transistors of the plurality of pixel units; a gate control circuit electrically connected to the pixel control array and comprising: a plurality of gate driver circuit groups, one of the gate driver circuit groups comprising a plurality of gate driver circuits, one of the gate driver circuits comprising a gate thin film transistor, wherein at least one of the gate thin film transistors is a thin film transistor with a low on-resistance, and the output terminal of one of the gate driver circuits is connected to one of the gate lines of the pixel control array; a plurality of control signal lines, one of the control signal lines being connected to the input terminal of one of the gate driver circuits of one of the gate driver circuit groups; a plurality of gate driver circuit group enable lines, one of the gate driver circuit group enable lines being connected to the enable control points of the plurality of gate driver circuits of one of the gate driver circuit groups.

2. The electrophoretic display according to claim 1, wherein one of the gate driver circuits comprises an output equivalent capacitance.

3. The electrophoretic display according to claim 2, wherein the capacitance value of the output equivalent capacitance is not less than 1 pF.

4. The electrophoretic display according to claim 2, wherein the output terminal of the gate driver circuit is the source or drain of the gate thin film transistor.

5. The electrophoretic display according to claim 1, wherein the low on-resistance is not greater than 1 MΩ.

6. The electrophoretic display according to claim 1, wherein the low on-resistance is not greater than 100 kΩ.

7. The electrophoretic display according to claim 1, wherein the W / L ratio value of one of the gate thin film transistors is greater than 50 / 1.

8. The electrophoretic display according to claim 1, wherein the enable control point of one of the gate driver circuits is the gate of the thin film transistor with the low on-resistance.

9. The electrophoretic display according to claim 1, wherein one of the gate driver circuits comprises a pre-stage thin film transistor and a post-stage thin film transistor with a low on-resistance, and the enable control point of the gate driver circuit is the gate of the pre-stage thin film transistor.

10. The electrophoretic display according to claim 2, wherein the output equivalent capacitance value is provided by a capacitor formed by sandwiching an insulating layer between two conductive layers of a thin film transistor process.

11. The electrophoretic display according to claim 1, wherein these pixel thin film transistors and these gate thin film transistors are all amorphous silicon thin film transistors or organic thin film transistors or indium gallium zinc oxide (IGZO) thin film transistors.

12. The electrophoretic display according to claim 1, wherein the substrate is a glass substrate or a flexible polymer material substrate.

13. The electrophoretic display according to claim 1, wherein the output terminals of the multiple groups of gate driving circuit groups can output three types of states, namely high voltage, low voltage, and high output impedance.

14. The electrophoretic display according to claim 1, wherein at least one output of these gate driving circuit groups is a high impedance at least once during the image update.

15. The electrophoretic display according to claim 1, wherein 50% of the gate driving circuit groups output a high impedance at least once during the image update.

16. The electrophoretic display according to claim 1, wherein 50% of the outputs of these gate driving circuit groups are low voltage at least once during the image update.

17. The electrophoretic display according to claim 1, wherein at least one output of these gate driving circuit groups is a high voltage at least once during the image update.

18. The electrophoretic display according to claim 1, wherein all gate outputs of these gate driving circuit groups are low voltage at least once during the image update.

19. The electrophoretic display according to claim 2, wherein one end of the output equivalent capacitor is connected to a potential not less than zero volts.

20. The electrophoretic display according to claim 19, wherein one end of the output equivalent capacitor is connected to a programmable potential.

21. The electrophoretic display according to claim 2, wherein one end of the output equivalent capacitor is connected to the output terminal of an amplifier, and the output voltage of the amplifier varies with the potential of one of the gate lines.

22. The electrophoretic display according to claim 21, wherein the output voltage of the amplifier varies complementarily with the variation of the potential of one of the gate lines.

23. The electrophoretic display according to claim 2, further comprising a tracking compensation circuit disposed between a sampling gate line and the output equivalent capacitors of each of the gate driving circuit groups, and the tracking compensation circuit includes a comparison circuit, a selection circuit, and an integration circuit.

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