Fault diagnosis function test system, method and equipment and storage medium
By designing a test system for fault diagnosis functions, using the fault injection module and processing module for fault diagnosis, the problem of degradation of fault diagnosis accuracy in the functional safety detection system is solved, and efficient fault testing is achieved.
Patent Information
- Application Number
- CN202410110008.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-25
- Publication Date
- 2025-07-25
AI Technical Summary
During fault diagnosis, the existing functional safety detection system is affected by equipment wear and faults, resulting in a decrease in diagnostic accuracy. The existing fault injection test method is logically complex and difficult to implement.
A test system with fault diagnosis function is designed, including a signal input module, a fault injection module and a fault processing module. Through the fault injection module, the fault injection module injects the fault in the preset fault test data set into the circuit to generate the fault output signal, and the fault processing module is used for fault diagnosis to generate fault detection accuracy and processing results.
Improves the accuracy of fault identification, simplifies fault injection testing, and improves fault testing efficiency.
Smart Images
Figure CN120370873A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of functional safety detection of control systems, and particularly to a test system for a fault diagnosis function, a test method for a fault diagnosis function, an electronic device, and a readable storage medium. Background Art
[0002] Function safety related systems - safety instrument systems (SIS) are one of the most important devices to ensure the safe production of petrochemical industries, which can maximize the avoidance of unsafe states of devices or equipment facilities, prevent accidents from occurring, or reduce the impact of accidents. When a function safety detection system performs fault diagnosis, the accuracy of fault diagnosis may be affected due to equipment wear, equipment failures, etc. within the function safety detection system. Therefore, it is necessary to perform functional testing on the function safety detection system to ensure the accuracy of fault diagnosis. The existing methods for performing functional testing on function safety detection systems usually use the method of fault injection for fault testing. The logic of the existing fault injection test method is complex and the implementation difficulty is relatively large. Summary of the Invention
[0003] The purpose of the embodiments of the present invention is to provide a test system, method, device, and storage medium for a fault diagnosis function to solve the above technical problems.
[0004] To achieve the above purpose, the embodiments of the present invention provide a test system for a fault diagnosis function, and the system includes:
[0005] A signal input module, configured to receive an input signal;
[0006] A fault injection module, connected to the signal input module, and configured to generate a fault output signal based on the input signal and a preset fault test data set;
[0007] A fault processing module, connected to the fault injection module, and configured to perform fault diagnosis according to the fault output signal to generate a target fault diagnosis result; wherein, the target fault detection result includes the fault detection accuracy rate of this round of testing and the fault processing result of this round of testing.
[0008] Optionally, the fault injection module includes a main board module and a fault conversion module;
[0009] The main board module is respectively connected to the signal input module and the fault processing module, and is configured to receive the input signal from the signal input module and output the fault output signal to the fault processing module;
[0010] The fault conversion module is configured to receive the input signal from the main board module, perform fault simulation on the input signal based on the preset fault test data set and a preset test sequence, generate the fault output signal, and output it to the main board module.
[0011] Optionally, the fault test data in the preset fault test dataset includes open - circuit test data, short - circuit test data, over - voltage test data, under - voltage test data, and over - current test data.
[0012] Optionally, the fault conversion module is specifically configured to:
[0013] Select the fault test data for this test from the preset fault test dataset based on the preset test order;
[0014] Convert the input signal into a corresponding fault output signal according to the fault test data.
[0015] Optionally, the fault processing module is specifically configured to:
[0016] Perform fault diagnosis on the fault output signal, determine the fault detection result corresponding to the fault test data of the current test, and record the fault detection result of the current test;
[0017] Judge whether the fault test data corresponding to the current test is the last fault test data in the preset test order;
[0018] If so, determine the fault detection accuracy rate and the fault processing result of this round of testing based on all the fault detection results of the current test.
[0019] Optionally, the fault processing module is further specifically configured to:
[0020] Compare the fault detection result of the current test with the fault test data in the preset fault test dataset corresponding to the current test, and judge whether the fault detection result of the current test is correct;
[0021] If it is correct, record the fault detection result of the current test as correct;
[0022] Otherwise, record the fault detection result of the current test as incorrect;
[0023] Repeat the comparison step until the fault test data corresponding to the current test is the last fault test data in the preset test order, and determine the fault detection accuracy rate of this round of testing based on the records of all the fault detection results of the current test.
[0024] Optionally, the fault processing module is further specifically configured to:
[0025] Based on the fault detection result of the current test, judge whether the fault processing operation corresponding to the fault detection result of the current test can be performed, and generate the fault processing result of the current test based on the judgment result;
[0026] Based on the fault handling results of all current tests, obtain the fault handling results of this round of tests.
[0027] In the second aspect of the embodiments of the present invention, a test method for a fault diagnosis function is provided. The method is implemented based on the test system for the fault diagnosis function described in the first aspect. The method includes:
[0028] Receive an input signal;
[0029] Based on the input signal and a preset fault test data set, generate a fault output signal;
[0030] Perform fault diagnosis according to the fault output signal to generate a target fault diagnosis result; wherein, the target fault detection result includes the fault detection accuracy rate of this round of tests and the fault handling results of this round of tests.
[0031] Optionally, the generating a fault output signal based on the input signal and a preset fault test data set includes:
[0032] Perform fault simulation on the input signal based on the preset fault test data set and a preset test order to generate a fault output signal.
[0033] Optionally, the performing fault simulation on the input signal based on the preset fault test data set and a preset test order to generate a fault output signal includes:
[0034] Based on the preset test order, select the fault test data for this test from the preset fault test data set;
[0035] According to the fault test data, convert the input signal into a corresponding fault output signal. Optionally, the performing fault diagnosis according to the fault output signal to generate a target fault diagnosis result includes:
[0036] Perform fault diagnosis on the fault output signal to determine the current fault detection result corresponding to the fault test data of the current test, and record the current fault detection result;
[0037] Judge whether the fault test data corresponding to the current test is the last fault test data in the preset test order;
[0038] If so, determine the fault detection accuracy rate of this round of tests and the fault handling results of this round of tests according to all current fault detection results.
[0039] Optionally, the determining the fault detection accuracy rate of this round of tests according to all current fault detection results includes:
[0040] Compare the fault detection result of the current test with the fault test data in the preset fault test dataset corresponding to the current test to determine whether the fault detection result of the current test is correct;
[0041] If it is correct, record the fault detection result of the current test as correct;
[0042] Otherwise, record the fault detection result of the current test as incorrect;
[0043] Repeat the comparison step until the fault test data corresponding to the current test is the last fault test data in the preset test order. Based on the records of the fault detection results of all current tests, determine the fault detection accuracy rate of this round of tests.
[0044] Optionally, determining the fault handling result of this round of tests according to all the current fault detection results includes:
[0045] Based on the fault detection result of the current test, determine whether the fault handling operation corresponding to the fault detection result of the current test can be executed, and generate the fault handling result of the current test based on the judgment result;
[0046] Based on the fault handling results of all the current tests, obtain the fault handling result of this round of tests.
[0047] The third aspect of this application provides an electronic device configured to execute the test method of the above-mentioned fault diagnosis function.
[0048] The fourth aspect of this application provides a machine-readable storage medium, on which instructions are stored. When the instructions are executed by a processor, the processor is configured to execute the test method of the above-mentioned fault diagnosis function.
[0049] In the embodiment of the present invention, a fault injection module is designed to inject faults in the preset fault test dataset into the circuit to generate a fault output signal, and then the fault handling module is used to perform fault diagnosis according to the fault output signal to generate the fault detection accuracy rate of this round of tests and the fault handling result of this round of tests. That is, in the embodiment of the present invention, fault injection is performed on the fault handling module to test the fault detection accuracy rate and fault handling result of the fault handling module, improving the accuracy of fault recognition, simplifying the fault injection test, and improving the fault test efficiency.
[0050] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent specific implementation part. Description of the Drawings
[0051] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention, and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the embodiments of the present invention, but do not constitute a limitation to the embodiments of the present invention. In the accompanying drawings:
[0052] Figure 1 is a schematic diagram of the architecture of a test system for a fault diagnosis function provided by an embodiment of the present invention;
[0053] Figure 2 is a circuit diagram of an open digital output signal;
[0054] Figure 3 is a circuit diagram of an overcurrent analog input signal;
[0055] Figure 4 is a circuit diagram of a short-circuited digital input signal;
[0056] Figure 5 is a circuit diagram of CPU undervoltage;
[0057] Figure 6 is an external view of the test box;
[0058] Figure 7 is a schematic diagram of the internal equipment and terminal block layout of the test box;
[0059] Figure 8 is a schematic diagram of the operation of a test system for a fault diagnosis function;
[0060] Figure 9 is a schematic flow diagram of a test method for a fault diagnosis function provided by an embodiment of the present invention.
[0061] Description of Reference Numerals
[0062] 10 Signal input module; 20 Fault injection module;
[0063] 21 Main board module; 22 Fault conversion module;
[0064] 30 Fault processing module; 41 Module current indicator light;
[0065] 42 Operation indicator light; 43 Fault indicator light;
[0066] 44 Module two-position rotary switch; 45 Fault insertion push-button switch;
[0067] 46 DC ammeter; 47 Adjustable potentiometer;
[0068] 48 Digital input signal push-button switch; 49 Digital output signal LED indicator light. Detailed Description of the Invention
[0069] The following will describe in detail the specific implementation manners of the embodiments of the present invention with reference to the accompanying drawings. It should be understood that the specific implementation manners described herein are only for explaining and illustrating the embodiments of the present invention, and are not used to limit the embodiments of the present invention.
[0070] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments, and are not intended to limit this application.
[0071] In the description of the embodiments of this application, technical terms such as "first" and "second" are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity, specific order or primary-secondary relationship of the indicated technical features. In the description of the embodiments of this application, "a plurality" means more than two, unless otherwise specifically defined.
[0072] Figure 1 is a schematic diagram of the architecture of a test system for a fault diagnosis function provided by an embodiment of the present invention; Figure 2 is a circuit diagram of an open digital output signal; Figure 3 is a circuit diagram of an overcurrent analog input signal; Figure 4 is a circuit diagram of a short-circuited digital input signal; Figure 5 is a circuit diagram of CPU undervoltage; Figure 6 is an external view of the test box; Figure 7 is a schematic diagram of the internal equipment of the test box and the layout of the wiring terminals; Figure 8 is a schematic diagram of the operation of a test system for a fault diagnosis function; Figure 9 is a schematic flowchart of a test method for a fault diagnosis function provided by an embodiment of the present invention.
[0073] Embodiment 1
[0074] Please refer to Figure 1 , Figure 1 which is a schematic diagram of the architecture of a test system for a fault diagnosis function provided in this embodiment.
[0075] A signal input module 10 is used to receive input signals. The digital input module 10 can be a circuit board. Specifically, the digital input module 10 accesses current, receives digital input signals and analog input signals, and divides the input signals into N input signals and inputs them to a fault injection module 20. Among them, the power supply for powering the test system for the fault diagnosis function can be 24VCD.
[0076] The fault injection module 20, which is connected to the signal input module, is used to receive the input signal and generate a fault output signal based on the input signal and a preset fault test data set. The fault injection module 20 includes a main board module 21 and a fault conversion module 22. The main board module can be a circuit board, which is used to implement the transmission of the input signal and the fault output signal. The opto-isolation method can be used to isolate the input signal and the fault processing module 30, and also isolate the preset fault test data set 22 and the fault processing module 30. The fault conversion module 22 can be a DIP switch conversion circuit board, which is connected to each circuit of the main board. Based on the preset test sequence, the fault test data for this test is selected from the preset fault test data set. According to the fault test data, the input signal in the main board is converted into the corresponding fault output signal.
[0077] The fault output signal includes open-circuit test data, short-circuit test data, overvoltage test data, undervoltage test data, and overcurrent test data. For example, the digital output signal under open circuit can be Figure 2 as shown, and the analog input signal under overcurrent can be Figure 3 as shown. The digital output signal under short circuit can be Figure 4 as shown, and the CPU under undervoltage can be Figure 5 as shown.
[0078] The fault processing module 30 is connected to the fault injection module 20 and is used to perform fault diagnosis based on the fault output signal and generate a target fault diagnosis result.
[0079] Among them, the target fault detection result includes the fault detection accuracy rate and the fault processing result of this round of testing. Specifically, the fault processing module 30 performs fault diagnosis on the fault output signal, determines the fault detection result corresponding to the fault test data of the current test, records the fault detection result of the current test, and judges whether the fault test data corresponding to the current test is the last fault test data in the preset test sequence. If so, based on all the fault detection results of the current test, the fault detection accuracy rate and the fault processing result of this round of testing are determined.
[0080] Among them, the fault detection accuracy rate of this round of testing is specifically determined by comparing the fault detection result of the current test with the fault test data in the preset fault test data set corresponding to the current test to judge whether the fault detection result of the current test is correct.
[0081] If the fault detection result is correct, record the fault detection result of the current test as correct. If the fault detection result is incorrect, record the fault detection result of the current test as incorrect. Repeat the step of comparing the current fault detection result with the fault test data corresponding to the current test until the fault test data corresponding to the current test is the last fault test data in the preset test sequence. Based on the records of all the fault detection results of the current test, determine the fault detection accuracy rate of this round of testing; the fault handling result of this round of testing is determined by judging whether the fault handling operation corresponding to the fault detection result can be executed based on the fault detection result of the current test, and generating the fault handling result of the current test based on the judgment result, where the fault handling operation can be cutting off the circuit. The above-mentioned fault handling module 30 can perform fault detection through software detection, communication fault detection, processor CPU fault detection, and crystal oscillator frequency comparison detection, and the fault handling module 30 is equipped with an extended external SD card slot connected to the core board, using the SPI (Serial Peripheral Interface) access method, with a capacity of not less than 8GB, for storing user application programs, fault detection accuracy rates, and fault handling results.
[0082] It can be understood that the above-mentioned test system for fault diagnosis functions can be integrated in a preset test box for convenient debugging. The appearance of the test box is as Figure 6 shown. The module current indicator light 41 is located in the upper left corner of the test box. Next to the module current indicator light 41 are the operation indicator light 42 and the fault indicator light 43 in sequence. In the upper right corner is the module two-position rotary switch 44. Below the module two-position rotary switch 44 are two rows of fault insertion push-button switches 45. In the middle two rows of the test box are DC ammeters 46. Each DC ammeter 46 is equipped with an adjustable potentiometer 47 below it. In the first row at the lower part of the test box is the digital input signal push-button switch 48, and in the next row is the digital output signal LED indicator light 49; the layout positions of the internal devices and wiring terminals of the test box are shown by Figure 7 shown. A signal input module 10 is set beside the power supply wiring terminal at the top of the test box to receive input signals. A fault conversion module 22 is set in the middle of the test box to inject faults. A main board module 21 is set at the bottom of the test box to realize the transmission of input signals and fault output signals, and each module is connected by a cable.
[0083] The test system for fault diagnosis functions can be operated as shown by Figure 8 shown. The interfaces of the test box are correspondingly connected to the various circuit interfaces in the test system for fault diagnosis functions. The power supply of the test box can be provided by the switching power supplies RD-65B and UHP-500-24, and the input signals can be input under the control of a computer.
[0084] In this embodiment, a fault injection module 20 is designed to inject faults from a preset fault test data set into a circuit to generate a fault output signal, and then a fault processing module 30 is used to perform fault diagnosis based on the fault output signal to generate the fault detection accuracy rate and the fault processing result of this round of testing. That is, in the embodiment of the present invention, fault injection is performed on the fault processing module 30 to test the fault detection accuracy rate and the fault processing result of the fault processing module 30, improving the accuracy rate of fault identification, simplifying the fault injection test, and improving the fault test efficiency.
[0085] Embodiment 2
[0086] Please refer to Figure 9 , Figure 9 which is a schematic flowchart of a test method for a fault diagnosis function provided by an embodiment of the present application.
[0087] Step S100: Receive an input signal.
[0088] The input signal includes a digital input signal and an analog input signal, and the input signal is divided into N input signals and input into the fault injection module 20. Among them, the power supply for the test system of the fault diagnosis function can be 24VCD.
[0089] Step S200: Generate a fault output signal based on the input signal and a preset fault test data set.
[0090] Specifically, in this step, based on a preset test order, the fault test data for this test is selected from the preset fault test data set, and according to the fault test data, the input signal in the main board is converted into a corresponding fault output signal. The fault output signal includes open - circuit test data, short - circuit test data, over - voltage test data, under - voltage test data, and over - current test data. For example, the digital output signal under open - circuit can be as shown by Figure 2 , the analog input signal under over - current can be as shown by Figure 3 , the digital output signal under short - circuit can be as shown by Figure 4 , and the CPU under under - voltage can be as shown by Figure 5 .
[0091] Step S300: Perform fault diagnosis according to the fault output signal to generate a target fault diagnosis result;
[0092] Among them, the target fault detection result includes the fault detection accuracy rate and the fault processing result of this round of testing.
[0093] Specifically, in this step, fault diagnosis is performed on the fault output signal to determine the fault detection result corresponding to the fault test data of the current test, and the fault detection result of the current test is recorded. It is judged whether the fault test data corresponding to the current test is the last fault test data in the preset test sequence. If so, based on all the fault detection results of the current test, the fault detection accuracy rate and the fault handling result of this round of test are determined.
[0094] Among them, the fault detection accuracy rate of this round of test is specifically determined by comparing the fault detection result of the current test with the fault test data in the preset fault test data set corresponding to the current test to judge whether the fault detection result of the current test is correct. If the fault detection result is correct, the fault detection result of the current test is recorded as correct; if the fault detection result is incorrect, the fault detection result of the current test is recorded as incorrect. The step of comparing the fault detection result of the current test with the fault test data corresponding to the current test is repeatedly executed until the fault test data corresponding to the current test is the last fault test data in the preset test sequence. Based on the records of all the fault detection results of the current test, the fault detection accuracy rate of this round of test is determined; the fault handling result of this round of test is determined by judging whether the fault handling operation corresponding to the fault detection result can be executed based on the fault detection result of the current test, and the fault handling result of the current test is generated based on the judgment result, where the fault handling operation can be cutting off the circuit.
[0095] Embodiment 3
[0096] In this embodiment, the fault code is SIS-HW-0003, and the fault content is that ASSR1-6_CO2 is open-circuited with the on-site digital input signal. The circuit diagram is as Figure 2 shown. The open-circuit test data in the preset fault test data set includes that the DO1 switch is open-circuited and the output is always off; the DO output is always on; when DO1-C02 is open-circuited, no signal is output. The fault conversion module 22 converts the input signal into a corresponding open-circuit fault output signal according to the fault code SIS-HW-0003 corresponding to the open-circuit test data. The fault processing module 30 performs fault detection on the open-circuit fault output signal: adjusting the DI-1, DI-2, and DI-3 switches (i.e., the three digital input signal toggle switches 48 from left to right) in sequence is ineffective, and the LED light of the DO-1 in the test box does not light up (i.e., the first digital output signal LED indicator 49 does not light up), determining it as an open-circuit fault, controlling the fault indicator light 43 of the test box to light up, and controlling the execution of corresponding fault repair measures. It can be seen that in this fault diagnosis function test, the fault detection and fault handling functions of the open circuit of the fault processing module 30 are normal.
[0097] Embodiment 4
[0098] In this embodiment, the fault code is SIS-HW-0018, the fault content is overcurrent of AI0, and the circuit diagram is as follows Figure 3 shown. The overcurrent test data in the preset fault test dataset includes applying 15% additional current to the circuit, that is, when the current is 24 mA, it should not affect the working stability of the A / D chip; when the input current at pin U3-1 is too large, the DO output is normal; the LED light at the DO-3 point of the test equipment can be turned off (that is, the LED indicator 49 of the third digital output signal can be turned off), and an emergency stop occurs without affecting the system operation. The fault conversion module 22 converts the input signal into a corresponding overcurrent fault output signal according to the fault code SIS-HW-0018 corresponding to the overcurrent test data. The fault processing module 30 performs fault detection on the overcurrent fault output signal: adjusts the applied current to 8 - 24 mA, the LED light at the DO-3 point on the test equipment can be turned off, and an emergency stop can be achieved, which is determined as an overcurrent fault. Controls the fault indicator 43 of the test box to light up and controls the execution of corresponding fault repair measures. It can be seen from this that in this fault diagnosis function test, the fault detection and fault processing functions of the fault processing module 30 for overcurrent are normal.
[0099] Embodiment Five
[0100] In this embodiment, the fault code is SIS-HW-0012, the fault content is short circuit of U45-FOD817D output, and the circuit diagram is as follows Figure 4 shown. The short circuit test data in the preset fault test dataset includes short circuit of U45 output, grounding the CHAN1 signal, and the signal CHAN1 collected at its output end is always at a low level, and the DI signal is always low. As a result, the input signal cannot be received at the output end of ASSR1-1, the LED light at the DO-1 point of the test box goes out (that is, the LED indicator 49 of the first digital output signal goes out), and a false stop occurs. The fault conversion module 22 converts the input signal into a corresponding short circuit fault output signal according to the fault code SIS-HW-0012 corresponding to the short circuit test data. The fault processing module 30 performs fault detection on the short circuit fault output signal: the LED light at the DO-1 point goes out, and the DI-1 to DI-3 switches are toggled in sequence on the test equipment. The switches are all ineffective and the system is in a stopped state, which is determined as a short circuit fault. Controls the fault indicator 43 of the test box to light up and controls the execution of corresponding fault repair measures. It can be seen from this that in this fault diagnosis function test, the fault detection and fault processing functions of the fault processing module 30 for short circuit are normal.
[0101] Embodiment Six
[0102] In this embodiment, the fault code is SIS-HW-0035, the fault content is CPU undervoltage, and the circuit diagram is as follows Figure 5As shown, the undervoltage test data in the preset fault test dataset includes a working voltage of 12V. Disconnect ISO + 12V, and externally apply a voltage adjustment reduction of 15% (10.43V). This range should not affect operation. At the same time, the fault indicator light 43 lights up, and an emergency stop occurs. The fault conversion module 22 converts the input signal into a corresponding undervoltage fault output signal according to the fault code SIS-HW-0035 corresponding to the undervoltage test data. The fault processing module 30 performs fault detection on the undervoltage fault output signal: adjust the externally applied voltage to +10.43V, measure the current of 0.086A, the power of 0.896W. Toggle the DI-1 to DI-6 switches, and when adjusting the AI-1 to AI-10 analog input signals to 1, the LED lights of DO-1 to DO-8 of the test box can go out, enter the safe stop state, determine it as an undervoltage fault, control the fault indicator light 43 of the test box to light up, and control the execution of corresponding fault repair measures. It can be seen from this that in this fault diagnosis function test, the fault processing module 30 has normal fault detection and fault processing functions for undervoltage.
[0103] Embodiment Seven
[0104] In this embodiment, a fault injection test is carried out on the safety remote control terminal (RTU). Through the Fault Mode and Effect Analysis (FEMDA), key parameters such as all possible fault modes, fault manifestations, and fault probabilities of this product are obtained. Connect the RTU device to be tested to the test box and power it on for operation. The previous data is used as the input information of the preset fault test dataset, and a test plan ( Figure 6 ) is established based on this preset fault test dataset. Implement fault injection in sequence, record the test results, compare the target fault test results with the fault test data in the preset fault test dataset, and the proportion of successful tests in the total test volume is 100%. It shows that the RTU passes the fault injection test.
[0105] In this embodiment, the faults in the preset fault test dataset can be injected into the circuit to generate fault output signals, and then fault diagnosis is performed based on the fault output signals to generate the fault detection accuracy rate and fault processing results of this round of test, improving the accuracy of fault recognition, simplifying the fault injection test, and improving the fault test efficiency.
[0106] Embodiment Eight
[0107] In a typical configuration, a computing device includes one or more processors (CPUs), an input / output interface, a network interface, and memory.
[0108] The memory may include non-permanent memory in the computer-readable medium, forms such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash memory (flash RAM). The memory is an example of the computer-readable medium.
[0109] A computer-readable medium includes permanent and non-permanent, removable and non-removable media that can implement information storage by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory, or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD), or other optical storage, magnetic cassette tapes, magnetic disk storage, or other magnetic storage devices, or any other non-transitory medium that can be used to store information accessible by a computing device. As defined herein, a computer-readable medium does not include transitory computer-readable media, such as modulated data signals and carrier waves.
[0110] Embodiment Nine
[0111] An embodiment of the present invention also provides a computer-readable storage medium, on which instructions are stored, and the instructions are adapted to execute a program of steps of a test method with a fault diagnosis function when executed by a processor. The specific steps to be executed include:
[0112] Step 1: Receive an input signal;
[0113] Step 2: Generate a fault output signal based on the input signal and a preset fault test data set; in this step, select the fault test data for this test from the preset fault test data set based on the preset test order; and convert the input signal into a corresponding fault output signal according to the fault test data;
[0114] Step 3: Perform fault diagnosis based on the fault output signal to generate a target fault diagnosis result; wherein, the target fault detection result includes the fault detection accuracy rate of this round of test and the fault handling result of this round of test.
[0115] Judge whether the fault test data corresponding to the current test is the last fault test data in the preset test order;
[0116] If so, determine the fault detection accuracy rate of this round of test and the fault handling result of this round of test according to all the current fault detection results.
[0117] Determining the fault detection accuracy rate of this round of test according to all the current fault detection results includes:
[0118] Compare the fault detection result of the current test with the fault test data in the preset fault test dataset corresponding to the current test to determine whether the fault detection result of the current test is correct;
[0119] If it is correct, record the fault detection result of the current test as correct;
[0120] Otherwise, record the fault detection result of the current test as incorrect;
[0121] Repeat the comparison step until the fault test data corresponding to the current test is the last fault test data in the preset test order. Based on the records of the fault detection results of all current tests, determine the fault detection accuracy rate of this round of tests.
[0122] Based on all the fault detection results of the current tests, determine the fault handling results of this round of tests, including:
[0123] Based on the fault detection result of the current test, judge whether the fault handling operation corresponding to the fault detection result of the current test can be executed, and generate the fault handling result of the current test based on the judgment result;
[0124] Based on the fault handling results of all current tests, obtain the fault handling result of this round of tests.
[0125] Through the above technical solutions, the accuracy rate of fault identification can be improved, the fault injection test can be simplified, and the fault test efficiency can be improved.
[0126] Those skilled in the art should understand that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0127] The present application is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, and the combination of processes and / or blocks in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.
[0128] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable memory produce a manufacture including an instruction device that implements the functions specified in one or more of the processes and / or blocks Figure 1 in one or more of the processes and / or blocks Figure 1 specified in one or more of the blocks or blocks.
[0129] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus, such that a series of operational steps are performed on the computer or other programmable apparatus to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable apparatus provide steps for implementing the functions specified in one or more of the processes and / or blocks Figure 1 in one or more of the processes and / or blocks Figure 1 specified in one or more of the blocks or blocks.
[0130] In addition, it should be noted that, in the above specific embodiments, the various specific technical features described can be combined in any suitable manner without conflict. To avoid unnecessary repetition, the embodiments of the present invention do not separately describe various possible combinations.
[0131] In addition, in each embodiment of the embodiments of the present application, the various functional modules can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.
[0132] It should also be noted that the term "comprising", "including" or any other variation thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or apparatus comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or apparatus. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising the element.
[0133] The above are only the embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.
Claims
1. A test system for a fault diagnosis function, characterized in that The system includes: A signal input module for receiving input signals; A fault injection module connected to the signal input module, for generating a fault output signal based on the input signal and a preset fault test data set; A fault processing module connected to the fault injection module, for performing fault diagnosis according to the fault output signal and generating a target fault diagnosis result; wherein, the target fault detection result includes the fault detection accuracy rate of the current round of testing and the fault processing result of the current round of testing.
2. The test system for the fault diagnosis function according to claim 1, wherein The fault injection module includes a main board module and a fault conversion module; The main board module is respectively connected to the signal input module and the fault processing module, for receiving the input signal from the signal input module and outputting the fault output signal to the fault processing module; The fault conversion module is used to receive the input signal from the main board module, perform fault simulation on the input signal based on the preset fault test data set and the preset test sequence, generate a fault output signal and output it to the main board module.
3. The test system for the fault diagnosis function according to claim 2, wherein The fault test data in the preset fault test data set includes open circuit test data, short circuit test data, overvoltage test data, undervoltage test data and overcurrent test data.
4. The test system for the fault diagnosis function according to claim 2, wherein Specifically, the fault conversion module is used for: Selecting the fault test data for the current test from the preset fault test data set based on the preset test sequence; Converting the input signal into a corresponding fault output signal according to the fault test data.
5. The test system for the fault diagnosis function according to claim 1, wherein Specifically, the fault processing module is used for: Performing fault diagnosis on the fault output signal, determining the current fault detection result corresponding to the fault test data of the current test, and recording the current fault detection result; Judging whether the fault test data corresponding to the current test is the last fault test data in the preset test sequence; If so, determining the fault detection accuracy rate of the current round of testing and the fault processing result of the current round of testing according to all the current fault detection results.
6. The test system for the fault diagnosis function according to claim 5, characterized in that, Specifically, the fault processing module is further used for: Comparing the current fault detection result with the fault test data in the preset fault test data set corresponding to the current test, and judging whether the fault detection result of the current test is correct; If it is correct, recording the fault detection result of the current test as correct; Otherwise, recording the fault detection result of the current test as incorrect; Repeating the comparison step until the fault test data corresponding to the current test is the last fault test data in the preset test sequence, and determining the fault detection accuracy rate of the current round of testing based on the records of all the current fault detection results.
7. The test system for the fault diagnosis function according to claim 6, wherein Specifically, the fault processing module is further used for: Judging whether the fault processing operation corresponding to the fault detection result of the current test can be executed based on the fault detection result of the current test, and generating the fault processing result of the current test based on the judgment result; Obtaining the fault processing result of the current round of testing based on all the fault processing results of the current test.
8. A test method for a fault diagnosis function, characterized in that, The method is implemented based on the test system for the fault diagnosis function described in any one of claims 1-7, and the method includes: Receiving an input signal; Generating a fault output signal based on the input signal and a preset fault test data set; Fault diagnosis is performed based on the fault output signal to generate a target fault diagnosis result; wherein, the target fault detection result includes the fault detection accuracy rate of this round of testing and the fault handling result of this round of testing.
9. The test method for the fault diagnosis function according to claim 8, wherein Generating the fault output signal based on the input signal and the preset fault test data set includes: Performing fault simulation on the input signal based on the preset fault test data set and the preset test order to generate a fault output signal.
10. The test method for the fault diagnosis function according to claim 9, characterized in that, Performing fault simulation on the input signal based on the preset fault test data set and the preset test order to generate a fault output signal, including: Selecting the fault test data for this test from the preset fault test data set based on the preset test order; Converting the input signal into a corresponding fault output signal according to the fault test data.
11. The test method for the fault diagnosis function according to claim 8, characterized in that, Performing fault diagnosis based on the fault output signal to generate a target fault diagnosis result, including: Performing fault diagnosis on the fault output signal to determine the fault detection result corresponding to the fault test data of the current test, and recording the fault detection result of the current test; Judging whether the fault test data corresponding to the current test is the last fault test data in the preset test order; If so, determining the fault detection accuracy rate of this round of testing and the fault handling result of this round of testing according to all the fault detection results of the current test.
12. The test method for the fault diagnosis function according to claim 11, characterized in that, Determining the fault detection accuracy rate of this round of testing according to all the fault detection results of the current test includes: Comparing the fault detection result of the current test with the fault test data in the preset fault test data set corresponding to the current test to judge whether the fault detection result of the current test is correct; If it is correct, recording the fault detection result of the current test as correct; Otherwise, recording the fault detection result of the current test as incorrect; Repeating the comparison step until the fault test data corresponding to the current test is the last fault test data in the preset test order, and determining the fault detection accuracy rate of this round of testing based on the records of all the fault detection results of the current test.
13. The test method for the fault diagnosis function according to claim 11, wherein Determining the fault handling result of this round of testing according to all the fault detection results of the current test includes: Based on the fault detection result of the current test, judging whether it is possible to execute the fault handling operation corresponding to the fault detection result of the current test, and generating the fault handling result of the current test based on the judgment result; Obtaining the fault handling result of this round of testing based on all the fault handling results of the current test.
14. An electronic device, characterized in that, Including: A processor and a memory, the memory stores machine-readable instructions executable by the processor, and when the machine-readable instructions are executed by the processor, the testing method for the fault diagnosis function described in any one of claims 8-13 is executed.
15. A computer-readable storage medium, characterized in that, Instructions are stored on the computer-readable storage medium, and the instructions are used to cause the machine to execute the testing method for the fault diagnosis function described in any one of claims 8-13.