Clock synchronization system and method, electronic equipment and server

Abstract

The invention provides a clock synchronization system and method, electronic equipment and a server. The clock synchronization system comprises a master control processor, three non-master control processors and a cascade switch network composed of a first high-speed switch, a second high-speed switch and a third high-speed switch. The input end of the first high-speed switch is connected with the clock output end of the main control processor; the output end of the first high-speed switch is in cascade connection with the input end of the second high-speed switch and the input end of the third high-speed switch, and the output end of the second high-speed switch is connected to the clock input end of the master control processor and the clock input end of a non-master control processor in a distributed mode. The output end of the third high-speed switch is connected to the clock input ends of the remaining two non-main-control processors, and the control end of the third high-speed switch is controlled by in-place signals of the remaining two non-main-control processors. Compared with the prior art, the cascade switch network formed by the first high-speed switch, the second high-speed switch and the third high-speed switch can realize multiple connection combination modes, and can meet the requirements of different application scenes.

Description

Technical Field

[0001] The present disclosure relates to the technical field of servers, and particularly to a clock synchronization system and method, an electronic device, and a server. Background Art

[0002] In a multi-way server design system, usually CPU0 is set as the master control processor (legacy CPU), and the remaining CPUs are non-master control processors (Non-legacy CPUs). Its synchronization mechanism mainly relies on the legacy CPU, and uses a hardware device to transmit and synchronize its own clock to other Non-legacy CPUs, so as to achieve clock synchronization at the system level. However, different application scenarios have different requirements for the interface usage and service allocation of the CPU, and a fixed CPU combination is difficult to adapt to this change. In addition, when a CPU slot on the motherboard fails, due to the lack of an effective redundant backup mechanism, the system cannot be powered on normally, increasing the usage cost and maintenance difficulty. Therefore, it is urgent to develop a more flexible, reliable and adaptable multi-CPU clock synchronization scheme. Summary of the Invention

[0003] The present disclosure provides a clock synchronization system and method, an electronic device, and a server. Its main purpose is to solve the problem that in the related art, complex application scenarios cannot be dealt with during clock synchronization, and the reliability of clock synchronization is low.

[0004] According to a first aspect of the present disclosure, there is provided a clock synchronization system, including: a master control processor, three non-master control processors, and a cascaded switch network composed of a first high-speed switch, a second high-speed switch, and a third high-speed switch;

[0005] The input end of the first high-speed switch is connected to the clock output end of the master control processor, and its control end is controlled by the presence signal of the master control processor;

[0006] The output end of the first high-speed switch is respectively cascaded to the input ends of the second high-speed switch and the third high-speed switch. The output end of the second high-speed switch is distributedly connected to the clock input ends of the master control processor and a non-master control processor, and its control end is controlled by the presence signals of the master control processor and a non-master control processor;

[0007] The output end of the third high-speed switch is connected to the clock input ends of the remaining two non-master control processors, and its control end is controlled by the presence signals of the remaining two non-master control processors.

[0008] Optionally, the first high-speed switch, the second high-speed switch, and the third high-speed switch each include four multiplexers. Every two multiplexers are connected in series to form two transmission channels, and the two transmission channels are connected in parallel;

[0009] The multiplexer in the transmission channel includes an input multiplexer and an output multiplexer; the in-position signal terminals of the main control processor and the three non-main control processors are respectively connected to the control terminals of their corresponding input multiplexers.

[0010] Optionally, the first high-speed switch responds to the in-position signal of the main control processor and conducts the transmission channels from the first high-speed switch to the second high-speed switch and the third high-speed switch.

[0011] The second high-speed switch synchronously responds to the in-position signal of the main control processor and conducts the transmission channel from the second high-speed switch to the main control processor to transmit the clock signal output from the clock output terminal to the clock input terminal of the main control processor.

[0012] Optionally, the second high-speed switch responds to the in-position signal of a non-main control processor and conducts the transmission channel from the second high-speed switch to a non-main control processor to transmit the clock signal to the clock input terminal of a non-main control processor.

[0013] The third high-speed switch responds to the in-position signals of the remaining two non-main control processors and respectively conducts the transmission channels from the third high-speed switch to the remaining two non-main control processors to transmit the clock signal to the clock input terminals of the remaining two non-main control processors.

[0014] Optionally, the second high-speed switch or the third high-speed switch responds to the in-position signal of any non-main control processor and conducts the transmission channel from the second high-speed switch or the third high-speed switch to any non-main control processor to transmit the clock signal to the clock input terminal of any non-main control processor.

[0015] Optionally, the clock synchronization system further includes: a fault repair module;

[0016] The fault detection module is respectively connected to the three non-main control processors. The fault detection module is used to detect the in-position states of the three non-main control processors and determine whether the three non-main control processors have faults.

[0017] Control the second high-speed switch or the third high-speed switch corresponding to the faulty processor with a fault to close the corresponding transmission channel in the second high-speed switch or the third high-speed switch.

[0018] According to the second aspect of the present disclosure, a clock synchronization method is provided, including:

[0019] Transmit the clock signal of the main control processor to the first high-speed switch and detect the in-position signal states of the main control processor and all non-main control processors;

[0020] When the in-position signal of the main control processor is detected to be valid, activate the transmission channel of the first high-speed switch.

[0021] According to the validity of the in-position signal of the non-master processor, the corresponding transmission channels of the second and third high-speed switches are sequentially turned on in cascade order to send the clock signal to the master processor and the non-master processor.

[0022] Optionally, the method for clock synchronization further includes:

[0023] If the in-position signal of the non-master processor is invalid, then the transmission channels in the corresponding second high-speed switch or third high-speed switch of the non-master processor with the invalid in-position signal are controlled to be closed.

[0024] According to a third aspect of the present disclosure, there is provided an electronic device, including: the clock synchronization system as described in the foregoing first aspect.

[0025] According to a fourth aspect of the present disclosure, there is provided a server, including: the clock synchronization system as described in the foregoing first aspect.

[0026] The present disclosure provides a clock synchronization system and method, an electronic device, and a server, relating to the technical field of servers. The present disclosure can implement various connection combination methods through a cascade switch network composed of first, second, and third high-speed switches. This means that the system can implement various configuration combinations, and this flexible configuration provides more choices for users and can meet the requirements of different application scenarios. When an abnormality occurs in the slot corresponding to a certain processor in the system, due to the existence of various configuration combination methods, the user can select other normal processor combinations to ensure the normal operation of the system. This can reduce the scrap rate and usage cost caused by hardware failures, improve the system stability, and reduce the downtime and maintenance cost. The system uses a pure hardware cascade switch network composed of high-speed switches to achieve clock synchronization, without additional logic control, and controls the high-speed switches through the processor in-position signal. This has higher stability and faster response speed compared with the clock synchronization scheme relying on software control in the related technical solutions, can reduce the dependence on software, reduce the risk of potential software failures, simplify the system complexity and maintenance difficulty, and further enhance the system reliability.

[0027] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. Description of the Drawings

[0028] The drawings are used to better understand the solution and do not constitute a limitation to the present disclosure. Among them:

[0029] Figure 1 is a schematic structural diagram of a clock synchronization system provided by an embodiment of the present disclosure;

[0030] Figure 2Structural schematic diagram of a high-speed switch provided by an embodiment of the present disclosure;

[0031] Figure 3 Structural schematic diagram of another clock synchronization system provided by an embodiment of the present disclosure;

[0032] Figure 4 Structural schematic diagram of another clock synchronization system provided by an embodiment of the present disclosure;

[0033] Figure 5 Flow schematic diagram of a clock synchronization method provided by an embodiment of the present disclosure. Detailed implementation manners

[0034] The following describes exemplary embodiments of the present disclosure with reference to the accompanying drawings. Various details of the embodiments of the present disclosure are included to assist understanding, and they should be considered merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0035] The following describes a clock synchronization system, method, electronic device, and server according to an embodiment of the present disclosure with reference to the accompanying drawings.

[0036] Figure 1 Structural schematic diagram of a clock synchronization system provided by an embodiment of the present disclosure. As Figure 1 shown, the system includes: a main control processor 11, three non-main control processors 12, and a cascaded switch network composed of a first high-speed switch 13, a second high-speed switch 14, and a third high-speed switch 15.

[0037] The input end of the first high-speed switch 13 is connected to the clock output end of the main control processor 11, and its control end is controlled by the in-position signal of the main control processor 11.

[0038] In an embodiment of the present disclosure, the first high-speed switch 13 plays a key role in data transmission and control. The main control processor 11, as the main output source of the system clock, has its clock output terminal directly electrically connected to the input terminal of the first high-speed switch 13. This connection method ensures that the clock signal generated by the main control processor 11 can be transmitted to the first high-speed switch 13 stably and efficiently. The presence signal of the main control processor 11 is used to control the working state of the first high-speed switch 13. The presence signal is a signal used to indicate whether the main control processor 11 is properly installed and in a workable state. When the main control processor 11 is properly present, the generated presence signal is transmitted to the control terminal of the first high-speed switch 13, causing the first high-speed switch 13 to enter the workable mode and allowing the clock signal to pass through. If the main control processor 11 is not present, the control terminal of the first high-speed switch 13 does not receive a valid presence signal. At this time, the first high-speed switch 13 will maintain a specific initial state, blocking abnormal clock signals from being transmitted and avoiding interference with the overall system clock synchronization.

[0039] This connection and control method is the basic architecture of the entire clock synchronization system. The connection between the input terminal of the first high-speed switch 13 and the clock output terminal of the main control processor 11 provides a stable signal source for subsequent clock signal distribution. And the control of the control terminal of the first high-speed switch 13 through the presence signal realizes the effective management of clock signal transmission, ensuring that the system can stably perform clock synchronization operations when the main control processor 11 is working properly, and improving the reliability and stability of the system. The three non-main control processors 12 are divided into: one non-main control processor 121 connected to the second high-speed switch 14 and the remaining two non-main control processors 12 connected to the third high-speed switch 15. It should be noted that in the subsequent description, there are expressions such as "any one", "one", and "the remaining two" for the purpose of distinguishing different non-main control processors. These expressions may include one of the non-main control processor 121, the non-main control processor 12, the non-main control processor 12, or a combination of them; the present disclosure does not limit this. When it is impossible to distinguish which specific non-main control processor it is, the non-main control processor 12 is temporarily used for replacement. This situation where the specific number cannot be distinguished is caused by technical means and is not a defect in the expression.

[0040] The output terminal of the first high-speed switch 13 is cascaded with the input terminals of the second high-speed switch 14 and the third high-speed switch 15 respectively. The output terminal of the second high-speed switch 14 is distributedly connected to the clock input terminals of the main control processor 11 and one non-main control processor 12, and its control terminal is controlled by the presence signals of the main control processor 11 and one non-main control processor 12.

[0041] In an embodiment of the present disclosure, a cascaded connection relationship is established between the output terminal of the first high-speed switch 13 and the input terminals of the second high-speed switch 14 and the third high-speed switch 15. This cascading method constructs a critical path for the further distribution and transmission of the clock signal. After receiving the clock signal from the main control processor 11 and processing it according to its in-position signal, the first high-speed switch 13 outputs the clock signal to the input terminals of the second high-speed switch 14 and the third high-speed switch 15. The output terminal of the second high-speed switch 14 is connected in a distributed manner to the clock input terminals of the main control processor 11 and a non-main control processor 12. This distributed connection design enables the second high-speed switch 14 to accurately distribute the received clock signal to different processor clock input interfaces, meeting the requirements of different processors for the clock signal. At the same time, the control terminal of the second high-speed switch 14 is controlled by the in-position signals of the main control processor 11 and the non-main control processor 12. Specifically, when the main control processor 11 and the corresponding non-main control processor 12 are in the normal in-position state, their in-position signals control different transmission channels of the second high-speed switch 14 through the control terminal (enable terminal), and the second high-speed switch 14 will transmit the appropriate clock signal to the corresponding processor clock input terminal according to the preset logic rules to ensure the accuracy and stability of the overall system clock synchronization. Through this cascading and distributed connection, as well as the control method based on the in-position signal of the processor, the system realizes the efficient management and accurate distribution of the clock signal, ensuring that each processor can obtain a stable and synchronized clock signal under different working states, providing a solid clock foundation for the normal operation of the entire system.

[0042] The output terminal of the third high-speed switch 15 is connected to the clock input terminals of the remaining two non-main control processors 12, and its control terminal is controlled by the in-position signals of the remaining two non-main control processors 12.

[0043] In an embodiment of the present disclosure, the output end of the third high-speed switch 15 is connected to the clock input ends of the remaining two non-master processors 12. From the perspective of the signal transmission process, the third high-speed switch 15 receives the clock signal cascaded from the first high-speed switch 13. When the first high-speed switch 13 outputs and cascades the clock signal to the input end of the third high-speed switch 15 under the control of the in-position signal of the master processor 11, the third high-speed switch 15 will determine whether to transmit the clock signal to the corresponding non-master processor 12 according to the state of the in-position signal received by its control end. The control end of the third high-speed switch 15 is controlled by the in-position signals of the remaining two non-master processors 12. These two non-master processors 12 respectively control the transmission channels in their corresponding third high-speed switches 15. When these two non-master processors 12 are in the normal in-position state, the in-position signals generated by them respectively will be transmitted to the control end of the third high-speed switch 15. After the third high-speed switch 15 receives a valid combination of in-position signals, the transmission channels inside it will be triggered, and then the input clock signal will be accurately distributed to the clock input ends of the corresponding non-master processors 12, so that these two non-master processors 12 can obtain synchronous clock signals to ensure that they maintain temporal consistency during operation and maintain the stable operation of the system.

[0044] The present disclosure provides a clock synchronization system. Through the cascaded switch network composed of the first, second, and third high-speed switches, the present disclosure can implement various connection combination methods. This means that the system can implement various configuration combinations, and this flexible configuration provides more choices for users and can meet the requirements of different application scenarios. When an abnormality occurs in the slot corresponding to a certain processor in the system, due to the existence of various configuration combination methods, the user can select other normal processor combinations to ensure the normal operation of the system. This can reduce the scrap rate and usage cost caused by hardware failures, improve the system stability, reduce the downtime and maintenance cost. The system uses a pure hardware cascaded switch network composed of high-speed switches to achieve clock synchronization, without additional logic control, and controls the high-speed switches through the in-position signals of the processors. Compared with the clock synchronization scheme relying on software control in the related technical solutions, the pure hardware design has higher stability and faster response speed, can reduce the dependence on software, reduce the risk of potential software failures, simplify the system complexity and maintenance difficulty, and further enhance the system reliability.

[0045] Further, in a possible implementation manner of this embodiment, as Figure 2 shown, the first high-speed switch 13, the second high-speed switch 14, and the third high-speed switch 15 each include four multiplexers. Every two multiplexers are connected in series to form two transmission channels, and the two transmission channels are connected in parallel; the multiplexers in the transmission channels include input multiplexers and output multiplexers; the in-position signal ends of the master processor 11 and the three non-master processors 12 are respectively connected to the control ends of their corresponding input multiplexers.

[0046] Specifically, in the embodiments of the present disclosure, the internal structure design of the first high-speed switch 13, the second high-speed switch 14, and the third high-speed switch 15 is the key to achieving precise clock signal transmission and control. Each high-speed switch includes four multiplexers, and these multiplexers are configured to form an efficient signal transmission network according to the connection mode in Figure 2 . Specifically, every two multiplexers are connected in series to form a transmission channel, and there are two such transmission channels in each high-speed switch, and the two transmission channels are connected in parallel. This design enables the high-speed switch to have high flexibility and reliability when processing clock signals.

[0047] In the transmission channel, the multiplexers are divided into input multiplexers and output multiplexers. The input multiplexer is responsible for receiving the externally input clock signal and selecting a suitable signal input source according to the control instruction generated by the in-position signal. The output multiplexer then accurately outputs the processed and selected clock signal to the clock input terminal of the target processor.

[0048] The in-position signal terminals of the main control processor 11 and the three non-main control processors 12 are respectively connected to the control terminals of the corresponding input multiplexers. This connection method establishes a close connection between the in-position state of the processor and the internal signal selection mechanism of the high-speed switch. When the main control processor 11 is in the normal in-position state, its in-position signal is transmitted to the control terminal of the corresponding input multiplexer in the first high-speed switch 13, controlling the input multiplexer to select the signal from the clock output terminal of the main control processor 11 as the input source. At the same time, the in-position signals of the three non-main control processors 12 respectively control the working states of the corresponding input multiplexers in the second high-speed switch 14 and the third high-speed switch 15.

[0049] Taking the second high-speed switch 14 as an example, when the connected main control processor 11 and a non-main control processor 12 are both in the normal in-position state, their in-position signals act on the control terminals of the corresponding input multiplexers in the second high-speed switch 14 at the same time. After receiving these in-position signals, the input multiplexer accurately outputs the signals to the clock input terminals of the main control processor 11 and the non-main control processor 12 through the series-connected output multiplexers. Similarly, in the third high-speed switch 15, when the remaining two non-main control processors 12 are both in the normal in-position state, their in-position signals control the input multiplexers in the third high-speed switch 15 to select the correct clock signal input, and then the signals are transmitted to the clock input terminals of these two non-main control processors 12 through the output multiplexers.

[0050] Through this mechanism in which the high-speed switch, the multiplexer, and the in-position signal of the processor work together, the system realizes precise control and efficient transmission of the clock signal, ensuring that each processor can obtain stable and synchronous clock signals in different working states, providing a strong guarantee for the stable operation of the entire system.

[0051] Suppose CPU0 is set as the main control processor 11 (legacy CPU), and CPU1, CPU2, and CPU3 are non-main control processors 12 (non-legacy CPU). Their clock input and output interfaces are XTAL_IN and PFT_OUT respectively, and the in-position signals correspond to PKG0, PKG1, PKG2, and PKG3. The Quick Switch has specific input, output, and enable control interfaces. The first, second, and third Quick Switch structures are the same, each having four multiplexers. Every two multiplexers are connected in series to form a transmission channel, with a total of two channels in parallel. The multiplexers are divided into input and output types, and the in-position signals of each processor are connected to the control terminals of the corresponding input multiplexers. When the processor is in position, its in-position signal controls the input multiplexer to select an appropriate clock signal, which is transmitted to the XTAL_IN interface of the corresponding processor through the output multiplexer to achieve clock synchronization.

[0052] Further, in a possible implementation of this embodiment, as Figure 3 shown, the first Quick Switch 13 responds to the in-position signal of the main control processor 11 and conducts the transmission channels from the first Quick Switch 13 to the second Quick Switch 14 and the third Quick Switch 15; the second Quick Switch 14 synchronously responds to the in-position signal of the main control processor 11 and conducts the transmission channel from the second Quick Switch 14 to the main control processor 11 to transmit the clock signal output from the clock output terminal to the clock input terminal of the main control processor 11.

[0053] Specifically, in the embodiment of the present disclosure, the first Quick Switch 13 serves as a key signal transmission hub, and its working state closely depends on the in-position signal of the main control processor 11. When the main control processor 11 is in a normal in-position state, a corresponding in-position signal will be generated. This signal is transmitted to the control terminal of the first Quick Switch 13. After the transmission channels inside the first Quick Switch 13 receive this in-position signal, the transmission channels from the first Quick Switch 13 to the second Quick Switch 14 and the third Quick Switch 15 are conducted. This conduction action means that the clock signal output from the clock output terminal of the main control processor 11 can smoothly transmit to the input terminals of the second Quick Switch 14 and the third Quick Switch 15 along the established circuit path, laying a foundation for subsequent clock signal distribution and synchronization.

[0054] The second high-speed switch 14 also has a specific response mechanism to the presence signal of the main control processor 11. When the second high-speed switch 14 receives the presence signal of the main control processor 11, the transmission channel inside it leading to the clock input terminal of the main control processor 11 will be turned on. At this time, the clock signal transmitted from the first high-speed switch 13, after being processed inside the second high-speed switch 14, can pass through the turned-on transmission channel and be accurately transmitted to the clock input terminal of the main control processor 11. This process ensures that the main control processor 11 can receive the feedback of its own output clock signal, thus realizing the circulation and synchronization of the clock signal within the system. In this way, the main control processor 11 can calibrate and adjust its own working state according to the received feedback clock signal, further ensuring the accuracy and stability of the system clock and providing important support for the reliable operation of the entire system.

[0055] When the main control processor 11 (CPU0) is present (PKG0 is valid), the first high-speed switch 13 turns on the transmission channels to the second and third high-speed switches, enabling the clock signal output by PFT_OUT to be transmitted. At the same time, under the action of PKG0, the second high-speed switch 14 turns on the transmission channel to the main control processor 11, and feeds back the clock signal to the XTAL_IN of the main control processor 11, completing the clock synchronization of the main control processor 11 itself and laying the foundation for the clock synchronization of the entire system.

[0056] Furthermore, in a possible implementation manner of this embodiment, as Figure 3 shown, the second high-speed switch 14 responds to a presence signal of a non-main control processor 12, and turns on the transmission channel of the second high-speed switch 14 to a non-main control processor 12 to transmit the clock signal to the clock input terminal of a non-main control processor 12; the third high-speed switch 15 responds to the presence signals of the remaining two non-main control processors 12, and respectively turns on the transmission channels of the third high-speed switch 15 to the remaining two non-main control processors 12 to transmit the clock signal to the clock input terminals of the remaining two non-main control processors 12.

[0057] Specifically, in the embodiments of the present disclosure, it is assumed that the main control processor 11 and the three non-main control processors 12 are all working normally and generate corresponding presence signals. The second high-speed switch 14 and the third high-speed switch 15 perform precise clock signal transmission control according to the presence signals of different non-main control processors 12 during the process of realizing the clock synchronization of multiple non-main control processors 12.

[0058] When a non-master processor 12 is in normal position, the processor generates a corresponding in-position signal. This in-position signal is used as a control instruction and is transmitted to the control terminal of the second high-speed switch 14. After receiving this in-position signal, the second high-speed switch 14 adjusts the internal transmission channels, enabling the transmission channel leading to the clock input terminal of this non-master processor 121 to conduct.

[0059] From the perspective of the signal transmission process, the first high-speed switch 13 transmits the clock signal from the master processor 11 to the input terminal of the second high-speed switch 14. After the second high-speed switch 14 receives the in-position signal of the non-master processor 12 and conducts the corresponding transmission channel, these clock signals can smoothly pass through the conducted path and be accurately transmitted to the clock input terminal of this non-master processor 12. In this way, this non-master processor 12 can obtain a clock signal synchronized with the master processor 11, ensuring its normal operation in the system and its coordinated work with other processors.

[0060] For the third high-speed switch 15, its working principle is similar to that of the second high-speed switch 14. When the remaining two non-master processors 12 are both in normal position, the in-position signals they generate respectively are simultaneously transmitted to the control terminal of the third high-speed switch 15. The third high-speed switch 15 controls the conduction of the transmission channels leading to the clock input terminals of these two non-master processors 12 respectively. After the first high-speed switch 13 transmits the clock signal to the input terminal of the third high-speed switch 15, the third high-speed switch 15 accurately distributes and transmits the clock signal to the clock input terminals of the remaining two non-master processors 12 according to the conducted transmission channels. This process ensures that these two non-master processors 12 can receive synchronized clock signals, maintaining their synchronized working state in the system and avoiding data transmission errors or system operation anomalies caused by clock asynchronization.

[0061] Through the precise response of the second high-speed switch 14 and the third high-speed switch 15 to the in-position signals of different non-master processors 12 and the effective control of the transmission channels, this clock synchronization system realizes the clock synchronization between multiple (three) non-master processors and the master processor, greatly improving the overall performance and stability of the system and ensuring the reliable operation of the system in a multi-processor coordinated working environment.

[0062] When one of the non-master processors (such as one of CPU1, CPU2, CPU3) connected to the second high-speed switch 14 is in position, its in-position signal (PKG1 or PKG2 or PKG3) will trigger the second high-speed switch 14. The internal logic of the second high-speed switch 14 controls the input multiplexer to select the clock signal transmitted through the first high-speed switch according to this signal, and then conducts it to the XTAL_IN interface of this non-master processor through the output multiplexer to achieve the clock synchronization of this processor.

[0063] If the remaining two non-master processors are present, their presence signals (such as PKG2 and PKG3, PKG1 and PKG3, PKG1 and PKG2) will act together on the third high-speed switch 15. Based on these signals, the internal logic of the third high-speed switch 15 controls the corresponding input multiplexer to select the appropriate clock signal, which is conducted through the output multiplexer to the XTAL_IN interface of their respective non-master processors, enabling these two non-master processors to achieve clock synchronization and ensuring the coordinated operation of each processor in the system.

[0064] Furthermore, in a possible implementation of this embodiment, as Figure 3 shown, the second high-speed switch 14 or the third high-speed switch 15 responds to the presence signal of any non-master processor 12, and conducts the transmission channel of the second high-speed switch 14 or the third high-speed switch 15 to any non-master processor 12, so as to transmit the clock signal to the clock input end of any non-master processor 12.

[0065] Specifically, in the embodiment of the present disclosure, when the system is running, there will be a working state where the master processor 11 is present normally, and at the same time only one non-master processor 12 is also present normally. This non-master processor 12 may be connected to the second high-speed switch 14 or the third high-speed switch 15.

[0066] When a non-master processor 12 is present normally, this processor will generate a presence signal. This presence signal, as a control signal, will be transmitted to the control end of the high-speed switch (i.e., the second high-speed switch 14 or the third high-speed switch 15) connected to it. Taking the second high-speed switch 14 as an example, when it receives the presence signal of the non-master processor 12 connected to itself, it controls the transmission channel leading to the clock input end of this non-master processor 12 in the second high-speed switch 14 to be conducted.

[0067] At this time, the clock signal transmitted from the first high-speed switch 13 enters its internal circuit through the input end of the second high-speed switch 14. Since the transmission channel leading to this non-master processor 12 has been conducted, the clock signal can be smoothly transmitted along this conducted path and finally accurately delivered to the clock input end of this non-master processor 12. In this way, this non-master processor 12 can obtain a clock signal synchronized with the master processor 11, ensuring its normal operation in the system and being consistent with the master processor 11 in time to achieve coordinated operation.

[0068] Through the precise response of the second high-speed switch 14 or the third high-speed switch 15 to the in-position signal of the non-master processor 12 and the effective control of the transmission channel, this clock synchronization system can achieve accurate transmission and synchronization of clock signals under different combinations of processor in-position conditions, greatly improving the adaptability and stability of the system and ensuring the reliable operation of the system in various complex working scenarios.

[0069] The second and third high-speed switches are responsible for transmitting the clock signal to the non-master processor. When any non-master processor (CPU1, CPU2, or CPU3) is in position, the in-position signal (PKG1, PKG2, or PKG3) generated by it will be received by the corresponding high-speed switch. If it is received by the second high-speed switch 14, the internal input multiplexer selects an appropriate clock signal under the control of this in-position signal, conducts the transmission channel through the output multiplexer, and sends the signal to the XTAL_IN interface of this non-master processor; if it is received by the third high-speed switch 15, the third high-speed switch 15 will also control the multiplexer to conduct the corresponding transmission channel according to a similar mechanism to ensure the accurate transmission of the clock signal and achieve the clock synchronization of the non-master processor.

[0070] Furthermore, in a possible implementation manner of this embodiment, as Figure 4 shown, the clock synchronization system further includes: a fault repair module 16;

[0071] The fault detection module 16 is respectively connected to the three non-master processors 12. The fault detection module 16 is used to detect the in-position status of the three non-master processors 12 and determine whether the three non-master processors 12 have faults;

[0072] Control the second high-speed switch 14 or the third high-speed switch 15 corresponding to the faulty processor, and close the corresponding transmission channel in the second high-speed switch 14 or the third high-speed switch 15.

[0073] Specifically, in the embodiment of the present disclosure, the fault detection module 16 has established a direct connection relationship with the three non-master processors 12. It monitors the in-position status of the non-master processors 12 in real time through specific hardware interfaces and communication protocols. Specifically, the fault detection module periodically sends detection signals to each non-master processor 12. These signals are used to query the working status information of the processor, including whether the processor is normally powered, whether the internal circuit is in a stable working state, and whether key control signals are normal, etc. After receiving the detection signals, the non-master processor 12 returns corresponding status feedback information. The fault detection module analyzes and processes these feedback information according to preset criteria and logical judgment rules to determine whether each non-master processor 12 has a fault.

[0074] When the fault detection module detects a fault in a certain non-master processor 12, it immediately triggers the corresponding control mechanism. This mechanism determines the high-speed switch corresponding to the faulty processor, that is, the second high-speed switch 14 or the third high-speed switch 15. This determination process is based on the pre-set connection relationship and logic mapping table of the system. By parsing the identification information of the faulty processor, it quickly locates the high-speed switch connected to it. Next, the control mechanism sends a control instruction to the corresponding high-speed switch to close the transmission channel leading to the faulty processor in the high-speed switch. Taking the second high-speed switch 14 as an example, if a certain non-master processor 12 connected to it fails, the fault detection module will send a control instruction to the control terminal of the second high-speed switch 14. After the logic circuit inside the second high-speed switch 14 receives this instruction, it will adjust the state of the internal switch elements or signal selectors, so that the transmission channel leading to the clock input terminal of the faulty processor is closed. In this way, the clock signal will no longer be able to be transmitted to the faulty processor, avoiding the chaos of the entire system clock synchronization that may be caused by the abnormal processing of the clock signal by the faulty processor.

[0075] Figure 5 It is a schematic flowchart of a clock synchronization method provided by an embodiment of the present disclosure.

[0076] As Figure 5 shown, this method includes the following steps:

[0077] Step 201, transmit the clock signal of the master processor to the first high-speed switch, and detect the in-position signal status of the master processor and all non-master processors.

[0078] Specifically, after the system starts, the master processor starts to work, and the internal clock generator of it generates a stable clock signal. This clock signal is transmitted to the first high-speed switch through specific electrical connection lines. In this transmission process, the integrity and stability of the signal are crucial. Therefore, the connection lines will undergo strict electrical performance design to ensure that the clock signal reduces signal attenuation and interference as much as possible during transmission.

[0079] At the same time, the detection module of the system starts to work. This module is connected to the master processor and all non-master processors through hardware interfaces respectively. The detection module periodically sends detection signals to each processor. These detection signals are used to query the in-position status of the processor. After receiving the detection signal, the processor will return a feedback signal containing its own in-position status information. The detection module parses and judges these feedback signals according to the pre-set protocol and logic rules, so as to determine the in-position signal status of the master processor and all non-master processors, and stores these status information in the status register of the system for subsequent processes to use.

[0080] Step 202: When the in-position signal of the main control processor is detected as valid, activate the transmission channels of the first high-speed switch.

[0081] Specifically, the system reads the status information of the in-position signal of the main control processor stored in the status register in real time. Once the in-position signal of the main control processor is detected as valid, it means that the main control processor has been normally started and is in a working state. At this time, the system sends an activation instruction to the first high-speed switch. The first high-speed switch integrates a dedicated control logic circuit inside. After receiving the activation instruction, this circuit operates on the internal switch elements or signal selectors. These operations activate the transmission channels in the first high-speed switch leading to the second and third high-speed switches, preparing for the subsequent transmission of the clock signal. During the activation process, the first high-speed switch performs a series of internal self-check operations to ensure the normal electrical performance of the transmission channels, so as to ensure the stable transmission of the clock signal.

[0082] Step 203: According to the validity of the non-main control processor in-position signal, sequentially conduct the corresponding transmission channels of the second and third high-speed switches in cascade order, so as to send the clock signal to the main control processor and the non-main control processors.

[0083] Specifically, the precise distribution of the clock signal is achieved based on the validity of the in-position signal of the non-main control processor. The system reads the status information of the in-position signals of each non-main control processor in the status register again. If there is a valid in-position signal of a non-main control processor connected to the second high-speed switch, the system sends a conduction instruction to the second high-speed switch. After receiving the instruction, the internal logic circuit of the second high-speed switch conducts the transmission channels leading to this non-main control processor and the main control processor (if it is necessary to feedback the clock signal to the main control processor) according to the preset rules. This operation is achieved by controlling elements such as multiplexers inside, ensuring that the clock signal can be accurately transmitted to the corresponding processor clock input terminal.

[0084] Similarly, if a valid in-position signal of a non-main control processor connected to the third high-speed switch is detected, the system sends a conduction instruction to the third high-speed switch. After receiving the instruction, the third high-speed switch conducts the transmission channels leading to these non-main control processors according to the internal preset logic, and transmits the clock signal from the first high-speed switch to the corresponding non-main control processor clock input terminal. During the entire conduction process, each level of high-speed switch operates strictly in cascade order to ensure the correct timing of the clock signal transmission, avoid signal conflicts or transmission errors, and thus achieve the clock synchronization of all in-position processors in the system.

[0085] The present disclosure provides a clock synchronization method. Through the cascaded switch network composed of the first, second, and third high-speed switches, the present disclosure can achieve various connection combination modes. This means that the system can achieve various configuration combinations, and this flexible configuration provides more choices for users and can meet the requirements of different application scenarios. When an abnormality occurs in the slot corresponding to a certain processor in the system, due to the existence of various configuration combination modes, the user can select other normal processor combinations to ensure the normal operation of the system. This can reduce the scrap rate and usage cost caused by hardware failures, improve the system stability, and reduce the downtime and maintenance cost. The system uses a pure hardware cascaded switch network composed of high-speed switches to achieve clock synchronization, without additional logic control, and controls the high-speed switches through the processor in-place signal. Compared with the clock synchronization scheme relying on software control in the related technical solutions, the pure hardware design has higher stability and faster response speed, can reduce the dependence on software, reduce the risk of potential software failures, simplify the system complexity and maintenance difficulty, and further enhance the system reliability.

[0086] Further, in a possible implementation manner of this embodiment, the clock synchronization method further includes:

[0087] If the in-place signal of the non-master processor is invalid, then control the transmission channel in the second high-speed switch or the third high-speed switch corresponding to the non-master processor with the invalid in-place signal to be closed.

[0088] Specifically, the system continuously monitors the in-place signals of non-master processors. Once it detects that the in-place signal of a certain non-master processor is invalid, it will locate the corresponding second or third high-speed switch of the processor according to the pre-stored connection configuration information. The system then sends a closing instruction to the corresponding high-speed switch. After receiving the order, the internal logic circuit of the high-speed switch controls the internal switch elements or multiplexers to cut off the transmission channel leading to the invalid in-place processor, preventing the mistransmission of clock signals and ensuring the stability and accuracy of the system clock synchronization.

[0089] It should be noted that there may be multiple steps in the embodiments of the present disclosure. For the convenience of description, these steps are numbered, but these labels are not intended to limit the execution time slots and execution orders between the steps; these steps can be implemented in any order, and the embodiments of the present disclosure do not make any limitations in this regard.

[0090] The embodiments of the present application further provide an electronic device and a server, including the system described in any of the above system embodiments of clock synchronization.

[0091] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered as exceeding the scope of this application.

[0092] The above has introduced in detail a clock synchronization system and method, an electronic device, and a server provided by this application. Specific examples are used herein to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art, without departing from the principle of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A clock synchronization system, characterized in that, Including: A main control processor, three non-main control processors, and a cascaded switch network composed of a first high-speed switch, a second high-speed switch, and a third high-speed switch; The input end of the first high-speed switch is connected to the clock output end of the main control processor, and its control end is controlled by the presence signal of the main control processor; The output end of the first high-speed switch is cascaded to the input ends of the second high-speed switch and the third high-speed switch respectively. The output end of the second high-speed switch is distributedly connected to the clock input ends of the main control processor and a non-main control processor, and its control end is controlled by the presence signals of the main control processor and the non-main control processor; The output end of the third high-speed switch is connected to the clock input ends of the remaining two non-main control processors, and its control end is controlled by the presence signals of the remaining two non-main control processors.

2. The clock synchronization system according to claim 1, wherein The first high-speed switch, the second high-speed switch, and the third high-speed switch each include four multiplexers. Every two multiplexers are connected in series to form two transmission channels, and the two transmission channels are connected in parallel; The multiplexers in the transmission channels include input multiplexers and output multiplexers; the presence signal ends of the main control processor and the three non-main control processors are respectively connected to the control ends of their corresponding input multiplexers.

3. The clock synchronization system according to claim 2, characterized in that, The first high-speed switch responds to the presence signal of the main control processor and conducts the transmission channels from the first high-speed switch to the second high-speed switch and the third high-speed switch; The second high-speed switch synchronously responds to the presence signal of the main control processor and conducts the transmission channel from the second high-speed switch to the main control processor to transmit the clock signal output from the clock output end to the clock input end of the main control processor.

4. The clock synchronization system according to claim 3, characterized in that, The second high-speed switch responds to the presence signal of a non-main control processor and conducts the transmission channel from the second high-speed switch to the non-main control processor to transmit the clock signal to the clock input end of the non-main control processor; The third high-speed switch responds to the presence signals of the remaining two non-main control processors and respectively conducts the transmission channels from the third high-speed switch to the remaining two non-main control processors to transmit the clock signal to the clock input ends of the remaining two non-main control processors.

5. The clock synchronization system according to claim 3, characterized in that, The second high-speed switch or the third high-speed switch responds to the presence signal of any non-main control processor and conducts the transmission channel from the second high-speed switch or the third high-speed switch to the any non-main control processor to transmit the clock signal to the clock input end of the any non-main control processor.

6. The clock synchronization system according to claim 1, characterized in that, The clock synchronization system further includes: a fault repair module; The fault detection module is respectively connected to the three non-main control processors. The fault detection module is used to detect the presence states of the three non-main control processors and determine whether the three non-main control processors have faults; Control the corresponding second high-speed switch or third high-speed switch of the faulty processor to close the corresponding transmission channel in the second high-speed switch or third high-speed switch.

7. A method for clock synchronization, applied to the clock synchronization system according to any one of claims 1-6, characterized in that, Including: Transmit the clock signal of the main control processor to the first high-speed switch, and detect the in-position signal status of the main control processor and all non-main control processors; When it is detected that the in-position signal of the main control processor is valid, activate the transmission channel of the first high-speed switch; According to the validity of the in-position signals of the non-main control processors, sequentially conduct the corresponding transmission channels of the second and third high-speed switches in a cascaded order, so as to send the clock signal to the main control processor and the non-main control processors.

8. The method for clock synchronization according to claim 7, wherein, The method further includes: If the in-position signal of the non-main control processor is invalid, then control the transmission channels corresponding to the second high-speed switch or the third high-speed switch of the non-main control processor with the invalid in-position signal to be closed.

9. An electronic device, characterized in that, The electronic device includes: the clock synchronization system according to any one of claims 1-6.

10. A server, characterized in that, The server includes: the clock synchronization system according to any one of claims 1-6.

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