Voltage sag processing method and apparatus, electronic device, chip, and storage medium

Abstract

The present disclosure provides a voltage sag processing method and device, electronic equipment, a chip and a storage medium. The method is executed by a voltage sag processing system, which comprises a power management unit (PMU), a system power management interface (SPMI) and a system on chip (SOC). The method comprises: the PMU generates voltage sag information; the PMU transmits the voltage sag information to the SOC through the SPMI; and the SOC executes voltage sag protection based on the voltage sag information. The complexity of the method can be reduced, the system response speed can be improved, and the continuity of key operations and the safety of data can be ensured when voltage sag occurs.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of electronics, and particularly relates to a voltage drop processing method and device, electronic equipment, chip and storage medium. BACKGROUND

[0002] Voltage drop under low-temperature environment and large load conditions can affect the stability of mobile devices, causing performance degradation or even sudden shutdown of the devices, and affecting user experience. The existing voltage drop processing method has high complexity and slow response. SUMMARY

[0003] The present disclosure provides a voltage drop processing method, device, electronic equipment, chip and storage medium to solve the problems in the related art.

[0004] The first aspect embodiment of the present disclosure provides a voltage drop processing method, which is executed by a voltage drop processing system including a power management unit PMU, a system power management interface SPMI and a system on chip SOC. The method comprises: the power management unit PMU generates voltage drop information; the power management unit PMU transmits the voltage drop information to the system on chip SOC through the system power management interface SPMI; and the system on chip SOC performs voltage drop protection based on the voltage drop information.

[0005] In some embodiments of the present disclosure, the power management unit PMU generating the voltage drop information comprises: the power management unit PMU monitoring a device voltage; when the device voltage is lower than a drop voltage threshold, the power management unit PMU determines that a voltage drop event occurs and generates the voltage drop information.

[0006] In some embodiments of the present disclosure, performing voltage drop protection comprises: the system on chip SOC determining a key sub-module, the key sub-module being a module whose load meets a preset condition in a device to which the voltage drop processing system belongs; and the system on chip SOC reducing the working frequency of the key sub-module.

[0007] In some embodiments of the present disclosure, the method further comprises: the system on chip SOC receiving device voltage information reported by the power management unit PMU through the system power management interface SPMI; or the system on chip SOC querying the device voltage information through the system power management interface SPMI, the device voltage information being obtained by the power management unit PMU monitoring the device voltage; and when the device voltage information meets a first condition, the system on chip SOC sends indication information to the power management unit PMU through the system power management interface SPMI, the indication information indicating the power management unit PMU to delete the voltage drop information.

[0008] In some embodiments of the present disclosure, the method further includes: deleting, by the power management unit PMU, the voltage drop information when the second condition is met; and sending, by the power management unit PMU, notification information to the system on chip SOC through the system power management interface SPMI, the notification information being used to notify the system on chip that the voltage drop information has been deleted.

[0009] In some embodiments of the present disclosure, the method further includes: increasing, by the system on chip SOC, the working frequency of the key sub-module based on the notification information.

[0010] A second aspect of the present disclosure provides a voltage drop processing system, which includes: a power management unit PMU, a system power management interface SPMI, and a system on chip SOC, the power management unit PMU being configured to generate voltage drop information and transmit the voltage drop information to the system on chip SOC through the system power management interface SPMI, and the system on chip SOC being configured to perform voltage drop protection based on the voltage drop information.

[0011] In some embodiments of the present disclosure, the voltage drop processing system further includes a key sub-module.

[0012] A third aspect of the present disclosure provides an electronic device, which includes: at least one processor; and a memory connected to the at least one processor in communication, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method described in the first aspect of the present disclosure.

[0013] A fourth aspect of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to perform the method described in the first aspect of the present disclosure.

[0014] A fifth aspect of the present disclosure provides a chip, which includes: at least one processor and a communication interface, the communication interface being configured to receive a signal input into the chip or output a signal from the chip, and the processor being in communication with the communication interface and being configured to implement the method described in the first aspect of the present disclosure through a logic circuit or by executing code instructions.

[0015] In summary, the voltage drop processing method provided by the present disclosure can monitor the device voltage through the power management unit, generate voltage drop information when the voltage is lower than the voltage drop threshold, and send the voltage drop information to the system on chip SOC through the system power management interface SPMI, so that the SOC can perform protection based on the voltage drop information, and the continuity of key operations and the safety of data can be ensured when voltage drop occurs. Moreover, the complexity can be reduced and the response speed of the system to voltage drop can be improved by using the mature SPMI communication protocol.

[0016] It should be understood that the foregoing general description and the following detailed description are only examples and explanatory, and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure, and, do not limit the present disclosure.

[0018] Figure 1 A flowchart of a voltage sag processing method provided for an embodiment of the present disclosure;

[0019] Figure 2 A flowchart of a voltage sag processing method provided for an embodiment of the present disclosure;

[0020] Figure 3 A flowchart of a voltage sag processing method provided for an embodiment of the present disclosure;

[0021] Figure 4 A flowchart of a voltage sag processing method provided for an embodiment of the present disclosure;

[0022] Figure 5 An application scenario diagram of a portable battery device power supply voltage sag defense method provided for an embodiment of the present disclosure;

[0023] Figure 6 A flowchart of a portable battery device power supply voltage sag defense method provided for an embodiment of the present disclosure;

[0024] Figure 7 A timing diagram of a portable battery device power supply voltage sag defense method provided for an embodiment of the present disclosure;

[0025] Figure 8 A structural diagram of a voltage sag processing system provided for an embodiment of the present disclosure;

[0026] Figure 9 A structural diagram of an electronic device provided for an embodiment of the present disclosure;

[0027] Figure 10 A chip structure diagram provided for an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, examples of which are shown in the drawings, wherein the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present disclosure, and cannot be understood as limiting the present disclosure.

[0029] Voltage sag under low temperature environment and heavy load conditions is an important factor affecting the stability of mobile devices such as smartphones. Under low temperature conditions, the internal chemical reaction speed of the battery slows down, significantly reducing the discharge efficiency of the battery, causing the voltage to drop rapidly, which may cause the device to shut down unexpectedly before the battery is completely discharged. This phenomenon is particularly common in cold climates, which is particularly troublesome for users who use devices in outdoor or low temperature environments.

[0030] On the other hand, when the device is running under heavy load, such as performing high-performance computing or using high-power functions, the battery needs to provide higher current. This high current demand will cause the internal resistance of the battery to increase, which in turn will cause the voltage to drop. If the voltage drops below the minimum operating voltage of the device, the device may suddenly shut down or performance may be reduced.

[0031] Therefore, it is important to develop effective voltage sag prevention techniques. The development of these techniques is crucial for improving the reliability and user experience of devices in low temperature environments.

[0032] Some technical solutions have been proposed in the prior art to deal with voltage sag phenomenon, the contents of which are as follows.

[0033] 1. A voltage fluctuation compensation method and corresponding circuit are proposed, including: a voltage fluctuation detection circuit: detects the fluctuation amplitude of the supply voltage of the load circuit and feeds back to the processor. Processor: calculate the voltage correction amount according to the fluctuation amplitude, and send it to the power management unit (PMU). Power management unit (PMU): adjust the output voltage according to the correction amount.

[0034] This solution relies on the processor to calculate the voltage correction amount, which may not be fast enough to respond to rapid or severe voltage fluctuations. If the power management unit PMU does not respond quickly or accurately to the correction instruction, it may not be able to effectively prevent the problems caused by voltage sag.

[0035] 2. Use a transmission capacitor connected to the power supply as a backup power supply. When the voltage detector finds that the power supply voltage is lower than the predetermined threshold, the transmission capacitor provides power to the controller to keep it running. This method not only ensures the power supply of critical components during transient voltage sag, but also effectively reduces the size and cost of the device compared to traditional dedicated backup power supplies.

[0036] Although this solution reduces the size and cost of the device, the energy storage of the transmission capacitor may not be sufficient to support long-term voltage stabilization requirements. There are high requirements for the performance of the capacitor, which may require the use of a specific type or high-quality capacitor.

[0037] 3. A protection module is proposed, which allows current to flow from the power storage device to the load and prevents current from flowing back to the power storage device. The protection module contains a voltage drop, which ensures that when the power source is missing power, the voltage drop is bypassed through a bypass module. In addition, the protection module also has a diode function in some embodiments, which ensures that current can only flow from the power storage device to the load, but not in the opposite direction. This design provides an effective voltage drop protection solution for electronic devices or circuits with limited size.

[0038] This solution can prevent current from flowing back to the power storage device, but more protection modules may be needed in complex circuits to cover all critical paths.

[0039] 4. Solution 1 increases the risk of sudden voltage drop for mobile devices such as smartphones under low battery conditions when under heavy load, which may cause the device to reset or shut down autonomously to prevent damage, affecting user experience. To solve this problem, a sudden voltage drop protection technology is proposed, which realizes sudden voltage drop detection and performance adjustment by integrating programmable low battery state awareness logic in the power management integrated circuit (PMIC) and application processor (AP). Mainly by controlling the clock frequency to maintain system stability, thereby minimizing unstable states and improving user satisfaction. Experimental results show that this technology can significantly reduce the failure rate caused by sudden voltage drop under low battery state.

[0040] This solution may be complex to integrate and implement, requiring additional logic to be integrated in the PMIC and AP; it does not explicitly state how the PMIC's warning information is transmitted to the SOC.

[0041] Therefore, in order to solve the above problems, the present disclosure proposes a voltage drop processing method, which can actively transmit voltage drop information to the system on chip (SOC) through the system power management interface (SPMI) communication bus after the power management unit (PMU) detects the battery voltage drop. After the SOC receives the warning signal, it immediately reduces the frequency to relieve the load; after the voltage rises, the frequency is increased to restore normal load; avoid system collapse and improve power load capacity.

[0042] The specific content of the method is as follows.

[0043] Figure 1 A flowchart of a voltage drop processing method provided by an embodiment of the present disclosure is shown in FIG. 1. As shown in FIG. 1, the voltage drop processing method includes the following steps. Figure 1As shown, the method can be performed by an electronic device, and optionally, the method can be performed by a voltage dip handling system including a power management unit PMU, a system power management interface SPMI, and a system on chip SOC. The method can include the following steps.

[0044] In step 101, the power management unit PMU generates voltage dip information.

[0045] In some embodiments, the power management unit (PMU) is a power management integrated circuit that can manage power supply. For example, the power management unit PMU can monitor the device voltage. The device can be an electronic device, and optionally, an Internet of Things device that relies on integrated power management. For example, the device can be a mobile device such as a smartphone, a tablet computer, a wearable device, etc. The device includes a voltage dip handling system.

[0046] In some embodiments, when the device voltage is lower than the dip voltage threshold, the power management unit PMU can determine that a voltage dip event has occurred and generate voltage dip information. The voltage dip can be a phenomenon of reduced power discharge efficiency caused by low temperature environment or heavy load condition, etc.

[0047] In some embodiments, the dip voltage threshold described above can be a threshold value set by the actual application, and the present disclosure does not limit this.

[0048] In some embodiments, after determining that a voltage dip event has occurred, the power management unit PMU can generate voltage dip information and store it locally in the power management unit PMU.

[0049] In step 102, the power management unit PMU transmits the voltage dip information to the system on chip SOC through the system power management interface SPMI.

[0050] In some embodiments, for example, the voltage dip information transmitted by the power management unit PMU can be an error alarm code predefined by a protocol, and when the system on chip SOC receives the alarm code, it knows that a voltage dip event has occurred.

[0051] In some embodiments, the system on chip (SOC) can send its clock information to the power management unit PMU when it starts working, for example, when the device starts. The power management unit PMU can adjust its clock based on the clock information to achieve clock synchronization with the system on chip SOC, facilitating synchronous transmission of data under the same clock.

[0052] In some embodiments, the power management unit PMU can supply power for the system on chip SOC.

[0053] In some embodiments, the power management unit PMU can transmit data with the system on chip SOC through a system power management interface (SPMI), which is an interface standard designed for power management, through which communication between the system on chip SOC and multiple power management units PMU can be achieved.

[0054] In some embodiments, when the power management unit PMU communicates with the system on chip SOC through the system power management interface SPMI, the SOC side can act as the master node of the SPMI, and the PMU can act as the slave node of the SPMI, at this time, the slave node of the SPMI, i.e. the power management unit PMU, has the ability to actively initiate a write request (master write command sequence), i.e. the power management unit PMU can actively send information to the system on chip SOC, so that the power management unit PMU can quickly return critical events to the system on chip SOC.

[0055] In some embodiments, the power management unit PMU can use the above-mentioned ability to actively initiate a write request (master write command sequence) to transmit voltage drop information to the system on chip SOC.

[0056] In some embodiments, the power management unit actively uploads voltage drop information through the system power management interface SPMI, which can improve the response speed of the system on chip SOC, and the system on chip SOC does not need to query the internal information of the PMU again, reducing the permanent damage to the chip physics.

[0057] Step 103, the system on chip SOC performs voltage drop protection based on the voltage drop information.

[0058] In some embodiments, the system on chip can perform voltage drop protection based on the voltage drop information to avoid the problem of poor device stability caused by voltage drop.

[0059] In some embodiments, the system on chip SOC can determine a critical sub-module, wherein the critical sub-module is a module whose load meets a preset condition in a device to which the voltage drop processing system belongs, for example, the preset condition can be that the load is greater than or equal to a load threshold, and the load threshold can be set based on the actual application scenario, which is not limited by the present disclosure.

[0060] In the above embodiment, after receiving the voltage drop information, the system on chip SOC can first determine the modules with large loads as key sub-modules, and process these key sub-modules. Since the load is large, it may be the cause of the voltage drop. In addition, when the voltage drop occurs, the large load of the key sub-module may cause the device performance to decrease or suddenly power off, and therefore needs to be processed.

[0061] In some embodiments, the system on chip SOC can dynamically determine the key sub-module after determining the voltage drop. The system on chip can determine the module whose load meets the condition in the current state as the key sub-module. The key sub-module can include a central processing unit (CPU), an embedded neural network processing unit (NPU), a graphics processing unit (GPU), etc. For example, when playing a game, the demand for CPU is high, and the load of CPU is high. At this time, the CPU can be determined as the key sub-module.

[0062] In some embodiments, the system on chip SOC can reduce the working frequency of the key sub-module. For example, the system on chip can control the key sub-module to reduce the frequency through hardware, such as the system on chip can reduce the main clock of the key sub-module through the clock control module, that is, reduce the working frequency of the key sub-module, so as to reduce the load of the key sub-module and avoid the key sub-module from affecting the device when the voltage drop occurs.

[0063] In some embodiments, the system on chip SOC can transmit the voltage drop information to the underlying software to control the key sub-module to reduce the frequency.

[0064] In summary, the above embodiments of the present disclosure, when the voltage drop occurs, the power management unit PMU can transmit the voltage drop information to the system on chip SOC through the system power management interface SPMI. The system on chip SOC can receive the voltage drop information and perform voltage drop protection. The device can be protected when the voltage drop occurs, ensuring the continuity of key operations and the safety of data. By using the mature SPMI protocol, the development time can be reduced, no additional hardware investment is needed, the complexity of the method implementation can be reduced, and the response speed can be improved.

[0065] Figure 2 A flowchart of a voltage drop processing method provided by an embodiment of the present disclosure is shown in FIG. 1. As shown in FIG. 1, based on the embodiment shown in FIG. 2, the method can further include the following steps. Figure 2 Figure 1

[0066] ​​In step 201, the system on chip (SOC) receives device voltage information reported by the power management unit (PMU) through a system power management interface (SPMI); or the SOC queries the device voltage information through the SPMI.

[0067] In some embodiments, the device voltage information can be monitored by the PMU, and the device voltage information can include a device voltage value, a device voltage state (e.g., whether the device voltage is stable), and the like.

[0068] For example, the SOC can receive the device voltage information reported by the PMU through the SPMI, i.e., the SOC can automatically obtain the device voltage information through a pure hardware automatic process. For example, after a voltage drop event occurs, the PMU can continuously monitor the device voltage. When the device voltage is greater than a voltage recovery threshold and / or the device voltage remains stable, the PMU can transmit the device voltage information to the SOC through the SPMI by using the ability to actively initiate a write request, to notify the SOC that the device voltage has recovered.

[0069] For example, the SOC can query the device voltage information through the SPMI, i.e., the SOC can obtain the device voltage through a software process. For example, after a voltage drop event occurs, the SOC can continuously query the device voltage information monitored by the PMU through the SPMI, to obtain the device voltage information.

[0070] In step 202, when the device voltage information satisfies a first condition, the SOC sends indication information to the PMU through the SPMI.

[0071] In some embodiments, the first condition can be that the device voltage is greater than a voltage recovery threshold and / or the device voltage remains stable. The voltage recovery threshold can be different from the voltage drop threshold, and preferably, the voltage recovery threshold can be higher than the voltage drop threshold. The specific values of the voltage drop threshold and the voltage recovery threshold can be specified according to actual conditions, and the present disclosure is not limited in this regard.

[0072] In some embodiments, the first condition can be that the device voltage information is obtained by the SOC through the above-mentioned software process. When the SOC obtains the device voltage information through the above-mentioned software process, the SOC can send the indication information to the PMU through the SPMI, to instruct the PMU to delete voltage drop information through the indication information.

[0073] In some embodiments, when the system on chip SOC adopts the above-mentioned pure hardware automatic processing flow to obtain the device voltage information, the power management unit PMU can actively delete the voltage drop information when the device voltage is greater than the recovery voltage threshold and / or the device voltage remains stable, and the system on chip SOC does not need to send indication information to the power management unit PMU at this time.

[0074] In the above-mentioned embodiments, when the power management unit monitors that the device voltage is greater than the recovery voltage threshold, if it is directly determined that the device voltage recovers and the voltage drop protection state is released, the system frequency may be unstable due to unstable voltage, and system jitter phenomenon may occur. Therefore, the first condition can be that the device voltage remains stable, for example, the voltage values of the device voltage in a period of time are all greater than the recovery voltage threshold, and float within a certain interval, at this time it can be determined that the device voltage remains stable.

[0075] In some embodiments, after the device voltage information meets the first condition, the system on chip SOC can send indication information to the power management unit PMU through the system power management interface SPMI, wherein the indication information indicates that the power management unit PMU deletes the voltage drop information. That is, when the device voltage information meets the first condition, it can instruct the power management unit PMU to delete the voltage drop information and release the voltage drop protection state.

[0076] In summary, in the above-mentioned embodiments of the present application, after the system on chip SOC determines that the device voltage information meets the first condition, it can send indication information to the power management unit PMU through the system power management interface SPMI, instructing the power management unit to delete the voltage drop information. By adopting the mature SPMI communication protocol, the response speed can be improved, and no additional hardware investment is needed, so that the device state can be adjusted faster.

[0077] Figure 3 A flowchart of a voltage drop processing method provided by an embodiment of the present disclosure is shown. As shown in Figure 3 Based on the above-mentioned embodiments, the method can further include the following steps. Figure 2

[0078] Step 301, the power management unit PMU deletes the voltage drop information when the second condition is met.

[0079] ​In some embodiments, the second condition may be that the power management unit (PMU) receives an indication message sent by the system on-chip (SOC) through the system power management interface (SPMI), or the second condition may be that the PMU determines, by monitoring the device voltage, that the device voltage has exceeded the recovery voltage threshold and / or the device voltage remains stable. That is, the PMU can delete the voltage drop information by receiving an indication from the SOC, or the PMU can actively delete the voltage drop information after detecting a recovery in the device voltage.

[0080] In some embodiments, when the System-on-Chip (SOC) obtains device voltage information using the above-described software processing flow, the Power Management Unit (PMU) can clear the locally recorded voltage drop information based on the instruction information sent by the SOC.

[0081] In some embodiments, when the System-on-Chip (SoC) obtains device voltage information using the above-described pure hardware automatic processing flow, the Power Management Unit (PMU) can actively delete voltage drop information when the device voltage is greater than the recovery voltage threshold and / or the device voltage remains stable. In this case, the SoC does not need to send instruction information to the PMU.

[0082] Step 302: The Power Management Unit (PMU) sends a notification message to the System on-chip (SOC) through the System Power Management Interface (SPMI).

[0083] In some embodiments, the notification information can be used to notify the system-on-chip that voltage dip information has been deleted, and the information indicating that the deletion is complete can be used to notify the system-on-chip (SOC) that voltage dip protection is no longer required.

[0084] In some embodiments, the Power Management Unit (PMU) can transmit notification information to the System-on-Chip (SOC) via the System Power Management Interface (SPMI) based on its ability to proactively initiate write requests (masterwrite command sequence). In summary, the embodiments of this application, where the PMU clears local voltage dip information based on instruction information from the SOC and notifies the SOC via the SPMI after clearing, can reduce complexity and improve response speed by utilizing the SPMI communication protocol, enabling rapid processing after voltage recovery.

[0085] Figure 4 This is a schematic flowchart illustrating a voltage drop handling method provided in an embodiment of this disclosure. Figure 4 As shown, based on Figure 3 In the illustrated embodiment, the method may further include the following steps.

[0086] In step 401, the system on chip SOC increases the working frequency of the key sub-module based on the notification information.

[0087] In some embodiments, the system on chip SOC can increase the working frequency of the key sub-module to the normal level based on the notification information sent by the power management unit PMU. For example, the system on chip can increase the main clock of the key sub-module through the clock control module.

[0088] In some embodiments, the system on chip SOC can increase the main clock of the key sub-module through hardware control, or the system on chip SOC can transmit the notification information to the underlying software, and then control the main clock of the key sub-module through the underlying software.

[0089] In summary, the above-mentioned embodiments of the present application can adjust the frequency of the key sub-module after the voltage is increased to the normal level, restore the normal load, and can realize adaptive adjustment of the system to meet the needs of users. The system on chip SOC can quickly respond and adjust by receiving the notification information through the SPMI communication protocol.

[0090] The technical solutions of the present disclosure will be further described in detail below in combination with specific application embodiments.

[0091] The following is a defense method for power supply voltage drop of a portable battery device provided by an embodiment of the present disclosure, as shown in the figure, after the power management unit PMU detects the battery voltage drop, the voltage drop information is actively transmitted to the system SOC through the SPMI communication bus. After the SOC receives the early warning signal, the frequency is immediately reduced to relieve the load; after the voltage is increased, the frequency is increased to restore the normal load; avoid system collapse and improve the power load capacity. Figure 5

[0092] As shown in the figure, the timing chart is as shown in the figure, and the specific content of the method is as follows. Figure 6 Figure 7 As shown in the figure, the timing chart is as shown in the figure, and the specific content of the method is as follows.

[0093] 1. The system power management interface SPMI is an interface standard designed for power management, aiming to realize data communication between the SOC and multiple power management units PMU. In this architecture, the SOC end acts as the master node of SPMI, and the PMU end acts as the slave node of SPMI. It is worth noting that the SPMI slave node has the ability to actively initiate a write request (master write command sequence), so that the PMU side can quickly return the key event to the SOC.

[0094] ​​2. The function of actively initiating write requests using SPMI master, PMU can actively report key PMU events to SOC, including battery voltage drop events. When PMU detects that the battery voltage is lower than the set threshold, it will record the relevant information of the voltage drop event. Subsequently, PMU transmits the information of this voltage drop event to SOC through SPMI master write command sequence.

[0095] 3. After receiving the information about voltage drop, SOC will specifically reduce the main clock of CPU, GPU and NPU system through clock control module. At the same time, SOC will inform the software about the occurrence of the event.

[0096] 4. After the voltage drop occurs, any one of the following two processing procedures can be used to continuously monitor the voltage:

[0097] Pure hardware automatic processing procedure: PMU continuously monitors whether the battery voltage has recovered, that is, whether it is higher than the recovery threshold; after the voltage recovers, PMU actively clears the voltage drop indication signal and returns the voltage recovery information to SOC through the master write command sequence function of SPMI.

[0098] Software processing procedure: software continuously queries whether the battery voltage has recovered in PMU through SPMI, once the battery voltage is recovered, SOC actively clears the battery voltage drop signal through SPMI, and PMU notifies SOC that the battery voltage has recovered through SPMI.

[0099] 5. Finally, after detecting the above information, SOC adjusts the main clock frequency of CPU, GPU and NPU system back to normal level through clock control module.

[0100] In summary, the above examples of the present disclosure enable the system to respond to voltage abnormality in a timely manner, avoiding system reset or crash. This active management method significantly enhances the robustness of the system under unstable power supply conditions, ensuring the continuity of critical operations and the safety of data.

[0101] The mature SPMI protocol used in the scheme reduces the additional cost and time required to develop a new protocol, and also avoids adding additional hardware ports such as GPIO ports. This scheme takes advantage of existing communication protocols, thereby reducing the overall system complexity and implementation difficulty and accelerating the development process.

[0102] The scheme mainly relies on the coordination between software logic and existing hardware (PMU and SOC). The advantage of this method is that it does not require additional hardware investment, but optimizes existing resources and logic. The implementation of this strategy is relatively simple, can quickly respond to voltage changes, and is easy to integrate into the existing power management framework.

[0103] Figure 8 A structural schematic diagram of a voltage sag processing system 800 provided by an embodiment of the present disclosure is shown. As shown in the figure, the system includes: Figure 8

[0104] A power management unit PMU 810, a system power management interface SPMI 820, and a system on chip SOC 830, wherein the power management unit PMU 810 is configured to generate voltage sag information, transmit the voltage sag information to the system on chip SOC 830 through the system power management interface SPMI 820; and the system on chip SOC 830 is configured to perform voltage sag protection based on the voltage sag information.

[0105] In some embodiments, the voltage sag processing system 800 further includes a critical sub-module.

[0106] In some embodiments, the power management unit PMU 810 can also be configured to monitor a device voltage; when the device voltage is lower than a sag voltage threshold, the power management unit PMU determines that a voltage sag event occurs, and generates the voltage sag information.

[0107] In some embodiments, the system on chip SOC 830 can also be configured to determine a critical sub-module, and reduce the working frequency of the critical sub-module, wherein the critical sub-module is a module whose load meets a preset condition in a device to which the voltage sag processing system belongs.

[0108] In some embodiments, the system on chip SOC 830 can also be configured to receive device voltage information reported by the power management unit PMU through the system power management interface SPMI; or can be configured to query the device voltage information through the system power management interface SPMI, wherein the device voltage information is obtained by monitoring the device voltage by the power management unit PMU.

[0109] In some embodiments, the system on chip SOC 830 further includes a clock control module configured to perform frequency increasing or frequency decreasing operation on the critical sub-module.

[0110] In some embodiments, the system on chip SOC 830 can also be configured to, when the device voltage meets a first condition, send, by the system on chip SOC, indication information to the power management unit PMU through the system power management interface SPMI, wherein the indication information indicates the power management unit PMU to delete the voltage sag information.

[0111] ​In some embodiments, the power management unit PMU 810 can also be configured to delete the voltage sag information when the second condition is met; send, to the system on chip SOC, a notification information through the system power management interface SPMI, the notification information being used to inform the system on chip that the voltage sag information has been deleted.

[0112] In some embodiments, the system on chip SOC 830 can also be configured to, based on the notification information, increase the working frequency of the key sub-module.

[0113] In summary, the voltage sag processing system 800 can maintain the stability of the device, ensure the continuity of the key operation and the safety of the data when the voltage sag occurs by transmitting the voltage sag information to the system on chip SOC through the system power management interface SPMI when it is determined that the voltage sag occurs, and the system on chip SOC performs voltage sag protection based on the voltage sag information. The complexity of the method can be reduced and the response speed of the system can be improved by using the mature communication protocol SPMI for data transmission.

[0114] The above embodiments of the present application are introduced. In order to realize the functions of the above-mentioned method, the electronic device can include a hardware structure, a software module, and the above-mentioned functions can be realized in the form of hardware structure, software module, or hardware structure plus software module. Some of the above-mentioned functions can be executed in the form of hardware structure, software module, or hardware structure plus software module.

[0115] Figure 9 is a block diagram of an electronic device 900 for implementing the above-mentioned method according to an exemplary embodiment. For example, the electronic device 900 can be a mobile phone, a computer, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0116] Referring to Figure 9 , the electronic device 900 can include one or more of the following components: a processing component 902, a memory 904, a power supply component 906, a multimedia component 908, an audio component 910, an input / output (I / O) interface 912, a sensor component 914, and a communication component 916.

[0117] The processing component 902 generally controls the overall operations of the electronic device 900, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 902 can include one or more processors 920 to execute instructions and to complete the steps of the methods described above, in whole or in part. Moreover, the processing component 902 can include one or more modules to facilitate the interaction between the processing component 902 and other components. For example, the processing component 902 can include a multimedia module to facilitate the interaction between the multimedia component 908 and the processing component 902.

[0118] The memory 904 is configured to store various types of data to support the operations of the electronic device 900. Examples of these data include instructions for any application or method operating on the electronic device 900, contact data, phonebook data, messages, pictures, videos, and so on. The memory 904 can be implemented by any type of volatile or non-volatile storage devices or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read only memory (EEPROM), erasable programmable read only memory (EPROM), programmable read only memory (PROM), read only memory (ROM), magnetic memory, flash memory, magnetic disc or optical disc.

[0119] The power component 906 provides power to the various components of the electronic device 900. The power component 906 can include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 900.

[0120] The multimedia component 908 includes a screen providing an output interface between the electronic device 900 and a user. In some embodiments, the screen can include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes the touch panel, the screen can be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touch, swiping, and gestures on the touch panel. The touch sensor can not only sense a boundary of a touching or swiping action, but also detect duration and pressure related to the touching or swiping action. In some embodiments, the multimedia component 908 includes a front camera and / or a rear camera. The front and / or rear camera can receive external multimedia data when the electronic device 900 is in an operating mode, such as a shooting mode or a video mode. Each of the front and rear camera can be a fixed optical lens system or have a focal length and optical zoom capability.

[0121] The audio component 910 is configured to output and / or input audio signals. For example, the audio component 910 includes a microphone (MIC) that is configured to receive an external audio signal when the electronic device 900 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 904 or transmitted via the communication component 916. In some embodiments, the audio component 910 also includes a speaker for outputting audio signals.

[0122] The I / O interface 912 provides an interface between the processing component 902 and peripheral interface modules, which can be a keypad, a click wheel, buttons, and the like. The buttons can include, but are not limited to, a home button, a volume button, a start button, and a lock button.

[0123] The sensor component 914 includes one or more sensors for providing status assessments of various aspects of the electronic device 900. For example, the sensor component 914 can detect an open / closed position of the electronic device 900, relative positioning of components, such as a display and a keypad of the electronic device 900, a change of position of the electronic device 900 or a component of the electronic device 900, presence or absence of user contact with the electronic device 900, orientation or acceleration / deceleration / g-force and temperature of the electronic device 900. The sensor component 914 can include a proximity sensor configured to detect presence of a nearby object without any physical touch. The sensor component 914 can also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor component 914 can also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0124] The communication component 916 is configured to facilitate wired or wireless communication between the electronic device 900 and other devices. The electronic device 900 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, 4G LTE, 5G NR (New Radio), or a combination thereof. In an example embodiment, the communication component 916 receives broadcast signals or broadcast-related information from an external broadcasting management system via a broadcast channel. In an example embodiment, the communication component 916 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technology.

[0125] In an example embodiment, the electronic device 900 can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, micro-controllers, microprocessors, or other electronic elements for executing the above-described methods.

[0126] In an example embodiment, a non-transitory computer-readable storage medium including instructions, such as the memory 904 including instructions, is also provided, which can be executed by the processor 920 of the electronic device 900 to complete the above-described methods. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0127] Embodiments of the present disclosure also provide a non-transitory computer-readable storage medium storing computer instructions, where the computer instructions are used to cause a computer to execute the methods described in the above embodiments of the present disclosure.

[0128] Embodiments of the present disclosure also provide a communication system including a terminal and a network device, the terminal is used to implement the method described in the first aspect of the present disclosure, and the network device is used to implement the method described in the second aspect of the present disclosure.

[0129] In some embodiments, the above communication system further includes a console, which can send modification instructions to the terminal, control the filtering information used by the terminal, and the like.

[0130] Figure 10 FIG. 9 is a structural schematic diagram of a chip 900 for implementing the above-described method according to an example embodiment. Referring to FIG. 9, Figure 10 The chip 1000 includes a communication interface 1001 and at least one processor 1002, the communication interface 1001 is used to receive a signal input into the chip 1000 or output from the chip 1000, and the processor 1002 communicates with the communication interface 801 and implements the methods described in the above embodiments of the present disclosure through logic circuits or execution of code instructions.

[0131] It is to be understood that the terms "first", "second", and the like, used in the description and the claims of the present disclosure as well as the foregoing drawings signify meanings that are used to distinguish like objects and do not necessarily signify a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all the embodiments consistent with the present disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0132] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example" or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the present specification, the exemplary description of the above terms does not necessarily mean the same embodiment or example. Also, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in at least one embodiment or example.

[0133] Any process or method descriptions or descriptions of the flow diagrams in the flow charts described herein and elsewhere can be understood as representing code modules, segments, or portions of code which include one or more executable instructions for performing specific logic functions or steps in the process, and that the various systems described herein can include one or more circuits, such as one or more processors, that include one or more modules, segments, or portions of code for performing the steps described. It is therefore to be understood that the preferred embodiments of the present disclosure can include additional or fewer processes or methods, as well as the possibility of a different order of the steps, as would be understood by those skilled in the art. The various embodiments of the present disclosure can be implemented in software, hardware, or a combination thereof.

[0134] The logic and / or steps represented in the flowcharts and / or described herein, for example, can be considered as a sequence of instructions to implement logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, apparatus, or device, such as a computer-based system, a system including a processing module, or other systems that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For purposes of this specification, a "computer-readable medium" can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer-readable medium can be a computer- readable storage medium or a computer-readable signal medium. The computer-readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include the following: an electrical connection having at least one wire (conventional electrical circuits), a portable computer diskette (magnetic), a RAM (random access memory), a ROM (read-only memory), an EPROM (erasable programmable ROM), an EEPROM (electrically erasable programmable ROM), and a portable compact disc read-only memory (CD-ROM). In addition, the computer-readable medium can even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, for example, via the optical scanner of a device or device, then compiled, interpreted, or otherwise processed in a suitable manner, if necessary, and stored in a computer memory.

[0135] It should be understood that aspects of the application can be implemented in hardware, software, firmware or combinations thereof. In the above embodiments, various steps or methods can be implemented in software or firmware that is stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any of the following technologies, known in the art, or their combinations can be used: discrete logic circuitry having logic gates for implementing logic functions on data signals, application specific integrated circuits having appropriate combinational logic gates, programmable gate arrays (PGA), field programmable gate arrays (FPGA), and the like.

[0136] Those skilled in the art can understand that all or part of the steps carried out by the above-mentioned embodiment method can be completed by programs instructing related hardware, and the programs can be stored in a computer-readable storage medium. When the programs are executed, they include one or a combination of the steps of the method embodiment.

[0137] In addition, each function unit in each embodiment of the present application can be integrated in one processing module, or each unit can exist physically independently, or two or more units can be integrated in one module. The integrated module can be realized in the form of hardware, or in the form of software function module. When the integrated module is realized in the form of software function module and sold or used as an independent product, it can also be stored in a computer readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0138] Although the embodiments of the present application have been shown and described above, it should be understood by those skilled in the art that the above embodiments are exemplary and cannot be construed as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

Claims

1. A voltage sag processing method, characterized by, The method is executed by a voltage drop processing system, the voltage drop processing system comprising a power management unit PMU, a system power management interface SPMI, a system on chip SOC, the method comprising: The power management unit PMU generates voltage drop information; The power management unit PMU transmits the voltage drop information to the system on chip SOC through the system power management interface SPMI; The system on chip SOC performs voltage drop protection based on the voltage drop information, the performing voltage drop protection comprising reducing the working frequency of a critical sub-module, the critical sub-module comprising a module in a device to which the voltage drop processing system belongs and whose load meets a preset condition; The power management unit PMU deletes the voltage drop information when a second condition is met; The power management unit PMU sends notification information to the system on chip SOC through the system power management interface SPMI, the notification information being used to notify the system on chip that the voltage drop information has been deleted; The system on chip SOC increases the working frequency of the critical sub-module based on the notification information.

2. The method of claim 1, wherein, The power management unit PMU generates voltage drop information, comprising: The power management unit PMU monitors device voltage; When the device voltage is lower than a drop voltage threshold, the power management unit PMU determines that a voltage drop event occurs and generates the voltage drop information.

3. The method of claim 1, wherein, The method further comprises: The system on chip SOC receives device voltage information reported by the power management unit PMU through the system power management interface SPMI; Or, The system on chip SOC queries the device voltage information through the system power management interface SPMI, the device voltage information being obtained by the power management unit PMU monitoring device voltage; When the device voltage information meets a first condition, the system on chip SOC sends indication information to the power management unit PMU through the system power management interface SPMI, the indication information instructing the power management unit PMU to delete the voltage drop information.

4. A voltage drop processing system, the voltage drop processing system comprising a power management unit PMU, a system power management interface SPMI, a system on chip SOC, The power management unit PMU is configured to generate voltage drop information and transmit the voltage drop information to the system on chip SOC through the system power management interface SPMI; The system on chip SOC is configured to perform voltage drop protection based on the voltage drop information, the performing voltage drop protection comprising reducing the working frequency of a critical sub-module, the critical sub-module comprising a module in a device to which the voltage drop processing system belongs and whose load meets a preset condition; The power management unit PMU deletes the voltage drop information when a second condition is met; The power management unit PMU sends notification information to the system on chip SOC through the system power management interface SPMI, the notification information being used to notify the system on chip that the voltage drop information has been deleted; The system on chip (SOC) increases the working frequency of the key sub-module based on the notification information.

5. The system of claim 4, wherein the voltage sag handling system further comprises the key sub-module.

6. An electronic device, comprising: Comprising: at least one processor; and a memory in communication with the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-3.

7. A non-transitory computer-readable storage medium having stored thereon computer instructions, wherein, The computer instructions are for causing a computer to perform the method of any one of claims 1-3.

8. A chip, characterized by Comprising at least one processor and a communication interface; the communication interface is used to receive the signal input into the chip or output from the chip, the processor is in communication with the communication interface and realizes the method as claimed in any one of claims 1 to 3 through logic circuit or execution of code instructions.

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