Semiconductor device and master controller

Abstract

The invention provides a semiconductor device and a main controller, and relates to the technical field of storage, the method comprises the following steps: receiving a plurality of host queues sent by a plurality of hosts, the plurality of host queues comprising a plurality of submission queues and a plurality of completion queues; determining at least one first submission queue in the plurality of submission queues, and obtaining a first read-write request in the at least one first submission queue; the first read-write request is processed through a memory, processed first processing data are stored in a first completion queue in a plurality of completion queues, the first completion queue comprises a completion queue corresponding to a first submission queue, and the read-write requests in the queues sent by the hosts are processed through a main controller. The concurrency of system access is improved, each read-write request does not need to be sorted in hardware, and the access efficiency and the access speed are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technologies, and particularly to a semiconductor device and a host controller. Background Art

[0002] With the development of computer applications and storage technologies, the requirements for storage devices are also getting higher and higher. Traditional storage technologies can no longer meet the needs of modern applications, especially in the case of processing large-scale data. To solve this problem, a Universal Flash Storage (UFS) has been designed. UFS (Universal Flash Storage) is a storage specification released by JEDEC, the global leader in the development of microelectronics industry standards. It has the advantages of high performance, low power consumption, high reliability, etc., and is widely used in fields such as embedded systems, mobile devices, and servers. However, with the continuous development of computer systems, higher requirements are also put forward for the access speed and concurrency of UFS host controllers.

[0003] In the related art, the UFS host controller adopts a single-queue access method, stores all read and write requests in the queue in the order of first in first out (FIFO), and then processes the read and write requests one by one in order, which limits the concurrency of the UFS host controller and reduces the access efficiency and access speed. Summary of the Invention

[0004] The present disclosure provides a semiconductor device and a host controller to solve the problem of access concurrency limitation in the related art. By processing the read and write requests in multiple queues sent by multiple hosts through the host controller, the concurrency of system access is improved, and each read and write request does not need to be sorted in hardware, thereby improving the access efficiency and access speed.

[0005] In a first aspect embodiment of the present disclosure, a semiconductor device is proposed. The semiconductor device includes: multiple hosts, a host controller, a memory, and a system memory; the multiple hosts are connected to the host controller, and the host controller processes the host queues sent by the multiple hosts to obtain first read and write requests; the host controller sends the first read and write requests to the memory by being connected to the memory, so that the memory processes the first read and write requests and sends the first processed data obtained after processing to the host controller; the system memory is connected to the main controller and is used to store the first read and write requests.

[0006] In some embodiments of the present disclosure, the host controller is configured to receive multiple host queues sent by multiple hosts, the multiple host queues include multiple submission queues and multiple completion queues; determine at least one first submission queue among the multiple submission queues, and obtain the first read and write requests in at least one first submission queue.

[0007] In some embodiments of the present disclosure, the memory is used to process a first read / write request and send the processed first processed data to the host controller, so as to store the first processed data into a first completion queue among multiple completion queues, and the first completion queue includes the completion queue corresponding to the first submission queue.

[0008] In some embodiments of the present disclosure, the host controller is connected to multiple hosts, and reports a completion interrupt notification in the host controller to a first host among the multiple hosts. The first host includes the host corresponding to the first submission queue, and the completion interrupt notification is used to notify the first host to process the first processed data in the first completion queue.

[0009] In some embodiments of the present disclosure, multiple hosts are connected to the host controller, determine an initialization host among the multiple hosts, and perform a first initialization process on the storage parameters in the host controller through the initialization host. The access privilege of the initialization host is the highest.

[0010] In some embodiments of the present disclosure, the host controller is used to determine the priority levels of multiple submission queues according to a preset priority rule and the priority identifiers corresponding to the multiple submission queues; traverse the multiple submission queues according to the priority levels to determine at least one first submission queue; traverse at least one first submission queue, and sequentially obtain a first read / write request from at least one first submission queue.

[0011] In some embodiments of the present disclosure, the host controller is used to traverse multiple submission queues according to a preset loop rule, and sequentially determine at least one first submission queue; traverse at least one first submission queue, and sequentially obtain a first read / write request from at least one first submission queue.

[0012] In some embodiments of the present disclosure, the host controller is connected to multiple hosts, and in response to the hardware error information of the host controller, reports the error interrupt information corresponding to the hardware error information to the multiple hosts; the multiple hosts clear the first read / write request; the initialization host performs a second initialization process on the storage parameters in the host controller.

[0013] In some embodiments of the present disclosure, multiple hosts are connected to the memory. The multiple hosts process the first processed data through an interrupt processing algorithm and clear the first read / write request in multiple submission queues; the initialization host clears the unprocessed first read / write request in the storage queue in the memory.

[0014] A second aspect embodiment of the present disclosure proposes a main controller, which includes: a plurality of register groups, a hardware lock unit, and an interrupt mapping unit; the plurality of register groups are respectively connected to a corresponding plurality of hosts, and the plurality of register groups are used to receive a plurality of host queues sent by the plurality of hosts, and the plurality of host queues include a plurality of submission queues and a plurality of completion queues; the hardware lock unit is connected to the plurality of register groups, and is used to determine at least one first submission queue among the plurality of submission queues, obtain a first read / write request in the at least one first submission queue, and send the first read / write request to the memory; the interrupt mapping unit is connected to the plurality of hosts, and reports a completion interrupt notification to a first host among the plurality of hosts, and the first host includes the host corresponding to the first submission queue, and the completion interrupt notification is used to notify the first host to process first processing data in the first completion queue.

[0015] In some embodiments of the present disclosure, the hardware lock unit is configured to determine the priority levels of the plurality of submission queues according to a preset priority rule and the priority identifiers corresponding to the plurality of submission queues; traverse the plurality of submission queues according to the priority levels to determine at least one first submission queue; traverse the at least one first submission queue, and sequentially obtain a first read / write request from the at least one first submission queue.

[0016] In some embodiments of the present disclosure, the hardware lock unit is configured to traverse the plurality of submission queues according to a preset cyclic rule to sequentially determine at least one first submission queue; traverse the at least one first submission queue, and sequentially obtain a first read / write request from the at least one first submission queue.

[0017] In some embodiments of the present disclosure, the interrupt mapping unit is configured to respond to a hardware error message in the main controller and report error interrupt information corresponding to the hardware error message to the plurality of hosts.

[0018] In summary, according to the semiconductor device and the main controller proposed by the present disclosure, by receiving a plurality of host queues sent by a plurality of hosts, the plurality of host queues including a plurality of submission queues and a plurality of completion queues; determining at least one first submission queue among the plurality of submission queues and obtaining a first read / write request in the at least one first submission queue; processing the first read / write request through a memory in the semiconductor device and storing the processed first processing data in a first completion queue among the plurality of completion queues, the first completion queue including the completion queue corresponding to the first submission queue, the read / write requests in the plurality of queues sent by the plurality of hosts are processed by the main controller, the concurrency of system access is improved, and each read / write request does not need to be sorted in hardware, thereby improving the access efficiency and access speed.

[0019] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. Description of the Drawings

[0020] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments in accordance with the present disclosure, and are used together with the specification to explain the principles of the present disclosure, and do not constitute an undue limitation to the present disclosure.

[0021] Figure 1 A schematic diagram of a traditional main controller provided for an embodiment of the present disclosure;

[0022] Figure 2 A schematic diagram of a specific main controller in the related art provided for an embodiment of the present disclosure;

[0023] Figure 3 A schematic diagram of a specific main controller in the related art provided for an embodiment of the present disclosure;

[0024] Figure 4 A schematic diagram of a semiconductor device provided for an embodiment of the present disclosure;

[0025] Figure 5 An architecture diagram of a specific semiconductor device provided for an embodiment of the present disclosure;

[0026] Figure 6 A schematic diagram of a main controller provided for an embodiment of the present disclosure;

[0027] Figure 7 An architecture diagram of a specific main controller provided for an embodiment of the present disclosure;

[0028] Figure 8 A flowchart of an access method provided for an embodiment of the present disclosure;

[0029] Figure 9 A flowchart of an access method provided for an embodiment of the present disclosure;

[0030] Figure 10 A schematic structural diagram of an access device provided for an embodiment of the present disclosure;

[0031] Figure 11 A schematic structural diagram of an electronic device provided for an embodiment of the present disclosure;

[0032] Figure 12 A schematic structural diagram of a chip provided for an embodiment of the present disclosure. Detailed Description of the Embodiment

[0033] The embodiments of the present disclosure will be described in detail below. The examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The implementation described below with reference to the accompanying drawings.

[0034] With the development of computer applications and storage technologies, the requirements for storage devices are also getting higher and higher. Traditional storage technologies can no longer meet the needs of modern applications, especially in the case of processing large-scale data. To solve this problem, a Universal Flash Storage (UFS) host controller is designed. UFS (Universal Flash Storage) is a storage specification released by JEDEC, the global leader in the development of microelectronics industry standards, which has the advantages of high performance, low power consumption, high reliability, etc., and is widely used in embedded systems, mobile devices, servers and other fields. However, with the continuous development of computer systems, higher requirements are also put forward for the access speed and concurrency of UFS host controllers.

[0035] As Figure 1 shown in the schematic diagram of the traditional host controller, the traditional access device, that is, the transport protocol module such as the UFS host controller only supports one host for access at the same time. In a complex system with multiple hosts or a virtualized scenario, software needs to queue the requirements of each host and then use one of the hosts to communicate with the UFS host controller, and then return the data to each host, which will undoubtedly affect the throughput of the system read operation. Therefore, from a hardware perspective, modifying the traditional UFS IP to support multi-host concurrent access can improve the throughput of the system read operation in a virtualized or multi-host scenario.

[0036] As Figure 2 、 Figure 3 shown, it is the schematic diagram of the specific host controller in the related technology. In the related technology, the UFS host controller completes the processing details of multi-host concurrent access, stores the read and write requests from each host in the host controller in the form of a queue, and records the host number that issues each request. When the host controller completes the request, it issues the completion interrupt to different hosts according to the host number carried in the incoming request.

[0037] It can be seen that the UFS host controller in the related technology adopts a single-queue access method, stores all read and write requests in the queue in the order of first in first out (FIFO), and then processes the read and write requests one by one in order, which easily leads to the situation that some read and write requests come from high-performance hosts and can only wait until the previous read and write requests are processed before being processed, limiting the concurrency of the UFS host controller. At the same time, since all hosts share the same queue, the single-queue access method cannot perform independent bandwidth control on the read and write requests of each host, easily resulting in the situation that the read and write requests of some hosts occupy too much bandwidth resources, while other hosts cannot obtain sufficient bandwidth resources, reducing the access efficiency and access speed.

[0038] To solve the problems existing in the related art, the present disclosure proposes an access method. By concurrently processing queue information sent by multiple hosts, multiple hosts do not need to synchronize through software when accessing the UFS main controller for data reading and writing operations. Instead, the hardware sorts and arbitrates read and write requests from each host. This improves the efficiency of concurrent access to the UFS main controller in scenarios with multiple hosts or multiple virtual machines, increases the throughput of system read and write operations, and makes the access of each host to the UFS main controller exclusive in terms of hardware technology.

[0039] The access method proposed by the present disclosure can be applied to fields such as servers, embedded systems, mobile devices, and high-performance computing. Specifically, it can be applied to various scenarios that require high-speed data storage and processing, and is not limited in the embodiments of the present disclosure.

[0040] The following will introduce the access method provided by the present application in detail with reference to the accompanying drawings.

[0041] Figure 4 It is a schematic diagram of a semiconductor device provided by an embodiment of the present disclosure. As Figure 4 shown, the semiconductor device includes:

[0042] Multiple hosts, a main controller, a memory, and a system memory; multiple hosts are connected to the main controller, and the main controller processes the host queues sent by multiple hosts to obtain a first read / write request; the main controller sends the first read / write request to the memory by connecting to the memory, so that the memory processes the first read / write request and sends the first processed data obtained after processing to the main controller; the system memory is connected to the main controller and is used to store the first read / write request.

[0043] In the embodiments of the present disclosure, the main controller is used to receive multiple host queues sent by multiple hosts, and the multiple host queues include multiple submission queues and multiple completion queues; determine at least one first submission queue among the multiple submission queues, and obtain the first read / write request in at least one first submission queue.

[0044] In the embodiments of the present disclosure, the memory is used to process the first read / write request and send the first processed data after processing to the main controller, so as to store the first processed data in the first completion queue among the multiple completion queues, and the first completion queue includes the completion queue corresponding to the first submission queue.

[0045] In the embodiments of the present disclosure, the main controller reports the completion interrupt notification in the main controller to the first host among the multiple hosts by connecting to the multiple hosts. The first host includes the host corresponding to the first submission queue, and the completion interrupt notification is used to notify the first host to process the first processed data in the first completion queue.

[0046] In an embodiment of the present disclosure, multiple hosts are connected to a host controller to determine an initialization host among the multiple hosts, and the initialization host performs a first initialization process on the storage parameters in the host controller. The access privilege of the initialization host is the highest.

[0047] In an embodiment of the present disclosure, the host controller is configured to determine the priority levels of multiple submission queues according to a preset priority rule and the priority identifiers corresponding to the multiple submission queues; traverse the multiple submission queues according to the priority levels to determine at least one first submission queue; and traverse the at least one first submission queue to sequentially obtain first read / write requests from the at least one first submission queue.

[0048] In an embodiment of the present disclosure, the host controller is configured to traverse multiple submission queues according to a preset loop rule to sequentially determine at least one first submission queue; and traverse the at least one first submission queue to sequentially obtain first read / write requests from the at least one first submission queue.

[0049] In an embodiment of the present disclosure, the host controller is connected to multiple hosts, and in response to the hardware error information of the host controller, reports the error interrupt information corresponding to the hardware error information to the multiple hosts; the multiple hosts clear the first read / write requests; and the initialization host performs a second initialization process on the storage parameters in the host controller.

[0050] In an embodiment of the present disclosure, multiple hosts are connected to a memory. The multiple hosts process first processing data through an interrupt processing algorithm and clear the first read / write requests in the multiple submission queues; the initialization host clears the unprocessed first read / write requests in the storage queue in the memory.

[0051] In an alternative embodiment of the present disclosure, as Figure 5 shown in the architecture diagram of the specific semiconductor device, the present disclosure is applicable to the scenario of multi-host concurrent access to a UFS host controller. Figure 5 Host 1 to Host N in [the figure] refer to multiple hosts. The multiple hosts may refer to hosts in different internal shared domains, may refer to physical hosts or multiple virtual hosts, or may be both present at the same time. UFS Controller is the host controller, UFS device is the memory, and RAW is the system memory. In the design of multiple queues, multiple hosts can access the UFS host controller for data reading and writing without software synchronization, and can access the hardware simultaneously. The hardware sorts and arbitrates the requests from each host.

[0052] In summary, through the semiconductor device of the present disclosure, the host controller can process the read / write requests in multiple queues sent by multiple hosts, improve the concurrency of system access, and each read / write request does not need to be sorted in the hardware, thereby improving the access efficiency and access speed.

[0053] Figure 6 A schematic diagram of a main controller provided by an embodiment of the present disclosure. As Figure 6 shown, the main controller includes:

[0054] Multiple register groups, a hardware lock unit, and an interrupt mapping unit; the multiple register groups are respectively connected to corresponding multiple hosts, and the multiple register groups are used to receive multiple host queues sent by the multiple hosts, and the multiple host queues include multiple submission queues and multiple completion queues; the hardware lock unit is connected to the multiple register groups, and is used to determine at least one first submission queue among the multiple submission queues, obtain a first read / write request in at least one first submission queue, and send the first read / write request to the memory; the interrupt mapping unit is connected to the multiple hosts, and reports a completion interrupt notification to a first host among the multiple hosts, and the first host includes the host corresponding to the first submission queue, and the completion interrupt notification is used to notify the first host to process first processing data in the first completion queue.

[0055] In an embodiment of the present disclosure, the hardware lock unit is used to determine the priority sizes of the multiple submission queues according to a preset priority rule and the priority identifiers corresponding to the multiple submission queues; according to the priority sizes, traverse the multiple submission queues to determine at least one first submission queue; traverse at least one first submission queue, and sequentially obtain a first read / write request from at least one first submission queue.

[0056] In an embodiment of the present disclosure, the hardware lock unit is used to traverse the multiple submission queues according to a preset loop rule to sequentially determine at least one first submission queue; traverse at least one first submission queue, and sequentially obtain a first read / write request from at least one first submission queue.

[0057] In an embodiment of the present disclosure, the interrupt mapping unit is used to respond to a hardware error message in the main controller and report an error interrupt message corresponding to the hardware error message to the multiple hosts.

[0058] In an optional embodiment of the present disclosure, as Figure 7 shown, the dashed box part is the architecture diagram of the specific main controller. By designing multiple register groups in the present disclosure, each host accesses the corresponding register group, which can improve the concurrency of the system and the throughput of the read requests of the multiple hosts.

[0059] Referring to Figure 7 , it is the hardware part designed for the present disclosure, and the rest is the basic controller of UFS4.0.

[0060] The hardware part designed for the present disclosure includes three components, namely multiple groups of register groups, a hardware lock unit, and an interrupt mapping unit.

[0061] For multiple register groups, each group of registers is mapped to the read / write space of a different host. Each host performs read / write operations on different register groups without software locking. Meanwhile, based on traditional registers, the present disclosure also adds some registers related to multiple hosts, mainly including: multi host enable register, multi-host controller Laddr & multi-host controller Uaddr, and multi host config register.

[0062] The format of the multi host enable register is shown in Table 1:

[0063] host enable(1bit) host num(31bit)

[0064] Table 1

[0065] The multi host enable register is used to enable or disable the multi-host function. When writing 1, it indicates enabling the multi-host function; when writing 0, it indicates disabling the multi-host function. Host num represents the number of hosts that need to access the UFS main controller simultaneously in the current system.

[0066] The multi-host controller Laddr & multi-host controller Uaddr are used to store the initial address of the multi host config register. After the address is allocated by software, it needs to be filled into this register, which supports a 64-bit address space.

[0067] The format of the multi host config register is shown in Table 2:

[0068] host id(16bit) queue offset(8bit) queue num(8bit)

[0069] Table 2

[0070] The multi host config register is used to store the configuration information of each host. Among them, the Host id is filled with the host ID by software, the Queue offset represents the starting ID of the queue used by the current host, and the Queue num represents the number of queues used by the current host.

[0071] It should be noted that only the trusted unit of the system (which can be the secure mode of one of the multiple hosts) has the write permission for the newly added registers above. This unit is responsible for collecting the number and requirements of the multiple hosts in the system and filling the information into the multi-host control register. The remaining hosts cannot access these newly added registers. Additionally, after a certain host writes to its own register set, the registers that can be read and written by the main controller will be synchronously updated to the register sets of other hosts. This design can ensure data consistency and synchronization.

[0072] For the hardware lock unit (hw semaphore unit), it mainly serializes the concurrent access of multiple hosts to multiple groups of registers, ensuring that each read and write access can be atomically sent to the UFS main controller. For example, for UIC cmd, it needs to pass through the registers related to the UIC Command Register of UFS. This hardware lock can ensure the serial execution of each UIC cmd from different hosts, without the need for software to maintain the order. Atomicity means that once a read and write operation starts, it will not be interrupted or interfered with by other operations until the current read and write operation is completely executed. UIC cmd is the Unified In-Memory Command, which is a command used to manage the Unified Storage System.

[0073] For the interrupt mapping unit, it is used to remap the interrupt information reported by the core unit of the UFS main controller. The UFS main controller reports the interrupt identifier (queue id) of this interrupt to the interrupt mapping unit. The interrupt mapping unit finds the corresponding host id (host identifier) by querying the internal interrupt mapping table (host–queue id table), that is, determines the corresponding host, and sends this interrupt to the interrupt main controller of the corresponding host.

[0074] In summary, for the method of the present disclosure, the present disclosure improves the traditional UFS multi-host main controller by combining the latest multi-queue technology of UFS4.0, enabling the read and write requests between the hosts of the multi-host system to be concurrently sent to the storage device. Compared with the prior art, the system concurrency is greatly improved, and the throughput of the multi-host read and write requests can be increased. In terms of usage scenarios, it can be used for the concurrent access of big and small cores in a mobile phone to the UFS memory. When the big core is sleeping, the small core can perform garbage collection or disk defragmentation on the file system, thereby achieving the purpose of reducing power consumption. In a vehicle-mounted computer, it can be used for multiple virtual hosts to concurrently access the storage device, simplifying the software design of the system and improving the processing efficiency of the system's read and write requests.

[0075] Figure 8The flowchart of an access method provided by an embodiment of the present disclosure. As Figure 8 shown, the access method includes steps 101-103.

[0076] Step 101, receiving multiple host queues sent by multiple hosts, where the multiple host queues include multiple submission queues and multiple completion queues.

[0077] In an embodiment of the present disclosure, the UFS host controller can receive multiple host queues sent by multiple hosts.

[0078] The multiple hosts specifically may refer to hosts in different internal shared domains, which may be multiple physical hosts, multiple virtual hosts, or both at the same time. Different internal shared domains mean that different networks or computer systems can share and exchange data and resources, but they are logically or physically isolated. Therefore, hosts in different internal shared domains need to comply with corresponding network security rules and protocols to ensure the security and reliability of data.

[0079] The multiple host queues refer to message queues sent by multiple hosts to the UFS host controller. The host queue is used to store read / write requests corresponding to multiple hosts. Specifically, when multiple hosts send read / write requests, they pack the data format used by the read / write requests according to a preset storage standard and put them into the message queue corresponding to the host. In the present disclosure, the preset storage standard may be a storage protocol for standardizing data interaction between the host and the UFS host controller, which may include UFS3.0 or UFS4.0. In the present disclosure, UFS4.0 may be taken as an example.

[0080] The multiple host queues are divided into multiple submission queues and multiple completion queues according to a preset storage standard. The submission queue and the completion queue are two important queues in the UFS4.0 protocol. The submission queue is used for the host to submit read / write requests to the UFS host controller. When the host needs to send a read / write request to the UFS device, it will put the read / write request into the submission queue. The completion queue is used to store the processed data after the read / write request is processed. When the memory finishes processing the read / write request, it will store the processed read / write request (i.e., the processed data) in the completion queue. In the present disclosure, by dividing the host queue into two parts, the submission queue and the completion queue, it is possible to better perform parallel processing on the host queues sent by multiple hosts and improve the concurrency of access.

[0081] In addition, it should be noted that before the UFS host controller receives the multiple host queues sent by multiple hosts, it is necessary to perform initialization processing on the UFS host controller through multiple hosts.

[0082] Step 102: Determine at least one first submission queue among multiple submission queues, and obtain first read / write requests in at least one first submission queue.

[0083] In an embodiment of the present disclosure, the UFS host controller may determine at least one first submission queue through the priority rule in multiple submission queues, manage and schedule read / write requests in at least one first submission queue, obtain first read / write requests, and send the first read / write requests to the memory in the host controller for processing.

[0084] In the present disclosure, at least one first submission queue refers to the submission queue with the highest current priority determined by the UFS host controller according to a preset priority rule, or may also be the submission queues sequentially selected according to a preset cyclic rule. The first submission queue may be one or multiple, which is specifically determined according to the actual situation and is not limited in the embodiments of the present disclosure.

[0085] Step 103: Process the first read / write requests through the memory in the semiconductor device, and store the processed first processed data into a first completion queue among multiple completion queues, where the first completion queue includes the completion queue corresponding to the first submission queue.

[0086] In an embodiment of the present disclosure, the host controller may be a UFS host controller. The memory in the semiconductor device is connected to the host controller. After receiving the first read / write requests, it processes the first read / write requests and stores the processed first processed data (i.e., completion data) into the first completion queue.

[0087] A read / write request refers to a request for reading and writing data in the memory of the semiconductor device, that is, an IO read / write request. IO refers to input and output (Input / Output). For a read request, data needs to be read from the memory for further processing or operation. When reading data, the initiator needs to provide the address of the specific data item or data block to be read. For a write request, the initiator also needs to provide the data to be written and the address to be written. Therefore, the read / write request includes address information. The memory in the semiconductor device can find the address in the first extraction queue that wants to perform a read or write operation through the first read / write request, and perform data reading or writing operations according to this address.

[0088] In addition, when storing the first processed data into the first completion queue, a completion interrupt notification may be sent to the first host corresponding to the current first extraction queue at the same time to notify the software in the first host to process the first processed data.

[0089] In summary, according to the access method proposed in the present disclosure, by receiving multiple host queues sent by multiple hosts, the multiple host queues include multiple submission queues and multiple completion queues; determining at least one first submission queue among the multiple submission queues, and obtaining a first read / write request in the at least one first submission queue; processing the first read / write request through a memory in a semiconductor device, and storing the processed first processed data into a first completion queue among the multiple completion queues, the first completion queue includes the completion queue corresponding to the first submission queue, and processing read / write requests in multiple queues sent by multiple hosts through a UFS host controller, improving the concurrency of system access, and each read / write request does not need to be sorted in hardware, improving the access efficiency and access speed.

[0090] Based on Figure 8 the embodiments shown, Figure 9 further shows a flowchart of an access method proposed in the present disclosure. Figure 9 Based on Figure 8 the embodiments shown, steps 101, 102, and 103 are further defined. In Figure 9 the embodiments shown, before step 101, steps 201 and 202 are included, step 102 includes step 203, and after step 103, step 206 is included. As Figure 9 shown, the method includes the following steps:

[0091] Step 201, determining an initialization host among multiple hosts, and the initialization host has the highest access authority.

[0092] In the embodiments of the present disclosure, since the initialization of the UFS host controller only needs to be performed once, therefore, in the present disclosure, only one host among multiple hosts can be used to initialize the UFS host controller, and other hosts do not need to initialize the UFS host controller. In the present disclosure, the initialization host for initializing the UFS host controller can be determined according to the access authority of multiple hosts. Among them, the initialization host has the highest access authority.

[0093] Specifically, by judging the access authority of multiple hosts, the initialization host with the highest access authority is determined. The highest access authority means the least access restrictions. The initialization host can also be any one of multiple hosts. In the present disclosure, based on security considerations, the host with the highest access authority is selected as the initialization host.

[0094] Step 202, performing a first initialization process on the storage parameters in the host controller based on the initialization host.

[0095] In an embodiment of the present disclosure, the storage parameters may include parameters in each device in the UFS host controller and the operation logic of each device. Each device may include a register bank and a memory in the UFS host controller. In the present disclosure, an initialized UFS host controller is obtained through a first initialization process for subsequent parallel access processing.

[0096] Step 203: Receive multiple host queues sent by multiple hosts. The multiple host queues include multiple submission queues and multiple completion queues.

[0097] In an alternative embodiment of the present disclosure, when each host sends a read / write request, it is necessary to pack the data format used in the read / write request according to the preset storage standard of the UFS4.0 standard and put it into the host queue corresponding to each host. The queue format of the host queue is divided into a submission queue and a completion queue according to the UFS4.0 protocol standard.

[0098] Step 203 has the same or similar functions as the above step 101, and its implementation manner can be referred to the above embodiment and will not be elaborated here.

[0099] Step 204: Determine at least one first submission queue among the multiple submission queues according to the preset priority rule and the priority identifier corresponding to the multiple submission queues, and obtain the first read / write request in at least one first submission queue.

[0100] In an embodiment of the present disclosure, the UFS host controller may determine the priority levels of the multiple submission queues according to the preset priority rule and the priority identifier corresponding to the multiple submission queues; according to the priority levels, traverse the multiple submission queues to determine at least one first submission queue; traverse at least one first submission queue and sequentially obtain the first read / write request from at least one first submission queue. The UFS host controller may also traverse the multiple submission queues according to the preset loop rule to sequentially determine at least one first submission queue; traverse at least one first submission queue and sequentially obtain the first read / write request from at least one first submission queue.

[0101] In an alternative embodiment of the present disclosure, according to the UFS4.0 protocol standard, the present disclosure sets two priority methods, and the two priority methods include a preset priority rule and a preset loop rule.

[0102] For the preset priority rule, in the present disclosure, by setting the priority identifier of each submission queue, according to the priority identifier of each submission queue, the priority level of each current submission queue is determined, and the submission queue with the highest priority is selected as the first submission queue according to the priority level, that is, the submission queue with a high priority is selected. Among them, in the present disclosure, the range of the priority identifier can be set to 0-7, with a total of 8 levels. The smaller the number of the priority identifier, the larger the priority level, that is, the higher the priority.

[0103] For the preset round-robin rule, it can be specifically implemented by the way of Round Robin. Round Robin is a commonly used scheduling algorithm, usually used to process multiple processes or tasks. This algorithm can achieve fair task allocation and ensure that each task can obtain an appropriate execution time. For the preset round-robin rule, the UFS host controller will sequentially take out a read / write request from each extraction queue for transmission.

[0104] In the present disclosure, based on the two priority design methods of the UFS4.0 multi-queue, the present disclosure can control the bandwidth that different hosts can occupy the UFS host controller by controlling the number of host queues assigned to different hosts, avoiding the problem of read / write request starvation of a certain host. In addition, for a host with a high priority, its extraction queue can be set to a high priority to ensure timely response.

[0105] Step 205, process the first read / write request through the memory in the semiconductor device, and store the processed first processed data in the first completion queue among multiple completion queues. The first completion queue includes the completion queue corresponding to the first submission queue.

[0106] In the embodiment of the present disclosure, when the host puts the read / write request into the extraction queue, the UFS host controller will take out the read / write request in the determined first extraction queue and send it to the memory (i.e., the UFS device) in the semiconductor device for processing. When the memory finishes processing the read request, the memory will put the processed first processed data into the completion queue.

[0107] Step 205 has the same or similar functions as the above step 103, and its implementation manner can refer to the above embodiment and will not be elaborated here.

[0108] Step 206, report the completion interrupt notification to the first host among multiple hosts. The first host includes the host corresponding to the first submission queue. The completion interrupt notification is used to notify the first host to process the first processed data in the first completion queue.

[0109] In an embodiment of the present disclosure, when the memory puts the processed first processed data into the completion queue, it reports a completion interrupt notification to the corresponding first host. After receiving the completion interrupt notification, the first host software processes the first processed data in the completion queue.

[0110] In addition, in the present disclosure, when a hardware error occurs, in response to the hardware error information of the main controller, the error interrupt information corresponding to the hardware error information can be reported to multiple hosts; based on the multiple hosts, the first read / write request is cleared; and based on the initialization host, a second initialization process is performed on the storage parameters in the main controller.

[0111] Among them, clearing the first read / write request based on multiple hosts includes: processing the first processed data through the interrupt processing algorithm in the multiple hosts and clearing the first read / write request in the multiple submission queues; and clearing the unprocessed first read / write request in the storage queue in the memory through the initialization host in the multiple hosts.

[0112] In an alternative embodiment of the present disclosure, the interrupt reporting includes interrupt reporting for hardware errors unrelated to the first read / write request and interrupt reporting related to the first read / write request. Among them, the interrupt reporting for hardware errors unrelated to the first read / write request refers to the reporting of error interrupt information; the interrupt reporting for hardware errors unrelated to the first read / write request refers to the reporting of the completion interrupt notification.

[0113] Specifically, for the reporting of error interrupt information, for system bus fatal error, UIC layor err, etc., the error interrupt information reporting will report the interrupt to all hosts for processing. If UFS main controller and memory (device reset) processing are required, the interrupt processing algorithms (such as interrupt handling functions) of each host will first complete their respective uncompleted first read requests and empty the read requests in their respective extraction queues, and then a host with the highest access privilege (i.e., the initialization host) will empty the unexecuted read / write requests in the storage queue (device queue) in the memory. Finally, a second initialization process is performed on the UFS main controller and the memory, and other hosts will wait for the initialization to complete and can continue to issue read / write requests after completion.

[0114] For the completion of interrupt notification reporting, that is, the read / write request completion interrupt, after processing the read / write request completion, the UFS host controller will issue an interrupt signal to notify the corresponding first host that the read / write request has been processed. The Interrupt Mapping Table is a data structure that stores the one-to-one correspondence between UFS host controller interrupts and multiple hosts. When the UFS host controller completes the interrupt notification reporting, it determines the first host by looking up the Interrupt Mapping Table, and then reports the completion interrupt notification to the corresponding first host. Other hosts will not receive this completion interrupt notification.

[0115] This approach helps to ensure the stability and security of the system because it can prevent the interrupt signal from being incorrectly sent to handlers or hosts that should not receive it, and also prevent conflicts and confusion of interrupt signals.

[0116] At the same time, in the present disclosure, the maximum bandwidth that can be occupied by the host queue of each host can also be set according to the requirements and control strategies of different hosts. Specifically, by monitoring the processing of read requests in the host queue of each host, when the bandwidth usage of the host queue of a certain host exceeds the set maximum bandwidth, the processing of the host queue in that host is paused, and the processing is continued after the read requests in its host queue are processed.

[0117] It can be seen that by continuously monitoring and adjusting the bandwidth usage of the host queue of each host, the efficient balance and resource optimization of the entire system are achieved.

[0118] In summary, through the method provided in the present disclosure, the multi-queue design method allows multiple read / write requests to be processed simultaneously on a single host controller, which increases the concurrency of the system and improves the throughput of the system. And in the multi-queue design, read / write requests can be sorted according to their priorities or other classifications in different queues, thus reducing the need for sorting in a single queue. This reduces the impact of sorting operations on system performance and flexibly processes different types of read / write requests. At the same time, the multi-queue design allows different priorities to be configured for different hosts, which means that the system can be configured according to requirements, so that the read / write requests of some hosts have higher priorities, thus ensuring that critical tasks or high-priority read / write requests can be processed first. The multi-queue design also allows the system IO bandwidth occupied by each host to be configured. This enables fair distribution of system resources according to the requirements and performance of each host, ensuring that each host can perform read / write operations at an appropriate speed while preventing some hosts from overusing system resources.

[0119] Figure 10 The following is a schematic structural diagram of an access device 1000 provided by an embodiment of the present disclosure. As Figure 10 shown, the access device includes:

[0120] A receiving unit 1010, configured to receive multiple host queues sent by multiple hosts, where the multiple host queues include multiple submission queues and multiple completion queues;

[0121] An obtaining unit 1020, configured to determine at least one first submission queue among the multiple submission queues, and obtain first read / write requests in the at least one first submission queue;

[0122] A processing unit 1030, configured to process the first read / write requests through a memory in a semiconductor device, and store the processed first processed data into a first completion queue among the multiple completion queues, where the first completion queue includes a completion queue corresponding to the first submission queue.

[0123] In some embodiments of the present disclosure, the access device further includes: an interrupt reporting unit, configured to, after processing the first read / write requests through the memory and storing the processed first processed data into the first completion queue among the multiple completion queues, report a completion interrupt notification to a first host among the multiple hosts, where the first host includes a host corresponding to the first submission queue, and the completion interrupt notification is used to notify the first host to process the first processed data in the first completion queue.

[0124] In some embodiments of the present disclosure, the access device further includes: an initialization unit, configured to determine an initialization host among the multiple hosts before receiving the multiple host queues sent by the multiple hosts, where the access privilege of the initialization host is the highest; and perform a first initialization process on storage parameters in the semiconductor device based on the initialization host.

[0125] In some embodiments of the present disclosure, the obtaining unit 1020 is configured to: determine the priority levels of the multiple submission queues according to a preset priority rule and priority identifiers corresponding to the multiple submission queues; traverse the multiple submission queues according to the priority levels to determine at least one first submission queue; and traverse the at least one first submission queue to sequentially obtain first read / write requests from the at least one first submission queue.

[0126] In some embodiments of the present disclosure, the obtaining unit 1020 is configured to: traverse the multiple submission queues according to a preset loop rule to sequentially determine at least one first submission queue; and traverse the at least one first submission queue to sequentially obtain first read / write requests from the at least one first submission queue.

[0127] In some embodiments of the present disclosure, the access device further includes: a clearing unit, configured to, in response to a hardware error message of a main controller, report error interrupt information corresponding to the hardware error message to the multiple hosts; clear the first read / write requests based on the multiple hosts; and perform a second initialization process on storage parameters in the main controller based on the initialization host.

[0128] In some embodiments of the present disclosure, a clearing unit is configured to: process first processing data through an interrupt handling algorithm in multiple hosts, and clear first read / write requests in multiple submission queues; clear unprocessed first read / write requests in a storage queue in a memory through an initialization host in the multiple hosts.

[0129] In summary, through an access device, by receiving multiple host queues sent by multiple hosts, the multiple host queues including multiple submission queues and multiple completion queues; determining at least one first submission queue in the multiple submission queues, and obtaining first read / write requests in the at least one first submission queue; processing the first read / write requests through a memory in a semiconductor device, and storing the processed first processing data into a first completion queue in the multiple completion queues, the first completion queue including a completion queue corresponding to the first submission queue, processing read / write requests in multiple queues sent by multiple hosts through a UFS host controller, improving the concurrency of the UFS host controller, and each read / write request does not need to be sorted in hardware, thereby improving the access efficiency and access speed.

[0130] Corresponding to the methods provided in the above several embodiments, the present disclosure further provides an access device. Since the device provided in the embodiments of the present disclosure corresponds to the methods provided in the above several embodiments, the implementation manners of the methods are also applicable to the device provided in this embodiment and will not be described in detail in this embodiment.

[0131] In the above embodiments provided in the present application, the methods and devices provided in the embodiments of the present application are introduced. To implement the various functions in the methods provided in the embodiments of the present application, an electronic device may include a hardware structure and software modules, and implement the above various functions in the form of a hardware structure, a software module, or a combination of a hardware structure and a software module. A certain function among the above various functions may be executed in the form of a hardware structure, a software module, or a combination of a hardware structure and a software module.

[0132] Figure 11 FIG. 13 is a block diagram of an electronic device 1100 for implementing the above access method according to an exemplary embodiment. For example, the electronic device 1100 may be a mobile phone, a computer, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0133] Referring to Figure 11 , the electronic device 1100 may include one or more of the following components: a processing component 1102, a memory 1104, a power component 1106, a multimedia component 1108, an audio component 1110, an input / output (I / O) interface 1112, a sensor component 1114, and a communication component 1116.

[0134] The processing component 1102 generally controls the overall operation of the electronic device 1100, such as operations associated with display, telephone calls, data communication, camera operations, and recording operations. The processing component 1102 may include one or more processors 1120 to execute instructions to complete all or part of the steps of the above methods. In addition, the processing component 1102 may include one or more modules to facilitate the interaction between the processing component 1102 and other components. For example, the processing component 1102 may include a multimedia module to facilitate the interaction between the multimedia component 1108 and the processing component 1102.

[0135] The memory 1104 is configured to store various types of data to support the operation of the electronic device 1100. Examples of such data include instructions for any application or method operating on the electronic device 1100, contact data, phone book data, messages, pictures, videos, etc. The memory 1104 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0136] The power component 1106 provides power to various components of the electronic device 1100. The power component 1106 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 1100.

[0137] The multimedia component 1108 includes a screen that provides an output interface between the electronic device 1100 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can not only sense the boundaries of touch or swipe actions but also detect the duration and pressure associated with the touch or swipe operation. In some embodiments, the multimedia component 1108 includes a front camera and / or a rear camera. When the electronic device 1100 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have focal length and optical zoom capabilities.

[0138] The audio component 1110 is configured to output and / or input audio signals. For example, the audio component 1110 includes a microphone (MIC) that is configured to receive external audio signals when the electronic device 1100 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 1104 or transmitted via the communication component 1116. In some embodiments, the audio component 1110 further includes a speaker for outputting audio signals.

[0139] The I / O interface 1112 provides an interface between the processing component 1102 and a peripheral interface module, and the peripheral interface module may be a keyboard, a click wheel, buttons, etc. These buttons may include, but are not limited to: a home button, a volume button, a power button, and a lock button.

[0140] The sensor component 1114 includes one or more sensors for providing an assessment of various aspects of the status of the electronic device 1100. For example, the sensor component 1114 can detect the open / closed state of the electronic device 1100, the relative positioning of components, such as the display and keypad of the electronic device 1100. The sensor component 1114 can also detect a change in the position of the electronic device 1100 or a component of the electronic device 1100, the presence or absence of user contact with the electronic device 1100, the orientation or acceleration / deceleration of the electronic device 1100, and a change in the temperature of the electronic device 1100. The sensor component 1114 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor component 1114 can also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor component 1114 can further include an acceleration sensor, a gyro sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0141] The communication component 1116 is configured to facilitate communication between the electronic device 1100 and other devices in a wired or wireless manner. The electronic device 1100 can access a wireless network based on communication standards, such as WiFi, 2G or 3G, 4G LTE, 5G NR (New Radio), or a combination thereof. In an exemplary embodiment, the communication component 1116 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 1116 further includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0142] In an exemplary embodiment, the electronic device 1100 may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), main controllers, micro main controllers, microprocessors, or other electronic components for performing the above method.

[0143] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as the memory 1104 including instructions. The above instructions can be executed by the processor 1120 of the electronic device 1100 to complete the above method. For example, the non-transitory computer-readable storage medium may be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0144] An embodiment of the present disclosure also proposes a non-transitory computer-readable storage medium storing computer instructions, where the computer instructions are used to cause a computer to execute the access method described in the above embodiments of the present disclosure.

[0145] An embodiment of the present disclosure also proposes a computer program product, including a computer program, where the computer program, when executed by a processor, executes the access method described in the above embodiments of the present disclosure.

[0146] An embodiment of the present disclosure also proposes a chip, as Figure 12 shown. The chip includes one or more interface circuits 1201 and one or more processors 1202; the interface circuit is used to receive a signal and send the signal to the processor. The signal includes computer instructions stored in a memory. When the processor executes the computer instructions, the chip executes the access method described in the above embodiments of the present disclosure.

[0147] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that such used data may be interchanged under appropriate circumstances so that the embodiments of the present disclosure described here can be implemented in an order other than those illustrated or described here. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0148] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples.

[0149] Any process or method description shown in a flowchart or described in other ways herein can be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a specific logical function or process. The scope of the preferred embodiments of the present invention includes additional implementations, where the functions may be executed in a manner that is not shown or discussed, including in a substantially simultaneous manner according to the functions involved or in a reverse order, which should be understood by those skilled in the art to which the embodiments of the present invention pertain.

[0150] The logic and / or steps represented in a flowchart or described in other ways herein, for example, can be considered as a sequenced list of executable instructions for implementing a logical function, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processing module, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or in conjunction with these instruction execution systems, apparatus, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection portion having one or more wirings (control method), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which a program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or, if necessary, other suitable processing, and then stored in a computer memory.

[0151] It should be understood that each part of the embodiments of the present invention can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits with logic gate circuits for implementing logic functions on data signals, application specific integrated circuits with suitable combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0152] Those of ordinary skill in the art can understand that all or part of the steps carried by the method of the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0153] In addition, each functional unit in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically alone, or two or more units can be integrated into one module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The above-mentioned storage medium can be a read-only memory, a magnetic disk, an optical disk, etc.

[0154] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: a plurality of hosts, a main controller, a memory, and a system memory; the plurality of hosts are connected to the main controller, and the main controller processes the host queues sent by the plurality of hosts to obtain first read / write requests; the main controller is connected to the memory, and sends the first read / write requests to the memory, so that the memory processes the first read / write requests, and sends the first processed data obtained after processing to the main controller; the system memory is connected to the main controller and is used to store the first read / write requests.

2. The semiconductor device according to claim 1, wherein The main controller is used to receive a plurality of host queues sent by a plurality of hosts, and the plurality of host queues include a plurality of submission queues and a plurality of completion queues; determine at least one first submission queue among the plurality of submission queues, and obtain the first read / write requests in the at least one first submission queue.

3. The semiconductor device according to claim 2, wherein The memory is used to process the first read / write requests, and send the first processed data after processing to the main controller, so as to store the first processed data into a first completion queue among the plurality of completion queues, and the first completion queue includes the completion queue corresponding to the first submission queue.

4. The semiconductor device according to claim 3, wherein The main controller reports the completion interrupt notification in the main controller to the first host among the plurality of hosts through connection with the plurality of hosts, and the first host includes the host corresponding to the first submission queue, and the completion interrupt notification is used to notify the first host to process the first processed data in the first completion queue.

5. The semiconductor device according to claim 4, wherein The plurality of hosts determine an initialization host among the plurality of hosts through connection with the main controller, and perform a first initialization process on the storage parameters in the main controller through the initialization host, and the access privilege of the initialization host is the highest.

6. The semiconductor device according to claim 5, wherein, The main controller is used to determine the priority levels of the plurality of submission queues according to a preset priority rule and the priority identifiers corresponding to the plurality of submission queues; traverse the plurality of submission queues according to the priority levels to determine the at least one first submission queue; traverse the at least one first submission queue, and sequentially obtain the first read / write requests from the at least one first submission queue.

7. The semiconductor device according to claim 5, wherein, The main controller is used to traverse the plurality of submission queues according to a preset loop rule, sequentially determine the at least one first submission queue; traverse the at least one first submission queue, and sequentially obtain the first read / write requests from the at least one first submission queue.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that, The main controller reports the error interrupt information corresponding to the hardware error information to the plurality of hosts in response to the hardware error information of the main controller through connection with the plurality of hosts; the plurality of hosts clear the first read / write requests; the initialization host performs a second initialization process on the storage parameters in the main controller.

9. The semiconductor device according to claim 8, wherein, The plurality of hosts are connected to the memory, and the plurality of hosts process the first processed data through an interrupt processing algorithm and clear the first read / write requests in the plurality of submission queues; the initialization host clears the unprocessed first read / write requests in the storage queue in the memory.

10. A main controller, characterized in that, The main controller includes: Multiple register groups, a hardware lock unit, and an interrupt mapping unit; The multiple register groups are respectively connected to corresponding multiple hosts, and the multiple register groups are used to receive multiple host queues sent by the multiple hosts, and the multiple host queues include multiple submission queues and multiple completion queues; The hardware lock unit is connected to the multiple register groups, and is configured to determine at least one first submission queue among the multiple submission queues, obtain a first read / write request in the at least one first submission queue, and send the first read / write request to the memory; The interrupt mapping unit is connected to the multiple hosts, and reports a completion interrupt notification to a first host among the multiple hosts, where the first host includes the host corresponding to the first submission queue, and the completion interrupt notification is used to notify the first host to process first processing data in the first completion queue.

11. The master controller according to claim 10, characterized in that, The hardware lock unit is configured to determine the priority levels of the multiple submission queues according to a preset priority rule and the priority identifiers corresponding to the multiple submission queues; traverse the multiple submission queues according to the priority levels to determine the at least one first submission queue; traverse the at least one first submission queue, and sequentially obtain first read / write requests from the at least one first submission queue.

12. The master controller according to claim 11, wherein The hardware lock unit is configured to traverse the multiple submission queues according to a preset loop rule, sequentially determine the at least one first submission queue; traverse the at least one first submission queue, and sequentially obtain first read / write requests from the at least one first submission queue.

13. The master controller according to claim 12, characterized in that, The interrupt mapping unit is configured to respond to a hardware error message in the main controller, and report error interrupt information corresponding to the hardware error message to the multiple hosts.

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