A fine-grained write request processing method for SRAM hardening

Abstract

The present invention provides a fine-grained write request processing method for SRAM reinforcement that balances performance and reliability, including the following steps: after receiving an external write request, determining whether the external write request is a fine-grained write request; if it is a fine-grained write request, converting the fine-grained write request into a read request; merging the corresponding fine-grained write data with the read return data corresponding to the read request according to the fine-grained write request, and writing the merged data item into the SRAM as a full write request. Compared to the existing technology, the present invention fully utilizes the transmission bandwidth of the SRAM by converting fine-grained write requests into read requests, reducing resource waste and achieving data reinforcement. During the write processing process, the main read and write ports remain consistent with the SRAM, reducing the difficulty of adjusting the RTL code and reducing verification time. At the same time, it supports and matches different error correction algorithms.

Description

Technical Field

[0001] The present invention relates to the technical field of memory read and write processing, and in particular to a fine-grained write request processing method for SRAM reinforcement. Background Art

[0002] Fine-grained writes refer to writing data to storage devices (such as SRAM and DRAM) in a manner where the bit width of the data to be written is significantly smaller than the transmission bit width of the memory. In many application scenarios, the requirements for updating and managing memory data are relatively strict, and independent write operations are required for specific bits or data units, which results in data being written to the memory in fine-grained manner.

[0003] However, fine-grained writes also bring some difficulties and challenges: First, fine-grained writes will significantly reduce the utilization of the read and write bit width of the memory, resulting in performance degradation, and frequent fine-grained writes may require data to be completed to the memory bit width, which is likely to cause errors during transmission and reduce data reliability. Second, fine-grained writes may cause concurrent update problems. In a multi-threaded or parallel processing system, performing fine-grained write operations on different parts of the memory at the same time may cause race conditions and data consistency issues. Third, fine-grained writes may increase the complexity of memory management. Compared with overall writes, fine-grained writes require more detailed data management and control, and introduce additional processing logic and algorithms.

[0004] In addition, fine-grained writes can cause wear and tear on the memory and reduce its lifespan. Frequent fine-grained writes can accelerate the number of erase and write operations on the memory, reducing its lifespan.

[0005] Currently, there are still many different technologies for fine-grained SRAM write processing, and there is still a lack of unified and concise solutions to some common problems. This will lead to the following problems: it increases the workload of designers. Different designers need to learn about memory read, write and access before designing, which increases the total design workload; there are many data consistency issues in the fine-grained SRAM write processing process, and various details need to be properly handled to ensure the correct and reliable SRAM read and write process;

[0006] Because different designers have different processing methods, the verification of data writing to SRAM, background processing, and data consistency processing needs to be performed separately, which will increase the difficulty of verification and shorten the chip's time to market. If the processing mechanism is not handled properly, it will lead to a decline in SRAM reading and writing performance, and make the data transmission process susceptible to external influences and errors, reducing reliability. At the same time, it will affect the logical control of the existing memory access pipeline, further increasing the difficulty of code modification.

[0007] Therefore, providing a fine-grained write request processing method for solving the above problems is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0008] The purpose of the present invention is to provide a fine-grained write request processing method for SRAM reinforcement, which has clear logic, is safe, effective, reliable and easy to operate, and can effectively improve processing performance and reliability.

[0009] Based on the above objectives, the technical solutions provided by the present invention are as follows:

[0010] A fine-grained write request processing method for SRAM hardening includes the following steps:

[0011] receiving an external write request, and determining whether the external write request is a fine-grained write request;

[0012] If so, write the data into the SRAM in different ways selected by the user according to the fine-grained write request;

[0013] When the fast write mode is selected, the corresponding fine-grained write data is written into the SRAM according to the fine-grained write request, and a preset signal is used as a fine-grained write identifier;

[0014] When a reliable write mode is selected, the fine-grained write request is converted into a read request; read return data corresponding to the read request is obtained; and according to the fine-grained write request, the corresponding fine-grained write data is merged with the read return data and written into the SRAM in a full write request mode.

[0015] Preferably, it also includes:

[0016] If the fine-grained write request is in different scenarios, the corresponding fine-grained write data is processed for consistency;

[0017] The corresponding fine-grained write data is the fine-grained write data after consistency processing.

[0018] Preferably, writing into the SRAM in different modes selected by the user according to the fine-grained write request comprises the following steps:

[0019] Determining whether the address of the fine-grained write request is the same as the access address of the corresponding item in the background buffer;

[0020] If yes, then merging the corresponding fine-grained write data with the data of the corresponding item in the background buffer, and inserting the merged data item into the background buffer;

[0021] When idle, the merged data item is written into the SRAM by the background buffer in a full write request manner.

[0022] Preferably, after determining whether the address of the fine-grained write request is the same as the access address of the corresponding item in the background buffer, the method further includes the following steps:

[0023] If not, comparing whether the memory access address of the fine-grained write request is the same as the memory access address of the corresponding item to be written into the background buffer;

[0024] If the memory access addresses of the two are the same, the fine-grained write data is merged with the data to be written into the corresponding item of the background buffer, and the merged data item is inserted into the background buffer. When idle, the merged data item data is written from the background buffer to the SRAM in a full write request mode;

[0025] If the memory access addresses of the two are different and the fast write mode is selected, the fine-grained write data is written to the corresponding address in the SRAM, and a preset signal is used as a fine-grained write identifier;

[0026] If the memory access addresses of the two are different and when a reliable write method is selected, a read request is sent to the SRAM to obtain the read return data corresponding to the fine-grained write request address of the SRAM, and after merging the read return data with the fine-grained write data, the merged data item is inserted into the background buffer, and when idle, the merged data item is written into the SRAM by the background buffer in a full write request mode.

[0027] Preferably, when the reliable write mode is selected, the fine-grained write request is converted into a read request; read return data corresponding to the read request is obtained; and according to the fine-grained write request, the corresponding fine-grained write data is merged with the read return data, and written into the SRAM in a full write request mode, including the following steps:

[0028] Determine whether the first read request is caused by the fine-grained write request, and if so, send the first read request to the SRAM to obtain first read return data corresponding to the fine-grained write request address of the SRAM;

[0029] receiving a second read request;

[0030] After obtaining first read return data corresponding to the fine-grained write request address of the SRAM, determining whether the memory access addresses of the first read request and the second read request are the same;

[0031] If yes, the second read request is cancelled, and the first read return data is outputted through the bypass path as the read return data of the second read request;

[0032] If not, send a second read request to the SRAM to obtain the second read return data corresponding to the fine-grained write request address of the SRAM;

[0033] After merging the second read return data with the fine-grained write data after the consistency processing, inserting the merged data item into the background buffer;

[0034] When idle, the merged data item is written into the SRAM by the background buffer in a full write request manner.

[0035] Preferably, when the reliable write mode is selected, the fine-grained write request is converted into a read request; read return data corresponding to the read request is obtained; and according to the fine-grained write request, the corresponding fine-grained write data is merged with the read return data and written into the SRAM in a full write request mode, further comprising the following steps:

[0036] Determine whether the third read request is caused by the first fine-grained write request, and if so, send the third read request to the SRAM to obtain third read return data corresponding to the first fine-grained write request address of the SRAM;

[0037] receiving a second fine-grained write request, determining whether the second fine-grained write request is a full write request, and if so, writing the second fine-grained write request into the SRAM during idle time;

[0038] If not, determining whether the memory access address of the third write request is the same as that of the second fine-grained write request;

[0039] If they are the same, the fourth read request converted from the second fine-grained write request is invalidated, and the third read return data is output through the bypass as the fourth read return data;

[0040] After merging the fourth read return data with the fine-grained write data after consistency processing, inserting the merged data item into the background buffer;

[0041] When idle, the merged data item is written into the SRAM by the background buffer in a full write request manner.

[0042] Preferably, when the reliable write mode is selected, the fine-grained write request is converted into a read request; read return data corresponding to the read request is obtained; and according to the fine-grained write request, the corresponding fine-grained write data is merged with the read return data and written into the SRAM in a full write request mode, further comprising the following steps:

[0043] Determining whether the first write request is the fine-grained write request;

[0044] If yes, send a fifth read request to the SRAM to obtain the fifth read return data corresponding to the fine-grained write request address of the SRAM; if no, send the first write request to the SRAM to write to the SRAM when idle;

[0045] Before merging the fifth read return data with the data of the corresponding item to be written into the background buffer, determining whether a sixth read request has been received, and if so, comparing whether the memory access addresses of the fifth read request and the sixth read request are the same;

[0046] If they are the same, the sixth read request is invalidated, and the fifth read return data is output through the bypass path as the sixth read return data;

[0047] If the sixth read request is not received, inserting the merged data item before the background buffer, determining whether a seventh read request is received, and if so, comparing whether the access address of the merged data item is the same as that of the seventh read request;

[0048] If they are the same, the seventh read request is invalidated, and the merged data item in the background buffer is output through the bypass as the sixth read return data;

[0049] If the seventh read request is not received, sending the seventh read request to the SRAM to obtain seventh read return data corresponding to the fine-grained write request address of the SRAM;

[0050] After merging the sixth read return data or the seventh read return data with the fine-grained write data after consistency processing, inserting the merged data item into a background buffer;

[0051] When idle, the merged data item is written into the SRAM by the background buffer in a full write request manner.

[0052] Preferably, when the reliable write mode is selected, the fine-grained write request is converted into a read request; read return data corresponding to the read request is obtained; and according to the fine-grained write request, the corresponding fine-grained write data is merged with the read return data and written into the SRAM in a full write request mode, further comprising the following steps:

[0053] Determine whether the memory access addresses of the second write request and the third write request are the same;

[0054] If they are the same, the second write request is invalidated, and it is determined whether the third write request is a fine-grained write;

[0055] If so, send an eighth read request to the SRAM, obtain the eighth read return data corresponding to the fine-grained write request address of the SRAM, and obtain the third fine-grained write data;

[0056] After merging the eighth read return data with the third fine-grained write data, inserting the merged data item into a background buffer; writing the merged data item from the background buffer to the SRAM in a full write request mode when idle;

[0057] If they are not the same, determining whether the third write request is a fine-grained write;

[0058] If yes, send the eighth read request to the SRAM, obtain the eighth read return data corresponding to the fine-grained write request address of the SRAM, and obtain the third fine-grained write data;

[0059] After merging the eighth read return data with the third fine-grained write data, inserting the merged data item into the background buffer; writing the merged data item from the background buffer to the SRAM in a full write request mode when idle;

[0060] If the third write request is not a fine-grained write, the third write request is sent to the SRAM and written into the SRAM during idle time.

[0061] The fine-grained write request processing method for SRAM reinforcement provided by the present invention includes the following steps: after receiving an external write request, determining whether the external write request is a fine-grained write request; if it is a fine-grained write request, converting the fine-grained write request into a read request; merging the corresponding fine-grained write data with the read return data corresponding to the read request according to the fine-grained write request, and writing the merged data item into the SRAM in a full write request manner.

[0062] Compared with the existing technology, the present invention fully utilizes the transmission bandwidth of SRAM by converting fine-grained write requests into read requests, reduces resource waste, and achieves data reinforcement; during the write processing process, the main read and write ports remain consistent with SRAM, which reduces the difficulty of adjusting the RTL code and reduces the verification time; at the same time, it supports and matches different error correction algorithms. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0064] Figure 1 A flowchart of a fine-grained write request processing method that balances performance and reliability is provided in an embodiment of the present invention;

[0065] Figure 2 A flowchart of step S2 provided in an embodiment of the present invention;

[0066] Figure 3 The flowchart after step A1 provided in the embodiment of the present invention;

[0067] Figure 4A flowchart of processing a fine-grained write request using reliable write in a read-after-read scenario in step S32 provided in an embodiment of the present invention;

[0068] Figure 5 A flowchart of processing a fine-grained write request using reliable write in a read-after-write scenario in step S32 provided by an embodiment of the present invention;

[0069] Figure 6 A flowchart of processing a fine-grained write request using reliable write in a read-after-write scenario in step S32 provided in an embodiment of the present invention;

[0070] Figure 7 This is a flowchart of using reliable write to process fine-grained write requests in a write-after-write scenario in step S32 provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0071] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0072] The embodiments of the present invention are written in a progressive manner.

[0073] The embodiment of the present invention provides a fine-grained write request processing method, which mainly solves the technical problems in the prior art, such as resource waste, high verification difficulty, and high difficulty in adjusting RTL code.

[0074] like Figure 1 As shown, a fine-grained write request processing method for SRAM hardening includes the following steps:

[0075] S1. Receive an external write request and determine whether the external write request is a fine-grained write request;

[0076] S2. If yes, write to SRAM in different ways selected by the user according to the fine-grained write request;

[0077] In step S1 to step S2, when the front end receives a write request from an external source, it determines whether the external write request is a fine-grained write. When the fine-grained write signal is high, the corresponding received write data is fine-grained write data. According to the fine-grained write request, the data is written into the SRAM in accordance with the write method selected by the user.

[0078] It's important to note that static random-access memory (SRAM) is a type of random-access memory. "Static" means that the data stored in this type of memory remains permanently as long as power is supplied. SRAM is primarily used for Level 2 cache. It uses transistors to store data. Compared to DRAM, SRAM is faster, but its capacity is smaller than other types of memory within the same area.

[0079] S31. When the fast write mode is selected, the corresponding fine-grained write data is written to the SRAM according to the fine-grained write request, with a preset signal as a fine-grained write identifier;

[0080] S32. When the reliable write mode is selected, the fine-grained write request is converted into a read request; the read return data corresponding to the read request is obtained; according to the fine-grained write request, the corresponding fine-grained write data is merged with the read return data, and written into the SRAM in a full write request mode.

[0081] In step S31 and step S32, two write modes are designed. The first is fast write, that is, according to the fine-grained write request, the corresponding fine-grained write data is written into the SRAM, and a preset signal is used as a fine-grained write identifier; the second is reliable write, that is, the fine-grained write request is converted into a read request, the read return data corresponding to the read request is obtained, and according to the fine-grained write request, the corresponding fine-grained write data is merged with the read return data, and written into the SRAM in a full write request mode;

[0082] In this embodiment, the fast writing method is specifically: without using EDAC encoding, the fine-grained write data is directly written to the SRAM, and an additional signal is used as a fine-grained write identifier; and the reliable writing method is specifically: the fine-grained write request is converted into a read request; according to the fine-grained write request, the corresponding fine-grained write data is merged with the read return data, and then encoded by EDAC and written to the SRAM in a full write request manner.

[0083] Preferably, it also includes:

[0084] If fine-grained write requests are in different scenarios, the corresponding fine-grained write data will be processed for consistency;

[0085] The corresponding fine-grained write data is the fine-grained write data after consistency processing.

[0086] During actual application, after determining that the external write request is a fine-grained write request, data inconsistency may exist during the execution of the fine-grained write processing. Corresponding data consistency processing is performed according to different scenarios. Step S31 corresponds to: when the fast write mode is selected, the corresponding fine-grained write data after consistency processing is written into the SRAM according to the fine-grained write request, and the preset signal is used as the fine-grained write identifier; Step S32 corresponds to: when the reliable write mode is selected, the fine-grained write request is converted into a read request, and the read return data corresponding to the read request is obtained. According to the fine-grained write request, the corresponding write data after consistency processing is merged with the read return data, and written into the SRAM in a full write request mode.

[0087] like Figure 2 As shown, preferably, step S2 includes the following steps:

[0088] A1. Determine whether the address of the fine-grained write request is the same as the access address of the corresponding item in the background buffer;

[0089] A2. If yes, merge the corresponding fine-grained write data with the data of the corresponding item in the background buffer, and insert the merged data item into the background buffer;

[0090] A3. When idle, the merged data items are written from the background buffer to the SRAM in a full write request manner.

[0091] In steps A1 to A3, determine whether the address of the fine-grained write request is the same as the corresponding item in the background buffer. If the address is the same, merge the fine-grained write data with the corresponding item in the background buffer and the data of the corresponding item in the background buffer, and insert the merged data item into the background buffer. When the background buffer is idle, write the merged data item into the SRAM in a full write request manner.

[0092] It should be noted that the background buffer module is used to manage the data and corresponding addresses after the read request error is corrected, as well as the data and corresponding addresses after the fine-grained write data is superimposed with the original location data. The background buffer will write the buffered data to the SRAM according to the corresponding address one by one and delete the corresponding entry in the buffer;

[0093] In this embodiment, for a foreground fine-grained write request, the address of the request is first compared to see if it is the same as the item in the background buffer. If they are the same, the fine-grained write data and the data of the corresponding item in the background buffer are merged, and the merged data is inserted into the background buffer. When the device is idle, the data item is written from the background buffer to the SRAM.

[0094] like Figure 3 As shown, preferably, after step A1, the following steps are further included:

[0095] B1. If not, compare whether the memory access address of the fine-grained write request is the same as the memory access address of the corresponding item to be written to the background buffer;

[0096] B21. If the memory access addresses of the two are the same, the fine-grained write data is merged with the data of the corresponding item to be written to the background buffer, and the merged data item is inserted into the background buffer. When idle, the merged data item data is written from the background buffer to the SRAM in a full write request mode;

[0097] B22. If the two memory access addresses are different, and when the fast write mode is selected, the fine-grained write data is written to the corresponding address in the SRAM, and the preset signal is used as a fine-grained write flag;

[0098] B23. If the memory access addresses of the two are different and when a reliable write method is selected, a read request is sent to the SRAM to obtain the read return data corresponding to the fine-grained write request address of the SRAM. After merging the read return data with the fine-grained write data, the merged data item is inserted into the background buffer. When idle, the merged data item is written from the background buffer to the SRAM in a full write request mode.

[0099] In steps B1 to B23, after determining whether the address of the fine-grained write request is the same as the corresponding item in the background buffer, if the address of the fine-grained write request is not the same as the corresponding item in the background buffer, compare whether the access address of the fine-grained write request is the same as the corresponding item data to be written to the background buffer; if the two are the same, merge the fine-grained write data with the data of the corresponding item to be written to the background buffer, insert the merged data item into the background buffer, and write the merged data item from the background buffer to the SRAM in a full write request mode when idle; if the two are not the same, there are two different situations: fast writing and reliable writing. When the fast write mode is selected, the fine-grained write data is written to the corresponding address in the SRAM, and a preset signal is used as a fine-grained write identifier; when the reliable write mode is selected, a read request is sent to the SRAM to obtain the read return data corresponding to the fine-grained write request address of the SRAM, merge the read return data and the fine-grained write data, insert the merged data item into the background buffer, and write the merged data item from the background buffer to the SRAM in a full write request mode when idle.

[0100] like Figure 4 As shown, preferably, step S32 includes the following steps:

[0101] C1. Determine whether the first read request is caused by a fine-grained write request. If so, send the first read request to the SRAM to obtain the first read return data corresponding to the fine-grained write request address of the SRAM;

[0102] C2. Receive the second read request;

[0103] C3. After obtaining the first read return data corresponding to the fine-grained write request address of the SRAM, it is determined whether the memory access address of the first read request and the second read request are the same;

[0104] C41. If so, the second read request is canceled, and the first read return data is output by the bypass as the read return data of the second read request;

[0105] C42. If not, a second read request is sent to the SRAM to obtain the second read return data corresponding to the fine-grained write request address of the SRAM;

[0106] C5. Merge the second read return data with the fine-grained write data after consistency processing, and insert the merged data item into the background buffer;

[0107] C6. When idle, write the merged data items from the background buffer to the SRAM in a full write request manner.

[0108] Steps C1 to C6 are specifically applied to a read-after-read scenario, i.e., a situation where two read requests are sent to the SRAM in succession due to receiving or being caused by fine-grained write-to-read conversion; a first read request and a second read request are received, and it is determined whether the received first read request is caused by a fine-grained write request. If so, the first read request is sent to the SRAM to obtain first read return data corresponding to the fine-grained write request address of the SRAM; after obtaining the first read return data, it is determined whether the memory access addresses between the first read request and the second read request are the same. If they are the same, the second read request is invalidated, and the first read return data is output by bypass as the read return data of the second read request; if they are not the same, the second read request is sent to the SRAM to obtain second read return data corresponding to the fine-grained write request address of the SRAM;

[0109] In this embodiment, for the received read request 1, the device will first determine whether the read request 1 is caused by a fine-grained write request. If so, the read request 1 is sent to the SRAM, and the data returned by the SRAM is the first read request return data; if a new read request 2 is received before the current step, the read request 2 will go through the same steps as the read request 1, and determine whether the two memory access addresses are the same. If they are the same, the read request 2 will be invalidated, and the read request 1 return data will be output through the bypass as the read request 2 return data. Otherwise, the read request 2 can be regarded as a new read request 1, and the data returned by the SRAM is the second read request return data.

[0110] like Figure 5 As shown, preferably, step S32 further includes the following steps:

[0111] D1 determines whether the third read request is caused by the first fine-grained write request. If so, a third read request is sent to the SRAM to obtain the third read return data corresponding to the first fine-grained write request address of the SRAM;

[0112] D21 receives a second fine-grained write request, determines whether the second fine-grained write request is a full write request, and if so, writes to the SRAM in idle time;

[0113] D22. If not, determine whether the memory access address of the third write request and the second fine-grained write request is the same;

[0114] D3. If they are the same, the fourth read request converted from the second fine-grained write request is invalidated, and the third read return data is output by bypass as the fourth read return data;

[0115] D4. After merging the fourth read return data with the fine-grained write data after consistency processing, the merged data item is inserted into the background buffer;

[0116] D5. When idle, write the merged data items from the background buffer to the SRAM in a full write request manner.

[0117] Steps D1 to D5 are applied to the read-after-write scenario, that is, the situation where a new write request is received after a read request is sent to the SRAM due to fine-grained write-to-read conversion; determine whether the received third read request is caused by the first fine-grained write request, and if so, send a third read request to the SRAM to obtain the third read return data corresponding to the first fine-grained write request address of the SRAM; receive a second fine-grained write request, and determine whether the second fine-grained write request is a full write request. If the second fine-grained write request is a full write request, write it to the SRAM when idle; if the second fine-grained write request is not a full write request, determine whether the memory access address of the third write request is the same as that of the second fine-grained write request; if the two are the same, invalidate the fourth read request converted from the second fine-grained write request, and output the third read return data by bypass as the fourth read return data; after merging the fourth read return data with the fine-grained write data after consistency processing, insert the merged data item into the background buffer, and write the merged data item from the background buffer to the SRAM as a full write request when idle.

[0118] It should be noted that bypass means that two networks can be physically connected directly through a specific trigger state (power outage or crash) without going through the network security device system. Therefore, with bypass, when the network security device fails, the networks connected to this device can still be connected to each other. Of course, at this time, this network device will no longer process the packets in the network.

[0119] In this embodiment, for the third read request received, it is first determined whether the read request is caused by a fine-grained write request, and a read request 1 is sent to the SRAM. The data returned by the SRAM is the data returned by the read request 1. At this time, if a new second fine-grained write request is received, if the second fine-grained write request is a full write request, it is written to the SRAM when idle. If the second fine-grained write request is not a full write request, it is determined whether the memory access address of the read request is the same as that of the second write request. If they are the same, the read request 2 converted from the second write request is invalidated, and the return data of the read request 1 is output by bypass as the return data of the read request 2. The return data of the read request 2 is merged with the fine-grained write data after consistency processing, and the merged data item is inserted into the background buffer; it is written to the SRAM when the device is idle.

[0120] like Figure 6 As shown, preferably, step S32 further includes the following steps:

[0121] E1. Determine whether the first write request is a fine-grained write request;

[0122] E21. If so, a fifth read request is sent to the SRAM to obtain the fifth read return data corresponding to the SRAM fine-grained write request address;

[0123] E22. If not, send the first write request to the SRAM and write to the SRAM when idle;

[0124] E3. Before merging the fifth read return data with the corresponding item data to be written to the background buffer, it is determined whether the sixth read request is received;

[0125] E41. If so, compare the memory access addresses of the fifth read request and the sixth read request to see if they are the same;

[0126] E51. If the data are the same, the sixth read request is canceled and the fifth read return data is output as the sixth read return data by bypass.

[0127] E42. If the sixth read request is not received, the merged data item is inserted into the background buffer before determining whether the seventh read request is received;

[0128] E52. If so, compare the merged data item with the memory access address of the seventh read request to see if they are the same;

[0129] E62. If they are the same, the seventh read request is canceled and the merged data item in the background buffer is output through the bypass as the sixth read return data;

[0130] E53. If the seventh read request is not received, a seventh read request is sent to the SRAM to obtain the seventh read return data corresponding to the fine-grained write request address of the SRAM;

[0131] E7. After merging the sixth read return data or the seventh read return data with the fine-grained write data after consistency processing, insert the merged data item into the background buffer;

[0132] E8. When idle, write the merged data items from the background buffer to the SRAM using a full write request.

[0133] Steps E1 to E8 are applied to the scenario of read-after-write, that is, the situation where a new read request is received after a write request is received or a read request is sent to the SRAM due to fine-grained write-to-read conversion. Specifically, it is determined whether the first write request received is a fine-grained write request. If so, a fifth read request is initiated to the SRAM to obtain the fifth read return data corresponding to the fine-grained write request address of the SRAM. If the first write request is not a fine-grained write request, the first write request is sent to the SRAM and written to the SRAM when idle. Before merging the fifth read return data with the data of the corresponding item to be written to the background buffer, it is first determined whether a sixth read request is received. If the sixth read request is received, the memory access addresses between the fifth read request and the sixth read request are compared to see if they are the same. If the two are the same, the sixth read request is invalidated, and the fifth read return data is output by bypass as the sixth read return data. If the sixth read request is not received, the fifth read return data is merged with the data to be written to the background buffer. The merged data item composed of the data of the corresponding items in the background buffer is inserted into the background buffer. Prior to this, it is first determined whether the seventh read request is received. If the seventh read request is received, the memory access address of the merged data item is compared with that of the seventh read request. If the two are the same, the seventh read request is invalidated, and the merged data item in the background buffer is output by bypass as the sixth read return data; if the seventh read request is not received, the seventh read request is sent to the SRAM to obtain the seventh read return data corresponding to the fine-grained write request address of the SRAM, and after merging the sixth read return data or the seventh read return data with the fine-grained write data after consistency processing, the merged data item is inserted into the background buffer, and the merged data item is written from the background buffer to the SRAM in a full write request mode when idle.

[0134] In this embodiment, for the first write request received, it is first determined whether the write request is a fine-grained write. If so, a fifth read request 1 is sent to the SRAM, and the data returned by the SRAM is the data returned by the fifth read request 1. If not, a first write request is sent to the SRAM, and the data is written to the SRAM during idle time. The fifth read return data is merged with the data to be written. If a new sixth read request is received before this, the memory access addresses of the two are compared. If they are the same, the sixth read request 2 is invalidated, and the merged data is output by bypass, which is the data returned by the sixth read request 2. If there is no new read request, the merged data item will be inserted into the background buffer. If a new seventh read request is received before this, the memory access addresses of the two will be compared. If they are the same, the seventh read request 2 will be invalidated, and the background buffer data will be output by bypass, which is the return data of read request 2. If there is no new read request, the data returned by SRAM is the return data of read request 2. After merging the read return data with the fine-grained write data after consistency processing, the merged data item will be inserted into the background buffer. When idle, the merged data item will be written from the background buffer to the SRAM in full write request mode.

[0135] like Figure 7 As shown, preferably, step S32 further includes the following steps:

[0136] F1. Determine whether the memory access address of the second write request and the third write request is the same;

[0137] F21. If they are the same, the second write request is invalidated, and the third write request is determined to be a fine-grained write.

[0138] F31. If so, an eighth read request is sent to the SRAM to obtain the eighth read return data corresponding to the fine-grained write request address of the SRAM, and obtain the third fine-grained write data;

[0139] F4. After merging the eighth read return data with the third fine-grained write data, the merged data item is inserted into the background buffer; when idle, the merged data item is written to the SRAM by the background buffer in a full write request mode;

[0140] F22. If they are not the same, determine whether the third write request is a fine-grained write;

[0141] F32. If so, an eighth read request is sent to the SRAM to obtain the eighth read return data corresponding to the fine-grained write request address of the SRAM, and obtain the third fine-grained write data;

[0142] F4. After the eighth read return data is merged with the third fine-grained write data, the merged data item is inserted into the background buffer; when idle, the merged data item is written to the SRAM by the background buffer in a full write request mode;

[0143] F33. If the third write request is not a fine-grained write, send the third write request to the SRAM and write to the SRAM when idle.

[0144] Steps F1 to F4 are applied to the write-after-write scenario, that is, the situation where a new write request is received after a write request is received. Specifically, for the received second write request and the newly received third write request, first determine whether the memory access addresses of the two are the same. If they are the same, invalidate the second write request, and determine whether the third write request is a fine-grained write. If the third write request is a fine-grained write, send an eighth read request to the SRAM, obtain the eighth read return data corresponding to the fine-grained write request address of the SRAM, and obtain the third fine-grained write data accordingly; after merging the eighth read return data with the third fine-grained write data, insert the merged item into the back The background buffer writes the merged data item from the background buffer to the SRAM in a full write request mode when idle; if the memory access addresses of the second write request and the third write request are different, it is determined whether the third write request is a fine-grained write. If the third write request is a fine-grained write, an eighth read request is sent to the SRAM to obtain the eighth read return data corresponding to the fine-grained write request of the SRAM, and the third fine-grained write data is obtained. After merging the eighth read return data and the third fine-grained write data, the merged data item is inserted into the background buffer. If the third write request is not a fine-grained write, the third write request is sent to the SRAM and written to the SRAM when idle.

[0145] In this embodiment, for the received second write request 1, if a new third write request 2 is received at this time, it will first be determined whether the memory access addresses of the two are the same. If they are the same, the second write request 1 will be invalidated, and it will be determined whether the third write request 2 is a fine-grained write. If so, a read request is sent to the SRAM, and the data returned by the SRAM is the read request return data. The third fine-grained write data is obtained accordingly, and the read request return data is merged with the fine-grained write request data. The merged data item is inserted into the background buffer. When idle, the merged data item is written from the background buffer to the SRAM in a full write request mode. If the memory access address of the second write request 1 is different from that of the third write request 2, determine whether the third write request 2 is a fine-grained write. If so, send a read request to the SRAM, and the data returned by the SRAM is the read request return data. Correspondingly, obtain the third fine-grained write data, merge the read request return data with the fine-grained write request data, insert the merged data item into the background buffer, and write the merged data item from the background buffer to the SRAM in a full write request manner when idle. If the third write request 2 is not a fine-grained write, send the third write request to the SRAM and write it to the SRAM when idle.

[0146] In the embodiments provided in this application, it should be understood that the disclosed methods can be implemented in other ways. The embodiments described above are merely illustrative. For example, the division of modules is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple modules or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0147] In addition, all functional modules in the embodiments of the present invention may be integrated into one processor, or each module may be a separate device, or two or more modules may be integrated into one device; the functional modules in the embodiments of the present invention may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0148] Those skilled in the art will understand that all or part of the steps of the above-mentioned method embodiment can be completed by program instructions and related hardware. The aforementioned program instructions can be stored in a computer-readable storage medium. When the program instructions are executed, the steps of the above-mentioned method embodiment are executed; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM), magnetic disks or optical disks, and other media that can store program codes.

[0149] As used in this application and the claims, unless the context clearly indicates an exception, the terms "a," "an," "an," and / or "the" are not intended to refer to the singular and may include the plural, unless the context clearly indicates otherwise. Generally speaking, the terms "comprises" and "include" only indicate the inclusion of the steps and elements specifically identified, and these steps and elements do not constitute an exclusive list. A method or apparatus may also include other steps or elements. The phrase "comprises a..." does not preclude the presence of additional identical elements in the process, method, product, or apparatus that includes the elements.

[0150] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the quantity of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features.

[0151] If a flow chart is used in this application, the flow chart is used to illustrate the operations performed by the system according to the embodiments of the application. It should be understood that the previous or subsequent operations are not necessarily performed in exact order. Instead, the steps can be processed in reverse order or simultaneously. At the same time, other operations can be added to these processes, or one or more operations can be removed from these processes.

[0152] The above is a detailed introduction to a fine-grained write request processing method for SRAM reinforcement provided by the present invention. The above description of the disclosed embodiments enables professionals and technicians in this field to implement or use the present invention. Various modifications to these embodiments will be obvious to professionals and technicians in this field, and the general principles defined in this article can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown in this article, but will conform to the widest scope consistent with the principles and novel features disclosed in this article.

Claims

1. A fine-grained write request processing method for SRAM hardening, characterized in that: The steps include: receiving an external write request, and determining whether the external write request is a fine-grained write request; If so, write the data into the SRAM in different ways selected by the user according to the fine-grained write request; When the fast write mode is selected, the corresponding fine-grained write data is written into the SRAM according to the fine-grained write request, and a preset signal is used as a fine-grained write identifier; When the reliable write mode is selected, the fine-grained write request is converted into a read request; Obtaining read return data corresponding to the read request; According to the fine-grained write request, the corresponding fine-grained write data is merged with the read return data, and written into the SRAM in a full write request manner; When the reliable write mode is selected, the fine-grained write request is converted into a read request; Obtaining read return data corresponding to the read request; According to the fine-grained write request, the corresponding fine-grained write data is merged with the read return data, and written into the SRAM in a full write request mode, comprising the following steps: Determine whether the first read request is caused by the fine-grained write request, and if so, send the first read request to the SRAM to obtain first read return data corresponding to the fine-grained write request address of the SRAM; receiving a second read request; After obtaining first read return data corresponding to the fine-grained write request address of the SRAM, determining whether the memory access addresses of the first read request and the second read request are the same; If yes, the second read request is cancelled, and the first read return data is outputted through the bypass path as the read return data of the second read request; If not, send a second read request to the SRAM to obtain the second read return data corresponding to the fine-grained write request address of the SRAM; After merging the second read return data with the fine-grained write data after consistency processing, inserting the merged data item into the background buffer; When idle, the merged data item is written into the SRAM by the background buffer in a full write request manner.

2. The fine-grained write request processing method for SRAM hardening according to claim 1, characterized in that: Also includes: If the fine-grained write request is in different scenarios, the corresponding fine-grained write data is processed for consistency; The corresponding fine-grained write data is the fine-grained write data after consistency processing.

3. The fine-grained write request processing method for SRAM hardening according to claim 1, characterized in that: Writing into the SRAM in different modes selected by the user according to the fine-grained write request comprises the following steps: Determining whether the address of the fine-grained write request is the same as the access address of the corresponding item in the background buffer; If yes, then merging the corresponding fine-grained write data with the data of the corresponding item in the background buffer, and inserting the merged data item into the background buffer; When idle, the merged data item is written into the SRAM by the background buffer in a full write request manner.

4. The fine-grained write request processing method for SRAM hardening according to claim 3, characterized in that: After determining whether the address of the fine-grained write request is the same as the access address of the corresponding item in the background buffer, the following steps are also included: If not, comparing whether the memory access address of the fine-grained write request is the same as the memory access address of the corresponding item to be written into the background buffer; If the memory access addresses of the two are the same, the fine-grained write data is merged with the data to be written into the corresponding item of the background buffer, and the merged data item is inserted into the background buffer. When idle, the merged data item data is written from the background buffer to the SRAM in a full write request mode; If the memory access addresses of the two are different and the fast write mode is selected, the fine-grained write data is written to the corresponding address in the SRAM, and a preset signal is used as a fine-grained write identifier; If the memory access addresses of the two are different and when a reliable write method is selected, a read request is sent to the SRAM to obtain the read return data corresponding to the fine-grained write request address of the SRAM, and after merging the read return data with the fine-grained write data, the merged data item is inserted into the background buffer, and when idle, the merged data item is written into the SRAM by the background buffer in a full write request mode.

5. The fine-grained write request processing method for SRAM hardening according to claim 1, characterized in that: When the reliable write mode is selected, the fine-grained write request is converted into a read request; read return data corresponding to the read request is obtained; and according to the fine-grained write request, the corresponding fine-grained write data is merged with the read return data, and written into the SRAM in a full write request mode, further comprising the following steps: Determine whether the third read request is caused by the first fine-grained write request, and if so, send the third read request to the SRAM to obtain third read return data corresponding to the first fine-grained write request address of the SRAM; receiving a second fine-grained write request, determining whether the second fine-grained write request is a full write request, and if so, writing the second fine-grained write request into the SRAM during idle time; If not, determining whether the memory access address of the third write request is the same as that of the second fine-grained write request; If they are the same, the fourth read request converted from the second fine-grained write request is invalidated, and the third read return data is output through the bypass as the fourth read return data; After merging the fourth read return data with the fine-grained write data after consistency processing, inserting the merged data item into the background buffer; When idle, the merged data item is written into the SRAM by the background buffer in a full write request manner.

6. The fine-grained write request processing method for SRAM hardening according to claim 1, characterized in that: When the reliable write mode is selected, the fine-grained write request is converted into a read request; read return data corresponding to the read request is obtained; and according to the fine-grained write request, the corresponding fine-grained write data is merged with the read return data, and written into the SRAM in a full write request mode, further comprising the following steps: Determining whether the first write request is the fine-grained write request; If yes, send a fifth read request to the SRAM to obtain the fifth read return data corresponding to the fine-grained write request address of the SRAM; if no, send the first write request to the SRAM to write to the SRAM when idle; Before merging the fifth read return data with the data of the corresponding item to be written into the background buffer, determining whether a sixth read request has been received, and if so, comparing whether the memory access addresses of the fifth read request and the sixth read request are the same; If they are the same, the sixth read request is invalidated, and the fifth read return data is output through the bypass path as the sixth read return data; If the sixth read request is not received, inserting the merged data item before the background buffer, determining whether a seventh read request is received, and if so, comparing whether the access address of the merged data item is the same as that of the seventh read request; If they are the same, the seventh read request is invalidated, and the merged data item in the background buffer is output through the bypass as the sixth read return data; If the seventh read request is not received, sending the seventh read request to the SRAM to obtain seventh read return data corresponding to the fine-grained write request address of the SRAM; After merging the sixth read return data or the seventh read return data with the fine-grained write data after consistency processing, inserting the merged data item into a background buffer; When idle, the merged data item is written into the SRAM by the background buffer in a full write request manner.

7. The fine-grained write request processing method for SRAM hardening according to claim 1, characterized in that: When the reliable write mode is selected, the fine-grained write request is converted into a read request; read return data corresponding to the read request is obtained; and according to the fine-grained write request, the corresponding fine-grained write data is merged with the read return data, and written into the SRAM in a full write request mode, further comprising the following steps: Determine whether the memory access addresses of the second write request and the third write request are the same; If they are the same, the second write request is invalidated, and it is determined whether the third write request is a fine-grained write; If so, send an eighth read request to the SRAM, obtain the eighth read return data corresponding to the fine-grained write request address of the SRAM, and obtain the third fine-grained write data; After merging the eighth read return data with the third fine-grained write data, inserting the merged data item into a background buffer; writing the merged data item from the background buffer to the SRAM in a full write request mode when idle; If they are not the same, determining whether the third write request is a fine-grained write; If yes, send the eighth read request to the SRAM, obtain the eighth read return data corresponding to the fine-grained write request address of the SRAM, and obtain the third fine-grained write data; After merging the eighth read return data with the third fine-grained write data, inserting the merged data item into the background buffer; writing the merged data item from the background buffer to the SRAM in a full write request mode when idle; If the third write request is not a fine-grained write, the third write request is sent to the SRAM and written into the SRAM during idle time.

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