Storage module and electronic system

Abstract

The invention discloses a storage module and an electronic system. The storage module comprises a dual in-line interface, a dynamic random access memory, a control unit and a nonvolatile memory, wherein the dynamic random access memory is connected with a memory interface of main control equipment through the dual in-line interface, is used as a cache unit controlled by the main control equipment, and is used for storing an access command issued by the main control equipment; wherein the control unit is connected with the dual in-line interface, the dynamic random access memory and the nonvolatile memory; the control unit controls data transfer between the dynamic random access memory and the nonvolatile memory according to the access command. The invention provides a scheme capable of considering both storage capacity identification and universal standard interface adaptation.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and particularly to a storage module and an electronic system. Background Art

[0002] With the development of electronic technology, various new storage devices have emerged. Among them, the Non-Volatile Dual In-line Memory Module (NVDIMM) can retain data content even when powered off, and can also improve application performance, data security, and system crash recovery time in some scenarios, thus being widely used.

[0003] However, due to the connection limitation of the standard Double Data Rate (DDR) interface defined by JEDEC (which can only be compatible with dynamic random access memory), for several existing NVDIMMs, there are either problems that the master device can only recognize the storage capacity of dynamic random access memory (DRAM), or problems that the DDR interface needs to be adapted and modified, making it difficult to balance the requirements of storage capacity recognition and adaptation to the general standard DDR interface. Summary of the Invention

[0004] In view of the above problems, the present invention is proposed to provide a storage module and an electronic system that overcome or at least partially solve the above problems.

[0005] In a first aspect, a storage module is provided, including: A dual in-line interface, a dynamic random access memory, a control unit, and a non-volatile memory; Wherein, the dynamic random access memory is connected to the memory interface of the master device through the dual in-line interface to serve as a cache unit controlled by the master device, and is used to store access commands issued by the master device; Wherein, the control unit is connected to the dual in-line interface, the dynamic random access memory, and the non-volatile memory; the control unit controls the data transfer between the dynamic random access memory and the non-volatile memory according to the access command.

[0006] Optionally, the dynamic random access memory includes a data area and a command area, the data area is used to store cache data, and the command area is used to store the access commands issued by the master device.

[0007] Optionally, both the dual in-line interface and the memory interface are standard double data rate interfaces.

[0008] Optionally, the control unit is further configured to upload the storage capacity information of the non-volatile memory to the host device.

[0009] Optionally, during a transfer period, the control unit controls data transfer between the dynamic random access memory and the non-volatile memory; wherein, the transfer period is within an address refresh cycle of the dynamic random access memory, and the address refresh cycle is a preset cycle period for performing a refresh operation on the dynamic random access memory; within the address refresh cycle, the host device stops performing data operations on the dynamic random access memory.

[0010] Optionally, within each maximum refresh interval cycle of the dynamic random access memory, it is divided into an address refresh cycle and a host device operable cycle; within the address refresh cycle, it is divided into a refresh execution period and an extended period, and the refresh execution period is a period for performing the refresh operation, and the transfer period is within the extended period.

[0011] Optionally, the control unit is further configured to read an access command stored in the dynamic random access memory; when the access command is to write write data to the non-volatile memory, the control unit transfers the write data cached in the dynamic random access memory to the non-volatile memory; when the access command is to read read data from the non-volatile memory, the control unit transfers the read data from the non-volatile memory to the dynamic random access memory for the host device to read.

[0012] Optionally, the storage module further includes: a driving unit, connected between the dual in-line interface and the dynamic random access memory, for enhancing the strength of a signal sent to the storage module, and the signal includes a combination of one or more of an address signal, a clock signal, and a data signal.

[0013] Optionally, the dual in-line interface, the dynamic random access memory, the control unit, and the non-volatile memory are all stacked using a three-dimensional heterogeneous stacking technology to form the storage module with a three-dimensional structure.

[0014] In a second aspect, there is provided an electronic system, including: a host device and the storage module according to any one of the first aspect; the host device is connected to the storage module through a standard double data rate interface, and the host device controls the dynamic random access memory as a cache unit; the host device receives the storage capacity information of the non-volatile memory uploaded by the storage module.

[0015] Optionally, the master device is further configured to send an access command to the storage module, and the storage module stores the access command in the dynamic random access memory; the control unit is further configured to read the access command stored in the dynamic random access memory; when the access command is to write write data to the non-volatile memory, the control unit transfers the write data cached in the dynamic random access memory to the non-volatile memory; when the access command is to read read data from the non-volatile memory, the control unit transfers the read data from the non-volatile memory to the dynamic random access memory for the master device to read.

[0016] The technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages: In the storage module and the electronic system provided in the embodiments of the present invention, it is set that the dynamic random access memory in the storage module is connected to the master device through a dual in-line interface, and the access commands issued by the master device are all stored in the dynamic random access memory. The control unit controls the data transfer between the dynamic random access memory and the non-volatile memory according to the access command. Therefore, the master device can realize data access without connecting to other types of memories and performing data transmission. Therefore, the storage module can be connected to the master device based on a standard DDR interface, and has strong versatility. Moreover, in this application, the dynamic random access memory is also set as a cache unit controlled by the master device. Therefore, the master device can not use the cache as the storage capacity it recognizes, so that it can recognize the capacity of the non-volatile memory in the storage module as the capacity of the storage module, taking into account the requirements of storage capacity recognition and adaptation to the general standard DDR interface.

[0017] The above description is only an overview of the technical solutions of the present invention. In order to be able to understand the technical means of the present invention more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention are specifically described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] By reading the detailed description of the preferred embodiments below, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention. Moreover, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings: Figure 1 is a schematic structural diagram of the storage module in the embodiment of the present invention Figure 1 ; Figure 2 is a schematic structural diagram of the dynamic random access memory in the embodiment of the present invention; Figure 3Schematic diagram of the refresh timing of the dynamic random access memory in the embodiment of the present invention; Figure 4 Schematic structure of the storage module in the embodiment of the present invention Figure 2 ; Figure 5 Schematic diagram of the structure of the electronic system in the embodiment of the present invention. Detailed implementation manners

[0019] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

[0020] Various schematic structural diagrams according to embodiments of the present disclosure are shown in the drawings. These figures are not drawn to scale, where for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary, and in practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0021] Please refer to Figure 1 , an embodiment of the present application provides a storage module, including: a dual in-line package (DIP) interface 1, a dynamic random access memory 2, a control unit 3, and a non-volatile memory 4. Among them, the dynamic random access memory 2 is connected to the memory interface of the main control device through the dual in-line package (DIP) interface 1 to serve as a cache unit controlled by the main control device and is used to store access commands issued by the main control device. Among them, the control unit 3 is connected to the dual in-line package (DIP) interface 1, the dynamic random access memory 2, and the non-volatile memory 4. The control unit 3 controls the data transfer between the dynamic random access memory 2 and the non-volatile memory 4 according to the access command.

[0022] In current mainstream NVDIMMs, after the NVDIMM-N is connected to the main control device, the main control device can only recognize the storage capacity of its DRAM by default, and the storage capacity of its flash memory (Negative-AND Flash Memory, NAND) cannot be recognized, thus affecting the overall capacity of the system. And for NVDIMM-F and NVDIMM-P, because their non-volatile memories need to be connected to the interface, they cannot be directly connected to the standard DDR interface, and the interface needs to be adapted and modified, resulting in poor versatility.

[0023] It should be noted that both the dual in-line pluggable interface 1 of the storage module of this application and the memory interface of the main control device (CPU or motherboard) are standard double data rate interfaces (standard DDR interfaces) defined by JEDEC, and no adaptation changes are required. Since the storage module provided in this application sets its dynamic random access memory 2 to be connected to the main control device through the dual in-line pluggable interface 1, and the dynamic random access memory 2 is controlled and accessed by the main control device (the dynamic random access memory 2 can be directly maintained by the driving unit of the main control device as a cache unit), while the non-volatile memory 4 is not directly accessed by the main control device. The access commands issued by the main control device are all stored in the dynamic random access memory 2, and the control unit 3 controls the data transfer between the dynamic random access memory 2 and the non-volatile memory 4 according to the access commands. Therefore, the main control device can achieve data writing and reading without connecting to the non-volatile memory 4 and performing data transmission. Thus, the storage module can be connected to the main control device based on the standard DDR interface, meeting the general requirements. Further, the dynamic random access memory 2 is also set as a cache unit controlled by the main control device. Therefore, the main control device can not use the cache as the storage capacity it recognizes, and thus can achieve the recognition of the capacity of the non-volatile memory 4 in the storage module through the control unit 3, taking into account the requirements of storage capacity recognition and adaptation to the general standard DDR interface.

[0024] Next, the structure of this storage module will be introduced in detail.

[0025] In an optional implementation manner, as Figure 2 shown, the dynamic random access memory 2 of the storage module can be divided into a data area 201 and a command area 202. The data area 201 is used to store cache data, and the command area 202 is used to store the access commands issued by the main control device.

[0026] Specifically, the access commands (at least including read commands and write commands) issued by the main control device to the storage module are all stored in the command area 202 of the dynamic random access memory 2. And the data issued by the main control device, or the data transferred from the non-volatile memory 4 to the dynamic random access memory 2 by the control unit 3, are all stored as cache data in the data area 201. Dividing the dynamic random access memory 2 in this way can improve the efficiency of the subsequent control unit 3 in obtaining access commands and transferring data, and can also avoid the interference of the control unit 3 in obtaining access commands with the storage of cache data due to mixed storage, and avoid interfering with the storage state of access commands when transferring data, effectively ensuring efficiency and reliability.

[0027] In an alternative embodiment, the control unit 3 can read the access commands stored in the dynamic random access memory 2. Specifically, the control unit 3 reads the access commands stored in the dynamic random access memory 2 in a triggered manner (the triggering factor can be detecting that the control device issues an access command, or receiving a transfer instruction) or periodically, and controls the data transfer between the dynamic random access memory 2 and the non-volatile memory 4 according to the access commands.

[0028] For example, when the access command is to write write data to the non-volatile memory 4, the control unit 3 transfers the write data cached in the dynamic random access memory 2 to the non-volatile memory 4.

[0029] Specifically, when the master device issues an access command for writing write data (the access command carries the address information of the non-volatile memory 4 and the write data) to the storage module, the access command is stored in the command area 202 of the dynamic random access memory 2, and the write data carried by the access command is stored as cached data in the data area 201 of the dynamic random access memory 2. The control unit 3 accesses the command area 202 to obtain the unprocessed access command, and transfers the corresponding write data in the data area 201 to the corresponding address of the non-volatile memory 4 for storage according to the address information carried by the access command. In this way, the master device can accurately write the write data without accessing the non-volatile memory 4.

[0030] As another example, when the access command is to read read data from the non-volatile memory 4, the control unit 3 transfers the read data from the non-volatile memory 4 to the dynamic random access memory 2 for the master device to read.

[0031] Specifically, when the master device issues an access command for reading read data (the access command carries address information) to the storage module, the access command is stored in the command area 202 of the dynamic random access memory 2. If the address information read by the master device is in the dynamic random access memory 2, the corresponding read data can be directly read from the data area 201 of the dynamic random access memory 2. If the address information read by the master device is in the non-volatile memory 4, the control unit 3 accesses the command area 202 to obtain the unprocessed access command, and transfers the read data at the corresponding address of the non-volatile memory 4 to the data area 201 of the dynamic random access memory 2 for storage according to the address information carried by the access command. Then the master device reads and obtains the read data from the dynamic random access memory 2. In this way, the master device can accurately read the read data without accessing the non-volatile memory 4.

[0032] In an alternative embodiment, after the access command of the master device is executed, the corresponding access command stored in the command area 202 of the dynamic random access memory 2 can be deleted, so that the commands read by the control unit 3 from the command area 202 are all commands that still need to be processed.

[0033] In an alternative embodiment, as Figure 3 shown ( Figure 3 where the abscissa is time t), the dynamic random access memory 2 needs to refresh to maintain the stored data, and the longest time interval for each refresh is the maximum refresh interval period tREFI. The maximum refresh interval period tREFI is the interval between two adjacent refresh commands. Within each maximum refresh interval period tREFI of the dynamic random access memory 2, it is divided into an address refresh period tRFC and a master device operable period. That is to say, the master device will only perform data operations on the dynamic random access memory 2 during the period outside the address refresh period tRFC.

[0034] The data transfer between the dynamic random access memory 2 and the non-volatile memory 4 controlled by the control unit 3 is all carried out during the transfer period. This transfer period is within the address refresh period tRFC of the dynamic random access memory 2, and the address refresh period tRFC is a preset cycle period for the dynamic random access memory 2 to perform the refresh operation. During the address refresh period tRFC, the master device stops performing data operations on the dynamic random access memory 2. In this way, performing the data transfer between the dynamic random access memory 2 and the non-volatile memory 4 within the address refresh period tRFC can effectively avoid conflicts between data transfer and the data operations of the master device, thereby ensuring the reliability of the data.

[0035] In an alternative embodiment, it can also be set that within the address refresh period tRFC, it is further divided into a refresh execution period t1 and an extended period t2. The refresh execution period t1 is the period for performing the refresh operation of the dynamic random access memory 2, and the data transfer period between the dynamic random access memory 2 and the non-volatile memory 4 is within the extended period t2. In this way, it can also effectively avoid conflicts between data transfer and the refresh operation, further ensuring the reliability of the data.

[0036] In an alternative embodiment, the control unit 3 is further configured to upload the storage capacity information of the non-volatile memory 4 to the master device. Since the master device controls the dynamic random access memory 2 as its cache unit rather than the terminal storage unit, the master device does not recognize the capacity of the dynamic random access memory 2 as the storage capacity of the storage module. The control unit 3 uploads the storage capacity information of the non-volatile memory 4 to the master device in a timely manner through the dual in-line interface 1, so that the master device can recognize the real-time storage capacity of the non-volatile memory 4 and use it as the storage capacity of the storage module, thereby enabling the connection of a non-volatile NVDIMM storage module with a larger capacity.

[0037] In an alternative embodiment, it may be set that the dual in-line interface 1, the dynamic random access memory 2, the control unit 3, and the non-volatile memory 4 are all stacked using a three-dimensional heterogeneous stacking technology to form a storage module with a three-dimensional structure. For example, the dual in-line interface 1, the dynamic random access memory 2, the control unit 3, and the non-volatile memory 4 can be respectively set on each wafer, and the wafers with the dual in-line interface, the wafers with the dynamic random access memory, the wafers with the control unit, and the wafers with the non-volatile memory are stacked using the three-dimensional heterogeneous stacking technology to form a storage module chip with a three-dimensional structure. Since the interaction between the dual in-line interface 1, the dynamic random access memory 2, the control unit 3, and the non-volatile memory 4 is completed inside the chip, the transmission speed between them is saved, and the storage access efficiency is improved.

[0038] Please refer to Figure 4 , it may be set that the storage module 401 further includes a driving unit 5, which is connected between the dual in-line interface 1 and the dynamic random access memory 2 and is configured to enhance the strength of the signal sent from the master device 402 to the storage module 401. The signal may include one or a combination of an address signal, a clock signal, and a data signal. By re-driving and enhancing the signal through the driving unit 5, the processing efficiency and reliability of the signal can be effectively improved.

[0039] Based on the same inventive concept, an embodiment of the present application further provides an electronic system, as Figure 5 shown, including: a master device 402 and the storage module 401 provided in any of the foregoing embodiments. The master device 402 is connected to the storage module 401 through a standard double data rate interface, and the master device 402 controls the dynamic random access memory as a cache unit. The master device 402 receives the storage capacity information of the non-volatile memory uploaded by the storage module 401.

[0040] Optionally, the master device 402 is further configured to send an access command to the storage module 401, and the storage module 401 stores the access command in the dynamic random access memory. The control unit is further configured to read the access command stored in the dynamic random access memory. When the access command is to write write data to the non-volatile memory, the control unit transfers the write data cached in the dynamic random access memory to the non-volatile memory. When the access command is to read read data from the non-volatile memory, the control unit transfers the read data from the non-volatile memory to the dynamic random access memory for the master device 402 to read.

[0041] Since the storage module 401 included in the electronic system introduced in the embodiments of the present application is exactly the storage module introduced in the foregoing embodiments of the present application, the principle and structure of the storage module, as well as its connection method with the master device 402 have been described in detail above, so it will not be repeated here. Any electronic system including the storage module of the embodiments of the present application falls within the scope of protection of the present invention.

[0042] The technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages: The storage module and the electronic system provided in the embodiments of the present invention are configured such that the dynamic random access memory in the storage module is connected to the master device through a dual in-line interface, and the access commands sent by the master device are all stored in the dynamic random access memory. The control unit controls the data transfer between the dynamic random access memory and the non-volatile memory according to the access command. Thus, the master device can achieve data access without connecting to other types of memories and performing data transmission. Therefore, the storage module can be connected to the master device based on a standard DDR interface, and has strong versatility. In addition, the present application also sets the dynamic random access memory as a cache unit controlled by the master device. Therefore, the master device can not use the cache as the storage capacity it recognizes, so as to be able to recognize the capacity of the non-volatile memory in the storage module, taking into account the requirements of storage capacity recognition and adaptation to the general standard DDR interface.

[0043] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings based herein. The structure required to construct such a system will be apparent from the above description. In addition, the present invention is not directed to any particular programming language. It should be understood that the content of the present invention described herein can be implemented using various programming languages, and the above description of specific languages is to disclose the best mode of the present invention.

[0044] In the description provided herein, numerous specific details are set forth. It will be understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0045] Similarly, it should be understood that in order to streamline this disclosure and assist in understanding one or more of the various inventive aspects, in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof.

[0046] Those skilled in the art will appreciate that the modules in the devices in the embodiments can be adaptively changed and disposed in one or more devices different from those of the embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and in addition, they can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all the features disclosed in this specification (including the abstract and drawings) and all the processes or units of any method or device so disclosed. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying abstract and drawings) can be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0047] In addition, those skilled in the art will be able to understand that although some embodiments herein include certain features included in other embodiments but not others, the combination of features of different embodiments means within the scope of the invention and forms different embodiments.

[0048] It should be noted that the above embodiments illustrate the invention rather than limit it. Any reference signs between parentheses should not be construed as limiting the invention. The word "comprising" does not exclude the presence of components or steps not listed in the invention. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The invention can be implemented by means of hardware including several different components and by means of a suitably programmed computer. In embodiments listing several devices, several of these devices can be embodied by the same item of hardware. The use of the words first, second, and third, etc. does not denote any order. These words can be interpreted as names.

Claims

1. A storage module, characterized in that, Comprising: Dual In-line Package (DIP) interface, Dynamic Random Access Memory (DRAM), control unit, and non-volatile memory; Wherein, the Dynamic Random Access Memory is connected to the memory interface of the host device through the Dual In-line Package (DIP) interface to serve as a cache unit controlled by the host device and is used to store the access commands issued by the host device; Wherein, the control unit is connected to the Dual In-line Package (DIP) interface, the Dynamic Random Access Memory, and the non-volatile memory; the control unit controls the data transfer between the Dynamic Random Access Memory and the non-volatile memory according to the access command.

2. The storage module according to claim 1, wherein The Dynamic Random Access Memory includes a data area and a command area, the data area is used to store cached data, and the command area is used to store the access commands issued by the host device.

3. The storage module according to claim 1, characterized in that: Both the Dual In-line Package (DIP) interface and the memory interface are standard Double Data Rate (DDR) interfaces; The control unit is further used to upload the storage capacity information of the non-volatile memory to the host device.

4. The storage module according to claim 1, characterized in that: During the transfer period, the control unit controls the data transfer between the Dynamic Random Access Memory and the non-volatile memory; Wherein, the transfer period is within the address refresh cycle of the Dynamic Random Access Memory, and the address refresh cycle is a preset cycle period for performing a refresh operation on the Dynamic Random Access Memory; within the address refresh cycle, the host device stops performing data operations on the Dynamic Random Access Memory.

5. The storage module according to claim 4, characterized in that: Within each maximum refresh interval cycle of the Dynamic Random Access Memory, it is divided into the address refresh cycle and the host device operable cycle; within the address refresh cycle, it is divided into a refresh execution period and an extended period, and the refresh execution period is the period for performing the refresh operation, and the transfer period is within the extended period.

6. The storage module according to claim 1, characterized in that: The control unit is further used to read the access commands stored in the Dynamic Random Access Memory; When the access command is to write write data to the non-volatile memory, the control unit transfers the write data cached in the Dynamic Random Access Memory to the non-volatile memory; When the access command is to read read data from the non-volatile memory, the control unit transfers the read data from the non-volatile memory to the Dynamic Random Access Memory for the host device to read.

7. The storage module according to claim 1, characterized in that Further comprising: A driving unit, connected between the Dual In-line Package (DIP) interface and the Dynamic Random Access Memory, for enhancing the strength of the signals sent to the storage module, and the signals include one or a combination of address signals, clock signals, and data signals.

8. The storage module according to claim 1, characterized in that: The dual in-line package interface, the dynamic random access memory, the control unit, and the non-volatile memory are all stacked using three-dimensional heterogeneous stacking technology to form the storage module with a three-dimensional structure.

9. An electronic system, characterized in that, Comprising: a main control device and the storage module according to any one of claims 1 to 8; the main control device is connected to the storage module through a standard double data rate interface, and the main control device controls the dynamic random access memory as a cache unit; the main control device receives the storage capacity information of the non-volatile memory uploaded by the storage module.

10. The electronic system according to claim 9, wherein: the main control device is further configured to issue an access command to the storage module, and the storage module stores the access command in the dynamic random access memory; the control unit is further configured to read the access command stored in the dynamic random access memory; when the access command is to write write data to the non-volatile memory, the control unit transfers the write data cached in the dynamic random access memory to the non-volatile memory; when the access command is to read read data from the non-volatile memory, the control unit transfers the read data from the non-volatile memory to the dynamic random access memory for the main control device to read.

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