Binary translation method, translator, electronic device and readable storage medium

Abstract

An embodiment of the present invention provides a binary translation method, a translator, an electronic device, and a readable storage medium. The method includes: when translating a direct jump instruction in a first code block, if it is determined that the jump target has a cross-page situation, then recording the jump target cross-page information, wherein the jump target cross-page information is used to indicate the cross-page type; according to the jump target cross-page information, executing a target link strategy for the first translation code block and the second translation code block; the target link strategy is used to determine whether the direct jump instruction meets the optimization condition based on the cross-page type indicated by the jump target cross-page information; if the optimization condition is met, then establishing a direct jump link between the first translation code block and the second translation code block. On the basis of ensuring correct execution, the embodiment of the present invention identifies the situation where the jump target crosses pages and can be optimized, further performs a link optimization operation, reduces the code block search operation during program execution, and improves program operation efficiency.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a binary translation method, a translator, an electronic device, and a readable storage medium. Background Art

[0002] Binary translation converts binary code from one ISA (Instruction Set Architecture) into binary code for another ISA. This technology allows applications written for one ISA (source architecture) to run on another ISA (target architecture).

[0003] Typically, "client" refers to the platform on which the simulated program runs, while "host" refers to the platform on which the binary translation system runs. This means that the binary translation system can simulate the running of client programs on the host. Depending on the level of the simulated program, binary translation can be categorized as user-level binary translation and system-level binary translation. User-level binary translation supports running client applications, while system-level binary translation supports running the entire client operating system, enabling the execution of any client application.

[0004] For direct jump instructions, since the jump target is always determined, code block linking can be used for translation optimization. By pre-generating direct jump paths between translation code blocks, execution can be continued directly from one translation code block to another, avoiding repeated search and translation overhead and improving execution efficiency.

[0005] However, system-level binary translation requires emulating the dynamic address mapping of the guest operating system (e.g., real-time conversion of virtual addresses to physical addresses). During a cross-page jump, the physical mapping of the target address may have changed, causing the originally linked translation block code to point to the wrong target, leading to semantic errors or crashes. Therefore, cross-page jumps typically do not utilize code block linking for translation optimization, sacrificing some performance to ensure correctness. Summary of the Invention

[0006] In view of the above problems, an embodiment of the present invention is proposed to provide a binary translation method that overcomes the above problems or at least partially solves the above problems. On the basis of ensuring correct execution, it can identify situations where jump targets can be optimized when they cross pages, thereby further performing optimization operations, further reducing the code block search operations during program execution, and improving program operation efficiency.

[0007] Correspondingly, the embodiments of the present invention further provide a binary translator, an electronic device, and a computer program product to ensure the implementation and application of the above method.

[0008] In a first aspect, an embodiment of the present invention discloses a binary translation method, which is applied to a system-level binary translator. The method includes:

[0009] When translating a direct jump instruction in the first code block, if it is determined that the jump target has a cross-page situation, then recording the jump target cross-page information; the jump target cross-page information is used to indicate the cross-page type; the direct jump instruction is to jump to the second code block;

[0010] executing a target linking strategy on a first translation code block and a second translation code block according to the recorded jump target cross-page information; the first translation code block is a code block after the first code block is translated, and the second translation code block is a code block after the second code block is translated; the target linking strategy is used to determine whether the direct jump instruction meets the optimization condition according to the cross-page type indicated by the jump target cross-page information;

[0011] If it is determined that the direct jump instruction meets the optimization condition, a direct jump link is established between the first translation code block and the second translation code block.

[0012] In a second aspect, an embodiment of the present invention discloses a system-level binary translator, the system-level binary translator comprising:

[0013] An information recording module is configured to record jump target cross-page information when translating a direct jump instruction in the first code block, if it is determined that the jump target crosses pages; the jump target cross-page information is used to indicate the type of cross-page; the direct jump instruction is to jump to the second code block;

[0014] a link detection module, configured to execute a target link strategy on a first translation code block and a second translation code block according to the recorded jump target cross-page information; the first translation code block is a code block translated from the first code block, and the second translation code block is a code block translated from the second code block; the target link strategy is configured to determine whether the direct jump instruction satisfies an optimization condition according to a cross-page type indicated by the jump target cross-page information;

[0015] The link optimization module is configured to establish a direct jump link between the first translation code block and the second translation code block if it is determined that the direct jump instruction meets the optimization condition.

[0016] In a third aspect, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of any of the binary translation methods described above.

[0017] In a fourth aspect, an embodiment of the present invention discloses a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the binary translation method as described above can be implemented.

[0018] In a fifth aspect, an embodiment of the present invention discloses a computer program product, comprising a computer program, which, when executed by a processor, performs the steps of any of the aforementioned binary translation methods.

[0019] The embodiments of the present invention include the following advantages:

[0020] When translating a direct jump instruction into the first code block, the embodiment of the present invention determines whether the jump target has a cross-page situation. If it is determined that the jump target has a cross-page situation, the jump target cross-page information is recorded, and the jump target cross-page information is used to indicate the type of cross-page. Thus, in the linking stage, the target linking strategy can be executed for the first translation code block and the second translation code block according to the jump target cross-page information recorded in the translation stage. The target linking strategy is used to determine whether the direct jump instruction meets the optimization condition based on the type of cross-page indicated by the jump target cross-page information. When it is determined that the direct jump instruction meets the optimization condition, the code block linking technology can be used to perform the optimization operation to establish a direct jump link between the first translation code block and the second translation code block. The embodiment of the present invention identifies different situations of cross-page jumps through the cooperation of the translation stage and the linking stage, and performs targeted processing to efficiently implement jump links, rather than completely abandoning the code block link optimization operation when the jump target crosses pages. On the basis of ensuring correct execution, the embodiment of the present invention identifies the situations where the jump target crosses pages and can be optimized, thereby further performing optimization operations, further reducing the code block search operations during program execution, and improving program operation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a flowchart of a binary translation method embodiment of the present invention;

[0022] Figure 2 It is a flow chart of executing the target link strategy according to the jump target cross-page information of the present invention;

[0023] Figure 3 is a schematic flow chart of the present invention performing the first detection operation;

[0024] Figure 4 is a schematic flow chart of the second detection operation performed by the present invention;

[0025] Figure 5 It is a schematic diagram of the present invention performing dynamic detection through a preset detection module;

[0026] Figure 6 is a structural block diagram of an embodiment of a system-level binary translator of the present invention;

[0027] Figure 7 It is a structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0029] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after the association are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0030] First, some concepts involved in the embodiments of the present invention are explained.

[0031] A code block is a continuous sequence of instructions (consisting of guest instructions) extracted from the guest program's executable binary code. It is the basic processing unit of binary translation. A code block, also known as a basic block, has only one entry point (the first instruction) and one exit point (the last instruction). There are no jump instructions in between. Except for the last instruction (such as a jump, call, or return instruction), all other instructions are executed sequentially, with no jumps out or jumps in.

[0032] A translated code block is a block of code that has undergone binary translation, meaning that the client instructions within the block have been translated into host instructions. Translated code blocks are typically cached in the code cache for subsequent direct execution, avoiding duplicate translation.

[0033] The Guest Virtual Address (GVA) is the virtual memory address used by the client program, that is, the logical address of the program code and data.

[0034] The Guest Physical Address (GPA) is the address obtained by the guest operating system through its memory management unit (MMU) after converting the GVA. This is what the guest operating system or runtime environment considers to be a "physical address." The guest operating system maps the GVA to the GPA, but these addresses are not actual physical addresses. Instead, they are further mapped into the host's address space by the binary translator or virtualization layer.

[0035] A page is the basic unit of memory management in an operating system. It is usually a fixed-size memory block (such as 4KB). In operating system memory management, in order to effectively manage memory, memory (virtual memory or physical memory) is divided into fixed-size pages.

[0036] A virtual page is a division unit of virtual memory space and is mapped to a physical page through a page table.

[0037] A physical page is a division unit of physical memory space and is a memory block that actually stores data.

[0038] The guest virtual address (GVA) consists of a virtual page number (VPN) and an offset within the page. The VPN is used to locate a virtual page, and the offset within the page is used to locate a specific byte within the virtual page.

[0039] The guest physical address (GPA) consists of a physical page frame number (PFN) and an offset within the page. The PFN is used to locate the physical page, and the offset within the page (Offset) is used to locate a specific byte within the physical page. It is exactly the same as the offset within the virtual page (because the virtual and physical pages are the same size).

[0040] The client virtual address GVA can obtain the corresponding physical page frame number PFN through page table mapping, and then combine it with the page offset to generate GPA to realize the conversion from virtual memory to physical memory.

[0041] A code block spans pages when it covers at least two virtual pages. For example, if some instructions in code block A are on one virtual page and others are on the next, then code block A is said to span pages. "Spanning" here means that the instruction address range of a code block straddles the boundaries of two or more virtual pages.

[0042] It should be noted that a code block spans pages if and only if the instruction sequence of the code block is continuously distributed in the virtual address space, and there is at least one instruction in the code block whose starting address is located on virtual page P1, and there is another instruction in the code block whose starting address is located on virtual page P2; or, part of an instruction is located on virtual page P1, and the other part is located on virtual page P2 (P1 ≠ P2).

[0043] For a code block, if it does not span pages, meaning all guest instructions in the code block are within the same virtual page, then the code block will correspond to only one guest physical page. After translation is complete, the corresponding translation code block is called an intra-page translation code block. If the code block spans pages, for example, if the guest instructions in the code block span two adjacent virtual pages, then the code block will correspond to two guest physical pages. After translation is complete, the corresponding translation code block is called an inter-page translation code block.

[0044] A direct jump instruction crosses pages when the jump target address of the direct jump instruction is different from the virtual page where the direct jump instruction resides. This is also called a cross-page jump. For example, if code block A ends with a direct jump instruction, which is used to jump to code block B, and the jump from code block A to code block B crosses pages, then the direct jump instruction is said to cross pages.

[0045] It should be noted that, in the embodiment of the present invention, "crossing pages" refers to crossing virtual pages, and pages in the following description all refer to virtual pages.

[0046] In binary translation, when translating to the direct jump instruction in the above-mentioned code block A, if code block B crosses pages, or the direct jump instruction crosses pages, the optimization operation of the translation code block of code block A and the translation code block of code block B through code block linking technology is abandoned, at the expense of translator performance to ensure correctness.

[0047] In order to further improve the translator performance and improve the program running efficiency on the basis of ensuring correctness, the embodiment of the present invention further determines whether the optimization conditions are met when the above two types of cross-page jumps exist. On the premise of ensuring the correctness of cross-page jumps, the code block linking technology can continue to be used for optimization to further improve the translator performance.

[0048] Reference Figure 1 , shows a flowchart of a binary translation method embodiment of the present invention, the method is applied to a system-level binary translator, and the method may include the following steps:

[0049] Step 101: When translating a direct jump instruction in a first code block, if it is determined that the jump target crosses pages, then record jump target cross-page information; the jump target cross-page information is used to indicate the type of cross-page; the direct jump instruction is to jump to a second code block;

[0050] Step 102: Execute a target linking strategy on a first translation code block and a second translation code block according to the recorded jump target cross-page information; the first translation code block is a code block after the first code block is translated, and the second translation code block is a code block after the second code block is translated; the target linking strategy is used to determine whether the direct jump instruction meets the optimization condition according to the cross-page type indicated by the jump target cross-page information;

[0051] Step 103: If it is determined that the direct jump instruction meets the optimization condition, a direct jump link is established between the first translation code block and the second translation code block.

[0052] In system-level binary translation, both the guest virtual address GVA and the actual address (guest physical address GPA) are needed to uniquely identify a code block.

[0053] For ease of description, the system-level binary translator is referred to as a translator in the embodiment of the present invention. Before executing the first translation code block in a page, the translator will check whether the virtual-to-real address mapping relationship of the page is correct. The virtual-to-real address mapping relationship refers to the mapping relationship between the client virtual address GVA and the actual address. This is because the operating system may perform various operations on the memory, such as page replacement, memory allocation adjustment, etc., which may cause the virtual-to-real address mapping relationship to change. If the virtual-to-real address mapping relationship is correct (such as no change), it means that all address accesses within the page are predictable and safe. When executing subsequent translation code blocks in the page, there is no need to repeatedly check the virtual-to-real address mapping relationship of the page.

[0054] In the embodiment of the present invention, the first code block refers to a code block ending with a direct jump instruction. The second code block refers to a target code block to which the direct jump instruction in the first code block jumps.

[0055] When translating a direct jump instruction into a first code block, an embodiment of the present invention determines whether the jump target has two page-crossing conditions: one is whether the second code block crosses pages; the second is whether the direct jump instruction crosses pages. When either of the above page-crossing conditions is determined, corresponding jump target page-crossing information is recorded. The jump target page-crossing information is used to indicate the type of page-crossing condition, such as the first page-crossing condition and / or the second page-crossing condition.

[0056] For example, assume that code block A (the first code block) ends with a direct jump instruction, which is used to jump to code block B (the second code block). When translating to the direct jump instruction in the first code block, whether code block A spans pages is known information for the following reasons: memory pages usually have a fixed size (such as 4KB), and the starting address is always aligned to the page size. When parsing code block A, the translator can record the starting address start_A of code block A and the size size_A of code block A, so it can calculate: the ending address end_A of code block A = start_A + size_A. By comparing whether start_A and end_A are located in the same page, it can be determined whether code block A spans pages.

[0057] When translating a direct jump instruction in a first code block (e.g., code block A), while the second code block (e.g., code block B) has not yet been translated, embodiments of the present invention preemptively determine whether the jump target spans pages. If so, the jump target spans pages, and if so, records the span information. Thus, after the translation of code block A is complete, in addition to recording the known information about whether code block A spans pages, the translator can also record the span information, providing a basis for subsequent optimization during linking.

[0058] Furthermore, the cross-page type may include at least one of the following: the second code block to which the direct jump instruction is to jump crosses pages; the direct jump instruction crosses pages. Exemplarily, the jump target cross-page information may be recorded as follows:

[0059] Information 1: The second code block spans pages.

[0060] Information 2: Direct jump instruction crosses pages.

[0061] The embodiment of the present invention does not limit the manner and location of recording the jump target cross-page information. For example, it can be recorded in the first translation code block or in the code cache.

[0062] An embodiment of the present invention determines in advance whether a jump target crosses pages during the code block translation stage, and if it is determined that the jump target crosses pages, records the jump target cross-page information to provide a reference basis for subsequent optimization processing, so that the code block linking technology can be used for optimization processing according to different situations during the linking stage.

[0063] According to the recorded jump target cross-page information, a target link strategy can be executed on the first translation code block and the second translation code block; the first translation code block is the code block translated from the first code block, and the second translation code block is the code block translated from the second code block.

[0064] The target linking strategy is used to determine whether the direct jump instruction meets the optimization conditions based on the cross-page type indicated by the jump target cross-page information, and then determine whether the first translation code block and the second translation code block can be optimized using code block linking technology, that is, whether it is possible to directly jump from the first translation code block to the second translation code block via a linking instruction sequence. The linking instruction sequence is used to jump to the starting address of the second translation code block in the code cache, eliminating the need to perform an operation to search for the second translation code block in the code cache. This can reduce the code block search operation during program execution and improve program operation efficiency.

[0065] For example, the target linking strategy can perform corresponding detection operations for two different types of jump target cross-pages to detect whether the virtual-to-real address mapping relationship of the page where the second code block is located is correct; if correct, the optimization operation can be performed; otherwise, the optimization operation is not performed. In this way, while ensuring correct execution, it is possible to further identify cases where the jump target crosses pages and optimize the operation.

[0066] If it is determined that the direct jump instruction meets the optimization conditions, the optimization operation can be performed. Specifically, a direct jump link can be established for the first translation code block and the second translation code block. The establishment of a direct jump link refers to directly jumping through the link instruction sequence without searching for the second translation code block in the code cache. If it is determined that the direct jump instruction does not meet the optimization conditions, the optimization operation is not performed. Specifically, the execution state can be exited and the second translation code block to be executed can be searched for, and then the jump can be performed. The search for the second translation code block to be executed can include: searching for the second translation code block corresponding to the second code block in the code cache, if found, obtaining the starting address of the second translation code block in the code cache, and jumping to the starting address for execution; if not found, entering the translation state, translating the second code block, and saving the second translation code block corresponding to the second code block to the code cache after the translation is completed, and jumping to the starting address of the second translation code block in the code cache for execution.

[0067] The embodiment of the present invention identifies different situations of cross-page jumps through the cooperation of the translation stage and the linking stage, and performs targeted processing to efficiently implement jump links, rather than completely abandoning the code block link optimization operation when the jump target crosses pages. On the basis of ensuring correct execution, the embodiment of the present invention identifies the situations where the jump target crosses pages and can be optimized, thereby further performing optimization operations, further reducing the code block search operations during program execution, and improving program operation efficiency.

[0068] In an optional embodiment of the present invention, the method may further include:

[0069] Step S11, determining the maximum instruction length of the client architecture;

[0070] Step S12: If the distance between the jump target address of the direct jump instruction and the current page boundary is less than the maximum instruction length, determining that the second code block spans pages;

[0071] Step S13, recording the jump target cross-page information includes: the second code block crosses pages.

[0072] The embodiment of the present invention determines whether the second code block spans pages based on the maximum instruction length of the client architecture and the distance between the jump target address of the direct jump instruction and the current page boundary.

[0073] In a specific implementation, the maximum instruction length of different client architectures may be different. For example, the instructions of the x86 architecture are variable length (1 to 15 bytes), that is, the maximum instruction length is 15 bytes, that is, the maximum length of an instruction is 15 bytes. If the distance between the jump target address of the direct jump instruction and the current page boundary is less than the maximum instruction length, such as less than 15 bytes, then its opcode or operand may extend to the next page. As a result, the second code block is divided into two parts by the page boundary: the first part is at the end of the current page, and the second part is at the beginning of the next page. Therefore, it can be determined that the second code block crosses pages, and the jump target cross-page information can be recorded including: the second code block crosses pages.

[0074] In an optional embodiment of the present invention, the method may further include:

[0075] Step S21, obtaining the address of the direct jump instruction according to the current program counter value;

[0076] Step S22: If the address of the direct jump instruction and the client virtual address of the second code block are not in the same page, determining that the direct jump instruction crosses pages;

[0077] Step S23 , recording the jump target cross-page information includes: the direct jump instruction crosses pages.

[0078] A direct jump instruction crosses pages when the jump target address of the direct jump instruction is different from the page where the direct jump instruction is located. For example, when jumping from code block A to code block B, the page crosses, and code block B is not on the same page as code block A.

[0079] The embodiment of the present invention can determine whether the direct jump instruction crosses pages by judging whether the address of the direct jump instruction (which is the client virtual address) and the client virtual address of the second code block are on the same page (that is, whether they are on the same virtual page).

[0080] Specifically, the address of the direct jump instruction can be obtained based on the current program counter value. The PC (Program Counter) is a register that stores the address of the instruction currently to be executed. In binary translation, the PC value typically refers to the guest virtual address (GVA). The current PC value indicates the address of the instruction currently to be executed (e.g., the address of the direct jump instruction in code block A).

[0081] The jump target address indicates the address to which the direct jump instruction is to jump, that is, the GVA address (such as GVA_B) of the second code block (such as code block B).

[0082] Determining whether a direct jump instruction spans pages involves comparing the current PC (the address of the current instruction) and GVA_B (the jump target address) to see if they are on the same page. Specifically, the direct jump instruction's address and the client virtual address of the second code block are compared to see if they are on the same page. If they are on the same page, the direct jump instruction does not span pages; if they are not, the direct jump instruction does span pages.

[0083] Furthermore, since the first code block (such as code block A) itself may also cross pages, when determining whether the direct jump instruction crosses pages, it is necessary to compare all pages covered by the first code block with the jump target address (the client virtual address of the second code block).

[0084] During the translation phase, the current PC value (i.e., the GVA address of the direct jump instruction, such as GVA_A_end) and the GVA address of the second code block (such as code block B) (such as GVA_B) are known and available. By comparing whether GVA_A_end and GVA_B are located on the same page, it can be determined whether the direct jump instruction crosses pages.

[0085] Assume that the page where the GVA address (GVA_A_end) of the direct jump instruction is located is denoted as Page_PC, and the page where the GVA address (GVA_B) of the second code block is located is denoted as Page_B. By determining whether Page_PC and Page_B are the same page, it is possible to determine whether the direct jump instruction crosses pages. Specifically, if Page_PC and Page_B are the same page, the direct jump instruction is determined not to cross pages; otherwise, the direct jump instruction is determined to cross pages.

[0086] The first code block (e.g., code block A) spans pages, which means that the first code block (e.g., code block A) covers at least two pages. In the embodiments of the present invention, the spanning of pages is described as covering two pages. For spanning three or more pages, the processing is similar and can be referenced.

[0087] Assume that the first code block (e.g., code block A) spans two pages. That is, the instruction sequence contained in the first code block (e.g., code block A) spans two adjacent pages, such as Page_A1 and Page_A2. The direct jump instruction may be in Page_A1 or Page_A2. It is necessary to determine whether Page_A1 and Page_B are the same page, and whether Page_A2 and Page_B are the same page. If Page_B is the same page as Page_A1 or Page_A2, then the direct jump instruction is determined not to span pages; otherwise, the direct jump instruction is determined to span pages.

[0088] It is understandable that if the first code block (such as code block A) spans multiple pages, all involved pages need to be checked.

[0089] When the jump target of the direct jump instruction in the first code block (such as code block A) crosses pages, this solution further determines whether the optimization conditions are met in the cross-page situation. During the judgment process, in addition to determining the cross-page situation of the second code block (such as code block B) and the cross-page situation of the direct jump instruction, the cross-page situation of the first code block (such as code block A) is also combined for judgment. Different situations are subdivided and different detection operations are performed to minimize the cost of executing the detection operation, improve the execution efficiency of detecting whether the optimization conditions are met in the cross-page situation, thereby improving the program running efficiency and the translator performance.

[0090] It should be noted that the embodiment of the present invention does not limit the method of determining whether the second code block crosses pages and determining whether the direct jump instruction crosses pages. Different judgment methods may be used according to different client architectures and translator implementations.

[0091] In an optional embodiment of the present invention, the cross-page type includes at least one of the following: the second code block to which the direct jump instruction is to jump crosses pages; the direct jump instruction crosses pages; and executing the target linking strategy on the first translation code block and the second translation code block based on the recorded jump target cross-page information may include:

[0092] Step S31: If the second code block spans pages, perform a first detection operation, and determine whether the direct jump instruction meets the optimization condition based on the result of the first detection operation;

[0093] Step S32: If the second code block does not span pages, and the direct jump instruction spans pages, a second detection operation is performed, and based on a result of the second detection operation, it is determined whether the direct jump instruction meets the optimization condition.

[0094] Step S33: If the second code block does not cross pages and the direct jump instruction does not cross pages, it is determined that the direct jump instruction meets the optimization condition.

[0095] Reference Figure 2 , shows a flow chart of the present invention for executing the target link strategy according to the jump target cross-page information. Figure 2 The process shown is executed at the stage of linking the first translated code block after the first code block is translated to obtain the first translated code block.

[0096] like Figure 2 As shown, based on the recorded jump target cross-page information, it is determined whether the second code block crosses pages. If the second code block crosses pages, a first detection operation is performed. If the second code block does not cross pages, but the direct jump instruction does cross pages, a second detection operation is performed. If the second code block does not cross pages, and the direct jump instruction does not cross pages, it can be directly determined that the direct jump instruction meets the optimization condition, and a direct jump link (direct link) can be established to perform a direct jump.

[0097] Wherein, if the second code block spans pages, it indicates that the second code block covers at least two pages. The first detection operation is used to detect whether the virtual-to-real address mapping relationship of the multiple pages covered by the second code block is correct. Based on the result of the first detection operation, it can be determined whether the direct jump instruction meets the optimization condition.

[0098] It can be understood that the single page, two pages, and multiple pages described in the embodiments of the present invention refer to a single virtual page, two virtual pages, and multiple virtual pages.

[0099] If the second code block does not span pages, but the direct jump instruction spans pages, the second code block only covers a single page. The second detection operation is used to detect whether the virtual-to-real address mapping relationship of the single page covered by the second code block is correct. Based on the result of the second detection operation, it can be determined whether the direct jump instruction meets the optimization condition.

[0100] If the jump target cross-page information recorded in the translation stage is empty, it means that the jump target does not cross pages, that is, the second code block does not cross pages, and the direct jump instruction does not cross pages. At this time, it can be directly determined that the direct jump instruction meets the optimization conditions without any detection operation, which can greatly improve the execution efficiency.

[0101] In an optional embodiment of the present invention, performing the first detection operation and determining whether the direct jump instruction meets the optimization condition according to the result of the first detection operation may include:

[0102] Step S41: Determine whether all pages covered by the second code block are the same as all pages covered by the first code block;

[0103] Step S42: If all pages covered by the second code block are the same as all pages covered by the first code block, it is determined that the direct jump instruction meets the optimization condition;

[0104] Step S43: If there are different pages among all the pages covered by the second code block and all the pages covered by the first code block, dynamic detection is performed on the different pages among all the pages covered by the second code block. If the different pages pass the dynamic detection, it is determined that the direct jump instruction meets the optimization condition; otherwise, it is determined that the direct jump instruction does not meet the optimization condition.

[0105] Reference Figure 3 , which shows a schematic flow chart of performing the first detection operation according to an embodiment of the present invention. Figure 3 The illustrated process is executed when the second code block is determined to span pages during the linking phase of the first translation code block. In this case, since the second code block covers at least two pages, the direct jump instruction can only be determined to meet the optimization conditions if the virtual-to-real address mapping relationship of all pages covered by the second code block is correct.

[0106] like Figure 3 As shown, taking the second code block covering two pages as an example, it is determined whether the two pages covered by the second code block are the same as all the pages covered by the first code block.

[0107] Furthermore, depending on whether the first code block spans pages, step S41 has the following two cases: In the first case, if the first code block spans pages (taking two pages as an example), it is determined whether the two pages covered by the second code block are identical to the two pages covered by the first code block. In the second case, if the first code block does not span pages, it is determined whether each of the two pages covered by the second code block is identical to a page covered by the first code block.

[0108] Assume that the two pages covered by the first code block are P1 and P2, and the two pages covered by the second code block are also P1 and P2. That is, all pages covered by the second code block are the same as all pages covered by the first code block, then it is determined that the direct jump instruction meets the optimization conditions and can be directly linked.

[0109] Suppose the two pages covered by the first code block are P1 and P2, and the two pages covered by the second code block are P2 and P3. That is, if there are different pages (such as P3) among all the pages covered by the second code block and all the pages covered by the first code block, dynamic detection needs to be performed on this different page (P3). When this different page (P3) passes the dynamic detection, it is determined that the direct jump instruction meets the optimization condition; otherwise, it is determined that the direct jump instruction does not meet the optimization condition. Among them, the dynamic detection is used to check whether the virtual-to-physical address mapping relationship of this page is correct. If it is correct, it passes the dynamic detection; otherwise, it fails the dynamic detection.

[0110] Similarly, suppose the two pages covered by the first code block are P1 and P2, and the two pages covered by the second code block are P0 and P1. That is, if there are different pages (such as P0) among all the pages covered by the second code block and all the pages covered by the first code block, dynamic detection needs to be performed on this different page (P0). When this different page (P0) passes the dynamic detection, it is determined that the direct jump instruction meets the optimization condition; otherwise, it is determined that the direct jump instruction does not meet the optimization condition.

[0111] Suppose the two pages covered by the first code block are P1 and P2, and the two pages covered by the second code block are P3 and P4. That is, if there are different pages (such as P3 and P4) among all the pages covered by the second code block and all the pages covered by the first code block, dynamic detection needs to be performed on this different page (P3) and this different page (P4) respectively. When this different page (P3) and this different page (P4) both pass the dynamic detection, it is determined that the direct jump instruction meets the optimization condition; otherwise, it is determined that the direct jump instruction does not meet the optimization condition.

[0112] It should be noted that in binary translation, when executing the direct jump instruction in the first code block, since the first code block has been executed, it means that the page where the first code block is located has passed the dynamic detection. At this time, it is necessary to jump to the second code block. If there are different pages between the pages covered by the second code block and the pages covered by the first code block, these different pages have not been dynamically detected yet. Therefore, only dynamic detection needs to be performed on each different page respectively. When all different pages pass the dynamic detection, it is determined that the direct jump instruction meets the optimization condition. If there is one different page that fails the dynamic detection, it is determined that the direct jump instruction does not meet the optimization condition.

[0113] It should be noted that in the above example, P0, P1, P2, P3, and P4 are 5 consecutive pages, and P0 < P1, and so on.

[0114] In an optional embodiment of the present invention, performing the second detection operation and determining whether the direct jump instruction meets the optimization condition according to the result of the second detection operation may include:

[0115] Step S51: Determine whether a single page covered by the second code block is the same as all pages covered by the first code block;

[0116] Step S52: If the single page covered by the second code block is the same as all the pages covered by the first code block, it is determined that the direct jump instruction meets the optimization condition;

[0117] Step S53: If the single page covered by the second code block is not the same as any of the pages covered by the first code block, dynamic detection is performed on the single page covered by the second translation code block. If the single page passes the dynamic detection, it is determined that the direct jump instruction meets the optimization condition; otherwise, it is determined that the direct jump instruction does not meet the optimization condition.

[0118] Reference Figure 4 , which shows a schematic flow chart of performing the second detection operation according to an embodiment of the present invention. Figure 4 The illustrated process is executed during the linking phase of the first translated code block, when it is determined that the second code block does not span pages, but the direct jump instruction spans pages. In this case, the second code block covers a single page. Therefore, as long as the mapping relationship between the virtual and real addresses of the single page covered by the second code block is correct, it can be determined that the direct jump instruction meets the optimization conditions.

[0119] like Figure 4 As shown, it is determined whether the single page covered by the second code block is the same page as all the pages covered by the first code block. It can be understood that, for the case where the first code block may cross pages or not, the first code block may cover a single page or multiple pages (taking two pages as an example). If the single page covered by the second code block is the same page as all the pages covered by the first code block, it can be directly determined that the direct jump instruction meets the optimization conditions without performing a detection operation. Since the page where the first code block is located has passed the dynamic detection at this time, and the second code block only covers a single page, therefore, if the single page covered by the second code block is the same page as all the pages covered by the first code block, it means that the single page covered by the second code block has also passed the dynamic detection, and no dynamic detection is required.

[0120] If the single page covered by the second code block does not exist in the same page as all the pages covered by the first code block, it is necessary to perform dynamic detection on the single page covered by the second translation code block. If the single page passes the dynamic detection, it is determined that the direct jump instruction meets the optimization conditions; otherwise, it is determined that the direct jump instruction does not meet the optimization conditions.

[0121] In an optional embodiment of the present invention, the method may further include:

[0122] A first instruction sequence and a second instruction sequence are inserted at the end of the first translation code block; the first instruction sequence is used to execute the target linking strategy and, if it is determined that the direct jump instruction meets the optimization condition, jump to the second instruction sequence; and, if it is determined that the direct jump instruction does not meet the optimization condition, exit the execution state and search for a second translation code block to be executed; the second instruction sequence is used to establish a direct jump link between the first translation code block and the second translation code block.

[0123] Exemplarily, when the system-level binary translator translates a direct jump instruction in the first code block, it translates the direct jump instruction into a target host machine instruction sequence, which is used to find the second translation code block to be jumped to (to be executed) according to the target jump address of the direct jump instruction and perform the jump.

[0124] An embodiment of the present invention inserts a first instruction sequence and a second instruction sequence before the target host machine instruction sequence, wherein the first instruction sequence is used to execute a target linking strategy on the first translation code block and the second translation code block according to the recorded jump target cross-page information, and jump to the second instruction sequence when it is determined that the direct jump instruction meets the optimization conditions, and jump to the above-mentioned target host machine instruction sequence when it is determined that the direct jump instruction does not meet the optimization conditions, exit the execution state and enter the code block search phase to search for the second translation code block to be executed.

[0125] The first instruction sequence and the second instruction sequence are both instruction sequences of the host machine architecture.

[0126] The second instruction sequence may initially be a NOP (No Operation) instruction sequence of the host architecture. When the CPU executes the NOP instruction sequence, it does not have any substantial impact on registers, memory, or program state. It simply consumes one or more clock cycles before continuing to execute the next instruction.

[0127] During the execution of the target link strategy, if it is determined that the direct jump instruction meets the optimization conditions, the NOP instruction sequence is replaced with a link instruction sequence, and the link instruction sequence can be used to directly jump to the starting address of the second translation code block in the code cache. If it is determined that the direct jump instruction does not meet the optimization conditions, the NOP instruction sequence is not replaced, and the original target host machine instruction sequence is continued to be executed, thereby exiting the execution state and searching for the second translation code block to be executed, and then jumping.

[0128] In an embodiment of the present invention, the cross-page situation of the jump target of a direct jump instruction is determined in advance during the translation phase, the jump target cross-page information is recorded, and preprocessing is performed during the translation phase, such as inserting a first instruction sequence and a second instruction sequence, in preparation for optimization processing during the linking phase. During the linking phase, a target linking strategy is implemented, and different detection operations are performed for different cross-page situations based on the jump target cross-page information recorded during the translation phase to determine whether the direct jump instruction meets the optimization conditions when the jump target has cross-pages. If the optimization conditions are met, the optimization operation can still be performed.

[0129] It should be noted that the embodiments of the present invention do not limit the method of dynamic detection. For example, when translating each code block, the GVA address of the code block can be converted to obtain the corresponding client physical address (such as recorded as GPA1), and the client physical address GPA1 of the code block during translation is recorded. When performing dynamic detection in the linking stage, the GVA address of the second code block can be input into a preset detection module, and the detection module converts the GVA address of the second code block to obtain the corresponding client physical address (such as recorded as GPA2), and compares the client physical address GPA2 obtained by real-time conversion with the client physical address GPA1 of the second code block recorded during translation. If the two are the same, it means that the virtual-to-real address mapping relationship of the page where the second code block is located is correct, and the dynamic detection passes; otherwise, it means that the virtual-to-real address mapping relationship of the page where the second code block is located is incorrect, and the dynamic detection fails.

[0130] Reference Figure 5 , shows a schematic diagram of an embodiment of the present invention performing dynamic detection using a pre-set detection module. The input of the detection module can be the client virtual address (GVA) of the page to be detected in the second code block. The client virtual address of the page to be detected can include the starting address (e.g., denoted as GVA_start) and the ending address (e.g., denoted as GVA_end) of the page to be detected. For example, when dynamic detection is required for two pages P3 and P4 covered by the second code block, P3 and P4 are the pages to be detected.

[0131] During the code block translation phase, the client virtual address (GVA) of the code block can be converted to obtain the corresponding client physical address (GPA1), and the client physical address (GPA1) corresponding to the client virtual address (GVA) is recorded. Specifically, the starting address (GVA_start) and ending address (GVA_end) of the client virtual address of the page covered by the code block are converted to obtain the corresponding starting address (GPA_start1) and ending address (GPA_end1) of the client physical address.

[0132] During the code block linking phase, the starting address GVA_start and ending address GVA_end of the page to be tested are input into a pre-set module. The detection module converts the received starting address GVA_start and ending address GVA_end of the page to be tested to obtain the corresponding starting address (e.g., GPA_start2) and ending address (e.g., GPA_end2) of the client physical address. The GPA_start2 calculated in real time is compared with the GPA_start1 recorded during translation, and the GPA_end2 calculated in real time is compared with the GPA_end1 recorded during translation. If the comparisons are the same, the virtual-to-real address mapping relationship of the page to be tested is correct and the page to be tested passes dynamic testing. Otherwise, the virtual-to-real address mapping relationship of the page to be tested is incorrect and the page to be tested fails dynamic testing.

[0133] Furthermore, the detection module may include a multi-page detection module and a single-page detection module, wherein the multi-page detection module is used to dynamically detect multiple pages covered by the second code block and the single-page detection module is used to dynamically detect a single page covered by the second code block.

[0134] For example, the pages covered by the second code block include P3 and P4. If dynamic detection is required for both P3 and P4, the GVA address range of the second code block is input into the multi-page detection module in the detection module. The multi-page detection module determines the starting address ranges corresponding to P3 and P4 respectively according to the GVA address range of the second code block, converts the GVA starting address ranges corresponding to P3 and P4 respectively, obtains the GPA starting address ranges corresponding to P3 and P4 respectively, and compares them with the GPA starting address ranges recorded during translation. If they are consistent, the dynamic detection passes, and it can be ensured that the mapping of P3 and P4 is correct; otherwise, the dynamic detection fails.

[0135] In summary, the embodiment of the present invention determines whether the jump target has a cross-page situation when translating to the direct jump instruction in the first code block. If it is determined that the jump target has a cross-page situation, the jump target cross-page information is recorded, and the jump target cross-page information is used to indicate the cross-page type. Therefore, in the linking stage, the target linking strategy can be executed for the first translation code block and the second translation code block according to the jump target cross-page information recorded in the translation stage. The target linking strategy is used to determine whether the direct jump instruction meets the optimization condition based on the cross-page type indicated by the jump target cross-page information. When it is determined that the direct jump instruction meets the optimization condition, the code block linking technology can be used to perform the optimization operation to establish a direct jump link between the first translation code block and the second translation code block. The embodiment of the present invention identifies different situations of cross-page jumps through the cooperation of the translation stage and the linking stage, and performs targeted processing to efficiently implement jump links, rather than completely abandoning the code block link optimization operation when the jump target crosses pages. On the basis of ensuring correct execution, the embodiment of the present invention identifies the situations where the jump target crosses pages and can be optimized, thereby further performing optimization operations, further reducing the code block search operations during program execution, and improving program operation efficiency.

[0136] Furthermore, the present invention pre-determines whether a jump target spans pages during the translation phase of the first code block and records this information, providing a basis for optimization during the subsequent linking phase. During the linking phase of the first code block, different detection operations are performed based on the different spans of the jump target, minimizing the dynamic detection cost to determine whether the direct jump instruction meets the optimization criteria, thereby improving system performance.

[0137] It should be noted that for the sake of simplicity, the method embodiments are described as a series of actions. However, those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0138] Reference Figure 6 , shows a structural block diagram of an embodiment of a system-level binary translator of the present invention, wherein the system-level binary translator may include:

[0139] An information recording module 601 is configured to record jump target cross-page information when translating a direct jump instruction in a first code block, if it is determined that the jump target crosses pages; the jump target cross-page information is used to indicate the type of cross-page; the direct jump instruction is to jump to a second code block;

[0140] A link detection module 602 is configured to execute a target link strategy on a first translation code block and a second translation code block according to the recorded jump target cross-page information; the first translation code block is a code block translated from the first code block, and the second translation code block is a code block translated from the second code block; the target link strategy is configured to determine whether the direct jump instruction meets the optimization condition according to the cross-page type indicated by the jump target cross-page information;

[0141] The link optimization module 603 is configured to establish a direct jump link between the first translation code block and the second translation code block if it is determined that the direct jump instruction meets the optimization condition.

[0142] Optionally, the cross-page type includes at least one of the following: the second code block to which the direct jump instruction is to jump crosses pages; the direct jump instruction crosses pages; the link detection module includes:

[0143] a first detection submodule, configured to perform a first detection operation if the second code block spans pages, and determine whether the direct jump instruction meets an optimization condition based on a result of the first detection operation;

[0144] a second detection submodule, configured to perform a second detection operation if the second code block does not cross pages and the direct jump instruction crosses pages, and determine whether the direct jump instruction meets an optimization condition based on a result of the second detection operation;

[0145] The third detection submodule is configured to determine that the direct jump instruction meets an optimization condition if the second code block does not cross pages and the direct jump instruction does not cross pages.

[0146] Optionally, the first detection submodule includes:

[0147] a first judging unit, configured to judge whether all pages covered by the second code block are the same as all pages covered by the first code block;

[0148] a first determining unit, configured to determine that the direct jump instruction satisfies an optimization condition if all pages covered by the second code block are the same as all pages covered by the first code block;

[0149] The first detection unit is used to perform dynamic detection on the different pages among all the pages covered by the second code block if there are different pages among all the pages covered by the second code block and all the pages covered by the first code block. If the different pages pass the dynamic detection, it is determined that the direct jump instruction meets the optimization condition; otherwise, it is determined that the direct jump instruction does not meet the optimization condition.

[0150] Optionally, the second detection submodule includes:

[0151] a second determining unit, configured to determine whether a single page covered by the second code block is the same as all pages covered by the first code block;

[0152] a second determining unit, configured to determine that the direct jump instruction satisfies an optimization condition if the single page covered by the second code block is the same as all the pages covered by the first code block;

[0153] The second detection unit is used to perform dynamic detection on the single page covered by the second translation code block if the single page covered by the second code block does not exist in the same page among all the pages covered by the first code block. If the single page passes the dynamic detection, it is determined that the direct jump instruction meets the optimization condition; otherwise, it is determined that the direct jump instruction does not meet the optimization condition.

[0154] Optionally, the system-level binary translator further includes:

[0155] a length determination module for determining a maximum instruction length of a client architecture;

[0156] a first information determining module, configured to determine that the second code block spans pages if the distance between the jump target address of the direct jump instruction and the current page boundary is less than the maximum instruction length;

[0157] The first information recording module is configured to record the jump target cross-page information including: the second code block crosses pages.

[0158] Optionally, the system-level binary translator further includes:

[0159] An address acquisition module, configured to acquire the address of the direct jump instruction according to a current program counter value;

[0160] a second information determining module, configured to determine that the direct jump instruction crosses pages if the address of the direct jump instruction and the client virtual address of the second code block are not in the same page;

[0161] The second information recording module is configured to record the jump target cross-page information including: the direct jump instruction cross-page information.

[0162] Optionally, the system-level binary translator further includes:

[0163] An instruction insertion module is configured to insert a first instruction sequence and a second instruction sequence at the end of the first translation code block; the first instruction sequence is configured to execute the target linking strategy and, if it is determined that the direct jump instruction satisfies an optimization condition, jump to the second instruction sequence; and, if it is determined that the direct jump instruction does not satisfy the optimization condition, exit the execution state and search for a second translation code block to be executed; and the second instruction sequence is configured to establish a direct jump link between the first translation code block and the second translation code block.

[0164] Optionally, the system-level binary translator further includes:

[0165] The exit search module is configured to exit the execution state and search for a second translation code block to be executed if it is determined that the direct jump instruction does not meet the optimization condition.

[0166] The system-level binary translator provided by an embodiment of the present invention determines whether the jump target has a cross-page situation when translating to a direct jump instruction in the first code block. If it is determined that the jump target has a cross-page situation, the jump target cross-page information is recorded, and the jump target cross-page information is used to indicate the type of cross-page. Therefore, in the linking stage, the target linking strategy can be executed on the first translation code block and the second translation code block according to the jump target cross-page information recorded in the translation stage. The target linking strategy is used to determine whether the direct jump instruction meets the optimization condition based on the type of cross-page indicated by the jump target cross-page information. In the case of determining that the direct jump instruction meets the optimization condition, the code block linking technology can be used to perform the optimization operation to establish a direct jump link between the first translation code block and the second translation code block. The embodiment of the present invention identifies different situations of cross-page jumps through the cooperation of the translation stage and the linking stage, and performs targeted processing to efficiently implement jump links, rather than completely abandoning the code block link optimization operation when the jump target crosses pages. On the basis of ensuring correct execution, the embodiment of the present invention identifies the situations where the jump target crosses pages and can be optimized, thereby further performing optimization operations, further reducing the code block search operations during program execution, and improving program operation efficiency.

[0167] Furthermore, the system-level binary translator provided by an embodiment of the present invention determines in advance during the translation phase of the first code block whether a jump target spans pages, and records this information, providing a basis for determining whether optimization operations are performed during the subsequent linking phase. During the linking phase of the first code block, different detection operations are performed based on the different spans of the jump target, thereby minimizing the dynamic detection cost to determine whether the direct jump instruction meets the optimization criteria, thereby helping to improve system performance.

[0168] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0169] Reference Figure 7 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 7 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method of the above embodiment.

[0170] An embodiment of the present invention provides a non-transitory computer-readable storage medium. When instructions in the storage medium are executed by a program or processor of a terminal, the terminal is enabled to perform the steps of the binary translation method of the aforementioned embodiment.

[0171] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0172] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, binary translators, or computer program products. Thus, embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0173] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0174] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0175] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0176] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0177] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A binary translation method, characterized in that: Applied to a system-level binary translator, the method includes: When translating a direct jump instruction in a first code block, if it is determined that the jump target spans pages, jump target span information is recorded; the jump target span information is used to indicate a span type; the direct jump instruction is to jump to a second code block; the span type includes at least one of the following: the second code block to which the direct jump instruction is to jump spans pages, which means that the second code block covers at least two pages; the direct jump instruction spans pages, which means that the jump target address of the direct jump instruction is different from the page where the direct jump instruction is located; executing a target linking strategy on a first translation code block and a second translation code block according to the recorded jump target cross-page information; the first translation code block is a code block after the first code block is translated, and the second translation code block is a code block after the second code block is translated; the target linking strategy is used to determine whether the direct jump instruction meets the optimization condition according to the cross-page type indicated by the jump target cross-page information; If it is determined that the direct jump instruction meets the optimization condition, a direct jump link is established between the first translation code block and the second translation code block.

2. The method according to claim 1, characterized in that The step of executing a target linking strategy on the first translation code block and the second translation code block according to the recorded jump target cross-page information includes: If the second code block spans pages, performing a first detection operation, and determining whether the direct jump instruction meets the optimization condition according to a result of the first detection operation; If the second code block does not cross pages and the direct jump instruction crosses pages, performing a second detection operation and determining whether the direct jump instruction meets the optimization condition according to a result of the second detection operation; If the second code block does not cross pages and the direct jump instruction does not cross pages, it is determined that the direct jump instruction meets the optimization condition.

3. The method according to claim 2, characterized in that The performing of the first detection operation and determining whether the direct jump instruction satisfies the optimization condition according to the result of the first detection operation includes: Determining whether all pages covered by the second code block are the same as all pages covered by the first code block; If all pages covered by the second code block are the same as all pages covered by the first code block, determining that the direct jump instruction meets the optimization condition; If there are different pages among all the pages covered by the second code block and all the pages covered by the first code block, dynamic detection is performed on the different pages among all the pages covered by the second code block. If the different pages pass the dynamic detection, it is determined that the direct jump instruction meets the optimization conditions; otherwise, it is determined that the direct jump instruction does not meet the optimization conditions.

4. The method according to claim 2, characterized in that The performing of the second detection operation and determining whether the direct jump instruction satisfies the optimization condition according to a result of the second detection operation includes: Determining whether a single page covered by the second code block is the same as all pages covered by the first code block; If the single page covered by the second code block is the same as all the pages covered by the first code block, determining that the direct jump instruction meets the optimization condition; If the single page covered by the second code block does not exist in the same page as all the pages covered by the first code block, dynamic detection is performed on the single page covered by the second translation code block. If the single page passes the dynamic detection, it is determined that the direct jump instruction meets the optimization condition; otherwise, it is determined that the direct jump instruction does not meet the optimization condition.

5. The method according to any one of claims 1 to 4, characterized in that The method further comprises: Determine the maximum instruction length for the client architecture; If the distance between the jump target address of the direct jump instruction and the current page boundary is less than the maximum instruction length, determining that the second code block spans pages; Recording the jump target cross-page information includes: the second code block crosses pages.

6. The method according to any one of claims 1 to 4, characterized in that The method further comprises: Obtaining the address of the direct jump instruction according to the current program counter value; If the address of the direct jump instruction and the client virtual address of the second code block are not in the same page, determining that the direct jump instruction crosses pages; Recording the jump target cross-page information includes: the direct jump instruction crosses pages.

7. The method according to any one of claims 1 to 4, characterized in that The method further comprises: A first instruction sequence and a second instruction sequence are inserted at the end of the first translation code block; the first instruction sequence is used to execute the target linking strategy and, if it is determined that the direct jump instruction meets the optimization condition, jump to the second instruction sequence; and, if it is determined that the direct jump instruction does not meet the optimization condition, exit the execution state and search for a second translation code block to be executed; the second instruction sequence is used to establish a direct jump link between the first translation code block and the second translation code block.

8. The method according to any one of claims 1 to 4, characterized in that The method further comprises: If it is determined that the direct jump instruction does not meet the optimization condition, the execution state is exited and the second translation code block to be executed is searched.

9. A system-level binary translator, characterized in that: The system-level binary translator includes: An information recording module is configured to, when translating a direct jump instruction in a first code block, record jump target cross-page information if it is determined that the jump target crosses pages; the jump target cross-page information is used to indicate a type of cross-page; the direct jump instruction is to jump to a second code block; the cross-page type includes at least one of the following: the second code block to which the direct jump instruction is to jump crosses pages, which means that the second code block covers at least two pages; the direct jump instruction crosses pages, which means that the jump target address of the direct jump instruction is different from the page where the direct jump instruction is located; a link detection module, configured to execute a target link strategy on a first translation code block and a second translation code block according to the recorded jump target cross-page information; the first translation code block is a code block translated from the first code block, and the second translation code block is a code block translated from the second code block; the target link strategy is configured to determine whether the direct jump instruction satisfies an optimization condition according to a cross-page type indicated by the jump target cross-page information; The link optimization module is configured to establish a direct jump link between the first translation code block and the second translation code block if it is determined that the direct jump instruction meets the optimization condition.

10. The system-level binary translator according to claim 9, characterized in that: The link detection module includes: a first detection submodule, configured to perform a first detection operation if the second code block spans pages, and determine whether the direct jump instruction meets an optimization condition based on a result of the first detection operation; a second detection submodule, configured to perform a second detection operation if the second code block does not cross pages and the direct jump instruction crosses pages, and determine whether the direct jump instruction meets an optimization condition based on a result of the second detection operation; The third detection submodule is configured to determine that the direct jump instruction meets an optimization condition if the second code block does not cross pages and the direct jump instruction does not cross pages.

11. The system-level binary translator according to claim 10, characterized in that: The first detection submodule includes: a first judging unit, configured to judge whether all pages covered by the second code block are the same as all pages covered by the first code block; a first determining unit, configured to determine that the direct jump instruction satisfies an optimization condition if all pages covered by the second code block are the same as all pages covered by the first code block; The first detection unit is used to perform dynamic detection on the different pages among all the pages covered by the second code block if there are different pages among all the pages covered by the second code block and all the pages covered by the first code block. If the different pages pass the dynamic detection, it is determined that the direct jump instruction meets the optimization condition; otherwise, it is determined that the direct jump instruction does not meet the optimization condition.

12. The system-level binary translator according to claim 10, wherein: The second detection submodule includes: a second determining unit, configured to determine whether a single page covered by the second code block is the same as all pages covered by the first code block; a second determining unit, configured to determine that the direct jump instruction satisfies an optimization condition if the single page covered by the second code block is the same as all the pages covered by the first code block; The second detection unit is used to perform dynamic detection on the single page covered by the second translation code block if the single page covered by the second code block does not exist in the same page among all the pages covered by the first code block. If the single page passes the dynamic detection, it is determined that the direct jump instruction meets the optimization condition; otherwise, it is determined that the direct jump instruction does not meet the optimization condition.

13. The system-level binary translator according to any one of claims 9 to 12, characterized in that: The system-level binary translator further includes: a length determination module for determining a maximum instruction length of a client architecture; a first information determining module, configured to determine that the second code block spans pages if the distance between the jump target address of the direct jump instruction and the current page boundary is less than the maximum instruction length; The first information recording module is configured to record the jump target cross-page information including: the second code block crosses pages.

14. The system-level binary translator according to any one of claims 9 to 12, characterized in that: The system-level binary translator further includes: An address acquisition module, configured to acquire the address of the direct jump instruction according to a current program counter value; a second information determining module, configured to determine that the direct jump instruction crosses pages if the address of the direct jump instruction and the client virtual address of the second code block are not in the same page; The second information recording module is configured to record the jump target cross-page information including: the direct jump instruction cross-page information.

15. The system-level binary translator according to any one of claims 9 to 12, characterized in that: The system-level binary translator further includes: An instruction insertion module is configured to insert a first instruction sequence and a second instruction sequence at the end of the first translation code block; the first instruction sequence is configured to execute the target linking strategy and, if it is determined that the direct jump instruction satisfies an optimization condition, jump to the second instruction sequence; and, if it is determined that the direct jump instruction does not satisfy the optimization condition, exit the execution state and search for a second translation code block to be executed; and the second instruction sequence is configured to establish a direct jump link between the first translation code block and the second translation code block.

16. The system-level binary translator according to any one of claims 9 to 12, characterized in that: The system-level binary translator further includes: The exit search module is configured to exit the execution state and search for a second translation code block to be executed if it is determined that the direct jump instruction does not meet the optimization condition.

17. An electronic device, characterized in that: include: A processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method according to any one of claims 1 to 8.

18. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the steps of the binary translation method according to any one of claims 1 to 8 are implemented.

19. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the binary translation method according to any one of claims 1 to 8 are implemented.

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