Upgrading method and device of complex programmable logic device, electronic equipment and medium

Abstract

The invention discloses an upgrading method and device of a complex programmable logic device (CPLD), electronic equipment and a medium, and the method comprises the steps: controlling a fifth input / output pin to send a starting signal to a first input / output pin based on a first code if the CPLD has an upgrading demand, sending a starting signal to a second input / output pin through a sixth input / output pin so as to load a second code; and under the condition that the second code is loaded, loading upgrading data of the CPLD based on a baseboard management controller (BMC), sending the upgrading data to a third input / output pin and a fourth input / output pin, and upgrading the CPLD through the upgrading data. Therefore, the problems that in the application scene of the current server, the power-on loading or upgrading process of the CPLD is interrupted by I2C communication of the BMC, loading or upgrading of the CPLD fails, and finally running of the whole server is abnormal are solved, and safe starting and successful upgrading of the CPLD and stable running of the server are guaranteed.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to an upgrade method, device, electronic device, and medium for a complex programmable logic device. Background Art

[0002] With the booming development of cutting-edge technologies such as the Internet of Things, big data, and artificial intelligence (AI), servers play an increasingly crucial role in supporting the digital wave. Especially at present when the demand for AI computing power is growing exponentially, not only higher standards are put forward for the performance of the graphics processing unit (GPU), but also almost stringent requirements are imposed on the stability of the servers that carry the GPU operation.

[0003] To meet the diverse requirements of different manufacturers' open accelerator modules (OAMs), the code iteration frequencies of the basic input / output system (BIOS), baseboard management controller (BMC), and complex programmable logic device (CPLD) are accelerating day by day. Among them, as the core component that determines the accuracy of the OAM power-on and power-off timing sequence, the stability of the CPLD is directly related to the normal operation of the OAM in the server.

[0004] The CPLD, as a hardware programmable logic device, its working principle is to compile and convert the hardware programming language (code) into a hardware circuit layout, and finally solidify it in the CPLD chip. Therefore, once the CPLD starts running, compared with the BMC and BIOS, its stability is significantly improved. Unless the chip itself is physically damaged, it rarely gets stuck. This characteristic is a key consideration in the server design for choosing the CPLD to undertake basic functions (such as timing control, fault monitoring, status indication, etc.).

[0005] However, as a programmable logic device, the CPLD needs to go through a firmware (FW) loading process every time it is powered on or the system is refreshed, that is, to transfer the code in the storage medium to the cache for execution. Although this process is extremely short, usually only about 5 milliseconds, with the continuous expansion of the number of CPLD applications and application scenarios in the server, there has currently been a situation where the CPLD fails to load after power-on or refresh, causing the entire server system to crash, bringing inconvenience and trouble to customers, and thus leading to customer complaints. Summary of the Invention

[0006] The present application provides an upgrading method, device, electronic device and medium for a complex programmable logic device, so as to at least solve the problem that in the application scenario of the current server for the complex programmable logic device (CPLD), the power-on loading or upgrading process of the CPLD is interrupted by the I2C communication of the BMC, resulting in the failure of CPLD loading or upgrading, and ultimately leading to the abnormal operation of the entire server.

[0007] The present application provides an upgrading method for a complex programmable logic device. The complex programmable logic device includes first to sixth input / output pins, the first input / output pin is connected to the fifth input / output pin, and the second input / output pin is connected to the sixth input / output pin. The method includes the following steps: determining whether there is an upgrading requirement for the complex programmable logic device; if there is an upgrading requirement for the complex programmable logic device, controlling the fifth input / output pin to send a start signal to the first input / output pin based on a preset first code, and sending the start signal to the second input / output pin through the sixth input / output pin to load a preset second code; in the case of loading the preset second code, loading the upgrading data of the complex programmable logic device based on the baseboard management controller, sending the upgrading data to the third input / output pin and the fourth input / output pin, and upgrading the complex programmable logic device through the upgrading data.

[0008] The present application further provides an upgrading device for a complex programmable logic device. The complex programmable logic device includes first to sixth input / output pins, the first input / output pin is connected to the fifth input / output pin, and the second input / output pin is connected to the sixth input / output pin. The device includes: a determination module, configured to determine whether there is an upgrading requirement for the complex programmable logic device; a start module, configured to, if there is an upgrading requirement for the complex programmable logic device, control the fifth input / output pin to send a start signal to the first input / output pin based on a preset first code, and send the start signal to the second input / output pin through the sixth input / output pin to load a preset second code; an upgrading module, configured to, in the case of loading the preset second code, load the upgrading data of the complex programmable logic device based on the baseboard management controller, send the upgrading data to the third input / output pin and the fourth input / output pin, and upgrade the complex programmable logic device through the upgrading data.

[0009] The present application further provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of the above-mentioned upgrading method for a complex programmable logic device when executing the computer program.

[0010] The present application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the above-mentioned method for upgrading a complex programmable logic device.

[0011] According to the present application, if there is a need to upgrade a complex programmable logic device (CPLD), a start signal is sent from a fifth input / output pin to a first input / output pin based on a first code, and a start signal is sent from a sixth input / output pin to a second input / output pin to load a second code. In the case of loading the second code, upgrade data of the CPLD is loaded based on a baseboard management controller (BMC), and the upgrade data is sent to a third input / output pin and a fourth input / output pin to upgrade the CPLD through the upgrade data. Thus, the problem that in the application scenario of the current server, the power-on loading or upgrade process of the CPLD is interrupted by the I2C communication of the BMC, resulting in the failure of CPLD loading or upgrade and ultimately the abnormal operation of the entire server is solved. It is possible to ensure the absolutely safe start and successful upgrade of the CPLD on the board card without changing the original board card function and without any increase in cost, ensure the stable operation of the server, and avoid customer complaint problems. Description of the Drawings

[0012] In order to more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0013] Figure 1 It is a schematic diagram of the connection topology of the CPLD peripheral circuit in the related art;

[0014] Figure 2 It is a schematic flowchart of a method for upgrading a complex programmable logic device according to an embodiment of the present application;

[0015] Figure 3 It is a schematic diagram of the connection topology of the CPLD peripheral circuit according to an embodiment of the present application;

[0016] Figure 4 It is a schematic diagram of the CPLD structure according to an embodiment of the present application;

[0017] Figure 5 It is a schematic diagram of the I2C frame format related to the upgrade according to an embodiment of the present application;

[0018] Figure 6 It is a schematic diagram of the device for upgrading a complex programmable logic device according to an embodiment of the present application;

[0019] Figure 7 It is a schematic diagram of the structure of an electronic device according to an embodiment of the present application. Specific implementation manners

[0020] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0021] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0022] Before specifically introducing the embodiments of the present application, a brief introduction to the commonly used CPLD peripheral circuit connection topology in current servers is as follows Figure 1 as shown.

[0023] A piece of non-volatile Flash is integrated inside the CPLD, which is defaultly divided into two areas, namely CFM and UFM. CFM is used to store the CPLD code, and UFM is used for users to solidify some important data. The BMC can use the dedicated I2C pins GPIO1 and GPIO2 on the CPLD to directly operate the Flash through the I2C hard core. It should be noted that CFM is the Flash area in the CPLD that provides code automatic loading configuration. The CPLD code can be automatically loaded from this area into the SRAM for operation. UFM is the Flash area in the CPLD provided for users to store some important information. After the CPLD is powered off, the data will not be lost. SRAM is the area where the CPLD code actually runs, and the power-off will cause data loss.

[0024] After the CPLD is powered on / reset, the CPLD chip bottom layer driver actively loads the code from the CFM into the SRAM. Relying on the SRAM, the CPLD runs the code normally, and the entire loading process takes about 5 ms.

[0025] For ease of use, the CPLD uses I2C as the remote upgrade interface. Compared with the JTAG upgrade which requires 4 hardware signals, the I2C upgrade only needs 2 hardware signals, which can save CPLD pins and is also beneficial to reducing the overall cables of the server. In addition, since the I2C upgrade uses the I2C hard core of the CPLD chip, even if there is no code in the CPLD chip, it will not affect the upgrade function.

[0026] However, through Figure 1 the shown hardware topology, it is found that the current BMC reads and writes the Flash area of the CPLD through the I2C link. On the same I2C, various I2C slave devices with other addresses are mounted, and the overall I2C topology is relatively complex; during the CPLD startup process or the CPLD refresh process, if there is data communication on this I2C of the BMC, it will cause the CPLD to fail to load or refresh. Consulting the CPLD manufacturer, the reply is that the communication of the I2C hard core of the CPLD has a higher priority than the behavior of SRAM loading the Flash, and the I2C hard core is sensitive to the signals of the I2C hardware link. Such as interference signals on the I2C link during the CPLD power-on process or non-upgrade communication data during the refresh process may cause abnormalities in the Flash area of the CPLD, ultimately resulting in abnormal loading of the CPLD chip, thus causing abnormal operation of the server and bringing extremely bad experience to customers.

[0027] In addition, due to cost considerations, dual-mirror CPLD chips with higher costs are not selected on the server, resulting in the inability to use the backup and recovery functions of the CPLD chip itself to avoid this problem.

[0028] To solve the above problems, an embodiment of the present application provides a method for upgrading a complex programmable logic device.

[0029] As Figure 2 shown, the method for upgrading the complex programmable logic device includes the following steps:

[0030] Among them, the complex programmable logic device includes first to sixth input / output pins, the first input / output pin is connected to the fifth input / output pin, and the second input / output pin is connected to the sixth input / output pin.

[0031] As Figure 3 shown, the first input / output pin is GPIO1 (General-purpose input / output), the second input / output pin is GPIO2, the third input / output pin is GPIO3, the fourth input / output pin is GPIO4, the fifth input / output pin is GPIO5, and the sixth input / output pin is GPIO6.

[0032] Since most of the main reasons for the failure of CPLD startup and upgrade in the CPLD peripheral circuit lie in the excessive complexity of the I2C upgrade link of the CPLD, there are too many unstable factors. Therefore, this application optimizes the link.

[0033] Specifically, only the hardware lines for data communication, namely GPIO3 and GPIO4, are retained between the Baseboard Management Controller (BMC) and the Complex Programmable Logic Device (CPLD), and the first input / output pin GPIO1 and the second input / output pin GPIO2 are disconnected. The fifth input / output pin GPIO5 and the sixth input / output pin GPIO6 of the CPLD are used as I2C pins and are respectively connected to the pins GPIO1 and GPIO2 dedicated to the I2C upgrade core of the CPLD.

[0034] Step S201: Determine whether there is an upgrade requirement for the Complex Programmable Logic Device.

[0035] In the embodiment of this application, to determine whether there is an upgrade requirement for the CPLD, the upgrade requirement can be:

[0036] (1) Functional requirement changes

[0037] For example: new function addition, interface protocol upgrade, hardware compatibility adjustment.

[0038] (2) Error repair

[0039] For example: fixing hardware design defects, logic errors (such as timing issues), compatibility vulnerabilities.

[0040] (3) Performance optimization

[0041] For example: improving system response speed, reducing power consumption, optimizing resource utilization.

[0042] Step S202: If there is an upgrade requirement for the Complex Programmable Logic Device, based on a preset first code, control the fifth input / output pin to send a start signal to the first input / output pin, and send a start signal to the second input / output pin through the sixth input / output pin to load a preset second code.

[0043] Specifically, as Figure 3 shown, Figure 3 is the schematic diagram of the CPLD peripheral circuit connection topology of this application. The block diagram of the CPLD is as Figure 4 shown. After the preset first code starts normally, the preset first code sends start signals by operating the fifth input / output pin GPIO5 and the sixth input / output pin GPIO6 through I2C Master, and sends them to the first input / output pin GPIO1 and the second input / output pin GPIO2 through the hardware link, and then operates the I2C upgrade core of the CPLD to trigger the normal loading of the preset second code.

[0044] Since the I2C upgrade core of the preset second code communicates only with the preset first code through the I2C link and there are no more I2C devices, there will be no other communication data on the I2C link. Therefore, there is no problem that the preset second code fails to load due to interference on the I2C link.

[0045] Optionally, in some embodiments, before controlling the fifth input / output pin to send a start signal to the first input / output pin based on the preset first code, it further includes: dividing the current code of the complex programmable logic device into the preset first code and the preset second code based on the preset division strategy; determining a first storage area and a second storage area in the CFM area of the complex programmable logic device; storing the preset first code in the first storage area, and storing the preset second code in the second storage area and / or the UFM area in the complex programmable logic device.

[0046] Specifically, as Figure 3 and 4 shown, the CPLD code is divided into the preset first code and the preset second code, and the preset division strategy is:

[0047] Storing the preset first code in the first storage area in the CFM area, and storing the preset second code in the second storage area in the CFM area and the UFM area in the complex programmable logic device.

[0048] Among them, the preset first code only includes three functions: I2C parsing, I2C filtering, and I2C sending, occupying a relatively small space in the CFM; the preset first code does not include the I2C upgrade core and cannot be upgraded through I2C, so there will be no problem that the I2C signal interference causes failure to start; the preset second code includes all the functions that the CPLD should originally complete, including the I2C upgrade core (such as Figure 4 the Hardened IP in it, whose address is 0x40), thus ensuring the normal function of the board.

[0049] It should be noted that in the embodiments of the present application, the BMC does not need to distinguish between the first code and the second code.

[0050] Through the above technical solution, the preset first code runs independently in the CFM area, avoiding signal interference caused by the I2C upgrade hard core, ensuring reliable system startup. The preset second code is loaded through the hardware link after normal startup, eliminating the risk of I2C link interference. The lightweight design of the preset first code occupies less CFM space. The preset second code is stored in some areas of the CFM and the UFM area, realizing efficient allocation of storage resources. After the hardware link is simplified, only necessary data channels are retained, reducing the complexity of the I2C link. The BMC does not need to distinguish between the first code and the second code, simplifying the upgrade process.

[0051] Step S203, when the preset second code is loaded, based on the baseboard management controller, load the upgrade data of the complex programmable logic device, and send the upgrade data to the third input / output pin and the fourth input / output pin, and upgrade the complex programmable logic device through the upgrade data.

[0052] Optionally, in some embodiments, sending the upgrade data to the third input / output pin and the fourth input / output pin, and upgrading the complex programmable logic device through the upgrade data includes: based on the baseboard management controller, packing the upgrade data according to a preset I2C frame format to obtain a data packet, where the data packet includes an upgrade start frame format and an upgrade data frame format; sequentially sending the upgrade start frame format and the upgrade data frame format to the third input / output pin and the fourth input / output pin, and when the third input / output pin and the fourth input / output pin receive the upgrade start frame format, filter the upgrade data frame format through the preset first code, and transparently transmit the filtered upgrade data frame format to the I2C upgrade hard core of the complex programmable logic device to upgrade the complex programmable logic device.

[0053] It can be understood that during the normal operation of the preset second code, when the BMC upgrades the CPLD, pack the upgrade data according to the preset I2C frame format (the preset I2C frame format is as Figure 5 shown), to obtain a data packet, and sequentially send the "upgrade start frame format" and the "upgrade data frame format" through the I2C device (whose address is 0x10). After the preset second code receives the I2C upgrade start command through the pins GPIO3 and GPIO4, it will immediately perform reloading. At this time, due to the chip characteristics, the CPLD will automatically jump to the preset first code for startup.

[0054] Furthermore, perform I2C Filter operation through the preset first code to filter the upgrade data frame format, and transparently transmit the filtered upgrade data frame format to the I2C upgrade hard core of the complex programmable logic device to upgrade the complex programmable logic device.

[0055] At any time, the BMC can interact with other I2C devices on the I2C bus without worrying about causing the upgrade to fail due to this.

[0056] Through the above technical solution, the baseboard management controller BMC packages the upgrade data according to a preset I2C frame format to ensure the unity of the data format and reduce transmission errors caused by format differences. When the upgrade start frame is received on GPIO3 and GPIO4, the preset first code is automatically activated to ensure that the upgrade process is executed in the established order and avoid misoperations or illegal upgrades.

[0057] Optionally, in some embodiments, the upgrade data frame format includes an upgrade data frame header and an upgrade data frame. The upgrade data frame format is filtered by a preset first code, and the filtered upgrade data frame format is transparently transmitted to the I2C upgrade hard core of the complex programmable logic device to upgrade the complex programmable logic device, including: identifying the upgrade data frame header in the upgrade data frame format; based on the preset first code, using a preset I2C filter to filter the upgrade data frame header, and transparently transmitting the upgrade data frame to the I2C upgrade hard core of the complex programmable logic device to upgrade the complex programmable logic device.

[0058] Specifically, the BMC continues to upgrade the CPLD according to the Figure 5 frame format shown, through the I2C device (0x10). At this time, the preset first code filters the upgrade data frame header in the upgrade data frame format through a preset I2C filter, and transparently transmits the upgrade data frame to the I2C upgrade hard core (0x40) of the complex programmable logic device to upgrade the complex programmable logic device.

[0059] Among them, the step of filtering the upgrade data frame header in the upgrade data frame format through a preset I2C filter (i.e., the I2C Filter in Figure 4 ) is: the preset first code filters out I2C instructions other than the upgrade data according to the upgrade data flag bit in the upgrade data frame format, so as to avoid the problem of CPLD upgrade failure caused by data communication on the I2C link in the original design.

[0060] Through the above technical solution, by parsing the header field in the upgrade data frame format, accurate identification of the data frame is achieved, interference from invalid data is avoided, and the upgrade reliability is improved. Based on the preset first code, a filter is used to filter the frame header, and only data frames that conform to the protocol specification are allowed to pass, effectively shielding noise and abnormal data, and reducing the risk of mis-upgrade.

[0061] Optionally, in some embodiments, when filtering the upgrade data frame header using a preset I2C filter based on a preset first code, it further includes: obtaining the continuity of the upgrade frame sequence in the upgrade data frame header; determining whether the continuity of the upgrade frame sequence meets a preset continuous condition; if the continuity of the upgrade frame sequence does not meet the preset continuous condition, sending an alarm message to the baseboard management controller.

[0062] It can be understood that the serial number of the upgrade frame sequence in the upgrade data frame header is parsed to further determine the continuity of the frame sequence.

[0063] For example, the serial numbers of the upgrade frame sequence should increase strictly (such as 1, 2, 3...). If there are missing frames, duplicate frames, or out-of-order frames in the serial numbers of the upgrade frame sequence, it means that the continuity of the upgrade frame sequence does not meet the preset continuous condition, and an alarm message is sent to the baseboard management controller to avoid the problem of CPLD upgrade failure caused by the BMC retransmitting or missing I2C upgrade data frames.

[0064] Among them, the alarm message may include "serial number of abnormal frame", "range of missing frame numbers", "alarm timestamp", etc.

[0065] Through the above technical solution, the continuity of the frame sequence is monitored, data transmission anomalies are detected and alarmed in a timely manner, which is convenient for maintenance personnel to quickly analyze the root cause of the problem, realizing the automation, intelligence and security of the CPLD upgrade process, and significantly improving the reliability, security and maintainability of the system.

[0066] Optionally, in some embodiments, after upgrading the complex programmable logic device with the upgrade data, it further includes: determining whether the baseboard management controller has received a duplicate frame alarm and / or a missing frame alarm; if the baseboard management controller has received a duplicate frame alarm and / or a missing frame alarm, re-executing the step of sending the upgrade data to the third input / output pin and the fourth input / output pin.

[0067] It can be understood that when the baseboard management controller (BMC) receives a duplicate frame alarm and / or a missing frame alarm fed back by the preset first code, corresponding upgrade data retransmission actions will be performed to ensure the integrity of the upgrade data.

[0068] Specifically, if the baseboard management controller receives a duplicate frame or missing frame alarm sent by the preset first code, the current upgrade is stopped, the subsequent frames are paused from being sent, and according to the alarm message, the range of frames to be retransmitted is determined. Starting from the abnormal frame, after retransmitting through the third input / output pin (GPIO3) and the fourth input / output pin (GPIO4), the upgrade process continues.

[0069] Among them, in some embodiments, the duplicate frame alarm and the missing frame alarm are sent from the complex programmable logic device to the baseboard management controller through the third input / output pin and the fourth input / output pin.

[0070] It can be understood that the duplicate frame alarm and the lost frame alarm are sent by the complex programmable logic device (CPLD) to the baseboard management controller (BMC) through the third input / output pin GPIO3 and the fourth input / output pin GPIO4.

[0071] Through the above technical solution, if a duplicate frame alarm or a lost frame alarm is detected, the system automatically triggers the upgrade data retransmission process without manual intervention, reducing the operation and maintenance costs.

[0072] In summary, the technical effects brought by the embodiments of the present application are as follows.

[0073] (1) Using the form of code layering: The CPLD code is divided into the first code and the second code. The first code is responsible for I2C parsing, filtering, and sending, and there is no upgrade core to avoid startup interference. The second code contains the complete function and the upgrade core. After the first code is started, it triggers the loading of the second code through the I2C core to ensure that its I2C link is independent and interference-free.

[0074] (2) When the BMC upgrades the CPLD, after the second code receives the upgrade start frame, it jumps to the first code. The first code filters the upgrade data frame format and transparently transmits it to the I2C upgrade core, and at the same time monitors the sequence continuity to prevent data loss, effectively preventing data loss or upgrade failure caused by I2C interference. Through the hardware isolation and filtering mechanism, the problem of upgrade failure caused by I2C interference is solved.

[0075] (3) When upgrading the CPLD, the BMC does not need to distinguish between the first code and the second code. It issues the "upgrade start frame format" according to the preset I2C frame format through the I2C address 0x10, and then loads the upgrade file, and sequentially packages and issues the "upgrade data frame format", supporting the BMC to interact concurrently with other I2C devices during the upgrade to ensure that the upgrade operation has no impact on the overall function of the system.

[0076] (4) Without adding any additional devices and costs, only two additional idle pins of the CPLD are required. The BMC and the CPLD only retain the GPIO3 / 4 communication, disconnect the GPIO1 / 2, and the CPLD uses the GPIO5 / 6 as the I2C pins to connect to the GPIO1 / 2 of the I2C core, realizing the flexible reuse of hardware resources.

[0077] (5) Compared with the dual-mirroring function that can only be completed by more advanced chips, the present application significantly reduces the cost and broadens the adaptation range, and can provide reference value for MCUs, BMCs, and all other programmable devices that can run code.

[0078] According to the upgrade method of a complex programmable logic device provided by an embodiment of the present application, if there is an upgrade requirement for the complex programmable logic device CPLD, a start signal is sent from the fifth input / output pin to the first input / output pin based on the first code, and a start signal is sent from the sixth input / output pin to the second input / output pin to load the second code; in the case of loading the second code, the upgrade data of the CPLD is loaded based on the baseboard management controller BMC, and the upgrade data is sent to the third input / output pin and the fourth input / output pin, and the CPLD is upgraded through the upgrade data. Thus, in the application scenario of the complex programmable logic device CPLD in the current server, the problem that the power-on loading or upgrade process of the CPLD is interrupted by the I2C communication of the BMC, resulting in the failure of the CPLD to be loaded or upgraded, and ultimately causing the abnormal operation of the entire server is solved. Through the modification of the CPLD, BMC code, and hardware topology, it is possible to ensure the absolutely safe startup and successful upgrade of the board CPLD without changing the original board function and without any increase in cost, and avoid the problem that the power-on loading or upgrade process of the CPLD is interrupted by the I2C communication of the BMC, resulting in the failure of the CPLD to be loaded or upgraded.

[0079] Next, the upgrade method of the complex programmable logic device according to the embodiment of the present application will be described with reference to the accompanying drawings.

[0080] Figure 6 It is a schematic diagram of the upgrade device of the complex programmable logic device according to the embodiment of the present application.

[0081] As Figure 6 shown, the upgrade device 10 of the complex programmable logic device includes: a judgment module 100, a start module 200, and an upgrade module 300.

[0082] Among them, the complex programmable logic device includes first to sixth input / output pins, the first input / output pin is connected to the fifth input / output pin, and the second input / output pin is connected to the sixth input / output pin.

[0083] Among them, the judgment module 100 is used to judge whether there is an upgrade requirement for the complex programmable logic device;

[0084] The start module 200 is used to, if there is an upgrade requirement for the complex programmable logic device, control the fifth input / output pin to send a start signal to the first input / output pin based on a preset first code, and send a start signal to the second input / output pin through the sixth input / output pin to load a preset second code; the upgrade module 300 is used to, in the case of loading the preset second code, load the upgrade data of the complex programmable logic device based on the baseboard management controller, and send the upgrade data to the third input / output pin and the fourth input / output pin, and upgrade the complex programmable logic device through the upgrade data.

[0085] Optionally, in some embodiments, the upgrade module 300 is further configured to: pack the upgrade data based on the baseboard management controller according to a preset I2C frame format to obtain a data packet, where the data packet includes an upgrade start frame format and an upgrade data frame format; sequentially send the upgrade start frame format and the upgrade data frame format to the third input / output pin and the fourth input / output pin, and when the third input / output pin and the fourth input / output pin receive the upgrade start frame format, filter the upgrade data frame format through a preset first code and transparently transmit the filtered upgrade data frame format to the I2C upgrade core of the complex programmable logic device to upgrade the complex programmable logic device.

[0086] Optionally, in some embodiments, before controlling the fifth input / output pin to send a start signal to the first input / output pin based on a preset first code, the start module 200 is further configured to: divide the current code of the complex programmable logic device into a preset first code and a preset second code based on a preset partitioning strategy; determine a first storage area and a second storage area in the CFM area of the complex programmable logic device; store the preset first code in the first storage area, and store the preset second code in the second storage area and / or the UFM area in the complex programmable logic device.

[0087] Optionally, in some embodiments, the upgrade data frame format includes an upgrade data frame header and an upgrade data frame. The upgrade module 300 is further configured to: identify the upgrade data frame header in the upgrade data frame format; filter the upgrade data frame header through a preset I2C filter based on a preset first code, and transparently transmit the upgrade data frame to the I2C upgrade core of the complex programmable logic device to upgrade the complex programmable logic device.

[0088] Optionally, in some embodiments, when filtering the upgrade data frame header through a preset I2C filter based on a preset first code, the upgrade module 300 is further configured to: obtain the continuity of the upgrade frame sequence in the upgrade data frame header; determine whether the continuity of the upgrade frame sequence meets a preset continuous condition; if the continuity of the upgrade frame sequence does not meet the preset continuous condition, send an alarm message to the baseboard management controller.

[0089] Optionally, in some embodiments, after upgrading the complex programmable logic device with the upgrade data, the upgrade module 300 is further configured to: determine whether the baseboard management controller has received a duplicate frame alarm and / or a missing frame alarm; if the baseboard management controller has received a duplicate frame alarm and / or a missing frame alarm, re-execute the step of sending the upgrade data to the third input / output pin and the fourth input / output pin.

[0090] Optionally, in some embodiments, the re-frame alarm and the dropped-frame alarm are sent by the complex programmable logic device to the baseboard management controller through the third input / output pin and the fourth input / output pin.

[0091] It should be noted that the descriptions of the features in the corresponding embodiments of the upgrade device of the complex programmable logic device can refer to the relevant descriptions of the corresponding embodiments of the above-mentioned upgrade method of the complex programmable logic device, and will not be elaborated here one by one.

[0092] Figure 7 The following is a schematic structural diagram of the electronic device provided by the embodiments of the present application. The electronic device may include:

[0093] A memory 701, a processor 702, and a computer program stored on the memory 701 and executable on the processor 702.

[0094] When the processor 702 executes the program, it implements the upgrade method of the complex programmable logic device provided in the above embodiments.

[0095] Furthermore, the electronic device further includes:

[0096] A communication interface 703 for communication between the memory 701 and the processor 702.

[0097] The memory 701 is used to store a computer program executable on the processor 702.

[0098] The memory 701 may include a high-speed RAM memory, and may also include a non-volatile memory, such as at least one disk memory.

[0099] If the memory 701, the processor 702, and the communication interface 703 are implemented independently, the communication interface 703, the memory 701, and the processor 702 can be interconnected through a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of representation, Figure 7 only a thick line is used to represent it in the figure, but it does not mean that there is only one bus or one type of bus.

[0100] Optionally, in a specific implementation, if the memory 701, the processor 702, and the communication interface 703 are integrated on a single chip, the memory 701, the processor 702, and the communication interface 703 can communicate with each other through an internal interface.

[0101] The processor 702 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0102] Embodiments of the present application further provide a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above-described embodiments of the method for upgrading a complex programmable logic device when running.

[0103] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: various media such as USB flash drives, read-only memories (ROMs), random access memories (RAMs), mobile hard disks, magnetic disks, or optical discs that can store computer programs.

[0104] Those skilled in the art can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0105] The above has introduced in detail a method, device, electronic device, and medium for upgrading a complex programmable logic device provided by the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. An upgrading method for a complex programmable logic device, characterized in that The complex programmable logic device includes first to sixth input / output pins. The first input / output pin is connected to the fifth input / output pin, and the second input / output pin is connected to the sixth input / output pin. The method includes the following steps: Determine whether there is an upgrade requirement for the complex programmable logic device; If there is an upgrade requirement for the complex programmable logic device, based on a preset first code, control the fifth input / output pin to send a start signal to the first input / output pin, and send the start signal to the second input / output pin through the sixth input / output pin to load a preset second code; When the preset second code is loaded, based on the baseboard management controller, load the upgrade data of the complex programmable logic device, send the upgrade data to the third input / output pin and the fourth input / output pin, and upgrade the complex programmable logic device through the upgrade data.

2. The method according to claim 1, characterized in that The step of sending the upgrade data to the third input / output pin and the fourth input / output pin and upgrading the complex programmable logic device through the upgrade data includes: Based on the baseboard management controller, pack the upgrade data according to a preset I2C frame format to obtain a data packet, where the data packet includes an upgrade start frame format and an upgrade data frame format; Send the upgrade start frame format and the upgrade data frame format to the third input / output pin and the fourth input / output pin in sequence. When the third input / output pin and the fourth input / output pin receive the upgrade start frame format, filter the upgrade data frame format through the preset first code, and transparently transmit the filtered upgrade data frame format to the I2C upgrade hard core of the complex programmable logic device to upgrade the complex programmable logic device.

3. The method according to claim 1, characterized in that Before controlling the fifth input / output pin to send a start signal to the first input / output pin based on the preset first code, it further includes: Based on a preset partitioning strategy, divide the current code of the complex programmable logic device into the preset first code and the preset second code; Determine a first storage area and a second storage area in the CFM area of the complex programmable logic device; Store the preset first code in the first storage area, and store the preset second code in the second storage area and / or the UFM area in the complex programmable logic device.

4. The method according to claim 1, wherein The upgrade data frame format includes an upgrade data frame header and an upgrade data frame. The step of filtering the upgrade data frame format through the preset first code and transparently transmitting the filtered upgrade data frame format to the I2C upgrade hard core of the complex programmable logic device to upgrade the complex programmable logic device includes: Identify the upgrade data frame header in the upgrade data frame format; Based on the preset first code, use a preset I2C filter to filter the upgrade data frame header, and transparently transmit the upgrade data frame to the I2C upgrade hard core of the complex programmable logic device to upgrade the complex programmable logic device.

5. The method according to claim 4, characterized in that, When filtering the upgrade data frame header by using the preset first code based on the preset I2C filter, it further includes: Obtaining the continuity of the upgrade frame sequence in the upgrade data frame header; Judging whether the continuity of the upgrade frame sequence meets a preset continuous condition; If the continuity of the upgrade frame sequence does not meet the preset continuous condition, sending an alarm message to the baseboard management controller.

6. The method according to claim 1, wherein After upgrading the complex programmable logic device by using the upgrade data, it further includes: Judging whether the baseboard management controller receives a duplicate frame alarm and / or a lost frame alarm; If the baseboard management controller receives the duplicate frame alarm and / or the lost frame alarm, re-executing the step of sending the upgrade data to the third input / output pin and the fourth input / output pin.

7. The method according to claim 6, characterized in that, The duplicate frame alarm and the lost frame alarm are sent from the complex programmable logic device to the baseboard management controller through the third input / output pin and the fourth input / output pin.

8. An upgrading device for a complex programmable logic device, characterized in that The complex programmable logic device includes first to sixth input / output pins, the first input / output pin is connected to the fifth input / output pin, and the second input / output pin is connected to the sixth input / output pin, and includes: A judging module, configured to judge whether there is an upgrade requirement for the complex programmable logic device; A starting module, configured to, if there is an upgrade requirement for the complex programmable logic device, control the fifth input / output pin to send a start signal to the first input / output pin based on a preset first code, and send the start signal to the second input / output pin through the sixth input / output pin to load a preset second code; An upgrading module, configured to, when the preset second code is loaded, load the upgrade data of the complex programmable logic device based on the baseboard management controller, send the upgrade data to the third input / output pin and the fourth input / output pin, and upgrade the complex programmable logic device by using the upgrade data.

9. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored on the memory and executable on the processor, and the processor executes the program to implement the upgrading method of the complex programmable logic device as described in any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, The program is executed by the processor to be used for implementing the upgrading method of the complex programmable logic device as described in any one of claims 1-7.

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