Data transmission method and device, electronic equipment, chip and medium

Abstract

The invention provides a data transmission method and device, electronic equipment, a chip and a medium. The method relates to the field of electronic communication. The method comprises the following steps: receiving a plurality of transmission requests from an AXI interface, wherein each transmission request has an operation address and an operation type; the transmission requests with the same operation type and continuous operation addresses are combined to obtain target transmission requests, and the target transmission requests comprise the combined transmission requests and single transmission requests which are not combined; and issuing the target transmission request to an RAM interface based on a preset arbitration mechanism. According to the method provided by the invention, the transmission requests with continuous operation addresses in the read operation and the write operation are combined, and the combined transmission requests and the uncombined transmission requests are arbitrated according to the preset arbitration mechanism and then are issued, so that the bandwidth utilization rate of data transmission after the AXI interface is converted into the RAM interface is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic communications, and particularly to a data transmission method, apparatus, electronic device, chip and medium. Background Art

[0002] When processing bus signals in a processing system, a solution can be provided to address the issue that when converting from an Advanced eXtensible Interface (AXI) to a Random Access Memory (RAM) interface, the conversion of parallel data streams to serial data streams can lead to a decrease in transmission bandwidth. Summary of the Invention

[0003] The present disclosure provides a data transmission method, apparatus, electronic device, chip and medium. By merging transmission requests with the same operation type and consecutive addresses, and arbitrating the merged and unmerged transmission requests according to a preset arbitration mechanism, and sending the transmission requests to the RAM interface to access the memory. It can solve the problem of the decrease in transmission bandwidth caused by the conversion of parallel data to serial data, and can better meet the bus performance requirements by adjusting the arbitration mechanism.

[0004] The first aspect embodiment of the present disclosure proposes a data transmission method, the method includes: receiving a plurality of transmission requests from an AXI interface, each transmission request having an operation address and an operation type; merging the transmission requests with the same operation type and consecutive operation addresses to obtain a target transmission request, the target transmission request including the merged transmission requests and unmerged individual transmission requests; based on a preset arbitration mechanism, sending the target transmission request to the RAM interface.

[0005] In some embodiments of the present disclosure, merging the transmission requests with the same operation type and consecutive operation addresses includes: merging the transmission requests with a read operation type and consecutive operation addresses to obtain a merged read request; merging the transmission requests with a write operation type and consecutive operation addresses to obtain a merged write request, the target transmission request including the merged read request and the merged write request.

[0006] In some embodiments of the present disclosure, merging the transmission requests with a read operation type and consecutive operation addresses includes: merging a first read request and a second read request with consecutive operation addresses to obtain a merged read request, the operation address of the merged read request being the operation address of the first read request; adding a first flag to the merged read request and a second flag to the unmerged third read request, the first flag being used to identify the merged read request as a merged read request, and the second flag being used to identify the third read request as an unmerged individual read request.

[0007] In some embodiments of the present disclosure, the method further includes: receiving data returned by the RAM interface, where the data is obtained by reading the memory according to the operation address of the target transmission request; splitting or intercepting valid bits of the data according to the first tag and / or the second tag to obtain target data.

[0008] In some embodiments of the present disclosure, merging transmission requests with a write operation type and consecutive operation addresses includes: merging a first write request and a second write request with consecutive operation addresses to obtain a merged write request, where the operation address of the merged write request is the operation address of the first write request; merging the data to be written in the first write request and the data to be written in the second write request to obtain merged data.

[0009] In some embodiments of the present disclosure, sending the target transmission request to the RAM interface based on a preset arbitration mechanism includes: determining the sending order of the read request and the write request in the target transmission request according to the read-write allocation ratio in the preset arbitration mechanism; sending the read request and the write request to the RAM interface according to the sending order.

[0010] A second aspect embodiment of the present disclosure provides a data transmission device, including: a receiving module, configured to receive multiple transmission requests from an AXI interface, each transmission request having an operation address and an operation type; a merging module, configured to merge transmission requests with the same operation type and consecutive operation addresses to obtain a target transmission request, where the target transmission request includes the merged transmission requests and unmerged individual transmission requests; an arbitration module, configured to send the target transmission request to the RAM interface based on a preset arbitration mechanism.

[0011] A third aspect embodiment of the present disclosure provides an electronic device, including: a processor and a memory for storing a computer program that can run on the processor, where, when the processor is used to run the computer program, it executes the method described in any one of the first aspect embodiments of the present disclosure.

[0012] A fourth aspect embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions, where the computer instructions are used to cause a computer to execute the method described in any one of the first aspect embodiments of the present disclosure.

[0013] A fifth aspect embodiment of the present disclosure provides a chip, including at least one processor and a communication interface, where the communication interface is configured to receive a signal input to the chip or output a signal from the chip, and the processor communicates with the communication interface and implements the method described in any one of the first aspect through a logic circuit or by executing code instructions.

[0014] In summary, the data transmission method, apparatus, electronic device, chip, and medium proposed by the present disclosure include: receiving multiple transmission requests from an AXI interface, each transmission request having an operation address and an operation type; merging transmission requests with the same operation type and continuous operation addresses to obtain a target transmission request, where the target transmission request includes the merged transmission requests and unmerged individual transmission requests; and based on a preset arbitration mechanism, sending the target transmission request to a RAM interface. The method proposed by the present disclosure merges two consecutive transmission requests in read requests and write requests into one transmission request respectively. For the merged and unmerged transmission requests, the ratio of the read requests and write requests to be sent is determined according to the preset arbitration mechanism, and the transmission requests are sent to the RAM interface to access the memory. It can solve the problem of the decrease in transmission bandwidth caused by parallel data converted to serial data, and can better meet the bus performance requirements by adjusting the arbitration mechanism.

[0015] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and do not limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure and do not constitute an improper limitation of the present disclosure.

[0017] Figure 1 It is a flowchart of a data transmission method proposed by an embodiment of the present disclosure;

[0018] Figure 2 It is a flowchart of a method for merging transmission requests proposed by an embodiment of the present disclosure;

[0019] Figure 3 It is a flowchart of a method for merging read operations proposed by an embodiment of the present disclosure;

[0020] Figure 4 It is a flowchart of a data transmission method proposed by an embodiment of the present disclosure;

[0021] Figure 5 It is a flowchart of a method for merging write operations proposed by an embodiment of the present disclosure;

[0022] Figure 6 It is a flowchart of a method for sending a target transmission request proposed by an embodiment of the present disclosure;

[0023] Figure 7A It is an overall framework diagram of a data transmission structure proposed by the present disclosure;

[0024] Figure 7B It is a timing diagram for read operation merging;

[0025] Figure 7C Timing diagram merged for write operation;

[0026] Figure 7D Timing diagram for arbitration module;

[0027] Figure 8 Structural schematic diagram of a data transmission device proposed by an embodiment of the present disclosure;

[0028] Figure 9 Structural schematic diagram of an electronic device proposed by an embodiment of the present disclosure;

[0029] Figure 10 Structural schematic diagram of a chip proposed by an embodiment of the present disclosure. Detailed implementation manners

[0030] The embodiments of the present disclosure will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present disclosure and should not be construed as a limitation to the present disclosure.

[0031] When data is transmitted in the system, the instructions sent from the CPU are first transmitted to the NOC bridge through the bus. After the NOC bus bridge distributes the data stream according to the ID, the read and write instructions will be further sent to the specified BLOCK block. By converting the data stream of the AXI interface into a data stream related to the RAM interface and sending it to the RAM, the read and write operations on the RAM are completed. Currently, by arbitrating the issued operations, the read and write operations can be issued alternately. The unselected operations will pull down the handshake signal to keep the upstream operation. However, during intensive reading and writing, the read and write operations will be blocked.

[0032] In summary, to solve the technical problems in the related art, an embodiment of the present disclosure provides a data transmission method. The method includes receiving a plurality of transmission requests from the AXI interface, each transmission request having an operation address and an operation type; merging the transmission requests with the same operation type and continuous operation addresses to obtain a target transmission request, where the target transmission request includes the merged transmission requests and the unmerged single transmission requests; and based on a preset arbitration mechanism, sending the target transmission request to the RAM interface. The data transmission method proposed by the present disclosure can solve the problem of the decrease in transmission bandwidth caused by the conversion of parallel data streams into serial data streams when the AXI interface is converted to the RAM interface. Specifically, in the conversion module for converting the AXI interface to the RAM interface, the bus channels are divided into two groups of channels for read operations and write operations, and the operations within each group of channels are merged separately according to whether the addresses are continuous. Then, in the arbitration module, the read and write operations are arbitrated according to the configured allocation ratio of the read and write operations, and then the operations are sent down.

[0033] The data transmission method provided by the present application will be described in detail below with reference to the accompanying drawings.

[0034] Figure 1 It is a schematic flowchart of a data transmission method proposed in an embodiment of the present disclosure. As Figure 1 shown, the method includes the following steps.

[0035] Step 101, receive multiple transmission requests from the AXI interface.

[0036] In some embodiments, each transmission request has an operation address and an operation type, where the operation type includes a read operation and a write operation.

[0037] In some embodiments, the multiple transmission requests can be read requests or write requests. Each read request has a read operation address, and each write request has a write operation address and data to be written.

[0038] In some embodiments, receiving multiple transmission requests from the AXI interface can be to receive the transmission requests of multiple read operations and the transmission requests of multiple write operations from the AXI interface through two channels respectively.

[0039] In some embodiments, receiving multiple transmission requests from the AXI interface can include receiving multiple transmission requests after the AXI interface is converted to the RAM interface, that is, the multiple transmission requests are the transmission requests in the data stream after the parallel data stream of the AXI interface is converted into the serial data stream of the RAM interface.

[0040] In an embodiment of the present disclosure, receiving multiple transmission requests from the AXI interface includes performing a timing conversion on the multiple transmission requests in the parallel data stream of the AXI interface. In other words, the parallel data stream of the AXI interface is converted into the serial data stream of the RAM interface.

[0041] Exemplarily, upstream of the AXI data path, the bus path is divided into two groups of channels. One group is the channels for write operations, including the write address channel, write data channel, and write response channel of the bus; the other group is the channels for read operations, including the read address channel and read response channel of the bus. The conversion module from the AXI interface to the RAM interface includes: Module 1, which is used to convert the data flow of the interface timing of the input AXI read operation channel into the data flow of the RAM interface timing; Module 2, which is used to convert the data flow of the interface timing of the input AXI write operation channel into the data flow of the RAM interface timing.

[0042] Step 102, merge the transmission requests with the same operation type and continuous operation addresses to obtain a target transmission request.

[0043] In an embodiment of the present disclosure, the target transfer request includes a merged transfer request and an unmerged individual transfer request.

[0044] In an embodiment of the present disclosure, merging transfer requests with the same operation type and consecutive operation addresses may be to merge the transfer requests for read operations and the transfer requests for write operations respectively.

[0045] In an embodiment of the present disclosure, merging transfer requests with the same operation type and consecutive operation addresses may be to determine the operation types of a series of consecutive transfer requests received. When the received transfer requests have consecutive addresses and the same type, they are merged.

[0046] In an embodiment of the present disclosure, merging transfer requests with the same operation type and consecutive operation addresses may be to merge the transfer requests with consecutive operation addresses for the received read operations.

[0047] In an embodiment of the present disclosure, merging transfer requests with the same operation type and consecutive operation addresses may be to merge the transfer requests with consecutive operation addresses for the received write operations.

[0048] In an embodiment of the present disclosure, merging transfer requests with the same operation type and consecutive operation addresses may be to separately receive the transfer requests for write operations and the transfer requests for read operations after the timing conversion from the AXI interface to the RAM interface, and separately merge the transfer requests with consecutive operation addresses in the transfer requests for write operations and the transfer requests for read operations. The target transfer request includes the merged transfer requests for read operations and the unmerged transfer requests for read operations, as well as the merged transfer requests for write operations and the unmerged transfer requests for write operations.

[0049] Exemplarily, Module 1 sends the data stream after timing conversion to Module 3, and Module 3 merges the operations with consecutive addresses in the sent data stream. Module 2 sends the data stream after timing conversion to Module 4, and Module 4 merges the operations with consecutive addresses in the sent data stream.

[0050] Step 103: Based on a preset arbitration mechanism, send the target transfer request to the RAM interface.

[0051] In an embodiment of the present disclosure, the preset arbitration mechanism may be a pre-configured allocation ratio of read and write operations. Based on the preset arbitration mechanism, sending the target transfer request to the RAM interface may be to arbitrate the transfer requests for read operations and the transfer requests for write operations sent, and send the transfer request to the RAM interface according to the pre-configured allocation ratio of read and write operations.

[0052] In an embodiment of the present disclosure, based on a preset arbitration mechanism, the target transfer request is sent to the RAM interface, which may alternately arbitrate the merged transfer requests and the unmerged individual transfer requests to send the transfer requests to the RAM interface, where the transfer requests include transfer requests for read operations and transfer requests for write operations.

[0053] In an embodiment of the present disclosure, based on a preset arbitration mechanism, the target transfer request is sent to the RAM interface, which may directly send the unmerged transfer requests and send the merged transfer requests according to the ratio of merged to unmerged, where the preset arbitration mechanism may be the sending ratio of the merged transfer requests to the unmerged transfer requests.

[0054] In an embodiment of the present disclosure, based on a preset arbitration mechanism, the target transfer request is sent to the RAM interface, which may directly send the transfer requests for read / write operations and send the transfer requests for write / read operations according to the sending ratio of read / write operations, where the preset arbitration mechanism may be the sending ratio of read operations to write operations.

[0055] Exemplarily, after module 3 and module 4 respectively merge the transfer requests for read operations and the transfer requests for write operations, they are sent to module 5, and module 5 arbitrates the merged transfer requests and the transfer requests for unmerged single operations and sends them according to the arbitration result.

[0056] In summary, according to the data transfer method proposed in the present disclosure, by receiving multiple transfer requests from the AXI interface, each transfer request having an operation address and an operation type; merging the transfer requests with the same operation type and continuous operation addresses to obtain a target transfer request, the target transfer request including the merged transfer requests and the unmerged individual transfer requests; based on a preset arbitration mechanism, sending the target transfer request to the RAM interface. The method provided by the present disclosure merges the transfer requests with continuous operation addresses in read operations and / or write operations, and arbitrates and sends the merged transfer requests and the unmerged transfer requests according to the preset arbitration mechanism, improving the bandwidth utilization rate of data transfer after the AXI interface is transferred to the RAM interface.

[0057] Based on Figure 1 the embodiment shown, Figure 2 is a flowchart of a method for merging transfer requests, Figure 2 For Figure 1 step 102 in Figure 2 is further described as follows.

[0058] Step 201, merge the transfer requests with the operation type of read operation and continuous operation addresses.

[0059] In an embodiment of the present disclosure, merging transmission requests with a read operation type and consecutive operation addresses may be performed by a separate module for processing read operations.

[0060] In an embodiment of the present disclosure, merging transmission requests with a read operation type and consecutive operation addresses may be to merge two requests with consecutive access addresses of the read operation to the memory into one read operation request, so that issuing one merged read operation request can read data at two addresses, improving the utilization rate of the transmission bandwidth.

[0061] Step 202: Merge transmission requests with a write operation type and consecutive operation addresses.

[0062] In an embodiment of the present disclosure, merging transmission requests with a write operation type and consecutive operation addresses may be performed by a separate module for processing write operations.

[0063] In an embodiment of the present disclosure, merging transmission requests with a write operation type and consecutive operation addresses may be to merge two requests with consecutive operation addresses in the write operation into one write operation request, and at the same time splice the data to be written, so that issuing one merged write operation request can write data at two addresses simultaneously, improving the utilization rate of the transmission bandwidth.

[0064] In the above embodiments, transmission requests with consecutive operation addresses in the transmission requests of read operations and write operations are merged respectively, so that issuing one merged transmission request can realize reading / writing of data at two operation addresses, improving the utilization rate of the transmission bandwidth.

[0065] Based on Figure 1-2 the embodiments shown, Figure 3 is a flowchart of a method for merging read operations. Figure 3 For Figure 2 step 201 in Figure 3 is further described as follows. As shown in

[0066] Step 301: Merge a first read request and a second read request with consecutive operation addresses to obtain a merged read request.

[0067] In an embodiment of the present disclosure, the operation address of the merged read request is the operation address of the first read request.

[0068] In an embodiment of the present disclosure, the first read request and the second read request are individual transmission requests in the transmission requests of multiple read operations, and both have operation addresses.

[0069] In an embodiment of the present disclosure, the consecutive operation addresses may mean that the operation address of the first read request and the operation address of the second read request differ by 1. The first read request is the first read request among two consecutively addressed read requests, and the second read request is the second read request among two consecutively addressed read requests.

[0070] In an embodiment of the present disclosure, merging the first read request and the second read request with consecutive operation addresses may mean merging the first read request and the second read request into a transmission request for one read operation to obtain a merged read request, and the operation address of the merged read request uses the operation address of the first read request.

[0071] Exemplarily, module 1 sends the data stream of the read operation after timing conversion to module 3, and module 3 merges two consecutively addressed read operations into one, and the address of the merged read operation uses the address of the first read operation.

[0072] Step 302, add a first mark to the merged read request and add a second mark to the unmerged third read request.

[0073] In an embodiment of the present disclosure, the first mark is used to identify that the merged read request is a merged read request, and the second mark is used to identify that the third read request is an unmerged single read request.

[0074] In an embodiment of the present disclosure, adding a first mark to the merged read request is used to distinguish that the merged read request is a transmission request after the first read request and the second read request are merged, and adding a second mark to the unmerged third read request is used to distinguish that the third read request is an unmerged single transmission request.

[0075] In an embodiment of the present disclosure, the second mark is used to identify that the transmission request is a single read request, and the second mark has a flag bit for indicating the valid bit of the returned data.

[0076] In an embodiment of the present disclosure, adding different marks to the merged read request and the unmerged third read request is used to distinguish the two types of transmission requests, so as to perform different processing on the data returned after reading the data.

[0077] Exemplarily, module 3 merges two read operations into one and retains a flag in the module to determine the type of this read operation, that is, a merged read operation or an unmerged single read operation.

[0078] In the above embodiments, by merging two consecutive transmission requests with consecutive operation addresses in the transmission request of the read operation and adding different tags to the merged and unmerged transmission requests, the utilization rate of the transmission bandwidth is improved during the arbitration and distribution processes. At the same time, after the data returned by the issued read operation, the returned data can be processed separately to obtain the target data of the transmission request of each read operation.

[0079] Based on Figure 1-3 the embodiments shown, Figure 4 FIG. is a flowchart of a data transmission method. Figure 4 Based on Figure 3 the embodiments shown, as Figure 4 shown, the method further includes the following steps:

[0080] Step 401, receiving the data returned by the RAM interface.

[0081] In the embodiments of the present disclosure, the data is obtained by reading the memory according to the operation address of the target transmission request.

[0082] In the embodiments of the present disclosure, receiving the data returned by the RAM interface may be that after the read request in the target transmission request is issued to the RAM interface, the data in the memory is read according to the operation address of the read request, and thus the data is returned through the RAM interface.

[0083] In the embodiments of the present disclosure, the data received by the RAM interface may be the data obtained by reading the memory according to the operation address of the merged read request. The data includes the data corresponding to the operation address of the first read request and the data corresponding to the operation address of the second read request. The data has a first tag. In other words, the memory is accessed according to the operation address of the first read request, the data of the operation address and the consecutive next operation address is read, and the data is returned through the RAM interface.

[0084] In the embodiments of the present disclosure, the data received by the RAM interface may be the data obtained by reading the memory according to the operation address of the unmerged third read request. The data is the data corresponding to the operation address of the third read request. The data has a second tag. In other words, the memory is accessed according to the operation address of the third read request, the data of the operation address is read, and the data is returned through the RAM interface.

[0085] Step 402, splitting or intercepting the valid bit positions of the data according to the first tag and / or the second tag to obtain the target data.

[0086] In an embodiment of the present disclosure, the first tag or the second tag indicates that the returned data is a merged transmission request or an unmerged single transmission request. Different tags indicate that different processing needs to be performed on the returned data to obtain the target data corresponding to each transmission request.

[0087] In an embodiment of the present disclosure, splitting the data may be based on the tag of the returned data. That is, when the returned data has the first tag, it indicates that the data is the returned data of a merged read request. Then, the data includes the data corresponding to the read requests of two consecutive operation addresses. The data is split to obtain the target data of the first read request and the target data of the second read request corresponding to the merged read request.

[0088] In an embodiment of the present disclosure, intercepting the valid bit positions of the data may be based on the tag of the returned data. That is, when the returned data has the second tag, it indicates that the data is the returned data of an unmerged third read request. Then, the data includes invalid bit positions, and the valid bit positions are intercepted according to the flag bit of the second tag.

[0089] Exemplarily, after the read operation returns data, module 3, according to the previously reserved flag, if the returned data is a merged read operation, splits the returned data into two parts and returns them upstream. If the previously reserved flag indicates that this read operation is a single-address read operation, intercepts the valid bit positions of the returned data and returns them upstream.

[0090] In the above embodiment, based on different tags, different processing operations are performed on the data returned by the read request to obtain the target data of each read request in the transmission request of the merged read operation, and to obtain the valid data in the data returned by the transmission request of the unmerged single read operation.

[0091] Based on Figure 1-4 the embodiment shown, Figure 5 is a flowchart of a method for merging write operations. Figure 5 For Figure 2 step 202 in Figure 5 is further described as follows. As

[0092] shown, it includes the following steps:

[0093] Step 501: Merge the first write request and the second write request with consecutive operation addresses to obtain a merged write request.

[0094] In an embodiment of the present disclosure, the operation address of the merged write request is the operation address of the first write request.

[0095] In an embodiment of the present disclosure, the consecutive operation addresses may mean that the operation address of the first write request differs from that of the second write request by 1. The first write request is the first write request among two consecutive write requests in terms of address, and the second write request is the second write request among two consecutive write requests in terms of address.

[0096] In an embodiment of the present disclosure, merging the first write request and the second write request with consecutive operation addresses may mean merging the first write request and the second write request into a transmission request for a single write operation to obtain a merged write request, and using the operation address of the first write request as the operation address of the merged write request.

[0097] Exemplarily, module 2 sends the data stream of the write operation after timing conversion to module 4. Module 4 merges two consecutive write operations into one, and uses the address of the first write operation as the address of the merged write operation.

[0098] Step 502: Merge the data to be written in the first write request and the data to be written in the second write request to obtain merged data.

[0099] In an embodiment of the present disclosure, merging the data to be written in the first write request and the data to be written in the second write request may mean concatenating the data to be written in two consecutive write operations with consecutive operation addresses.

[0100] Exemplarily, module 4 merges two consecutive write operations into one. The data of the merged write operation is concatenated from the data of the two upstream write operations, and the strobe signal of the output write operation is concatenated from the strobe signals of the two upstream write operations. If the write operations are not for two consecutive addresses, the address of the output write operation only uses the address of a single write operation, and 0 is filled in the high bit of the data of the write operation and 0 is filled in the high bit of the write strobe signal.

[0101] In the above embodiment, by separately merging the transmission requests with consecutive addresses in the write operation, after sending a merged write request, data can be written to two addresses in the memory, improving the utilization rate of the transmission bandwidth.

[0102] Based on Figure 1-5 the embodiment shown, Figure 6 is a flowchart of a method for sending a target transmission request. Figure 6 For Figure 1 step 103 in Figure 6 is further described as follows. As shown in

[0103] Step 601: Determine the sending order of the read request and the write request in the target transmission request according to the read-write allocation ratio in the preset arbitration mechanism.

[0104] In an embodiment of the present disclosure, the read requests in the target transfer requests include merged read requests and unmerged third read requests, and the write requests include merged write requests and unmerged third write requests.

[0105] In an embodiment of the present disclosure, the preset arbitration mechanism may be a pre-configured allocation ratio of read and write operations, for example, a configured signal of the allocation ratio of read and write operations.

[0106] In an embodiment of the present disclosure, according to the read-write allocation ratio in the preset arbitration mechanism, determining the order of issuing the read requests and write requests in the target transfer requests may be to determine to issue the second number of write requests after issuing the first number of read requests according to the pre-configured allocation ratio of read and write operations, so as to ensure that the read and write operations are issued alternately.

[0107] Exemplarily, after receiving the transfer requests issued by Module 3 and Module 4, Module 5 arbitrates the read and write operations according to the configured signal of the allocation ratio of read and write operations, and ensures that the ratio of the issued read and write operations meets the actual requirements.

[0108] Exemplarily, if the read-write allocation ratio in the preset arbitration mechanism is 8:1, then when the transfer requests of the read operation and the transfer requests of the write operation are issued to the arbitration module, it will be determined to issue 1 write operation after issuing 8 read operations in sequence.

[0109] Step 602: Issue the read requests and write requests to the RAM interface according to the issuing order.

[0110] In an embodiment of the present disclosure, issuing the read requests and write requests to the RAM interface according to the issuing order may be to issue the read requests and write requests to the RAM interface according to the issuing order of issuing the first number of read requests and then issuing the second number of write requests, so as to realize the access to the memory.

[0111] Exemplarily, when the read and write operations are issued simultaneously, Module 5 counts the specific number of issued read and write operations according to the configured signal of the ratio of the number of read and write operations, so that the number of issued read and write operations meets the configured ratio, and selects to receive the read and write operations issued by Module 3 and Module 4 by controlling the control signal.

[0112] In summary, the data transmission method proposed in the present disclosure, by respectively performing the merging operation with consecutive addresses on the transfer requests of the read operation and the write operation, and arbitrating the merged and unmerged transfer requests according to the preset arbitration mechanism, enables the read and write operations to be issued according to the preset ratio, realizes the reading and writing of the memory, improves the utilization rate of the transmission bandwidth when the AXI interface is transferred to the RAM interface, and can better meet the requirements of the system bus performance by adjusting the read-write allocation ratio in the preset arbitration mechanism.

[0113] Figure 7AThe overall framework diagram of the specific structure for data transmission provided by this disclosure includes 5 modules, and the following will introduce the 5 modules separately:

[0114] Upstream of the AXI data path, the bus path is divided into two groups of channels. One group is the channels for write operations, including the write address channel, write data channel, and write response channel of the bus; the other group is the channels for read operations, including the read address channel and read response channel of the bus.

[0115] Module 1: It is a conventional transfer bridge for AXI to RAM. It mainly completes the conversion of the data flow of the interface timing of the input AXI read operation channel into the data flow of the RAM interface timing.

[0116] Optionally, the processing flow of the data transmission method of Module 1 can refer to Figure 1 the optional embodiment of Step 101 in

[0117] Module 2: It is a conventional transfer bridge for AXI to RAM. It mainly completes the conversion of the data flow of the interface timing of the input write operation channel into the data flow of the RAM interface timing.

[0118] Optionally, the processing flow of the data transmission method of Module 2 can refer to Figure 1 the optional implementation manner in the embodiment shown in Step 101 in

[0119] Module 3: It is a module for read operation merging. It regards two consecutive read operations with consecutive addresses as one, and the address of the merged read operation uses the address of the first read operation, and a flag is reserved in the module to determine the type of this read operation. When the data is returned for the issued read operation, according to the previously reserved flag, if the returned data is a merged read operation, the returned data is split into two and returned upstream. If the previously reserved flag indicates that this read operation is a single-address read operation, the valid bit positions of the returned data are intercepted and returned upstream.

[0120] Optionally, the processing flow of the data transmission method of Module 3 can refer to Figure 3 、 Figure 4 the optional implementation manner in the embodiment shown in

[0121] The timing diagram of read operation merging is as shown in Figure 7BAs shown in the figure, the input signal of the module is marked with the letter I on the left, the output signal of the module is marked with the letter O on the left, clk is the clock signal, ram_ce is the read operation enable signal output from module 1 to module 3, ram_we being pulled high indicates write validity, ram_we being pulled low indicates read validity, ram_addr is the address for each read operation output from module 1 to module 3, ram_rdata is the read data returned from module 5 to module 3, ram_ready being pulled high indicates that module 5 has the ability to process read operations, and ram_ready being pulled low can backpressure to prevent module 3 from sending operations to module 5.

[0122] After the downstream returns the read data ram_rdata, it will split the data according to the previously saved flag. If the read operation passed from module 3 to module 5 before was a continuous address merge operation, then module 3 will split the read-back data into two rcore_ram_rdata and return them to module 1. If the read operation passed from module 3 to module 5 before was a single-address operation, then module 3 will intercept the valid bit positions and upload them to module 1, and return the rcore_ram_valid signal indicating data validity from module 3 to module 1.

[0123] Module 4: A module for write operation merging. It regards two consecutive write operations as one. For the merged write operation address, it uses the address of the first write operation. The write operation data is spliced from the data of the two upstream write operations. The write operation strobe signal output by this module is spliced from the strobe signals of the two upstream write operations. If the write operations are not for two consecutive addresses, then the write operation address output by this module only uses the address of a single write operation, the high bits of the write operation data are filled with 0, and the high bits of the write strobe signal are filled with 0 before output.

[0124] Optionally, the processing flow of the data transfer method of module 4 can refer to Figure 5 the optional implementation methods in the embodiments shown in the figure.

[0125] The timing diagram of write operation merging is as shown in Figure 7C the figure. The input signal of the module is marked with the letter I on the left, the output signal of the module is marked with the letter O on the left, clk is the clock signal, ram_ce is the write operation enable signal input from module 2 to module 4, ram_we being pulled high indicates write validity, ram_we being pulled low indicates read validity, ram_addr is the address for each write operation input from module 2 to module 4, ram_wdata is the write data for each write operation input from module 2 to module 4, ram_ready is the input from module 5 to module 4, and this signal being pulled high indicates that module 5 has the ability to process write operations. If ram_ready of module 5 is pulled low, it can backpressure to module 4 to prevent module 4 from sending operations downstream.

[0126] The output of the merged write operation is shown in the figure. wcore_ram_ce is the enable signal of the merged write operation. wcore_ram_we is the write enable signal of the merged write operation. wcore_ram_addr is the write address signal of the merged write operation. If it is a continuous address, the value is the write address of the first operation with consecutive addresses. If it is not a continuous address, the value is the address of this operation. wcore_ram_wdata is the data signal of the merged write operation. If it is a continuous address, the value is the concatenation result of the data of two consecutive operations. If it is not a continuous address, the value is the data of this operation. wcore_ram_bwe is the data strobe signal of the merged write operation. If it is a continuous address, the value is the concatenation result of the write strobe signals of two consecutive operations. If it is not a continuous address, the value is the write strobe signal of this operation.

[0127] Module 5: An arbitration module for read and write operations. It arbitrates read and write operations according to the configured ratio signal of read and write operation allocations to ensure that the ratio of the issued read and write operations meets our actual needs.

[0128] Optionally, the processing flow of the data transmission method of Module 5 can refer to Figure 6 the optional implementation manners of the embodiments shown.

[0129] The timing diagram of the arbitration module is as shown in Figure 7D When read and write operations are issued simultaneously, Module 5 will count and statistically analyze the specific number of issued read and write operations according to the configured signal of the ratio of the number of read and write operation strokes, so that the number of issued read and write operation strokes meets the configured ratio, and selects to receive the read and write operations issued by Module 3 and Module 4 by controlling the wcore_splice_ready signal and the rcore_splice_ready signal.

[0130] In summary, the above specific structure for data transmission can solve the problem that the transmission bandwidth is halved due to the conversion of parallel data flow to serial data flow after the AXI interface is converted to the RAM interface, and better meet the system bus performance requirements by adjusting the ratio of issued read and write operations.

[0131] Figure 8 This is a schematic structural diagram of a data transmission device 800 according to an embodiment of the present disclosure. As shown in Figure 8 the figure, the device includes: a receiving module 810, a merging module 820, and an arbitration module 830.

[0132] The receiving module 810 is configured to receive multiple transmission requests from the AXI interface, and each transmission request has an operation address and an operation type.

[0133] The merging module 820 is used to merge transfer requests with the same operation type and consecutive operation addresses to obtain a target transfer request, where the target transfer request includes the merged transfer requests and unmerged individual transfer requests.

[0134] The arbitration module 830 is used to send the target transfer request to the RAM interface based on a preset arbitration mechanism.

[0135] In some embodiments, the merging module is further used to merge transfer requests with a read operation type and consecutive operation addresses to obtain a merged read request; and merge transfer requests with a write operation type and consecutive operation addresses to obtain a merged write request. The target transfer request includes the merged read request and the merged write request.

[0136] In some embodiments, the merging module may further include a first merging module and a second merging module. The first merging module is used to merge transfer requests with a read operation type and consecutive operation addresses to obtain a merged read request; and the second merging module is used to merge transfer requests with a write operation type and consecutive operation addresses to obtain a merged write request.

[0137] In some embodiments, the merging module is further used to merge a first read request and a second read request with consecutive operation addresses to obtain a merged read request, where the operation address of the merged read request is the operation address of the first read request; add a first flag to the merged read request and a second flag to the unmerged third read request. The first flag is used to identify the merged read request as a merged read request, and the second flag is used to identify the third read request as an unmerged individual read request. Specifically, it may be executed by the first merging module.

[0138] In some embodiments, the merging module is further used to receive data returned by the RAM interface, where the data is obtained by reading the memory according to the operation address of the target transfer request; split or intercept valid bit positions of the data according to the first flag and / or the second flag to obtain target data. Specifically, it may be executed by the first merging module.

[0139] In some embodiments, the merging module is further used to merge a first write request and a second write request with consecutive operation addresses to obtain a merged write request, where the operation address of the merged write request is the operation address of the first write request; and merge the data to be written in the first write request and the data to be written in the second write request to obtain merged data. Specifically, it may be executed by the second merging module.

[0140] In some embodiments, the arbitration module is further used to determine the sending order of read requests and write requests in the target transfer request according to the read / write allocation ratio in the preset arbitration mechanism; and send the read requests and write requests to the RAM interface according to the sending order.

[0141] In summary, the data transmission device proposed by the present disclosure receives multiple transmission requests from the AXI interface, merges the transmission requests with consecutive operation addresses in read operations and write operations respectively, and based on a preset arbitration mechanism, sends the merged transmission requests or unmerged transmission requests to the RAM interface. This improves the transmission bandwidth utilization rate after the parallel data flow of the AXI interface is converted into a serial data stream.

[0142] Figure 9 FIG. 5 is a schematic structural diagram of an electronic device 900 for implementing the above data transmission method according to an exemplary embodiment.

[0143] Referring to Figure 9 , the electronic device 900 may include one or more of the following components: a processing component 902, a memory 904, a power supply component 906, a multimedia component 908, an audio component 910, an input / output (I / O) interface 912, a sensor component 914, and a communication component 916.

[0144] The processing component 902 generally controls the overall operation of the electronic device 900, such as operations associated with display, telephone calls, data communication, camera operations, and recording operations. The processing component 902 may include one or more processors 920 to execute instructions to complete all or part of the steps of the above method. In addition, the processing component 902 may include one or more modules to facilitate the interaction between the processing component 902 and other components. For example, the processing component 902 may include a multimedia module to facilitate the interaction between the multimedia component 908 and the processing component 902.

[0145] The memory 904 is configured to store various types of data to support the operation of the electronic device 900. Examples of such data include instructions for any application or method operating on the electronic device 900, contact data, phone book data, messages, pictures, videos, etc. The memory 904 may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, a magnetic disk, or an optical disk.

[0146] The power supply component 906 provides power to various components of the electronic device 900. The power supply component 906 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 900.

[0147] The multimedia component 908 includes a screen that provides an output interface between the electronic device 900 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can sense not only the boundaries of the touch or swipe actions but also detect the duration and pressure associated with the touch or swipe operations. In some embodiments, the multimedia component 908 includes a front camera and / or a rear camera. When the electronic device 900 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have a focal length and optical zoom capabilities.

[0148] The audio component 910 is configured to output and / or input audio signals. For example, the audio component 910 includes a microphone (MIC) that is configured to receive external audio signals when the electronic device 900 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals can be further stored in the memory 904 or transmitted via the communication component 916. In some embodiments, the audio component 910 further includes a speaker for outputting audio signals.

[0149] The I / O interface 912 provides an interface between the processing component 902 and a peripheral interface module, which can be a keyboard, a click wheel, buttons, etc. These buttons can include but are not limited to: a home button, a volume button, a power button, and a lock button.

[0150] The sensor component 914 includes one or more sensors for providing status assessments of various aspects of the electronic device 900. For example, the sensor component 914 can detect the on / off state of the electronic device 900, the relative positioning of components, such as the display and keypad of the electronic device 900. The sensor component 914 can also detect a change in the position of the electronic device 900 or a component of the electronic device 900, the presence or absence of user contact with the electronic device 900, the orientation or acceleration / deceleration of the electronic device 900, and a change in the temperature of the electronic device 900. The sensor component 914 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor component 914 can also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor component 914 can further include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0151] The communication component 916 is configured to facilitate communication between the electronic device 900 and other devices in a wired or wireless manner. The electronic device 900 can access a communication standard-based wireless network, such as WiFi, 2G or 3G, 4G LTE, 5G NR (New Radio), or a combination thereof. In an exemplary embodiment, the communication component 916 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 916 further includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on Radio Frequency Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra Wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0152] In an exemplary embodiment, the electronic device 900 can be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components for performing the above-described method.

[0153] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 904 including instructions, and the above instructions can be executed by a processor 920 of the electronic device 900 to complete the above method. For example, the non-transitory computer-readable storage medium can be a ROM, Random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0154] Embodiments of the present disclosure also propose a non-transitory computer-readable storage medium storing computer instructions, where the computer instructions are used to cause a computer to execute the data transmission method described in the above embodiments of the present disclosure.

[0155] Embodiments of the present disclosure also propose a computer program product, including a computer program, and the computer program executes the data transmission method described in the above embodiments of the present disclosure when being executed by a processor.

[0156] Embodiments of the present disclosure also propose a chip, including at least one processor and a communication interface, where the communication interface is used to receive a signal input to the chip or output a signal from the chip, and the processor communicates with the communication interface and implements the data transmission method described in the above embodiments of the present disclosure through logic circuits or by executing code instructions.

[0157] Figure 10 is a schematic structural diagram of a chip 1000 for implementing the above data transmission method shown according to an exemplary embodiment. Refer to Figure 10, the chip 1000 includes at least one communication interface 1001 and a processor 1002. The communication interface 1001 is configured to receive signals input to the chip 1000 or signals output from the chip 1000. The processor 1002 communicates with the communication interface 1001 and implements the data transmission method described in the above embodiments of the present disclosure through logic circuits or by executing code instructions.

[0158] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0159] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0160] Any process or method description shown in the flowchart or described in other ways herein can be understood as representing a module, segment, or portion of code including one or more executable instructions for implementing a specific logical function or process. The scope of the preferred embodiments of the present disclosure includes additional implementations, where the functions can be executed in a manner other than shown or discussed, including in a substantially simultaneous manner according to the functions involved or in a reverse order, which should be understood by those skilled in the technical field to which the embodiments of the present disclosure pertain.

[0161] The logic and / or steps represented in the flowchart or otherwise described herein can, for example, be considered as a definable sequence list of executable instructions for implementing logical functions, which can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processing module, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or used in conjunction with these instruction execution systems, apparatus, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion having one or more wirings (control method), a portable computer disk cartridge (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, a computer-readable medium can even be paper or other suitable media on which a program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other appropriate processing as necessary, and then stored in a computer memory.

[0162] It should be understood that various parts of the embodiments of the present disclosure can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application-specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0163] Those of ordinary skill in the art of this technology can understand that all or part of the steps carried by the methods of the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0164] In addition, each functional unit in various embodiments of the present disclosure may be integrated into a processing module, or each unit may exist physically alone, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium. The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disc, etc.

[0165] Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A data transmission method, characterized in that, The method includes: Receiving a plurality of transfer requests from an AXI interface, each transfer request having an operation address and an operation type; Merging transfer requests with the same operation type and consecutive operation addresses to obtain a target transfer request, where the target transfer request includes the merged transfer requests and unmerged individual transfer requests; Based on a preset arbitration mechanism, sending the target transfer request to a RAM interface.

2. The method according to claim 1, wherein The merging of transfer requests with the same operation type and consecutive operation addresses includes: Merging transfer requests with a read operation type and consecutive operation addresses to obtain a merged read request; Merging transfer requests with a write operation type and consecutive operation addresses to obtain a merged write request, where the target transfer request includes the merged read request and the merged write request.

3. The method according to claim 2, wherein The merging of transfer requests with a read operation type and consecutive operation addresses includes: Merging a first read request and a second read request with consecutive operation addresses to obtain the merged read request, where the operation address of the merged read request is the operation address of the first read request; Adding a first flag to the merged read request and a second flag to an unmerged third read request, where the first flag is used to identify the merged read request as a merged read request, and the second flag is used to identify the third read request as an unmerged individual read request.

4. The method according to claim 3, wherein The method further includes: Receiving data returned by the RAM interface, where the data is obtained by reading a memory according to the operation address of the target transfer request; According to the first flag and / or the second flag, splitting the data or intercepting valid bit positions to obtain target data.

5. The method according to claim 2, characterized in that The merging of transfer requests with a write operation type and consecutive operation addresses includes: Merging a first write request and a second write request with consecutive operation addresses to obtain the merged write request, where the operation address of the merged write request is the operation address of the first write request; Merging the data to be written in the first write request and the data to be written in the second write request to obtain merged data.

6. The method according to claim 2, characterized in that, Based on a preset arbitration mechanism, sending the target transfer request to a RAM interface includes: Determining the sending order of read requests and write requests in the target transfer request according to the read-write allocation ratio in the preset arbitration mechanism; Sending the read requests and the write requests to the RAM interface according to the sending order.

7. A data transmission device, characterized in that, Includes: A receiving module for receiving a plurality of transfer requests from an AXI interface, each transfer request having an operation address and an operation type; A merging module for merging transfer requests with the same operation type and consecutive operation addresses to obtain a target transfer request, where the target transfer request includes the merged transfer requests and unmerged individual transfer requests; An arbitration module for sending the target transfer request to a RAM interface based on a preset arbitration mechanism.

8. An electronic device, characterized in that, Includes: A processor and a memory for storing a computer program that can run on the processor, where, when the processor is used to run the computer program, it executes the method according to any one of claims 1-6.

9. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute the method according to any one of claims 1-6.

10. A chip, characterized in that, Comprising at least one processor and a communication interface; the communication interface is used to receive signals input to the chip or signals output from the chip, and the processor communicates with the communication interface and implements the method according to any one of claims 1-6 through logic circuits or by executing code instructions.

Images