Read acceleration device, data reading method, communication system, equipment and medium

Abstract

The invention discloses a read acceleration device, a data reading method, a communication system, equipment and a medium, and relates to the technical field of integrated circuits. The device comprises a judgment module used for judging whether a read request sent by bus master equipment hits a first-in first-out queue storage module or not so as to generate a corresponding hit state signal; the first-in first-out queue storage module is used for storing read data information returned by the bus slave equipment according to the read request and returning the read data information to the bus master equipment according to the hit state signal; the replacement arbitration module is used for determining target read data information from the first-in first-out queue storage module and replacing the target read data information according to the hit state signal; the target read data information is read data information of which the use frequency does not meet a preset use condition in a preset time period. According to the technical scheme, the data reading bandwidth of the AXI bus can be improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a read acceleration device, a data reading method, a communication system, a device and a medium. Background Art

[0002] With the rapid development of integrated circuit technology, modern embedded systems and high-performance computing platforms have put forward higher requirements for high-speed and low-latency data transmission in data processing and storage. As a communication protocol widely used in multi-core processors, hardware accelerators, embedded devices and other high-performance systems, the AXI (Advanced Extensible Interface) bus has the advantages of high bandwidth and low latency when processing data exchange, and can effectively support the transmission of parallel data streams. The AXI bus adopts a transaction-based protocol, which can achieve efficient data transmission between the host and the slave.

[0003] However, with the increase in system scale and data traffic, the performance bottleneck of the AXI bus gradually appears. Especially when a large number of read operations are involved, the latency and bandwidth utilization rate of data reading have become problems that need to be solved urgently. When the AXI bus reads data, it usually needs to initiate multiple requests to obtain data from the target device. However, due to problems such as queuing between read requests, access conflicts, and response latency of the target device, the transmission efficiency will decrease, and the system response speed will be affected. Therefore, how to improve the efficiency of the AXI bus in the data process, especially in the case of frequent read operations and large data volume transmission, has become an important research topic in modern embedded systems and high-performance computing platforms. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a read acceleration device, a data reading method, a communication system, a device and a medium, which can improve the read data bandwidth of the AXI bus and further improve the read data efficiency of the AXI bus. The specific solutions are as follows:

[0005] In the first aspect, the present application discloses a read acceleration device, including:

[0006] A judgment module, configured to judge whether a read request sent by a bus master device hits a first-in-first-out queue storage module to generate a corresponding hit status signal;

[0007] The first-in-first-out queue storage module is configured to store read data information returned by a bus slave device according to the read request, and return the read data information to the bus master device according to the hit status signal;

[0008] A replacement arbitration module, configured to determine target read data information from the FIFO queue storage module and perform replacement on the target read data information according to the hit status signal; the target read data information is read data information that does not meet the preset usage condition in a preset time period.

[0009] Optionally, the read acceleration device further includes:

[0010] A device interface module, configured to transmit the read request and the read data information between the bus master device and the bus slave device;

[0011] A command queue module, configured to identify and store read requests sent by different bus master devices respectively;

[0012] A polling arbitration module, configured to poll the command queue module according to pre-configured arbitration weights to provide command queue information for current access.

[0013] Optionally, the read acceleration device further includes:

[0014] A lookup table module, configured to store data information corresponding to the FIFO queue storage module; the data information includes a start address, an end address, and an effective data volume corresponding to each read data information; wherein, the start address is the start address of the read request, the end address is the sum of the start address and the effective data volume, and the effective data volume is the product of the data width and the data length of the Advanced Extensible Interface bus;

[0015] A lookup table update module, configured to, when the hit status signal is a first status signal indicating a miss, update the lookup table module according to the replaced FIFO queue storage module after replacing the target read data information by using the replacement arbitration module.

[0016] Optionally, the judgment module further includes:

[0017] A prefetch operation unit, configured to perform a prefetch operation on the bus slave device based on a preset data length and a preset data width when the data volume stored in the FIFO queue storage module is less than a preset threshold; wherein, the prefetch address corresponding to the prefetch operation is equal to the current end address in the lookup table module.

[0018] Optionally, the judgment module is specifically configured to:

[0019] Determine a current read request, and judge whether there is a corresponding relationship between the read address information of the current read request in the command queue module and the data information in the lookup table module;

[0020] If there is no corresponding relationship between the read address information and the data information in the lookup table module, it is determined that the current read request misses the first-in-first-out queue storage module, and a first status signal indicating a miss is generated;

[0021] If there is a corresponding relationship between the read address information and the data information in the lookup table module, it is determined that the current read request hits the first-in-first-out queue storage module, and a second status signal indicating a hit is generated.

[0022] Optionally, the replacement arbitration module is specifically configured to:

[0023] When the hit status signal is the first status signal, send the current read request in the command queue module to the bus slave device;

[0024] Obtain the current read data information returned by the bus slave device according to the current read request, and determine the target read data information from the first-in-first-out queue storage module;

[0025] Replace the target read data information with the current read data information, and send the current read data information to the bus master device.

[0026] In a second aspect, the present application discloses a data reading method, which is applied to the aforementioned read acceleration device, and includes:

[0027] Obtain a read request sent by a bus master device, and determine whether the read request hits the first-in-first-out queue storage module in the read acceleration device to generate a corresponding hit status signal;

[0028] Store the read data information returned by the bus slave device according to the read request through the first-in-first-out queue storage module, and return the read data information to the bus master device according to the hit status signal;

[0029] Determine the target read data information from the first-in-first-out queue storage module, and replace the target read data information according to the hit status signal; the target read data information is the read data information whose usage times do not meet the preset usage conditions within a preset time period.

[0030] In a third aspect, the present application discloses a communication system, including:

[0031] A bus master device, configured to send a read request to a bus slave device and receive the read data information returned by the bus slave device through a read acceleration device;

[0032] The bus slave device is configured to return corresponding read data information to the read acceleration device according to the read request sent by the bus master device;

[0033] The read acceleration device is configured to determine whether a read request sent by the bus master device hits the first-in-first-out (FIFO) queue storage module to generate a corresponding hit status signal; store read data information returned by the bus slave device according to the read request through the FIFO queue storage module, and return the read data information to the bus master device according to the hit status signal; determine target read data information from the FIFO queue storage module, and replace the target read data information according to the hit status signal; the target read data information is read data information whose usage times within a preset time period do not meet the preset usage conditions.

[0034] In a fourth aspect, the present application discloses an electronic device, which includes a processor and a memory; wherein, the memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the data reading method as described above.

[0035] In a fifth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the data reading method as described above.

[0036] The present application provides a read acceleration device, including: a judgment module configured to judge whether a read request sent by a bus master device hits a first-in-first-out (FIFO) queue storage module to generate a corresponding hit status signal; a FIFO queue storage module configured to store read data information returned by a bus slave device according to the read request, and return the read data information to the bus master device according to the hit status signal; a replacement arbitration module configured to determine target read data information from the FIFO queue storage module, and replace the target read data information according to the hit status signal; the target read data information is read data information whose usage times within a preset time period do not meet the preset usage conditions.

[0037] The beneficial effects of the present application are as follows: The read request sent by the bus master device will first pass through the read acceleration device. The judgment module judges the read request to generate a corresponding hit status signal to determine whether it hits the read data information sent by the bus slave device stored in the FIFO queue storage module. Further, if it does not hit, the replacement arbitration module adopts the least recently used strategy to replace the target read data information arbitrated from the FIFO queue storage module, ensuring that the data replaced each time when there is no hit is not frequently used, improving the subsequent hit probability, and further enhancing the bus read data efficiency. In addition, the design of the present invention adopts a module design independent of the bus, which is convenient for SOC (System on Chip) design and can be easily called.

[0038] In addition, a data reading method, a communication system, a device, and a storage medium provided by this application correspond to the above read acceleration device, and have the same effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0040] Figure 1 Structural schematic diagram of a read acceleration device disclosed in this application;

[0041] Figure 2 Structural schematic diagram of a specific read acceleration device disclosed in this application;

[0042] Figure 3 Structural schematic diagram of a lookup table disclosed in this application;

[0043] Figure 4 Processing flow schematic diagram of a read acceleration device disclosed in this application;

[0044] Figure 5 Prefetch function flow schematic diagram disclosed in this application;

[0045] Figure 6 Flowchart of a data reading method disclosed in this application;

[0046] Figure 7 Structural schematic diagram of a communication system architecture disclosed in this application;

[0047] Figure 8 Structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0048] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0049] Currently, with the increase in system scale and data traffic, the performance bottleneck of the AXI bus is gradually emerging. Especially when a large number of read operations are involved, the latency of data reading and the bandwidth utilization rate have become difficult problems to be solved urgently. When the AXI bus reads data, it usually needs to initiate multiple requests to obtain data from the target device. However, due to problems such as queuing between read requests, access conflicts, and response latency of the target device, the transmission efficiency will decrease and the system response speed will be affected.

[0050] Currently, almost all solutions on the market improve the read efficiency of the AXI bus through request scheduling and queuing optimization: by means of priority scheduling, pipelining, etc., the order and concurrent access capabilities of read requests are optimized to reduce access competition and latency. There are also solutions on the market that increase the support for multiple channels or multiple data streams to improve the data transmission bandwidth and throughput.

[0051] However, these methods cannot guarantee the optimal scheduling effect in scenarios with heavy system load or complex applications, and there are certain performance bottlenecks. And when there are multiple different data streams and requests, conflicts and competitions in read operations cannot be avoided.

[0052] Therefore, this application provides a read acceleration device that can overcome the above shortcomings and, as a supplement to the existing solutions, further improve the read data efficiency of the AXI bus.

[0053] An embodiment of the present invention discloses a read acceleration device. The read addresses and read data channel information of all bus master devices will first pass through the read acceleration device, and after being processed by the read acceleration device, they will be sent to the bus slave device; the read data information returned by the bus slave device will first pass through the read acceleration device and then be returned by the read acceleration device to the corresponding bus master device. See Figure 1 As shown, the device includes:

[0054] A judgment module 11, configured to judge whether the read request sent by the bus master device hits the first-in-first-out queue storage module to generate a corresponding hit status signal.

[0055] Before introducing the judgment module, first introduce other modules also included in this application. See Figure 2 for description, including:

[0056] The device interface module is used to transfer the read request and the read data information between the bus master device and the bus slave device. This module includes an AXI slave read interface and an AXI master read interface. Among them, the AXI slave read interface is used to interact with the bus master device, including receiving and responding to the read request of the bus master device, and returning the read data information to the bus master device. It should be noted that when the read acceleration device is busy and unable to receive the read request of the bus master device, the AXI slave read interface will notify the bus master device. The AXI master read interface is used to interact with the bus slave device, and it will convert the information inside the read acceleration device into standard AXI read channel information and send it to the bus slave device, and receive and respond to the read data and response information sent by the bus slave device.

[0057] The command queue module 14 is used to identify and store the read requests issued by different bus master devices respectively. For example, the CPU, GPU, and DMA controller can all initiate read requests actively. When they respectively request to read data from different memory addresses, the command queue module identifies the different bus master devices sending the read requests and stores the read request information sent by different bus master devices separately.

[0058] The polling arbitration module 15 is used to poll the command queue module according to the pre-configured arbitration weight to provide the command queue information of the current access. Among them, the device also includes a software configuration interface, which is responsible for updating some functional configurations inside the read acceleration device. The arbitration weight can be arbitrarily configured through this interface to improve the flexibility and versatility of the device. The polling arbitration module accesses each command queue in turn according to the configured arbitration weight.

[0059] The lookup table module 16 is used to store the data information corresponding to the First-In-First-Out (FIFO) storage module; the data information includes the start address, end address, and valid data volume corresponding to each read data information; among them, the start address is the starting address of the read request, the end address is the sum of the starting address and the valid data volume, and the valid data volume is the product of the data width and data length of the Advanced eXtensible Interface bus. As Figure 3 shown is a schematic structural diagram of a lookup table exemplarily provided in this embodiment.

[0060] In this embodiment, the judgment module 11 generates a corresponding hit status signal by judging whether the read request of the bus master device is consistent with the information in the lookup table module. Specifically, the judgment module is used to perform the following steps:

[0061] Step 1: Determine the current read request, and judge whether there is a corresponding relationship between the read address information of the current read request in the command queue module and the data information in the lookup table module;

[0062] Step 2: If there is no corresponding relationship between the read address information and the data information in the lookup table module, it is determined that the current read request misses the first-in-first-out queue storage module, and a first status signal indicating a miss is generated.

[0063] Step 3: If there is a corresponding relationship between the read address information and the data information in the lookup table module, it is determined that the current read request hits the first-in-first-out queue storage module, and a second status signal indicating a hit is generated.

[0064] In this embodiment, if the address information in the current command queue does not correspond to all the addresses in the lookup table, it means that the read data information corresponding to the current read request has not been stored in the first-in-first-out queue storage module of the read acceleration device. That is, the current read request misses the first-in-first-out queue storage module. At this time, a first status signal indicating a miss, that is, a miss signal, is generated.

[0065] If the address information in the current command queue corresponds to the address information in the lookup table, it means that the read data information corresponding to the current read request has been stored in the first-in-first-out queue storage module of the read acceleration device. That is, the current read request hits the first-in-first-out queue storage module. At this time, a second status signal indicating a hit, that is, a hit signal, is generated. At this time, the judgment module will give the serial number of the hit FIFO, and the bus slave read interface will convert the data and response information in the corresponding FIFO into the format of the AXI read data channel and return it to the bus master device.

[0066] The first-in-first-out queue storage module 12 is used to store the read data information returned by the bus slave device according to the read request, and return the read data information to the bus master device according to the hit status signal.

[0067] In this embodiment, all the read data information related to the read request returned by the bus slave device is stored in this module. It can be understood that if there is read data information corresponding to the read request in the first-in-first-out queue storage module, that is, the hit status signal is the second status signal hit of a hit, then the read data information at this time will be returned to the bus master device.

[0068] As Figure 4 shown is a schematic diagram of the processing logic for a specific read acceleration device to return read data information. Whenever the bus master device initiates a read operation, as long as the read acceleration device is not in a state where it cannot respond, the bus slave read interface will receive and respond to the read request of the bus master device; at the same time, the command queue module stores the read request information of different master devices into the corresponding queues.

[0069] After the bus master issues a read request, it determines whether the read request hits the FIFO in this device, and then executes the hit or miss operation. When it hits, the corresponding information of the hit FIFO is given through the lookup table, and then the read data information is returned to the corresponding bus master. If it misses, the read request will be sent to the bus slave to receive the corresponding read data information. After waiting for the data to return, the read data information will be stored in the corresponding FIFO. At this time, the lookup table is updated according to the FIFO storage module. Meanwhile, the replacement arbitration module will give the sequence number of the least recently used FIFO in the FIFO storage module, indicating that the information in this FIFO can be cleared, and at the same time, the read data and read response returned by the slave device this time are stored, and the information in the corresponding lookup table is updated.

[0070] Therefore, in a specific embodiment, the read acceleration device of the present application further includes a lookup table update module, which is used to, when the hit status signal is the first status signal indicating a miss, use the replacement arbitration module to replace the target read data information, and then update the lookup table module according to the replaced first-in-first-out queue storage module. It can be understood that since the lookup table stores the data information corresponding to the FIFO storage module, and the FIFO storage module is used to store the read data information returned by the bus slave. Therefore, as long as the bus slave returns the read data information, and there is a replacement operation for the read data information in the FIFO storage module, the lookup table will be updated accordingly according to the FIFO storage module. When updating, the starting address in the lookup table is the starting address of this read request, the ending address is the starting address of this read request plus the data width of the AXI bus multiplied by the data length, and the effective data volume is equal to the data width of the AXI bus multiplied by the data length.

[0071] It should be noted that the design of the present invention adopts a module design independent of the bus, which is convenient for SOC design and can be easily called. The number, depth, and width of the FIFOs inside the device can be expanded according to the design requirements of different SOCs. Currently, there are few designs in SOC design aimed at improving the read operation bandwidth of the AXI bus.

[0072] The replacement arbitration module 13 is used to determine the target read data information from the first-in-first-out queue storage module, and replace the target read data information according to the hit status signal; the target read data information is the read data information whose usage times do not meet the preset usage conditions within a preset time period.

[0073] In this embodiment, in order to improve the hit efficiency, each time the FIFO storage module is not hit and it is necessary to store the read data information obtained from the bus slave in the FIFO storage module this time, the "least recently used replacement strategy" is adopted, and the replacement arbitration module is used to replace the read data information that is not frequently used in the FIFO.

[0074] Specifically, the replacement arbitration module is used to perform the following steps:

[0075] When the hit status signal is the first status signal, the current read request in the command queue module is sent to the bus slave device;

[0076] Obtain the current read data information returned by the bus slave device according to the current read request, and determine the target read data information from the first-in-first-out queue storage module;

[0077] Use the current read data information to replace the target read data information, and send the current read data information to the bus master device.

[0078] It can be seen that the replacement arbitration module can ensure that when in the miss state, it will give a least recently used FIFO, so as to replace the old data in the FIFO and improve the read data efficiency of the device. Specifically, when in the miss state, all the information in the FIFO will be cleared, and the latest data and response will be stored in the FIFO.

[0079] In a feasible implementation manner, the arbitration strategy of the replacement arbitration module can also be adjusted accordingly. For example, combining the access frequency and the recent usage time, or dynamically adjusting the strategy according to the access mode of the data type. For example, data that is frequently accessed but not recently used may be more valuable to retain than data that is infrequently accessed but recently used, and a weighted strategy can be designed. Or, consider the energy consumption factor during the replacement process, such as preferentially replacing some data with high access energy consumption, or adopting a more energy-saving replacement strategy during low load. In addition, security enhancement can also be performed during the replacement process, such as adding encryption or integrity verification to prevent sensitive data from being leaked or tampered with when being replaced.

[0080] The beneficial effects of this application are as follows: The read request sent by the bus master device will first pass through the read acceleration device, and the judgment module will judge the read request to generate a corresponding hit status signal to determine whether it hits the read data information sent by the bus slave device stored in the first-in-first-out queue storage module. Further, if it does not hit, the replacement arbitration module adopts the least recently used strategy to replace the target read data information arbitrated from the first-in-first-out queue storage module, ensuring that the data replaced each time when not hitting is not frequently used, improving the subsequent hit probability, and further enhancing the bus read data efficiency. In addition, the design of this invention adopts a module design independent of the bus, which is convenient for SOC (System on Chip) design and can be easily called.

[0081] Based on the above embodiments, the judgment logic in the judgment module can determine whether the read request sent by the bus master device hits the FIFO in this device, so as to perform hit or miss operations; the calculation logic can calculate the data volume of the FIFO and the address information of the lookup table; the control logic can control the update timing of the lookup table. In addition, in a feasible implementation manner, the calculation logic in the judgment module can also calculate the prefetch address. Specifically, the judgment module further includes:

[0082] A prefetch operation unit, configured to perform a prefetch operation on the bus slave device based on a preset data length and a preset data width when the data volume stored in the first-in-first-out queue storage module is less than a preset threshold; wherein, the prefetch address corresponding to the prefetch operation is equal to the current end address in the lookup table module.

[0083] In this embodiment, in order to improve the overall data reading efficiency, the judgment module in the read acceleration device further includes a prefetch operation unit, which is used to judge whether the threshold in the corresponding FIFO reaches a set value. The prefetch function process is as Figure 5 shown: If the data volume in the FIFO is less than the set value, a prefetch operation will be performed through the bus master device read interface. The length and width of the prefetch data can be defined through the software configuration interface. The prefetch address is equal to the end address of the current lookup table, and the corresponding lookup table is updated at the same time. In this way, by preloading in advance, the miss rate is reduced.

[0084] It should be noted that the miss, hit, and prefetch operations in the design of the present invention are all in parallel, which greatly improves the efficiency of reading data.

[0085] An embodiment of the present invention discloses a data reading method. Refer to Figure 6 as shown, which is applied to the aforementioned read acceleration device. The method includes:

[0086] Step S11: Obtain a read request sent by the bus master device, and judge whether the read request hits the first-in-first-out queue storage module in the read acceleration device to generate a corresponding hit status signal;

[0087] Step S12: Store the read data information returned by the bus slave device according to the read request through the first-in-first-out queue storage module, and return the read data information to the bus master device according to the hit status signal;

[0088] Step S13: Determine target read data information from the first-in-first-out queue storage module, and replace the target read data information according to the hit status signal; the target read data information is read data information whose usage times within a preset time period do not meet the preset usage conditions.

[0089] Among them, for the more specific working processes of the above steps, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be elaborated herein.

[0090] The beneficial effects of the present application are as follows: The read request sent by the bus master device will first pass through the read acceleration device. The judgment module judges the read request to generate a corresponding hit status signal to determine whether it hits the read data information sent by the bus slave device stored in the first-in-first-out queue storage module. Further, if it does not hit, the replacement arbitration module adopts the least recently used strategy to replace the target read data information arbitrated from the first-in-first-out queue storage module, ensuring that the data replaced each time when there is no hit is not frequently used, improving the subsequent hit probability and further enhancing the bus read data efficiency. In addition, the design of the present invention adopts a module design independent of the bus, which is convenient for SOC (System on Chip) design and can be easily called.

[0091] Corresponding to the above device embodiment, the embodiment of the present invention further provides a communication system. The communication system described below can be mutually corresponding and referred to the read acceleration device described above.

[0092] The communication system provided in this embodiment mainly includes:

[0093] A bus master device, configured to send a read request to a bus slave device and receive the read data information returned by the bus slave device through the read acceleration device;

[0094] A bus slave device, configured to return corresponding read data information to the read acceleration device according to the read request sent by the bus master device;

[0095] A read acceleration device, configured to judge whether the read request sent by the bus master device hits the first-in-first-out queue storage module to generate a corresponding hit status signal; store the read data information returned by the bus slave device according to the read request through the first-in-first-out queue storage module, and return the read data information to the bus master device according to the hit status signal; determine target read data information from the first-in-first-out queue storage module, and replace the target read data information according to the hit status signal; the target read data information is the read data information whose usage times do not meet the preset usage conditions within a preset time period.

[0096] As Figure 7 shown is the system architecture diagram corresponding to the communication system in this embodiment. The bus master device refers to a device that can obtain bus control rights and initiate data transmission. It sends commands to the slave device through the bus and controls the read and write operations of data. The bus slave device refers to a device that responds to the commands of the master device and performs data transmission. The slave device can only passively receive the commands of the master device and complete the read or write operation of data according to the commands.

[0097] In a specific embodiment, the communication device further includes a bus matrix. The bus matrix is a multi-layer interconnection structure for connecting multiple master devices and slave devices, aiming to improve the parallel access capability and efficiency of the system. The bus matrix manages the access requests of multiple master devices to the same slave device through an arbitration mechanism, ensuring that only one master device can access the slave device at any given time.

[0098] In this embodiment, the information of the read and write channels of all bus master devices will first enter the bus matrix. After arbitration by the bus matrix, the information of the write address, write data, and write response channels will directly reach the corresponding bus slave devices; while the information of the read address and read data channels will first pass through the read acceleration device, which processes it and then sends it to the bus slave device. The read data information returned by the bus slave device will first pass through the read acceleration device, and then the read acceleration device will send it back to the bus matrix, and finally reach the corresponding bus master device. Among them, for the more specific working process of the read acceleration device, reference can be made to the corresponding content disclosed in the previous embodiment, and details will not be elaborated here.

[0099] The beneficial effects of this application are as follows: The read requests sent by the bus master device will first pass through the read acceleration device. The judgment module judges the read requests to generate corresponding hit status signals to determine whether the read data information sent by the bus slave device stored in the first-in-first-out queue storage module is hit. Further, if not hit, the replacement arbitration module adopts the least recently used strategy to replace the target read data information arbitrated from the first-in-first-out queue storage module, ensuring that the data replaced each time when not hit is not frequently used, improving the subsequent hit probability, and further enhancing the bus read data efficiency. In addition, the design of the present invention adopts a module design independent of the bus, which is convenient for SOC (System on Chip) design and can be easily called.

[0100] Furthermore, the embodiment of this application also discloses an electronic device, Figure 8 It is a structural diagram of the electronic device 20 shown according to an exemplary embodiment. The content in the figure should not be considered as any limitation to the scope of use of this application.

[0101] Figure 8 This is a schematic structural diagram of an electronic device 20 provided by an embodiment of this application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the data reading method disclosed in any of the previous embodiments.

[0102] In this embodiment, the power supply 23 is used to provide operating voltages for the various hardware devices on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and no specific limitation is imposed thereon herein; the input / output interface 25 is used to obtain external input data or output data to the outside world, and the specific interface type thereof can be selected according to specific application requirements, and no specific limitation is imposed herein.

[0103] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, a random access memory, a magnetic disk, an optical disk, etc. The resources stored thereon can include an operating system 221, a computer program 222, data 223, etc., and the data 223 can include various kinds of data. The storage method can be transient storage or permanent storage.

[0104] Among them, the operating system 221 is used to manage and control the various hardware devices and the computer program 222 on the electronic device 20, and it can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the data reading method executed by the electronic device 20 disclosed in any of the foregoing embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

[0105] Furthermore, the embodiment of this application also discloses a computer-readable storage medium. The computer-readable storage medium mentioned here includes a random access memory (RAM), an internal memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a magnetic disk, an optical disk, or any other form of storage medium well-known in the technical field. Among them, when the computer program is executed by a processor, the foregoing data reading method is implemented. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details are not described herein again.

[0106] In this specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and reference can be made to the description of the method part for related parts.

[0107] The steps of the data reading method or algorithm described in combination with the embodiments disclosed in this article can be implemented directly by hardware, software modules executed by a processor, or a combination of both. The software module can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.

[0108] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0109] The above has introduced in detail a read acceleration device, a data reading method, a communication system, a device and a medium provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A read acceleration device, characterized in that, Comprising: A judgment module, configured to judge whether a read request sent by a bus master device hits a first-in-first-out queue storage module, so as to generate a corresponding hit status signal; The first-in-first-out queue storage module is configured to store read data information returned by a bus slave device according to the read request, and return the read data information to the bus master device according to the hit status signal; A replacement arbitration module, configured to determine target read data information from the first-in-first-out queue storage module, and replace the target read data information according to the hit status signal; the target read data information is read data information whose usage times within a preset time period do not meet a preset usage condition.

2. The read acceleration device according to claim 1, wherein Further comprising: A device interface module, configured to transmit the read request and the read data information between the bus master device and the bus slave device; A command queue module, configured to identify and store read requests sent by different bus master devices respectively; A polling arbitration module, configured to poll the command queue module according to a pre-configured arbitration weight, so as to provide command queue information for current access.

3. The read acceleration device according to claim 2, wherein Further comprising: A lookup table module, configured to store data information corresponding to the first-in-first-out queue storage module; the data information includes a start address, an end address, and an effective data volume corresponding to each read data information; wherein, the start address is the start address of the read request, the end address is the sum of the start address and the effective data volume, and the effective data volume is the product of the data width and the data length of the Advanced Extensible Interface bus; A lookup table update module, configured to, when the hit status signal is a first status signal indicating a miss, update the lookup table module according to the replaced first-in-first-out queue storage module after replacing the target read data information by using the replacement arbitration module.

4. The read acceleration device according to claim 3, wherein The judgment module further comprises: A prefetch operation unit, configured to perform a prefetch operation on the bus slave device based on a preset data length and a preset data width when the data volume stored in the first-in-first-out queue storage module is less than a preset threshold; wherein, the prefetch address corresponding to the prefetch operation is equal to the current end address in the lookup table module.

5. The read acceleration device according to claim 3, wherein, The judgment module is specifically configured to: Determine a current read request, and judge whether there is a corresponding relationship between the read address information of the current read request in the command queue module and the data information in the lookup table module; If there is no corresponding relationship between the read address information and the data information in the lookup table module, it is determined that the current read request misses the first-in-first-out queue storage module, and a first status signal indicating a miss is generated; If there is a corresponding relationship between the read address information and the data information in the lookup table module, it is determined that the current read request hits the first-in-first-out queue storage module, and a second status signal indicating a hit is generated.

6. The read acceleration device according to claim 5, wherein, The replacement arbitration module is specifically configured to: When the hit status signal is the first status signal, send the current read request in the command queue module to the bus slave device; Obtain the current read data information returned by the bus slave device according to the current read request, and determine the target read data information from the first-in-first-out queue storage module; Replace the target read data information with the current read data information, and send the current read data information to the bus master device.

7. A data reading method, characterized in that, Applied to the read acceleration device according to any one of claims 1 to 6, comprising: Obtain the read request sent by the bus master device, and determine whether the read request hits the first-in-first-out queue storage module in the read acceleration device to generate a corresponding hit status signal; Store the read data information returned by the bus slave device according to the read request through the first-in-first-out queue storage module, and return the read data information to the bus master device according to the hit status signal; Determine the target read data information from the first-in-first-out queue storage module, and replace the target read data information according to the hit status signal; the target read data information is the read data information whose usage times do not meet the preset usage conditions within a preset time period.

8. A communication system, characterized in that, Comprising: A bus master device, configured to send a read request to a bus slave device, and receive the read data information returned by the bus slave device through a read acceleration device; The bus slave device is configured to return corresponding read data information to the read acceleration device according to the read request sent by the bus master device; The read acceleration device is configured to determine whether the read request sent by the bus master device hits the first-in-first-out queue storage module to generate a corresponding hit status signal; store the read data information returned by the bus slave device according to the read request through the first-in-first-out queue storage module, and return the read data information to the bus master device according to the hit status signal; Determine the target read data information from the first-in-first-out queue storage module, and replace the target read data information according to the hit status signal; the target read data information is the read data information whose usage times do not meet the preset usage conditions within a preset time period.

9. An electronic device, characterized in that, The electronic device includes a processor and a memory; wherein, the memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the data reading method according to claim 7.

10. A computer-readable storage medium, characterized in that, For storing a computer program; wherein the computer program, when executed by a processor, implements the data reading method according to claim 7.

Images