A chip based on a reconfigurable neuromorphic interconnect architecture

Abstract

The application discloses a chip based on a reconfigurable neuromorphic interconnection architecture, comprising a layered dynamic reconfigurable interconnection network layer and a memristor-CMOS reconfigurable interconnection unit, and the layered dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit are dynamically adjusted in a routing path through a dynamic routing algorithm. The application has the beneficial effects that: the dynamic routing algorithm is combined with the layered dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit, thereby performing dynamic prediction of network congestion and dynamic adjustment of a routing path, and the CMOS switch and the memristor switch are connected in parallel, avoiding the limitation of traditional single devices or static interconnections, so that the network performance and reliability are improved, and the delay and power consumption of data transmission are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a chip based on a reconfigurable neuromorphic interconnection architecture. BACKGROUND

[0002] With the rapid development of artificial intelligence technology, the traditional von Neumann architecture faces significant performance bottlenecks when processing computationally intensive tasks such as deep neural networks due to the separation of processor and memory. Studies have shown that when running typical deep learning models, data transfer power consumption can account for more than 50%, leading to low system efficiency, especially in edge computing scenarios where power consumption needs to be controlled below 1W. Neuromorphic computing attempts to break through the above limitations with low power consumption and high parallelism by drawing on the information processing mechanism of the human brain. However, existing neuromorphic chips mostly rely on a single interconnection topology or static switch units, facing problems such as limited bandwidth, high delay, and high power consumption, and lack of dynamic hierarchical communication and low-power high-speed switching, making it difficult to meet the stringent requirements of real-time and energy efficiency in edge computing. For example, in autonomous driving, the chip needs to complete complex perception and decision-making within milliseconds, while existing solutions often experience a sharp drop in efficiency when the number of neurons expands. Existing hierarchical interconnections are mostly static topologies, and the application of memristors is also limited to storage, none of which are optimized for neuromorphic computing pulse communication requirements, and there is no specific method for using memristors and CMOS in parallel for neuromorphic interconnection. SUMMARY

[0003] The present application aims to overcome the shortcomings of the prior art and provide a chip based on a reconfigurable neuromorphic interconnection architecture.

[0004] The purpose of the present application is achieved by the following technical solution: a chip based on a reconfigurable neuromorphic interconnection architecture, comprising a hierarchical dynamic reconfigurable interconnection network layer and a memristor-CMOS reconfigurable interconnection unit, the hierarchical dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit dynamically adjusting the routing path through a dynamic routing algorithm.

[0005] The hierarchical dynamic reconfigurable interconnection network layer is used for dynamic communication and cooperation between computing units in the chip.

[0006] The memristor-CMOS reconfigurable interconnection unit is composed of a memristor switch, a CMOS switch, and a control circuit. The memristor switch controls whether the current passes through by changing the resistance state, dynamically adjusting the interconnection path. The CMOS switch is connected in parallel with the memristor switch, and the control circuit is used to control the on-off of the memristor switch and the CMOS switch.

[0007] Preferably, the hierarchical dynamic reconfigurable interconnection network layer has a three-layer architecture, including an intra-neuron cluster interconnection layer, an inter-cluster interconnection layer, and a global reconfigurable interconnection layer.

[0008] The interconnection layer within the neuron cluster is the lowest layer, which is used for the interconnection within the neuron cluster;

[0009] The interconnection layer between clusters is the middle layer, which is used for the interconnection between different neuron clusters to establish a communication path;

[0010] The global reconfigurable interconnection layer is the topmost layer, which is used for the global interconnection of the entire chip to provide a cross-area communication path.

[0011] Preferably, the specific steps of dynamically adjusting the routing path based on the dynamic routing algorithm are as follows:

[0012] S1: Initialize all nodes and links, and set the initial routing table and congestion detection threshold;

[0013] S2: Collect real-time traffic data and link state information through sensors and monitoring points, and perform data cleaning and preprocessing;

[0014] S3: Analyze the data to predict the congested links that will occur in the future time period;

[0015] S4: According to the congestion prediction result, use the shortest path algorithm to select the optimal path,

[0016] dist[v]=min(dist[v],dist[u]+weight(u,v));

[0017] where dist[v] is the shortest distance from the source node to node v, and weight(u,v) is the link weight from node u to node v;

[0018] S5: Use the adaptive routing algorithm to dynamically adjust the routing path according to the current load of the link,

[0019] new_path=argpathminlink∈path∑load(link);

[0020] where load(link) is the current load of the link;

[0021] S6: When the network reaches a stable state and the load of all links is within the set range, output the final routing configuration, otherwise return to step S2 and continue to execute.

[0022] Preferably, in step S3, a bidirectional gated recurrent network is used for long sequence prediction,

[0023] htf=GRU(Xt,ht-1f)htb=GRU(Xt,ht+1b)ht=htf+htb;

[0024] Wherein, htf is the forward propagated hidden information, htb is the backward propagated hidden information, and ht is the final hidden state.

[0025] The application has the following advantages: the dynamic routing algorithm combines with the hierarchical dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit, thereby performing dynamic prediction of network congestion and dynamic adjustment of routing paths, and connecting the CMOS switch and the memristor switch in parallel, avoiding the limitation of traditional single device or static interconnection, thereby improving network performance and reliability, and reducing delay and power consumption of data transmission. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 Figure 1 is a schematic diagram of a three-layer topology of a hierarchical dynamic reconfigurable interconnection network layer;

[0027] Figure 2 Figure 2 is a schematic diagram of a circuit principle of a memristor-CMOS reconfigurable interconnection unit;

[0028] Figure 3 Figure 3 is a schematic diagram of a structure of a memristor material;

[0029] Figure 4 Figure 4 is a schematic diagram of a timing of a memristor-CMOS reconfigurable interconnection unit. DETAILED DESCRIPTION

[0030] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in connection with the drawings of the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.

[0031] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0032] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0033] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0034] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship commonly understood by those skilled in the art, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first", "second" and the like are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance.

[0035] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "arrangement", "installation", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0036] In the present embodiment, as shown in Figure 1 , Figure 2 and Figure 4 , a chip based on a reconfigurable neuromorphic interconnection architecture includes a layered dynamic reconfigurable interconnection network layer and a memristor-CMOS reconfigurable interconnection unit, and the layered dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit dynamically adjust the routing path through a dynamic routing algorithm.

[0037] The layered dynamic reconfigurable interconnection network layer is used for dynamic communication and cooperation of each computing unit in the chip.

[0038] The memristor-CMOS reconfigurable interconnection unit is composed of a memristor switch, a CMOS switch and a control circuit. The memristor switch controls whether the current passes through by changing the resistance state, dynamically adjusts the interconnection path, the CMOS switch is connected in parallel with the memristor switch, and a 5nm SiO2 isolation layer and a 10nm porous SiO2 layer are added. The porosity of the SiO2 layer is 20%, thereby reducing the capacitive coupling interference and local heat diffusion, and the control circuit is used for controlling the on-off of the memristor switch and the CMOS switch. Specifically, the memristor switch controls the passage of current through the change of its resistance state, thereby realizing dynamic adjustment of the interconnection path and logical operation; the CMOS switch is connected in parallel with the memristor switch, providing additional reliability guarantee, when the memristor switch fails or needs a backup path, the CMOS switch can serve as a backup path, ensuring the reliability of the interconnection, thereby avoiding the limitation of traditional single device or static interconnection, preferably, as shown in Figure 3 The memristor switch is a TiO2 memristor, and the gray matrix TiN, the black matrix TiO2 and the gray matrix TiN are stacked. The control circuit optimizes the working state of the memristor switch and the CMOS switch through dual-mode control, realizing the synergistic optimization of ultra-low power consumption and high-speed switching, i.e. the static power consumption is lower than 0.05μW, the dynamic switching frequency reaches 2GHz, and the unit area is less than 0.3μm 2 As shown in Figure 4 The X-axis is time and the Y-axis is amplitude. The PROG(1.5V, 100ns) and EN(0V / 1.2V, 2GHz) waveforms are plotted. The static mode PROG triggers low resistance, and the dynamic mode EN high-frequency switching. The dynamic routing algorithm combines with the hierarchical dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit, thereby dynamically predicting network congestion and dynamically adjusting the routing path. At the same time, the CMOS switch is connected in parallel with the memristor switch, avoiding the limitation of traditional single device or static interconnection, not only improving the network performance and reliability, but also reducing the delay and power consumption of data transmission. In this embodiment, the hierarchical dynamic reconfigurable interconnection network layer is used to provide a macro interconnection framework, and the memristor-CMOS reconfigurable interconnection unit is used to provide a micro interconnection framework. The dynamic routing algorithm avoids network congestion by dynamically adjusting the routing path, and the hierarchical dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit provide the hardware basis and interconnection architecture for realizing such dynamic adjustment. The hierarchical dynamic reconfigurable interconnection network layer provides a hierarchical interconnection architecture, supports dynamic reconfiguration, and provides a communication path for the routing adjustment of the dynamic routing algorithm. The memristor-CMOS reconfigurable interconnection unit serves as a basic building unit of the hierarchical dynamic reconfigurable interconnection network layer, and provides efficient interconnection and logical operation functions.

[0039] In this embodiment, the hierarchical dynamic reconfigurable interconnection network layer has a three-layer architecture, which is a neuron cluster interconnection layer, an inter-cluster interconnection layer and a global reconfigurable interconnection layer.

[0040] The intra-cluster interconnection layer is the lowest layer and is used for intra-cluster interconnection of the neuron cluster;

[0041] The inter-cluster interconnection layer is the middle layer and is used for interconnection between different neuron clusters to establish a communication path;

[0042] The global reconfigurable interconnection layer is the topmost layer and is used for global interconnection of the entire chip to provide a cross-area communication path. Specifically, the intra-cluster interconnection layer is responsible for intra-cluster interconnection of the neuron cluster to ensure that the neurons in the same cluster can quickly and efficiently communicate and exchange data, the inter-cluster interconnection layer is used for interconnection between different neuron clusters to establish a communication path, so that the neurons of different clusters can work cooperatively to support a complex neural network junction, that is, through path planning and load balancing strategies, efficient use of the communication path is ensured to avoid communication bottlenecks; the global reconfigurable interconnection layer is used for global interconnection of the entire chip to provide a cross-area communication path to support the communication needs of a large-scale neural network, and the global reconfigurable interconnection layer also supports a dynamic routing strategy, which can dynamically adjust the communication path according to real-time communication needs and network states to optimize communication efficiency. In this embodiment, the intra-cluster interconnection layer is a 16x16 crossbar matrix, the inter-cluster interconnection layer is a 64x64 grid topology, and the global reconfigurable interconnection layer is an 8x8 NoC with a bandwidth of 200 Mbps per channel.

[0043] In this embodiment, the specific steps of dynamically adjusting the routing path based on the dynamic routing algorithm are as follows:

[0044] S1: Initialize all nodes and links, and set an initial routing table and a congestion detection threshold;

[0045] S2: Collect real-time traffic data and link state information through sensors and monitoring points, and perform data cleaning and preprocessing; specifically, the main role of data cleaning and preprocessing is to remove noise and outliers.

[0046] S3: Analyze the data to predict the congested links that will occur in the future time period; further, a bidirectional gated recurrent network is used for long sequence prediction,

[0047] htf = GRU(Xt, ht-1f) htb = GRU(Xt, ht+1b) ht = htf + htb;

[0048] where htf is the forward-propagated hidden information, htb is the backward-propagated hidden information, and ht is the final hidden state.

[0049] S4: According to the congestion prediction result, use the shortest path algorithm to select the optimal path,

[0050] dist[v] = min(dist[v], dist[u] + weight(u, v));

[0051] wherein dist[v] is the shortest distance from the source node to node v, and weight(u, v) is the link weight from node u to node v;

[0052] S5: dynamically adjusting the routing path according to the current load of the link using the adaptive routing algorithm,

[0053] new_path = argpath min link∈path∑load(link);

[0054] wherein load(link) is the current load of the link;

[0055] S6: when the network reaches a stable state and the load of all links is within the set range, output the final routing configuration, otherwise return to step S2 for continuous execution. Specifically, the dynamic routing algorithm, in combination with the hierarchical dynamic reconfigurable interconnection network layer and the memristor-CMOS reconfigurable interconnection unit, realizes the dynamic prediction of network congestion and the adaptive adjustment of the routing path, thereby improving the reliability of the network and significantly reducing the delay and power consumption of data transmission. Through the above algorithm steps, the dynamic routing algorithm can effectively avoid congestion in a complex network environment and ensure efficient data transmission.

[0056] Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can modify the technical solutions described in the foregoing embodiments or make equivalent replacements to some of the technical features, and any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A chip based on a reconfigurable neuromorphic interconnect architecture, characterized in that: It includes a hierarchical dynamically reconfigurable interconnect layer and a memristor-CMOS reconfigurable interconnect unit, wherein the hierarchical dynamically reconfigurable interconnect layer and the memristor-CMOS reconfigurable interconnect unit dynamically adjust the routing path through a dynamic routing algorithm; The layered, dynamically reconfigurable interconnect layer enables dynamic communication and collaboration among the computing units in the chip. The memristor-CMOS reconfigurable interconnect unit consists of a memristor switch, a CMOS switch, and a control circuit. The memristor switch controls whether current flows by changing the resistance state, thereby dynamically adjusting the interconnect path. The CMOS switch is connected in parallel with the memristor switch. The control circuit is used to control the on / off state of the memristor switch and the CMOS switch. The hierarchical dynamic reconfigurable interconnection layer has a three-layer architecture, namely, the intra-cluster interconnection layer, the inter-cluster interconnection layer, and the globally reconfigurable interconnection layer; The interconnection layer within the neuron cluster is the lowest layer and is used for interconnection within the neuron cluster. The inter-cluster interconnection layer is an intermediate layer used for interconnection between different neuron clusters and to establish communication paths. The globally reconfigurable interconnect layer is the top layer, used for global interconnection of the entire chip, providing communication paths across regions; The specific steps for dynamically adjusting the routing path based on the dynamic routing algorithm are as follows: S1: Initialize all nodes and links, and set the initial routing table and congestion detection threshold; S2: Collect real-time traffic data and link status information through sensors and monitoring points, and perform data cleaning and preprocessing; S3: Analyze the data to predict congested links in the future; S4: Based on the congestion prediction results, use the shortest path algorithm to select the optimal path. ； in, From source node to node The shortest distance, For nodes To the node Link weights; S5: Uses an adaptive routing algorithm to dynamically adjust the routing path based on the current load of the link. ； in, The current load on the link; S6: When the network reaches a stable state and the load of all links is within the set range, output the final routing configuration; otherwise, return to step S2 to continue execution.

2. The chip based on a reconfigurable neuromorphic interconnect architecture according to claim 1, characterized in that: In step S3, a bidirectional gated recurrent network is used for long sequence prediction. ； in, Implicit information propagated forward. This is the implicit information for backpropagation. This is the final implicit state.

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