Sparse matrix vector multiplication implementation method and system for Shenwei processor

Abstract

The invention relates to the technical field of computers, in particular to a Shenwei processor-oriented sparse matrix vector multiplication implementation method and system. The implementation method comprises the following steps: a task division step: acquiring an input sparse matrix, grouping matrix elements, and distributing the matrix elements to slave cores of a Shenwei processor; a memory allocation step: acquiring a coefficient vector, and configuring a storage space for storing the sparse matrix and the coefficient vector in a slave core memory based on the sparse matrix and the data transmission times in the coefficient vector; and a vector multiplication implementation step: performing data distribution based on the configured storage space, and executing vector multiplication operation. According to the method, the waiting time caused by data loading in the vector multiplication process is shortened to the maximum extent.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular, to a method and system for implementing sparse matrix-vector multiplication for the ShenWei processor. Background Art

[0002] Sparse Matrix-Vector Multiplication (SpMV) is considered to be one of the most important scientific and engineering computing methods in the past decade. In numerical simulation calculations of many applications, such as fluid dynamics simulation software (Openfoam) and medical imaging, etc., solving large-scale sparse matrix linear equations is usually encountered. Among them, the performance of the SpMV operation has a decisive impact on the entire linear equation solving process, and thus is directly related to the computing efficiency and performance of the entire application system. Therefore, the implementation and optimization of SpMV on various high-performance architectures have become a research hotspot, such as multi-core CPUs, GPUs, etc.

[0003] The CSR format (Compressed Sparse Row, CSR) is the current most popular sparse matrix storage method, which has the advantages of high storage efficiency, high arithmetic operation efficiency of sparse matrices, efficient row slicing, fast matrix-vector product operation, etc. The CSR storage format represents the values, column numbers, and row offsets through three arrays value 、 row_ptr 、 col_ind respectively, Value stores all non-zero elements, row_ind records the row indices corresponding to each non-zero element, col_ind stores the column indices of non-zero elements.

[0004] Since the number of non-zero elements in the sparse matrix is very small, and they are usually extremely irregularly distributed and have strong randomness, this data characteristic directly leads to the irregularity of the memory access process, restricting the exertion of the hardware vectorization ability. In addition, the irregular access pattern also causes a significant reduction in the cache hit rate, seriously restricting the overall floating-point computing performance. Summary of the Invention

[0005] Embodiments of this application provide a method and system for implementing sparse matrix-vector multiplication for the ShenWei processor, so as to at least solve the problem of irregularity in the memory access process or low cache hit rate in related technologies.

[0006] In a first aspect, embodiments of this application provide a method for implementing sparse matrix-vector multiplication for the ShenWei processor, including: A task partitioning step of obtaining the input sparse matrix A, grouping the matrix elements, and allocating them to the slave cores of the ShenWei processor; Memory allocation step, obtain a coefficient vector, and configure the storage space for storing the sparse matrix A and the coefficient vector X in the slave core memory based on the number of data transmissions in the sparse matrix A and the coefficient vector X; Vector multiplication implementation step, perform data allocation based on the configured storage space and execute vector multiplication operations.

[0007] In some embodiments, the memory allocation step further includes: Load the dynamic data of the coefficient vector through RMA access from the first memory of the sparse matrix stored in the slave core local memory LDM, the second memory storing the coefficient vector, and a remaining memory, and load the static data of the sparse matrix and the coefficient vector through DMA access for vector multiplication operations, and count the number of DMA accesses, the number of RMA accesses, and the corresponding single access time during the operation; Calculate the total running time based on the number of DMA accesses, the number of RMA accesses, and the corresponding single access time during the operation, and configure the first memory, the second memory, and the remaining memory with the minimum total running time as the goal. The remaining memory is used to store code and other variables. The sparse matrix includes non-zero element values , the column indices of non-zero elements and the number of non-zero elements at the starting position of the current row , the coefficient vector includes static data and dynamic data .

[0008] Based on the above algorithm, load the coefficient vector corresponding to the non-zero elements through RMA access or DMA access for sparse matrix vector multiplication calculation to generate a result vector. Use an RMA counter to increment and count the number of RMA accesses, use a DMA counter to increment and count the number of DMA accesses, and calculate the total running time. In the embodiments of the present application, the configuration ratio of the first memory, the second memory, and the remaining memory is optimized with the minimum total running time as the goal to minimize the waiting time caused by data loading during vector multiplication.

[0009] In some embodiments, the memory allocation step further includes a coefficient vector allocation step: Configure the second memory space to include a static buffer and a dynamic buffer; After equally dividing the static data according to the number of slave cores used, store them in the static buffer in sequence according to the slave core order; The dynamic buffer is configured to include 8 data blocks, and each data block stores 128 dynamic data.

[0010] In some embodiments, the vector multiplication implementation step further includes: Configuring a temporary buffer T1 and a protection buffer T2 from the nuclear local memory LDM, The temporary buffer T1 is used to store data blocks with an access count of 1 and their subscripts. When the access count of a data block in the temporary buffer T1 is greater than 1, it is considered likely to become a frequently accessed data block. The subscript and access count of the data block are stored in a temporary linked list B1, and the subscript of the data block with the maximum access count in the temporary linked list B1 is recorded, so as to save the metadata information of the data blocks eliminated from the temporary buffer T1 to the temporary linked list B1; The protection buffer T2 is used to store data blocks with an access count of at least 2. The sizes of the temporary buffer and the protection buffer are dynamically adjusted according to the load performance to adapt to the cache pressure in different computing stages.

[0011] In some embodiments, when the protection buffer T2 is not full, the data block with the maximum access count in the temporary linked list B1 is stored in the protection buffer T2.

[0012] In some embodiments, when the protection buffer T2 is full, the maximum access count B1_max of the data blocks in the temporary linked list B1 and the minimum access count T2_min of the data blocks in the protection buffer T2 are judged. The subscript of the data block with a larger access count is stored in the protection buffer T2, and the subscript of the data block with a smaller access count is stored in a protection linked list B2, that is, the metadata information of the data blocks eliminated from the protection buffer T2 is saved to the protection linked list B2.

[0013] In some embodiments, if the maximum access count B2_max in the protection linked list B2 is greater than the minimum access count T2_min in the protection buffer T2, the corresponding data block subscripts of the two are exchanged, that is, the subscript of the data block with a larger access count is stored in the protection buffer T2, and the subscript of the data block with a smaller access count is eliminated to the protection linked list B2. The cache distribution is corrected through the swap operation to ensure that the data block with a larger access count returns to the protection buffer T2, prevent long-term low-frequency data blocks from occupying the cache space, avoid repeatedly loading data from the remote core group, enable the cache to dynamically adapt to the changing trend of hot data, and improve the hit rate.

[0014] In some embodiments, the matrix elements are grouped based on a first constraint condition, denoted as m the total number of matrix elements, the number of rows of the matrix, the number of columns of the matrix, the number of elements in the th row, the number of rows calculated by the th slave core of the Shenwei processor. The first constraint condition is configured as: When then For 。

[0015] Based on this, after the allocation, the number of matrix rows executed by each slave core is basically the same. After the element allocation of the first 63 slave cores is completed, all the remaining elements are handed over to the last slave core for calculation and processing, which can effectively avoid the problem of uneven load caused by too large a difference in the number of row elements in equal-row allocation.

[0016] In a second aspect, an embodiment of the present application provides a sparse matrix-vector multiplication implementation system for a ShenWei processor, which is used to implement the sparse matrix-vector multiplication implementation method described in the first aspect above, including: A task division unit, which obtains the input sparse matrix A, groups the matrix elements and allocates them to the slave cores of the ShenWei processor; A memory allocation unit, which obtains the coefficient vector and configures the storage space for storing the sparse matrix A and the coefficient vector in the slave core memory based on the number of data transmission times in the sparse matrix A and the coefficient vector X; A vector multiplication implementation unit, which performs data allocation based on the configured storage space and executes the vector multiplication operation.

[0017] In some of these embodiments, the memory allocation unit further includes a coefficient vector allocation unit.

[0018] The details of one or more embodiments of the present application are set forth in the following drawings and description, so that the other features, objects, and advantages of the present application become more concise and understandable. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the drawings: Figure 1 is a flowchart of the sparse matrix-vector multiplication implementation method according to an embodiment of the present application; Figure 2 is a step-by-step flowchart of the sparse matrix-vector multiplication implementation method according to an embodiment of the present application; Figure 3 is a schematic diagram of the principle of the memory allocation step according to an embodiment of the present application; Figure 4 is a schematic diagram of the principle of the coefficient vector allocation step according to an embodiment of the present application; Figure 5 is a schematic diagram of the configuration principle of configuring the temporary buffer T1 and the protection buffer T2 according to an embodiment of the present application; Figure 6 is a block diagram of the structure of the sparse matrix-vector multiplication implementation system for a ShenWei processor according to an embodiment of the present application.

[0020] In the figure: 1. Task division unit; 2. Memory allocation unit; 201. Coefficient vector allocation unit; 3. Vector multiplication implementation unit. Specific implementation manners

[0021] In order to make the objectives, technical solutions and advantages of the present application more clear and understandable, the present application will be described and explained below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided in the present application without creative efforts belong to the scope of protection of the present application.

[0022] Obviously, the accompanying drawings in the following description are only some examples or embodiments of the present application. For those of ordinary skill in the art, without creative efforts, the present application can also be applied to other similar scenarios based on these drawings. In addition, it can also be understood that although the efforts made in this development process may be complex and lengthy, for those of ordinary skill in the art related to the content disclosed in the present application, some design, manufacturing or production changes made on the basis of the technical content disclosed in the present application are only conventional technical means and should not be understood that the content disclosed in the present application is insufficient.

[0023] Referring to "embodiments" in the present application means that specific features, structures or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase appears in various positions in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those of ordinary skill in the art explicitly and implicitly understand that the embodiments described in the present application can be combined with other embodiments without conflict.

[0024] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the ordinary meanings understood by those of ordinary skill in the technical field to which this application pertains. The words such as "a", "an", "one", "the" and the like involved in this application do not denote a limitation of quantity and may represent singular or plural. The terms "comprise", "include", "have" and any variations thereof involved in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may further include unlisted steps or units, or may further include other steps or units inherent to these processes, methods, products or devices. The words such as "connect", "be connected", "couple" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "plurality" involved in this application means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, "A and / or B" may represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after. The terms "first", "second", "third" and the like involved in this application are only used to distinguish similar objects and do not represent a specific order for the objects.

[0025] The SW-64 multi-core processor is composed of general computing master cores and streamlined computing slave cores, and has high fixed-point and floating-point peak performance and high practical application performance. The SW-64 multi-core processor integrates 6 core groups, each core group includes 1 master core and one slave core array, and 1 slave core array contains 64 slave cores; two system interfaces are integrated on the chip, and the above main components are connected through a ring network.

[0026] During program operation, the main process runs on the MPE. The MPE is essentially a general-purpose processor, and the complex computing part can be assigned to the CPE. Each CPE is a lightweight core and executes a single thread. The slave cores of the SW-64 multi-core chip are managed in units of slave core arrays arranged in an 8x8 array. The interaction between slave cores and outside the slave cores is interconnected through the in-array network. A group of fast scratchpad memories called LDM (Local Data Memory) are embedded in each CPE core and provide users with explicit control over data locality. 64 CPE cores are arranged in an 8*8 grid and are connected through row / column and signal / data buses. The MPE shares the main memory with all CPEs in a CG, but when loading / storing continuous data blocks through the DMA (Direct Memory Access) mechanism, the entire set of CPEs can maintain a much higher aggregate bandwidth than the MPE.

[0027] The access speed of the slave core memory LDM of the Shenwei processor is very fast, equivalent to a cache, which can be completed in several clock cycles, while it takes more than 200 clock cycles for the slave core to access the master core. To achieve communication within the core group, the Shenwei processor designs two interfaces, namely the DMA communication method (Direct Memory Access, DMA) and the RMA communication method (Random Access Memory, RMA). The communication between the slave core and the master core adopts the DMA method, and the communication method between the slave cores is the RMA method.

[0028] In the sparse matrix-vector multiplication SpMV (Sparse Matrix-vector Multiplication), since the number of non-zero elements in the sparse matrix is very small, in order to effectively save storage space and reduce operation time. Currently, sparse matrices are usually stored in a compressed manner. In short, only non-zero elements are stored, and the sparse matrix of this application is stored in CSR format.

[0029] This embodiment provides a method for implementing sparse matrix-vector multiplication for the Shenwei processor. Figure 1 - Figure 2 It is a flowchart of the method for implementing sparse matrix-vector multiplication for the Shenwei processor according to the embodiments of the present application, as Figures 1 to 2 shown, and the process includes the following steps: Task division step S1, obtaining the input sparse matrix A, grouping the matrix elements and allocating them to the slave cores of the Shenwei processor; Memory allocation step S2, obtaining the coefficient vector, and configuring the storage space for storing the sparse matrix A and the coefficient vector X in the slave core memory based on the number of data transmission times in the sparse matrix A and the coefficient vector X; Vector multiplication implementation step S3, performing data allocation based on the configured storage space and executing vector multiplication operations.

[0030] Based on the above steps, the embodiments of the present application balance the load of the slave cores by reasonably dividing tasks and allocating them to the slave cores, and optimize the memory structure, configure the local memory space in the slave cores to minimize data reading across slave cores or within slave cores, and reduce the data transmission bottleneck.

[0031] In some of the embodiments, the memory allocation step S2 further includes: The first memory of the sparse matrix stored in the slave core local memory LDM, the second memory for storing the coefficient vector, and a remaining memory, loading the dynamic data of the coefficient vector through RMA access, and loading the static data of the sparse matrix and the coefficient vector through DMA access for vector multiplication operations, and counting the number of DMA accesses, the number of RMA accesses and the corresponding single access time during the operation process; The total running time is calculated based on the number of DMA accesses, the number of RMA accesses, and the corresponding single - access time during the operation process, and the first memory, the second memory, and the remaining memory are configured with the goal of minimizing the total running time. The remaining memory is used to store code and other variables, and the sparse matrix includes non - zero element values , the column indices of the non - zero elements , and the number of non - zero elements at the starting position of the current row . The coefficient vector includes static data and dynamic data ; Specifically, the vector multiplication operation process refers to the following pseudo - code example:

[0032] Based on the above algorithm, the coefficient vectors corresponding to non - zero elements are loaded through RMA access or DMA access for sparse matrix - vector multiplication calculation to generate a result vector. An RMA counter is incremented to count the number of RMA accesses, and a DMA counter is incremented to count the number of DMA accesses, and the total running time is calculated T time . In the embodiment of the present application, the configuration ratios of the first memory, the second memory, and the remaining memory are optimized with the goal of the minimum total running time to minimize the waiting time caused by data loading during the vector multiplication process.

[0033] In one embodiment, after testing, the first memory is configured as 56.25% of the slave - core local memory LDM space to store the data of the sparse matrix, the second memory is configured as 28.125% of the slave - core local memory LDM storage space to store the coefficient vector, and the remaining memory is configured as 15.625% of the slave - core local memory space to store code and other variables, and the total running time is the shortest and the effect is the best.

[0034] When the scale of the sparse matrix is large, considering that the coefficient vector generally requires a large storage space, and the slave - core local memory is limited, there may be a situation where the current coefficient vector cannot be stored. Therefore, in the embodiment of the present application, the coefficient vector is allocated according to the number of slave - cores used. Specifically: In some of the embodiments, the memory allocation step S2 further includes a coefficient vector allocation step S201: The second memory space is configured to include a static buffer and a dynamic buffer; As Figure 4 shown, after the static data is equally divided according to the number of slave - cores used, such as C0 to C63, it is sequentially stored in the static buffer according to the slave - core order, starting from the LDM of slave - core No. 0, C0. After the storage is completed, if there is remaining space in the static buffer, the subsequent vector data is continued to be stored; The dynamic buffer is configured to include 8 data blocks, and each data block stores 128 pieces of dynamic data. The dynamic buffer is divided into a private segment, a continuous shared segment, and a Cache.

[0035] Based on the above coefficient vector allocation step S201, each slave core stores the coefficient vector in a double-buffer mode, that is, it is divided into static data and dynamic data. Based on this, when performing a vector multiplication operation, if the coefficient vector required by the current slave core is stored in the current slave core, it can be directly loaded. If it is in other slave cores, the slave core to which the required coefficient belongs is determined by the matrix subscript of the current non-zero element, and it is loaded from the corresponding slave core through RMA access, as Figure 4 shown, which improves the hit rate of x and reduces the time complexity. The double-buffer strategy combines static allocation and dynamic access, effectively improving the hit rate and timeliness of vector access. Compared with the traditional centralized vector storage and unified scheduling mechanism, this method can better adapt to the calculation scenarios where the sparse matrix elements are unevenly distributed and the coefficient vector hotspots change frequently, thereby reducing the overall calculation latency and communication load, and improving the overall throughput performance of the vector multiplication operation.

[0036] In other possible embodiments, the number of data blocks and the single-block capacity of the dynamic buffer can be dynamically adjusted according to the application scenario. For example, the number of blocks can be adjusted from 8 to 16 or 32, or the number of dynamic data stored in each block can be set to variants such as 64 or 256 to adapt to different data access modes.

[0037] Furthermore, when accessing data during the operation process and the data to be accessed is not in the current slave core, that is, in the case of a miss, it is necessary to access other slave cores to obtain the data. Therefore, the number of communication accesses will increase and the calculation performance will decrease. Therefore, it is necessary to further increase the hit rate and reduce the communication with other slave cores.

[0038] In some of these embodiments, the vector multiplication implementation step S3 further includes: Configure a temporary buffer T1 and a protection buffer T2 in the local memory LDM of the slave core, and its principle is as Figure 5 shown, The temporary buffer T1 is used to store the data blocks and their subscripts with an access count of 1. When the access count of the data blocks in the temporary buffer T1 is greater than 1, it is considered that they may become frequently accessed data blocks. The subscripts and access counts of the data blocks are stored in a temporary linked list B1, and the subscript of the data block with the maximum access count in the temporary linked list B1 is recorded, so as to save the metadata information of the data blocks eliminated from the temporary buffer T1 into the temporary linked list B1; The protection buffer T2 is used to store data blocks with an access count of at least 2 times. The sizes of the temporary buffer and the protection buffer are dynamically adjusted according to the load performance to adapt to the cache pressure in different computing stages.

[0039] In some of these embodiments, when the protection buffer T2 is not full, the data block with the maximum access count in the temporary linked list B1 is stored in the protection buffer T2.

[0040] In some of these embodiments, when the protection buffer T2 is full, the maximum access count B1_max of the data blocks in the temporary linked list B1 and the minimum access count T2_min of the data blocks in the protection buffer T2 are judged. The subscript of the data block with a larger access count is stored in the protection buffer T2, and the subscript of the data block with a smaller access count is stored in a protection linked list B2, that is, the metadata information to be eliminated from the protection buffer T2 is saved to the protection linked list B2.

[0041] In some of these embodiments, if the maximum access count B2_max in the protection linked list B2 is greater than the minimum access count T2_min in the protection buffer T2, the corresponding data block subscripts of the two are exchanged, that is, the subscript of the data block with a larger access count is stored in the protection buffer T2, and the subscript of the data block with a smaller access count is eliminated to the protection linked list B2. The cache distribution is corrected through the swap operation to ensure that the data block with a larger access count returns to the protection buffer T2, prevent long-term low-frequency data blocks from occupying the cache space, avoid repeatedly loading data from the remote core group, enable the cache to dynamically adapt to the changing trend of hot data, and improve the hit rate.

[0042] Specifically, the adjustment process of the temporary buffer T1 and the protection buffer T2 refers to the following pseudo-code example:

[0043] Based on the above steps, the present application realizes the dynamic management of the data block distribution in the slave-core local memory LDM, optimizes the cache hit rate, reduces the latency of remote memory access between core groups. The data blocks frequently accessed in sparse computing can stay resident for a long time. The data blocks that have not been recorded by any cache partition are added to the end of the temporary buffer T1 as newly accessed blocks. The history of the eliminated data blocks is tracked through the temporary linked list B1 and the protection linked list B2 to quickly identify newly frequently accessed data blocks or eliminate long-term low-frequency data blocks, and adaptively adjust the sizes of the temporary buffer T1 and the protection buffer T2. During the operation process, the vector element blocks frequently accessed (such as near the diagonal) will enter the protection buffer T2, and the sparse region blocks will be eliminated to the temporary linked list B1 and the protection linked list B2, constructing a multi-level cache management strategy driven by access heat, effectively avoiding the elimination of frequently used data blocks, and being used to optimize the access efficiency of the coefficient vector in the vector multiplication operation of the slave-core, thereby reducing the number of RMA accesses between core groups and reducing the total running time.

[0044] In some of these embodiments, considering that each computing core group of the Shenwei processor includes 1 main core and 64 slave cores, in order to make the number of elements calculated by each slave core uniform and achieve load balancing for sparse matrices with irregular structures, the matrix elements are grouped based on the first constraint condition. Denote m as the total number of matrix elements, as the number of rows of the matrix, as the number of columns of the matrix, as the number of elements in the th row, as the number of elements in the th row, as the number of rows calculated by the th slave core of the Shenwei processor. The first constraint condition is configured as: When then is .

[0045] Based on this, the number of matrix rows executed by each slave core after allocation is basically the same. After the element allocation for the first 63 slave cores is completed, the remaining elements are all handed over to the last slave core for calculation and processing, which can effectively avoid the problem of load imbalance caused by too large a difference in the number of row elements in equal-row allocation.

[0046] It should be noted that the steps shown in the above process or the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0047] This embodiment also provides a system for implementing sparse matrix-vector multiplication for the Shenwei processor. This system is used to implement the above embodiments and preferred implementation manners, and those that have been described will not be repeated. As used below, terms such as "module", "unit", "sub-unit", etc. can be a combination of software and / or hardware that can achieve a predetermined function. Although the systems described in the following embodiments are preferably implemented in software, implementations in hardware, or a combination of software and hardware are also possible and contemplated.

[0048] Figure 6 is a structural block diagram of a system for implementing sparse matrix-vector multiplication for the Shenwei processor according to an embodiment of the present application. As Figure 6 shown, the system includes: A task division unit that acquires the input sparse matrix A, groups the matrix elements, and allocates them to the slave cores of the Shenwei processor; A memory allocation unit obtains a coefficient vector and configures the storage spaces for storing the sparse matrix A and the coefficient vector in the slave core memory based on the number of data transmissions in the sparse matrix A and the coefficient vector X. A vector multiplication implementation unit performs data allocation based on the configured storage spaces and executes vector multiplication operations.

[0049] In some embodiments, the memory allocation unit further includes a coefficient vector allocation unit.

[0050] It should be noted that the above-mentioned modules can be functional modules or program modules, and can be implemented either by software or by hardware. For the modules implemented by hardware, the above-mentioned modules can be located in the same processor; or the above-mentioned modules can also be located in different processors in any combined form.

[0051] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0052] The above embodiments only represent several implementation manners of the present application, and the description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for implementing sparse matrix-vector multiplication for Shenwei processors, characterized in that, Including: A task division step, which obtains the input sparse matrix, groups the matrix elements and allocates them to the slave cores of the SW processor; A memory allocation step, which obtains the coefficient vector and configures the storage spaces for storing the sparse matrix and the coefficient vector in the slave core memory based on the data transfer times in the sparse matrix and the coefficient vector; A vector multiplication implementation step, which performs data allocation based on the configured storage space and executes the vector multiplication operation.

2. The method for implementing sparse matrix-vector multiplication for the ShenWei processor according to claim 1, wherein The memory allocation step further includes: The first memory for storing the sparse matrix, the second memory for storing the coefficient vector, and a remaining memory in the local memory LDM of the slave core. Dynamically load the data of the coefficient vector through RMA access, and statically load the sparse matrix and the coefficient vector through DMA access for vector multiplication operation, and count the DMA access times, RMA access times and the corresponding single access time during the operation process; Calculate the total running time based on the DMA access times, RMA access times and the corresponding single access time during the operation process, and configure the first memory, the second memory and the remaining memory with the goal of minimizing the total running time.

3. The method for implementing sparse matrix-vector multiplication for the ShenWei processor according to claim 2, wherein The memory allocation step further includes a coefficient vector allocation step: Configure the second memory space to include a static buffer and a dynamic buffer; Divide the static data equally according to the number of slave cores used, and store them in the static buffer in sequence according to the slave core order; The dynamic buffer is configured to include 8 data blocks, and each data block stores 128 dynamic data.

4. The method for implementing sparse matrix-vector multiplication for the ShenWei processor according to claim 3, wherein The vector multiplication implementation step further includes: Configure a temporary buffer and a protection buffer in the local memory LDM of the slave core, The temporary buffer is used to store the data blocks with 1 access time and their subscripts. When the access times of the data blocks in the temporary buffer are greater than 1, store the subscripts and access times of the data blocks in a temporary linked list; The protection buffer is used to store the data blocks with at least 2 access times.

5. The method for implementing sparse matrix-vector multiplication for the ShenWei processor according to claim 4, wherein When the protection buffer is not full, store the data block with the maximum access times in the temporary linked list into the protection buffer.

6. The method for implementing sparse matrix-vector multiplication for the ShenWei processor according to claim 5, wherein When the protection buffer is full, judge the maximum access times of the data blocks in the temporary linked list and the minimum access times of the data blocks in the protection buffer, store the subscripts of the data blocks with greater access times in the protection buffer, and store the subscripts of the data blocks with smaller access times in a protection linked list.

7. The method for implementing sparse matrix-vector multiplication for the ShenWei processor according to claim 6, wherein If the maximum access times in the protection linked list are greater than the minimum access times in the protection buffer, perform a swap operation on the corresponding data block subscripts of the two.

8. The method for implementing sparse matrix-vector multiplication for the SW processor according to claim 1, wherein Group the matrix elements based on the first constraint condition, denoted as m the total number of matrix elements, the number of rows of the matrix, the number of columns of the matrix, the number of elements in the th row, the number of rows calculated by the th slave core of the SW processor, and the first constraint condition is configured as: When then is .

9. A sparse matrix-vector multiplication implementation system for the ShenWei processor, characterized in that Used to implement the sparse matrix vector multiplication implementation method according to any one of claims 1 to 8, including: A task division unit, which obtains the input sparse matrix, groups the matrix elements and allocates them to the slave cores of the SW processor; A memory allocation unit, which obtains the coefficient vector and configures the storage spaces for storing the sparse matrix and the coefficient vector in the slave core memory based on the data transfer times in the sparse matrix and the coefficient vector; A vector multiplication implementation unit, which performs data allocation based on the configured storage space and executes the vector multiplication operation.

10. The sparse matrix-vector multiplication implementation system for the ShenWei processor according to claim 9, wherein The memory allocation unit further includes a coefficient vector allocation unit.

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