Module-level simulation test method and device, electronic equipment and storage medium
By performing static timing analysis of netlist data and timing data, the target time difference is calculated and the data signal arrival time is corrected, the problem of time-consuming and inaccurate module-level simulation testing of netlist strap timing simulation is solved, and efficient and accurate chip design verification is achieved.
Patent Information
- Application Number
- CN202510489792.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-18
- Publication Date
- 2025-07-25
AI Technical Summary
The existing mesh band timing simulation tests take too long in complex chip designs, have limited resources, and module-level simulation tests are difficult to accurately perform, resulting in an increase in the number of iterations of chip design and extending the time to market.
By static timing analysis of the netlist data and timing data of the module to be tested, the first time difference and the second time difference between the driving interface are calculated, the target time difference is determined, and the netlist data is simulated and tested based on this to correct the arrival time of the data signal to ensure synchronization with the clock signal.
The module-level simulation test is successful, which avoids sampling errors caused by timing misalignment, ensures that the signal is stable in the clock effective window, improves the efficiency and accuracy of simulation tests, and supports optimization of timing characteristics of different driver interfaces.
Smart Images
Figure CN120373219A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data processing, and in particular to a module-level simulation test method, apparatus, electronic device, and storage medium. Background Art
[0002] Chip netlist timing simulation test is a key step in the chip development process, and its purpose is to ensure that the chip can work as expected in the actual hardware environment. In the highly competitive semiconductor industry, the competition between enterprises is very fierce. The speed of product listing may directly affect the position of an enterprise in the market. Therefore, once the design is finalized and manufacturing begins, the netlist simulation test must be carried out quickly to ensure that the product can be launched as soon as possible. Chip manufacturing is an expensive process, and delays at each stage will result in additional costs. If the netlist simulation test takes too long, it may cause the entire project to exceed the budget. Therefore, accelerating the test is the key to cost savings. However, as chip designs become increasingly complex, the difficulty of netlist simulation testing is also increasing. The number of functional and performance points that engineers need to test is growing exponentially, which requires more tests to be completed within a limited time. However, compared with RTL testing (a simulation test method), netlist timing simulation testing usually requires a large amount of resources, including the time of test engineers, hardware emulators, test equipment, and laboratory resources. The limited resources also exacerbate the time pressure. The larger the design scale, the more simulation resources are occupied, and the slower the simulation speed. Once a problem is found during the netlist timing test, it is necessary to return to the design stage for correction and then verify again. This process may require multiple iterations, and each iteration takes time, which increases the sense of urgency of time. Therefore, it is particularly important to find a method to accelerate the netlist simulation test.
[0003] Currently, module-level simulation testing of the netlist is usually carried out to accelerate the simulation testing of the netlist. However, it is quite tricky to perform accurate module-level simulation testing. Since the netlist contains numerous interfaces, after the netlist is backannotated with timing, there are different delays between different signals from different interfaces to the registers. For example, the delay of the clock signal to a certain register is different from the delay of other data signals passing through some combinational logic to this register. If the simulation test is carried out in a way that aligns the rising edge of the clock with the driving signal, the next-level register cannot receive a valid signal, resulting in the failure of the module-level simulation test. Summary of the Invention
[0004] This application provides a module-level simulation test method, apparatus, electronic device, and storage medium.
[0005] In one aspect, an embodiment of this application provides a module-level simulation test method, and the method includes:
[0006] Obtain the netlist data and timing data of the module to be tested;
[0007] Perform static timing analysis on the module to be tested based on the netlist data and the timing data to obtain a first time difference and a second time difference of at least one driving interface, where the first time difference represents the time from the generation of the clock signal of the module to be tested to its transmission to the first register, and the second time difference represents the time from the generation of the data signal of the corresponding driving interface to its transmission to the register;
[0008] Determine the target time difference of the driving interface based on the second time difference corresponding to the driving interface and the first time difference;
[0009] Perform a simulation test on the netlist data of the module to be tested based on the target time differences of the at least one driving interface.
[0010] Among them, the determining the target time difference of the driving interface based on the second time difference corresponding to the driving interface and the first time difference includes:
[0011] Obtain a third time difference, where the third time difference is the setup time of the register;
[0012] Determine the target time difference of the driving interface based on the second time difference corresponding to the driving interface, the first time difference, and the third time difference.
[0013] Among them, the determining the target time difference of the driving interface based on the second time difference, the first time difference, and the third time difference of the driving interface includes:
[0014] If it is determined that the second time difference of the driving interface is greater than the first time difference, then determine the difference between the second time difference and the first time difference;
[0015] Determine the sum of the difference and the third time difference as the target time difference of the driving interface.
[0016] Among them, the determining the target time difference of the driving interface based on the second time difference, the first time difference, and the third time difference of the driving interface includes:
[0017] If it is determined that the second time difference of the driving interface is less than the first time difference, then determine the third time difference as the target time difference of the driving interface.
[0018] Among them, the method further includes:
[0019] Obtain a waveform diagram, where the waveform diagram is obtained after performing a simulation test on the netlist data of the module to be tested;
[0020] If it is determined based on the waveform diagram that the data signal read by the drive interface is unstable, the time for the drive interface to read the data signal is corrected so that the drive interface reads a stable data signal;
[0021] The netlist data of the module under test is simulated and tested again based on the target time difference of the at least one drive interface.
[0022] Among them, the correction of the time for the drive interface to read the data signal based on the fourth time difference includes:
[0023] Determine the fourth time difference based on the waveform diagram;
[0024] Create a corrected clock signal, which is obtained by delaying the clock signal by the fourth time difference, and the corrected clock signal is used to make the drive interface read the data signal after the fourth time difference at the rising edge of the clock signal.
[0025] Among them, the correction of the time for the drive interface to read the data signal based on the fourth time difference includes:
[0026] Determine that the first signal changes from low level to high level, and after one clock signal cycle, switch the second signal from low level to high level, so that the drive interface reads the data signal at the first rising edge of the clock signal after determining that both the first signal and the second signal are high level. When the first signal is high level, it indicates that the data signal can be read.
[0027] Another aspect of the embodiments of the present application provides a module-level simulation test device, and the device includes:
[0028] An acquisition module, configured to obtain the netlist data and timing data of the module under test;
[0029] A calculation module, configured to perform static timing analysis on the module under test based on the netlist data and the timing data to obtain a first time difference and a second time difference of at least one drive interface. The first time difference represents the time from the generation of the clock signal of the module under test to its transmission to the first register, and the second time difference represents the time from the generation of the data signal corresponding to the drive interface to its transmission to the register;
[0030] The calculation module is further configured to determine the target time difference of the drive interface based on the second time difference corresponding to the drive interface and the first time difference;
[0031] A processing module, configured to perform simulation testing on the netlist data of the module under test based on the target time difference of the at least one drive interface.
[0032] Another aspect of the present application provides an electronic device, including:
[0033] A processor and a memory for storing instructions executable by the processor;
[0034] The processor is configured to read the executable instructions from the memory and execute the instructions to implement the module-level simulation test method.
[0035] In another aspect of the present application, a computer-readable storage medium is provided, which stores a computer program for executing the module-level simulation test method.
[0036] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become easily understandable through the following description.
[0037] In the above solution, by performing static timing analysis on the netlist data and timing data of the module under test, the first time difference (the time from the generation of the clock signal to its transmission to the first register) and the second time difference of each driving interface (the time from the generation of the data signal of each driving interface to its transmission to the first register) are obtained, providing a quantitative basis for timing alignment. The target time difference is dynamically determined based on the difference between the second time difference and the first time difference of each driving interface. Essentially, by adjusting the arrival time of the data signal, an accurate phase difference is formed between the data signal and the clock signal at the first register. This ensures that the data signal is stably established and maintained within the valid clock window, thus avoiding sampling errors caused by timing misalignment and guaranteeing the successful module-level simulation test of the netlist. Secondly, the introduction of the target time difference enables the data signals of each driving interface to be strictly synchronized with the clock signal, ensuring that when the signal is transmitted from the first register to subsequent registers step by step, the timing margin is always within a safe range. This not only solves the problem of logical correctness but timing failure in traditional simulation tests due to ignoring actual physical delays, but also supports differential optimization of the timing characteristics of different driving interfaces. For example, for long-path interfaces, the target time difference can be appropriately relaxed to insert buffers, while for critical-path interfaces, the performance can be preferentially guaranteed by tightening the target time difference. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] By referring to the accompanying drawings and reading the following detailed description, the above and other objects, features, and advantages of the exemplary embodiments of the present application will become easily understandable. In the drawings, several embodiments of the present application are shown in an exemplary and non-limiting manner, where:
[0039] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.
[0040] Figure 1 Shows a flowchart of a module-level simulation test method according to an embodiment of the present application;
[0041] Figure 2 A schematic diagram showing the static timing analysis result according to an embodiment of the present application;
[0042] Figure 3 A waveform diagram showing the clock signal and data signal before and after realizing the phase difference according to an embodiment of the present application;
[0043] Figure 4 A flowchart showing the module-level simulation test method according to another embodiment of the present application;
[0044] Figure 5 A flowchart showing the module-level simulation test method according to another embodiment of the present application;
[0045] Figure 6 A flowchart showing the module-level simulation test method according to another embodiment of the present application;
[0046] Figure 7 A waveform diagram obtained after simulation test according to an embodiment of the present application;
[0047] Figure 8 A flowchart showing the module-level simulation test method according to another embodiment of the present application;
[0048] Figure 9 A waveform diagram after creating a corrected clock signal according to an embodiment of the present application;
[0049] Figure 10 A waveform diagram after correcting the time point when the second signal switches from low level to high level according to an embodiment of the present application;
[0050] Figure 11 A schematic structural diagram of a module-level simulation test device according to an embodiment of the present application;
[0051] Figure 12 A schematic diagram showing the composition structure of an electronic device according to an embodiment of the present application. Detailed implementation manners
[0052] To make the objectives, features, and advantages of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are only a part of the embodiments of the present application, rather than all of them. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present application.
[0053] To enable the register to receive a valid signal and successfully perform a module-level simulation test on the netlist, an embodiment of the present application provides a module-level simulation test method, as Figure 1 shown, the method includes:
[0054] Step 101, obtain the netlist data and timing data of the module to be tested.
[0055] The netlist data of the module to be tested is a structured representation of the module, usually describing logic units (such as AND gates, flip-flops) and their interconnection relationships at the gate level or transistor level, generated by a logic synthesis tool, and providing a circuit blueprint for simulation and physical implementation.
[0056] The timing data (SDF file) of the module to be tested records the actual timing parameters after placement and routing, including the gate delay of logic units and the wire delay of interconnecting wires, extracted by a backend design tool and backannotated to the netlist to simulate the signal behavior under real physical conditions.
[0057] When the backend work progresses to a certain stage, the netlist data and timing data will be fed back to facilitate the timing simulation test of the netlist. The backend will provide multiple versions of files throughout the project cycle, and the time when the backend feeds back the module-level netlist data and timing data is earlier than the time when the netlist data and timing data are fed back. Therefore, in this embodiment, after the backend feeds back the module-level netlist data and timing data, the module-level simulation test of the netlist can be performed on this module.
[0058] Step 102, perform static timing analysis on the module to be tested based on the netlist data and the timing data, to obtain a first time difference and a second time difference of at least one driving interface, where the first time difference represents the time from the generation of the clock signal of the module to be tested to the transmission to the first register, and the second time difference represents the time from the generation of the data signal of the corresponding driving interface to the transmission to the register.
[0059] In this embodiment, static timing analysis can be performed on the module to be tested based on the netlist data and the timing data through software such as PrimeTime software, Cadence Tempus software, and OpenTimer tool, to obtain the time point when the clock signal is generated, the time point when the clock signal is transmitted to the first register, the time point when the data signal of each driving interface is generated, and the time point when the data signal of each driving interface is transmitted to this register. Then, based on these time points, the first time difference and the second time difference of each driving interface are calculated.
[0060] For example, as Figure 2 shown, Figure 2The data in the middle is obtained after static timing analysis of the netlist data and timing data of a module to be tested by PrimeTime software. The data includes the time point t_clk0 when the clock signal is generated in the module to be tested, the time point t_clk1 when the clock signal is transmitted to register A (the first register on the clock signal transmission path), the time point t_d0 when the data signal of drive interface A is generated, and the time point t_d1 when the data signal of drive interface A is transmitted to register A. Based on the time point t_clk0 when the clock signal is generated and the time point t_clk1 when the clock signal is transmitted to register A, the first time difference is determined to be T C = t_clk1 - t_clk0. The time point t_d0 when the data signal of drive interface A is generated and the time point t_d1 when the data signal of drive interface A is transmitted to register A determine that the second time difference of drive interface A is T D = t_d1 - t_d0.
[0061] Step 103: Determine the target time difference of the drive interface based on the second time difference corresponding to the drive interface and the first time difference.
[0062] When determining the target time difference of the drive interface, there are two cases:
[0063] First, when the second time difference T D of the drive interface is greater than the first time difference T C , the target time difference T_skew of this drive interface = T D - T C .
[0064] Second, when the second time difference T D of the drive interface is less than the first time difference T C , the target time difference T_skew of this drive interface = 0.
[0065] It should be noted that when calculating the target time difference of the drive interface, there is usually a large amount of data for the drive interface. Therefore, batch calculation can be performed through a script (such as a python script). Moreover, the drive interfaces can be divided into write command channels, write data channels, write response channels, read command channels, read data channels, etc. according to the channel types of the data signals of the drive interfaces, which is convenient for writing scripts of the same channel type for calculation.
[0066] Step 104: Perform a simulation test on the netlist data of the module to be tested based on the target time differences of the at least one drive interface.
[0067] Modify the interface file (configuration file) of the test environment to implement the phase difference between the clock signal and the data signal within the clock block corresponding to the drive interface. For example, when the drive interface is slave (a type of drive interface), the test environment drives the signal in the clock block mcb (a type of clock block), and when the drive interface is master (a type of drive interface), the test environment drives the signal in the clock block scb (a type of clock block).
[0068] Then instantiate the drive interface and assign values to the phase differences between the clock signal and the data signal in the instantiated drive interface.
[0069] Finally, perform a simulation test on the netlist data of the module under test through the instantiated drive interface.
[0070] As Figure 3 shown,[[]]END]] Figure 3 are the signal waveform diagrams of the data signal and the clock signal of a certain drive interface before and after implementing the phase difference between the clock signal and the data signal based on the target time difference of the drive interface. Before implementing the phase difference between the clock signal and the data signal of the data signal and the clock signal of the drive interface based on the target time difference of the drive interface, the time when the data signal reaches the register is the same as the rising edge of the clock signal. However, due to the physical delay of the data signal, at this time, it is impossible to ensure that the data signal is effectively driven to the register. After implementing the phase difference between the clock signal and the data signal of the data signal and the clock signal of the drive interface based on the target time difference of the drive interface, the data signal has reached the register before the rising edge of the clock signal arrives, thus ensuring that the data signal is effectively driven to the register.
[0071] It should be noted that for the simulation test of the netlist data of the module under test in this application, it is necessary to reuse the environment and test stimuli of the pre-simulation at the module level (i.e., RTL test), and replace the RTL under test with the netlist data and timing data of the post-simulation for the post-simulation test (i.e., netlist simulation test).
[0072] In the above solution, by performing static timing analysis on the netlist data and timing data of the module under test, the first time difference (the time from the generation of the clock signal to its transmission to the first register) and the second time difference of each driving interface (the time from the generation of the data signal of each driving interface to its transmission to the first register) are obtained, providing a quantitative basis for timing alignment. The target time difference is dynamically determined based on the difference between the second time difference and the first time difference of each driving interface. Essentially, by adjusting the arrival time of the data signal, an accurate phase difference is formed between it and the clock signal at the first register. This ensures that the data signal is stably established and maintained within the valid window of the clock, thus avoiding sampling errors caused by timing misalignment and guaranteeing the successful module-level simulation test of the netlist. Secondly, the introduction of the target time difference enables the data signal of each driving interface to be strictly synchronized with the clock signal, ensuring that when the signal is transmitted step by step from the first register to subsequent registers, the timing margin always remains within a safe range. This not only solves the problem of logical correctness but timing failure caused by ignoring the actual physical delay in traditional simulation tests but also supports the differential optimization of the timing characteristics of different driving interfaces. For example, for long-path interfaces, the target time difference can be appropriately relaxed to insert buffers, while for critical-path interfaces, the performance can be preferentially guaranteed by tightening the target time difference.
[0073] In an example of the present application, a module-level simulation test method is also provided. As Figure 4 shown, determining the target time difference of the driving interface based on the second time difference corresponding to the driving interface and the first time difference includes:
[0074] Step 201, obtaining a third time difference, where the third time difference is the setup time of the register.
[0075] The third time difference is the setup time of the register. The setup time of the register refers to the minimum stable time that the data signal must maintain before the effective edge (such as the rising edge or falling edge) of the clock signal arrives.
[0076] In this embodiment, since the setup times of different registers are different, it is necessary to pre-obtain the setup times of different registers to determine the range of the setup times of these registers, and then determine the third time difference based on this range. For example, in the current process, the range of the setup time of the register is 40ps - 60ps, then the third time difference is determined to be 80ps.
[0077] Step 202, determining the target time difference of the driving interface based on the second time difference corresponding to the driving interface, the first time difference, and the third time difference.
[0078] Similarly, when determining the target time difference of the driving interface, there are two cases:
[0079] The first one is the second time difference T of the drive interface D is greater than the first time difference T C When this is the case, the target time difference T_skew of the drive interface = T D -T C +T S , where T S is the third time difference
[0080] The second one is that the second time difference T of the drive interface D is less than the first time difference T C When this is the case, the target time difference T_skew of the drive interface = T S , where T S is the third time difference
[0081] In the above solution, the time when the clock signal is transmitted to the first register (the first time difference), the delay when the drive interface data signal is transmitted to the register (the second time difference), and the setup time of the register (the third time difference) are combined to reconstruct the determination method of the target time difference, ensuring that the data signal can have a stable window at least one setup time in advance before the effective edge of the clock arrives, so as to strictly meet the timing constraint requirements of the register. The introduction of the third time difference enables the determination method of the target time difference to bind to the physical characteristics of the register, avoiding the risk of sampling errors caused by ignoring the setup time from the root. It enables the simulation test to accurately simulate the real scenario after physical implementation, effectively exposing the marginal problems caused by incomplete coverage of the timing window in the traditional method, and significantly improving the effect of the simulation test
[0082] In an example of this application, a module-level simulation test method is also provided. As Figure 5 shown, determining the target time difference of the drive interface based on the second time difference, the first time difference, and the third time difference of the drive interface includes
[0083] Step 301, if it is determined that the second time difference of the drive interface is greater than the first time difference, then determine the difference between the second time difference and the first time difference
[0084] This is the first case of determining the target time difference of the drive interface based on the second time difference, the first time difference, and the third time difference corresponding to the drive interface. When the second time difference T of the drive interface D is greater than the first time difference T C , first determine the difference T between the second time difference and the first time difference of this drive interface D -T C .
[0085] Step 302, determine the sum of the difference and the third time difference as the target time difference of the drive interface
[0086] Then determine the sum T of the difference and the third time differenceD -T C +T S and determine it as the target time difference of the drive interface.
[0087] In the above solution, when it is detected that the second time difference of the drive interface is greater than the first time difference, the sum of the difference between the two and the third time difference is determined as the target time difference. By quantifying the delay excess of the data signal path relative to the clock signal path, the data signal is forced to arrive early enough before the clock edge to cover the double constraints of path imbalance and setup time. The above solution can actively identify the delay imbalance risk and improve the strictness of the target time difference for the scenario where the data signal path is significantly longer than the clock signal path, ensuring that the simulation test covers marginal timing issues (such as signal jitter or crosstalk interference at the boundary of the setup time window) ignored by traditional methods. This enables the simulation test to accurately simulate the real scenario after physical implementation and further improve the effect of the simulation test.
[0088] In an example of the present application, a module-level simulation test method is further provided. Determining the target time difference of the drive interface based on the second time difference, the first time difference, and the third time difference of the drive interface includes:
[0089] If it is determined that the second time difference of the drive interface is less than the first time difference, then the third time difference is determined as the target time difference of the drive interface.
[0090] That is, the second case in determining the target time difference of the drive interface based on the second time difference, the first time difference, and the third time difference corresponding to the drive interface. When the second time difference T D of the drive interface is less than the first time difference T C , the third time difference T S is determined as the target time difference of the drive interface.
[0091] In the above solution, by directly determining the third time difference as the target time difference of the drive interface when it is detected that the second time difference of the drive interface is less than the first time difference, the calculation process can be significantly simplified and design redundancy can be reduced on the premise of ensuring timing safety. When the second time difference of the drive interface is less than the first time difference, it indicates that the data signal can arrive at the register in advance. At this time, it is only necessary to ensure that the data signal is stable within a setup time window before the effective clock edge, and no additional path delay difference compensation is required. By distinguishing the delay relationship between the data signal path and the clock signal path, the balance of "strictly constraining the critical path and efficiently releasing the non-critical path" is achieved. For short data signal paths, redundant difference calculations are skipped, reducing the computational overhead of simulation iterations and accelerating the verification process. In addition, this solution accurately matches the physical design requirements, strictly exposes real timing defects while simplifying the calculation, rather than misreporting problems due to algorithm errors, thereby improving the credibility of the simulation test results.
[0092] In an example of the present application, a module-level simulation test method is also provided. As Figure 6 shown, the method further includes:
[0093] Step 401: Obtain a waveform diagram, which is obtained after performing a simulation test on the netlist data of the module to be tested.
[0094] After performing a simulation test on the netlist data of the module to be tested, a waveform diagram as Figure 7 shown can be obtained. The waveform diagram includes the waveform diagrams of a clock signal, a data signal, a first signal (read valid signal), and a second signal (read ready signal). The first signal is sent by a data provider (usually a slave device or a memory controller), indicating that the currently transmitted data signal is valid and appears on the data bus. The second signal is sent by a data receiver (usually a master device or a processor), indicating that the receiver is ready to receive data.
[0095] Only when both the first signal and the second signal are at a high level, the drive interface will read the data signal at the rising edge of the clock signal.
[0096] Step 402: Based on the waveform diagram, determine that the data signal read by the drive interface is unstable, and then correct the time when the drive interface reads the data signal so that the drive interface reads a stable data signal.
[0097] At the rising edge of the clock, if both the first signal and the second signal are at a high level, the drive interface reads the data signal. However, since the data signal is a multi-bit wide signal, at the rising edge of the clock signal, some of the bits of the signal have not been driven to the drive interface yet, resulting in the drive interface reading an unstable data signal ( Figure 7 the data signals in the areas within the two dotted lines).
[0098] As Figure 7 shown, at the first rising edge of the clock signal after both the first signal and the second signal are at a high level ( Figure 7 the time point where the straight line with an arrow is located), the drive interface reads the data signals in the areas within the two dotted lines, and it is determined that the data signal read by the drive interface is unstable.
[0099] In this embodiment, the time when the drive interface reads the data signal can be corrected in the following two ways:
[0100] First, delay the clock signal, and then delay the rising edge of the clock signal to delay the time when the drive interface reads the data signal, so that the drive interface reads a stable data signal.
[0101] Second, control the second signal. When the first signal is at a low level, control the second signal to be at a low level. After detecting that the first signal transitions to a high level, switch the second signal from a low level to a high level after one clock signal cycle, realizing the delay in the time for the drive interface to read the data signal, so that the drive interface reads a stable data signal.
[0102] Step 403: Re - perform simulation testing on the netlist data of the module to be tested based on the target time difference of the at least one drive interface.
[0103] After correcting the time for the drive interface to read the data signal to ensure that the drive interface can read a stable data signal, re - perform simulation testing on the netlist data of the module to be tested based on the target time differences of each drive interface.
[0104] In the above - mentioned solution, a waveform diagram is generated through simulation testing of the netlist data of the module to be tested, visually presenting the actual timing behavior of the drive interface reading the data signal, and analysis is performed based on the waveform diagram. When it is determined that the data signal read by the drive interface is unstable, correct the time for the drive interface to read the data signal so that the drive interface can read a stable data signal, and then re - execute the simulation testing based on the corrected parameters. By correcting the time for the drive interface to read the data signal, the risk of simulation testing failure caused by unstable data is significantly reduced, providing a key guarantee for the design of high - reliability chips.
[0105] In an example of the present application, a module - level simulation testing method is also provided, as Figure 8 shown, correcting the time for the drive interface to read the data signal based on the fourth time difference includes:
[0106] Step 501: Determine the fourth time difference based on the waveform diagram.
[0107] For example, as Figure 7 shown, Figure 7 shows that at the rising edge of the first clock signal after both the first signal and the second signal are at a high level, the drive interface reads the data signal within the area between the two dashed lines, and it is determined that the data signal read by the drive interface is unstable. At this time, it is necessary to obtain the time point of the rising edge of the first clock signal after both the first signal and the second signal are at a high level, and the time point when the data signal is stable ( Figure 7 the time point at the position of the right - hand dashed line in
[0108] ), and determine the fourth time difference based on these two time points. The fourth time difference can be slightly larger than the difference between these two time points.
[0109] Continuing with the above example, after determining the fourth time difference, a corrected clock signal is created. The corrected clock signal is, as shown in Figure 9 , the signal obtained by delaying the clock signal by the fourth time difference. After both the first signal and the second signal are at a high level, the driving interface no longer reads the data signal at the rising edge of the first clock signal, but reads the data signal at the rising edge of the first corrected clock signal, so that a stable data signal can be read.
[0110] In the above solution, the fourth time difference is determined based on the waveform diagram obtained from the simulation test (i.e., the difference between the rising edge of the first clock signal after the first signal (such as RVALID) and the second signal (such as RREADY) are both at a high level and the actual stable time point of the data signal), and a corrected clock signal is created accordingly (by delaying the clock signal by the fourth time difference). This corrected clock signal is used to control the driving interface to read the data signal at the rising edge of the delayed clock signal, ensuring that the data signal is completely stable at the reading moment. For example, if the data signal is still in a transitional state (such as having jitter or not meeting the setup time) when the rising edge of the first clock signal arrives after the first signal and the second signal are both at a high level, then by using the corrected clock signal with the fourth time difference delay, the reading moment is postponed to within the stable window of the data signal. By precisely aligning the data stable point and the clock signal sampling point, sampling errors caused by insufficient signal establishment are completely eliminated, thereby directly improving the effectiveness and reliability of the simulation test without modifying the physical design, and providing high-precision timing adaptation capabilities for complex interface scenarios.
[0111] In an example of the present application, a module-level simulation test method is also provided. Correcting the time when the driving interface reads the data signal based on the fourth time difference includes:
[0112] Determine that the first signal changes from a low level to a high level, and after one clock signal cycle, switch the second signal from a low level to a high level, so that the driving interface reads the data signal at the rising edge of the first clock signal after determining that both the first signal and the second signal are at a high level. When the first signal is at a high level, it indicates that the data signal can be read.
[0113] For example, as shown in Figure 7 Figure 7 shows that at the rising edge of the first clock signal after the first signal and the second signal are both at a high level, the driving interface reads the data signal in the area within the two dotted lines, and it is determined that the data signal read by the driving interface is unstable. At this time, the time when the second signal is switched to a high level needs to be adjusted. As shown in Figure 10 As shown in the corrected second signal waveform diagram, the time when the second signal is switched to the high level is corrected to the time point after it is determined that the first signal changes from the low level to the high level and after one clock signal period. At this time, the data signal has stabilized, and the drive interface reads the stable data signal at the rising edge of the first clock signal after it is determined that both the first signal and the second signal are at the high level.
[0114] In the above solution, by controlling the delayed switching logic of the second signal, after the first signal jumps from the low level to the high level (indicating that the data signal can be read), wait for a complete clock cycle, and then switch the second signal from the low level to the high level. At this time, the data signal has stabilized, enabling the drive interface to read the stable data signal at the rising edge of the first clock signal after the second signal is switched from the low level to the high level. By forcibly aligning the timing relationship between the valid states of the dual signals and the clock edge, it is ensured that the data signal is fully stable at the reading moment (meeting the setup time and hold time requirements), and completely eliminates the risk of sampling errors caused by asynchronous signal switching. Through clock cycle-level delay control, signal competition and glitch interference are avoided, ensuring that the drive interface samples only at the clock edge when the data is completely stable, thereby improving the accuracy of the reading operation and the system robustness, and further enhancing the effectiveness and reliability of the simulation test.
[0115] The following describes the above module-level simulation test method in combination with the actual application scenario:
[0116] Step 601, the netlist to be tested (the netlist data of the module to be tested), the sdf file (the timing data of the module to be tested), and the Prime Time software (static timing analysis software) are provided with the drive interface signal name and the clock signal name.
[0117] Step 602, the Prime Time software reports the delay of all paths from the data signal of a certain drive interface to the next-level register, and the phase difference that needs to be maintained between the data signal of the drive interface and the clock signal is calculated.
[0118] Perform static timing analysis using the Prime Time software to obtain an rpt format file. By viewing the information in the rpt format file, the delay T of the clock signal reaching the first register can be obtained C = t_clk1 - t_clk0, and the delay of the drive interface data signal reaching this register is T D = t_d1 - t_d0. Then calculate the phase difference T_skew that needs to be maintained between the drive interface data signal and the clock signal. When T D > T C , T_skew = T D - T C + T S When TD <T C When T_skew = T S . Such calculation is to ensure that the data signal has sufficient setup time and can be effectively saved by this register.
[0119] Step 603, use a script to sort out the delay of the file. If a certain data signal has a multi-bit width, then take the maximum value of the delays of all bits.
[0120] Step 604, modify the configuration file to implement the phase difference between the clock signal and the driving interface data signal in the clock block of the interface.
[0121] Step 605, instantiate and connect the driving interface for simulation testing.
[0122] To implement the above module-level simulation testing method, as Figure 11 shown, an example of the present application provides a module-level simulation testing device, including:
[0123] An acquisition module 701, configured to obtain the netlist data and timing data of the module to be tested;
[0124] A calculation module 702, configured to perform static timing analysis on the module to be tested based on the netlist data and the timing data, to obtain a first time difference and a second time difference of at least one driving interface, where the first time difference represents the time from the generation of the clock signal of the module to be tested to its transmission to the first register, and the second time difference represents the time from the generation of the data signal of the corresponding driving interface to its transmission to the register;
[0125] The calculation module 702 is further configured to determine the target time difference of the driving interface based on the second time difference corresponding to the driving interface and the first time difference;
[0126] A processing module 703, configured to perform simulation testing on the netlist data of the module to be tested based on the target time difference of the at least one driving interface.
[0127] Wherein, the acquisition module 701 is further configured to obtain a third time difference, and the third time difference is the setup time of the register;
[0128] The calculation module 702 is further configured to determine the target time difference of the driving interface based on the second time difference corresponding to the driving interface, the first time difference, and the third time difference.
[0129] Wherein, the calculation module 702 is further configured to determine the difference between the second time difference and the first time difference if it is determined that the second time difference of the driving interface is greater than the first time difference;
[0130] The calculation module 702 is further configured to determine the sum of the difference and the third time difference as the target time difference of the drive interface.
[0131] Wherein, if the calculation module 702 further determines that the second time difference of the drive interface is less than the first time difference, the third time difference is determined as the target time difference of the drive interface.
[0132] Wherein, the processing module 703 is further configured to obtain a waveform diagram, which is obtained after simulating and testing the netlist data of the module under test.
[0133] The calculation module 702 is further configured to determine that the data signal read by the drive interface is unstable based on the waveform diagram, and then correct the time for the drive interface to read the data signal, so that the drive interface reads a stable data signal.
[0134] The processing module 703 is further configured to re-simulate and test the netlist data of the module under test based on the target time differences of the at least one drive interface.
[0135] Wherein, the calculation module 702 is further configured to determine a fourth time difference based on the waveform diagram.
[0136] The processing module 703 is further configured to create a corrected clock signal, which is obtained by delaying the clock signal by the fourth time difference, and the corrected clock signal is used to make the drive interface read the data signal after the fourth time difference from the rising edge of the clock signal.
[0137] Wherein, the processing module 703 is further configured to determine that the first signal changes from a low level to a high level, and after one clock signal period, switch the second signal from a low level to a high level, so that the drive interface reads the data signal at the first rising edge of the clock signal after determining that both the first signal and the second signal are at a high level. When the first signal is at a high level, it indicates that the data signal can be read.
[0138] In the above solution, by performing static timing analysis on the netlist data and timing data of the module under test, the first time difference (the time from the generation of the clock signal to its transmission to the first register) and the second time differences of each drive interface (the time from the generation of the data signal of each drive interface to its transmission to the first register) are obtained, providing a quantitative basis for timing alignment. The target time difference is dynamically determined based on the difference between the second time difference and the first time difference of each drive interface. Essentially, by adjusting the arrival time of the data signal, an exact phase difference is formed with the clock signal at the first register. This ensures that the data signal is stably established and maintained within the valid clock window, thereby avoiding sampling errors caused by timing misalignment and guaranteeing the successful module-level simulation test of the netlist. Secondly, the introduction of the target time difference enables the data signals of each drive interface to be strictly synchronized with the clock signal, ensuring that when the signal is transmitted from the first register to subsequent registers step by step, the timing margin always remains within a safe range. This not only solves the problem of logical correctness but timing failure caused by ignoring the actual physical delay in traditional simulation tests, but also supports differential optimization of the timing characteristics of different drive interfaces. For example, the target time difference can be appropriately relaxed for long-path interfaces to insert buffers, while for critical-path interfaces, the performance can be preferentially guaranteed by tightening the target time difference.
[0139] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.
[0140] Figure 12 FIG. shows a schematic block diagram of an exemplary electronic device 800 that can be used to implement embodiments of the present disclosure. The electronic device is intended to represent various forms of digital computers, such as, for example, a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as, for example, a personal digital processor, a cellular phone, a smart phone, a wearable device, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.
[0141] As Figure 12 shown, the device 800 includes a computing unit 801 that can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.
[0142] Multiple components in device 800 are connected to I / O interface 805, including: input unit 806, such as a keyboard, mouse, etc.; output unit 807, such as various types of displays, speakers, etc.; storage unit 808, such as a disk, optical disc, etc.; and communication unit 809, such as a network card, modem, wireless communication transceiver, etc. Communication unit 809 allows device 800 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.
[0143] Computing unit 801 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of computing unit 801 include but are not limited to a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Computing unit 801 executes the various methods and processes described above, such as the module-level simulation test method. For example, in some embodiments, the module-level simulation test method can be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed onto device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by computing unit 801, one or more steps of the module-level simulation test method described above can be executed. Alternatively, in other embodiments, computing unit 801 can be configured to execute the module-level simulation test method in any other suitable way (e.g., by means of firmware).
[0144] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special or general-purpose programmable processor, and can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit the data and instructions to the storage system, the at least one input device, and the at least one output device.
[0145] The program code for implementing the methods of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general purpose computer, a special purpose computer, or other programmable data processing device, such that the program codes, when executed by the processor or controller, cause the functions / operations specified in the flowchart and / or block diagram to be implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.
[0146] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
[0147] In order to provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and the input received from the user can be in any form (including acoustic input, speech input, or tactile input).
[0148] The systems and techniques described herein can be implemented in a computing system including backend components (e.g., as a data server), or a computing system including middleware components (e.g., an application server), or a computing system including frontend components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described herein), or a computing system including any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected to each other by digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), and the Internet.
[0149] A computer system can include a client and a server. The client and the server are generally remote from each other and typically interact through a communication network. The relationship between the client and the server is generated by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, can also be a server of a distributed system, or a server incorporating a blockchain.
[0150] It should be understood that various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recited in this disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this is not limited herein.
[0151] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" can explicitly or implicitly include at least one such feature. In the description of this disclosure, "a plurality" means two or more unless otherwise specifically defined.
[0152] As described above, the above are only specific implementation manners of this disclosure, but the protection scope of this disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed in this disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be subject to the protection scope of the claimed rights.
Claims
1. A module-level simulation test method, characterized in that, The method includes: Obtaining the netlist data and timing data of the module to be tested; Performing static timing analysis on the module to be tested based on the netlist data and the timing data to obtain a first time difference and a second time difference of at least one driving interface, where the first time difference represents the time from the generation of the clock signal of the module to be tested to its transmission to the first register, and the second time difference represents the time from the generation of the data signal of the corresponding driving interface to its transmission to the register; Determining the target time difference of the driving interface based on the second time difference corresponding to the driving interface and the first time difference; Performing a simulation test on the netlist data of the module to be tested based on the target time differences of the at least one driving interface.
2. The method according to claim 1, wherein The determining the target time difference of the driving interface based on the second time difference corresponding to the driving interface and the first time difference includes: Obtaining a third time difference, where the third time difference is the setup time of the register; Determining the target time difference of the driving interface based on the second time difference corresponding to the driving interface, the first time difference, and the third time difference.
3. The method according to claim 2, wherein The determining the target time difference of the driving interface based on the second time difference, the first time difference, and the third time difference of the driving interface includes: If it is determined that the second time difference of the driving interface is greater than the first time difference, determining the difference between the second time difference and the first time difference; Determining the sum of the difference and the third time difference as the target time difference of the driving interface.
4. The method according to claim 2, wherein The determining the target time difference of the driving interface based on the second time difference, the first time difference, and the third time difference of the driving interface includes: If it is determined that the second time difference of the driving interface is less than the first time difference, determining the third time difference as the target time difference of the driving interface.
5. The method according to claim 1, wherein The method further includes: Obtaining a waveform diagram, where the waveform diagram is obtained after performing a simulation test on the netlist data of the module to be tested; If it is determined based on the waveform diagram that the data signal read by the driving interface is unstable, correcting the time for the driving interface to read the data signal so that the driving interface reads a stable data signal; Performing a simulation test on the netlist data of the module to be tested again based on the target time differences of the at least one driving interface.
6. The method according to claim 5, wherein The correcting the time for the driving interface to read the data signal based on the fourth time difference includes: Determining a fourth time difference based on the waveform diagram; Creating a corrected clock signal, where the corrected clock signal is obtained by delaying the clock signal by the fourth time difference, and the corrected clock signal is used to enable the driving interface to read the data signal after the rising edge of the clock signal passes through the fourth time difference.
7. The method according to claim 5, characterized in that, The correcting the time for the driving interface to read the data signal based on the fourth time difference includes: Determining that the first signal changes from low level to high level, and after one clock signal period, switching the second signal from low level to high level, so that the driving interface reads the data signal at the first rising edge of the clock signal after determining that both the first signal and the second signal are high level, where the data signal can be read when the first signal is high level.
8. A module-level simulation test device, characterized in that, The device includes: An acquisition module for obtaining the netlist data and timing data of the module to be tested; A calculation module, configured to perform static timing analysis on the module under test based on the netlist data and the timing data, to obtain a first time difference and second time differences of at least one driving interface, where the first time difference represents the time from the generation of the clock signal of the module under test to its transmission to the first register, and the second time difference represents the time from the generation of the data signal of the corresponding driving interface to its transmission to the register; The calculation module is further configured to determine a target time difference of the driving interface based on the second time difference corresponding to the driving interface and the first time difference; A processing module, configured to perform a simulation test on the netlist data of the module under test based on the target time differences of the at least one driving interface.
9. An electronic device, characterized in that, Comprising: A processor and a memory for storing executable instructions of the processor; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the module-level simulation test method according to any one of claims 1-7.
10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, and the computer program is used to execute the module-level simulation test method according to any one of claims 1-7.