Physical design optimization method and system, electronic equipment and storage medium

Abstract

The invention provides a physical design optimization method and system, electronic equipment and a storage medium, and the method comprises the steps: obtaining a specified optimization target; based on the optimization target, determining an optimization object needing to be optimized from a to-be-optimized netlist; corresponding target netlist transformation method combinations are obtained based on the optimization targets, different optimization targets are configured to correspond to different netlist transformation method combinations, and each netlist transformation method combination comprises a plurality of netlist transformation methods according to a preset sequence; and traversing all the optimization objects, and optimizing the traversed current optimization object by using the target netlist transformation method combination. The technical problems that in the prior art, different netlist transformation methods are fused, the strategy flexibility is insufficient, and the operation time is too long can be solved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic design automation (EDA), and particularly to a physical design optimization method, system, electronic device, and storage medium. Background Art

[0002] EDA refers to a chip automatic design methodology that uses computer-aided design software to complete design functions of very large scale integrated circuit chips, such as functional design, synthesis, verification, physical design (including floorplanning, placement, and routing), and physical verification. A netlist is the core data file that describes the logical connection relationships of an integrated circuit in the EDA process. In essence, it is a structured text that records all the units (instances) within the design and the interconnect network (nets) between the units.

[0003] With the continuous pursuit of high performance in integrated circuits, conventional design processes usually cannot meet the design requirements in a single run and instead require netlist transformation. Netlist transformation is a key technical means to optimize physical design goals by directly modifying the structure and parameters of an integrated circuit netlist. In essence, it is to dynamically adjust the netlist based on accurate physical information (such as unit positions, wire parasitic parameters, etc.) in the backend physical design stage (after placement and routing) to resolve conflicts in key design metrics such as timing, area, and power consumption. Currently, commonly used netlist transformation methods include cell sizing, buffer insertion, cell clone, cell relocation, etc. However, using a single netlist transformation method is likely to result in insufficient optimization.

[0004] In response to this, the following literature introduces algorithms for integrating different netlist transformation methods for physical design optimization, as follows:

[0005] Literature 1 [Y. Jiang, et al., “Interleaving Buffer Insertion and Transistor Sizing into a Single Optimization”, IEEE Trans. VLSI, Vol. 6, No. 4, pp. 625 - 633, 1998.] discloses an optimization strategy that integrates cell sizing and buffer insertion. This strategy attempts both cell sizing and buffer insertion for each selected net. Although this strategy has better optimization effects than simple sequential execution, it may still fall into a local optimum and can only combine two netlist transformation methods, cell sizing and buffer insertion, for optimization, lacking flexibility.

[0006] Reference 2 [Huan Ren, Shantanu Dutt, "Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure", 2008 IEEE / ACM International Conference on Computer-Aided Design, pp.93-100, 2008.] discloses an optimization strategy that integrates four netlist transformation methods: cell size transformation, buffer insertion, cell cloning, and cell repositioning. This strategy is based on the minimum cost network flow algorithm. For each selected net, an optimal netlist transformation method is selected based on this algorithm for netlist transformation to obtain an optimized effect. Although this strategy can integrate more netlist transformation methods, the running time of the minimum cost network flow algorithm increases exponentially compared to other strategies, and its usability for relatively large industrial circuits is not high.

[0007] Reference 3 [Apostolos Stefanidis, Dimitrios Mangiras, Chrysostomos Nicopoulos, David Chinnery, Giorgos Dimitrakopoulos, "Autonomous Application of Netlist Transformations Inside Lagrangian Relaxation-Based Optimization", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.40, no.8, pp.1672-1686, 202.] discloses a sequential execution strategy based on reinforcement learning. The difference between this strategy and the previous sequential execution strategies is that each selected netlist transformation method is judged by a selection engine based on reinforcement learning, rather than using a fixed transformation order. However, it does not change the essence of sequential execution and is prone to falling into local optimal solutions.

[0008] In addition, the optimization objectives of existing strategies are too single. For example, some strategies can only optimize tns (total negative slack). In scenarios where wns (worst negative slack) is more important than tns, the optimization effects of these strategies will be greatly reduced. The fundamental reason is that the integration strategy is not flexible enough and the robustness of the architecture or algorithm is insufficient. Summary of the Invention

[0009] To solve the technical problems of insufficient flexibility of strategies for integrating different netlist transformation methods and excessive running time in the prior art, the present invention provides a physical design optimization method, system, electronic device, and storage medium.

[0010] To achieve the above object, the present invention adopts the following technical solutions:

[0011] In a first aspect, the present invention provides a physical design optimization method, including:

[0012] Obtain a specified optimization target;

[0013] Based on the optimization target, determine the optimization objects to be optimized from the netlist to be optimized;

[0014] Based on the optimization target, obtain the corresponding target netlist transformation method combination, where different optimization targets are configured to correspond to different netlist transformation method combinations, and each netlist transformation method combination respectively includes multiple netlist transformation methods in a predetermined order;

[0015] Traverse all the optimization objects and optimize the currently traversed optimization object using the target netlist transformation method combination.

[0016] Further, the optimization target includes total negative timing slack, worst negative timing slack, area, or power consumption.

[0017] Further, the configuration process of the netlist transformation method combinations corresponding to different optimization targets is as follows:

[0018] Based on the optimization target, select several corresponding netlist transformation methods;

[0019] Based on the optimization target, combine the selected netlist transformation methods in a predetermined order to obtain the netlist transformation method combination corresponding to the optimization target.

[0020] Further, after selecting the netlist transformation methods, it further includes performing fine-grained splitting on some of the selected netlist transformation methods.

[0021] Further, when the optimization target is total negative timing slack, the corresponding netlist transformation method combination includes unit re-placement, unit cloning, multi-buffer insertion, unit size up-transformation, unit size down-transformation, single-buffer insertion, buffer insertion for solving high load, and netlist reconstruction methods executed in sequence;

[0022] When the optimization objective is the worst negative timing margin, the corresponding netlist transformation method combination includes pin swapping, cell repositioning, cell size upscaling, cell size downscaling, single buffer insertion, multi-buffer insertion, buffer insertion for solving high load, and netlist reconstruction methods executed in sequence; and / or,

[0023] When the optimization objective is area or power consumption, the corresponding netlist transformation method combination includes cell repositioning, cell size downscaling, buffer deletion, and netlist reconstruction methods executed in sequence.

[0024] Further, when the optimization objective is area or power consumption, the optimization object is determined from the netlist according to the topological order of the netlist;

[0025] When the optimization objective is the total negative timing margin, the optimization object is determined from the critical path of the netlist according to the topological order, or the bottleneck optimization object is determined from the critical path of the netlist as the optimization object;

[0026] When the optimization objective is the worst negative timing margin, the optimization object is determined from the netlist according to the topological order of the netlist, or the bottleneck optimization object is determined from the critical path of the netlist as the optimization object.

[0027] Further, before traversing the optimization object, the method further includes configuring an optimization end condition, where the optimization end condition is that all methods are executed, or the current optimization object is successfully optimized;

[0028] When the optimization end condition is that all methods are executed, optimizing the currently traversed optimization object includes: sequentially optimizing the current optimization object using all the netlist transformation methods in the target netlist transformation method combination;

[0029] When the optimization end condition is that the current optimization object is successfully optimized, optimizing the currently traversed optimization object includes: sequentially optimizing the current optimization object using the netlist transformation methods in the target netlist transformation method combination until the current optimization object is successfully optimized.

[0030] In a second aspect, the present invention provides a physical design optimization system, including:

[0031] An optimization objective acquisition module for acquiring a specified optimization objective;

[0032] An optimization object determination module for determining an optimization object to be optimized from the netlist to be optimized based on the optimization objective;

[0033] A method combination acquisition module is used to acquire a corresponding target netlist transformation method combination based on the optimization objective, where different optimization objectives are configured to correspond to different netlist transformation method combinations, and each netlist transformation method combination includes multiple netlist transformation methods in a predetermined order;

[0034] An optimization module is used to traverse all the optimization objects and optimize the currently traversed optimization object by using the target netlist transformation method combination.

[0035] In a third aspect, the present invention provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the steps of the physical design optimization method described above are implemented.

[0036] In a fourth aspect, the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the physical design optimization described above are implemented.

[0037] By adopting the above technical solutions, the present invention has the following beneficial effects:

[0038] The present invention differentiates different optimization objectives and configures different netlist transformation method combinations for different optimization objectives. Since various netlist transformation methods can be fused in the combination, and the execution order of each netlist transformation method in the combination can be flexibly configured according to the optimization objective, the optimization method of the present invention can be flexibly adapted to different optimization objectives, has a better optimization effect than the optimization strategies in the prior art, and does not need to adopt the minimum cost network flow algorithm, reducing the time consumption. Description of the Drawings

[0039] Figure 1 It is a flowchart of the physical design optimization method in Embodiment 1 of the present invention;

[0040] Figure 2 It is a structural block diagram of the physical design optimization system in Embodiment 2 of the present invention;

[0041] Figure 3 It is a hardware architecture diagram of the electronic device in Embodiment 3 of the present invention. Detailed Embodiments

[0042] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the protection scope of the present invention.

[0043] The terms used in the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The singular forms "a", "the" and "said" used in the present disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0044] In order to solve the technical problems of insufficient flexibility of the strategy for integrating different netlist transformation methods and too long running time in the prior art, the present invention provides a physical design optimization method, system, electronic device and storage medium.

[0045] It should be noted that the present invention refers to netlist transformation actions such as cell size transformation and buffer insertion as netlist transformation methods, and the specific network (net), cell (inst) or pin (pin) that needs to be transformed and optimized is called the optimization object.

[0046] Embodiment 1

[0047] This embodiment provides a physical design optimization method, as Figure 1 shown, the method specifically includes the following steps S1 to S4:

[0048] S1, obtain a specified optimization target.

[0049] Existing optimization strategies usually can only achieve a single optimization target, and this embodiment needs to meet the requirements of different optimization targets. Therefore, it is very important to first determine the optimization target, which will affect the selection of the subsequent combination of optimization objects and netlist transformation methods.

[0050] In actual situations, due to different running environments of the specific design of the circuit, some designs focus on optimizing power consumption (power or area), and some designs focus on optimizing timing. In timing optimization, some focus on optimizing wns, and some focus on optimizing tns.

[0051] Therefore, the optimization target in this embodiment can be the total negative timing slack (tns), the worst negative timing slack (wns), the area (area) or the power consumption (power).

[0052] S2. Based on the optimization objective, determine the optimization objects to be optimized from the netlist to be optimized.

[0053] Specifically, after confirming the optimization objective, it is necessary to determine the optimization objects and sort them according to their importance. As mentioned above, in Document 1, only a simple topological order was used to select the optimization objective, lacking flexibility; while in Document 2, the minimum cost network algorithm was used to select the optimization objective, with too long running time. Moreover, both are based on tns optimization as the standard, with insufficient consideration for other optimization objectives.

[0054] Therefore, for the purpose of flexibility and multiple optimization objectives in this embodiment, multiple methods are provided for selecting optimization objects:

[0055] The first method is to select optimization objects from the netlist according to the topological order. The advantage of this method is that it can maximize the accuracy of timing during the optimization process. Since in the process of circuit transformation, pins or nets with a higher order in the topological order will not be affected by nets with a lower order, or the influence is very small. Therefore, this method can ensure the accuracy of timing in the optimization, thereby improving the quality of the final optimization result. And this method will traverse all nets or insts in the circuit that can be optimized (i.e., not prohibited from optimization), so it is particularly applicable when the optimization objective is area or power, and will also focus more on tns optimization when optimizing timing. However, the disadvantage is that the running time may be too long.

[0056] The second method is to select optimization objects from the critical paths of the netlist. The advantage of this method is that it can select pins on the critical paths to directly optimize slack (single-path timing margin) and wns. The delay of insts or nets on the critical paths is the direct reason for the poor wns. Therefore, the selection of pins on the critical paths has a good effect on wns. Among them, the critical path is defined as: the worst path that does not meet the timing constraints for each constraint point (endpoint) of the circuit. There are multiple constraint points in the circuit, that is, there is a critical path for each constraint point. An inst or net that appears in multiple critical paths is a bottleneck optimization object.

[0057] The third type is to select the bottleneck optimization objects that appear multiple times on the critical path. This way of selecting optimization objects combines the respective advantages of the above two ways of selecting optimization objects. If a net or inst appears multiple times on the critical path, it indicates that this optimization object is likely to be the bottleneck that prevents the optimization goal from being achieved. This is called the bottleneck optimization object in this embodiment. Then, sort these optimization objects according to the number of occurrences and the size of the slack, and the importance of each optimization object can be determined. Therefore, the strategy based on this way of selecting optimization objects can take both wns and tns into account, but the tns optimization effect is not as good as the way of selecting according to the topological order.

[0058] Based on the above, when selecting optimization objects in this embodiment, the specific selection process is as follows:

[0059] When the optimization goal is area or power consumption, all nets or insts that can be optimized are extracted from the netlist according to the topological order of the netlist as the optimization objects.

[0060] When the optimization goal is the total negative timing margin, pins are extracted from the critical path of the netlist as the optimization objects according to the topological order, or bottleneck optimization objects (bottleneck optimization objects are nets or insts that appear multiple times on the critical path during the optimization process) are extracted from the critical path of the netlist as the optimization objects. Among them, the user can select which way to extract through configuration.

[0061] When the optimization goal is the worst negative timing margin, all nets or insts that can be optimized are extracted from the netlist according to the topological order of the netlist as the optimization objects, or bottleneck optimization objects are extracted from the critical path of the netlist as the optimization objects. Among them, the user can select which way to extract through configuration.

[0062] S3. Based on the optimization goal, obtain the corresponding target netlist transformation method combination, where different optimization goals are configured to correspond to different netlist transformation method combinations, and each netlist transformation method combination includes multiple netlist transformation methods in a predetermined order (this predetermined order corresponds to the optimization goal).

[0063] Specifically, after selecting the optimization goal and determining the optimization objects, it is necessary to confirm the netlist transformation method combination corresponding to different optimization goals. In this embodiment, the combination method composed of different netlist transformation methods is called the netlist transformation method combination.

[0064] As described above, only the strategy of integrating two netlist transformation methods is used in Document 1, and only 4 netlist transformation methods are combined in Document 2. However, the number of combined netlist transformation methods in this embodiment is not limited, and multiple strategies can be integrated to form a netlist transformation method combination based on different objectives according to different optimization objectives. Among them, the methods in the combination can be conventional netlist transformation methods or user-defined netlist transformation methods.

[0065] For considerations of running time and optimization effect, this patent can also split conventional netlist transformation methods into more fine-grained sub-netlist transformation methods to reduce useless attempts. The specific process is as follows:

[0066] First, select the netlist transformation methods to be integrated based on the optimization objective. This netlist transformation method can be any suitable netlist transformation method. For example, when optimizing timing, the following methods can be selected: cell sizing, buffer insertion, cloning, cell repositioning, netlist restructuring, pin swapping; when optimizing power, the following methods can be selected: cell sizing, cell repositioning, buffer deletion, netlist restructuring.

[0067] Then, perform fine-grained splitting on the selected partial netlist transformation methods. For example, cell sizing and buffer insertion can be split into more fine-grained netlist transformation methods according to different purposes and transformation methods. Since cell sizing and buffer insertion are two main netlist transformation methods, in order to save running time and avoid unnecessary attempts during combination, these two netlist transformation methods are split into more fine-grained netlist transformation methods.

[0068] For example, the cell sizing method can be split into: among them, the cell upsize method and the cell downsize method. For cell upsize: select cells with better timing but larger area; for cell downsize: select cells with worse timing but smaller area. The buffer insertion method can be split into: single buffer insertion (only insert one buffer in one net), multi-buffer insertion (multiple buffers can be inserted on one net), buffer insertion for solving high load (insert buffers for high load nets).

[0069] This embodiment makes a more fine-grained distinction for the netlist transformation method. During optimization, once an optimization is found, subsequent netlist transformation methods can be stopped from being tried. Therefore, the netlist transformation methods with a high probability of generating optimization can be set at the relatively front positions in the netlist transformation method combination.

[0070] Finally, the obtained netlist transformation methods are combined in a certain order based on the optimization objectives. Since the acceptance probabilities of different netlist transformation methods under different optimization objectives are inconsistent, it is very necessary to sort different netlist transformation methods in the combination based on different optimization objectives.

[0071] In an implementable manner, this embodiment provides different combination orders based on four optimization objectives of tns, wns, area, and power, forming different netlist transformation method combinations, which are specifically as follows:

[0072] When the optimization objective is the total negative slack (tns), the corresponding netlist transformation method combination can be {cell re-placement, cell cloning, multi-buffer insertion, cell size up-transformation, cell size down-transformation, single-buffer insertion, high-load buffer insertion solution, netlist reconstruction}. During subsequent optimization, each method in the combination is executed in the order from front to back;

[0073] When the optimization objective is the worst negative slack (wns), the corresponding netlist transformation method combination can be {pin swapping, cell re-placement, cell size up-transformation, cell size down-transformation, single-buffer insertion, multi-buffer insertion, high-load buffer insertion solution, and netlist reconstruction method}; and / or,

[0074] When the optimization objective is area or power, the corresponding netlist transformation method combination includes cell re-placement, cell size down-transformation, buffer deletion, and netlist reconstruction method executed in sequence.

[0075] During subsequent optimization using the corresponding target netlist transformation method combination, it is executed in the order from front to back of the methods in the combination.

[0076] Among them, the area and power optimizations are relatively common because area and power are linearly related in most cases. Therefore, area and power can use the same netlist transformation method combination.

[0077] Among the above combinations of netlist transformation methods based on different optimization objectives, cell repositioning is a netlist transformation method with relatively low cost, so it is in a relatively prioritized position in each combination corresponding to the objectives. Pin swapping has an obvious optimization effect on wns, so it is only used when optimizing wns. The cost required for netlist reconstruction (whether it is the running cost or the evaluation cost) is relatively high, so it is placed at the end in the combination of netlist transformation methods. After cell sizing and buffer insertion are subdivided into different fine-grained netlist transformation methods, their orders are also adjusted according to different optimization objectives.

[0078] S4. Traverse all the above-mentioned optimization objects, and use the combination of the target netlist transformation methods to optimize the currently traversed optimization object.

[0079] Specifically, in this step, the combination of the target netlist transformation methods obtained from step S3 will be applied to the optimization objects obtained from step S2 in the sorted order in turn. Each optimization object will be successively attempted to be optimized by the methods in the combination of the target netlist transformation methods.

[0080] Out of the trade-off between running time and optimization effect, in this embodiment, different optimization intensities and running times can be determined by selecting the way of extracting optimization objects in S2. For example, if the topological order is selected, more running time will be spent to obtain a greater tns gain, which is very effective for some high-frequency circuits.

[0081] In this step, it can be determined whether to continue executing the subsequent netlist transformation methods in the combination of netlist transformation methods when executing one netlist transformation method in the combination according to the importance degree or the requirement of running time. Therefore, this patent provides flexibility for the trade-off between running time and optimization objectives based on different scenarios and requirements.

[0082] Specifically, before executing this step, the method of this embodiment further includes configuring an optimization end condition, which can be that all methods are executed, or that the current optimization object is successfully optimized. When the optimization end condition is met, the optimization process of the current optimization object is ended, and the traversal proceeds to the next optimization object until all optimization objects are traversed.

[0083] For example, assume that the optimization end condition flag is HAR. When HAR is configured as true, it means that the optimization end condition is configured as the current optimization object being successfully optimized; when HAR is configured as false, it means that the optimization end condition is configured as all methods being executed.

[0084] When the optimization end condition is that all methods have been executed, in this step, the netlist transformation methods in the target netlist transformation method combination are successively used to optimize the current optimization object until all the netlist transformation methods in the combination have been used, and then the optimization process of the current optimization object ends.

[0085] When the optimization end condition is that the current optimization object is successfully optimized, in this step, the netlist transformation methods in the target netlist transformation method combination are successively used to optimize the current optimization object until the current optimization object is successfully optimized, and then the optimization process of the current optimization object ends.

[0086] By adopting the above steps, compared with the existing strategy, the running time of this embodiment is reduced and the expected optimization effect can be achieved. It is applicable to chip layouts with more nodes and more complex structures, and can meet design scenarios with more optimization goals. Specifically, it has the following advantages:

[0087] 1. Reduced running time. In this embodiment, by distinguishing different optimization goals, configuring different netlist transformation method combinations for different optimization goals, and providing the principle of exiting as long as there is an optimization, the attempt time for other useless netlist transformation methods can be greatly shortened.

[0088] At the same time, by integrating a variety of netlist transformation methods, the data of the optimization goal can converge faster, thereby reducing the running time in another aspect.

[0089] In addition, in this embodiment, by splitting the conventional netlist transformation methods (such as cell size transformation and buffer insertion) into finer granularity and adjusting these split netlist transformation methods through different optimization goals, the running time in conventional netlist transformation methods such as cell size transformation and buffer insertion is shortened.

[0090] 2. Higher flexibility. In this embodiment, the netlist transformation methods can be specified by the user to have different orders of combined netlist transformation methods through different optimization goals; and it is no longer limited to a few conventional netlist transformation methods such as cell size transformation, buffer insertion, cell cloning, and position re-placement.

[0091] 3. Better optimization effect. Compared with the existing strategy, this embodiment can fuse more netlist transformation methods, and the selection method for the optimization object is also more flexible. Therefore, the optimization effect is more obvious than that of other strategies.

[0092] This embodiment can be used for advanced process dimensions such as 7nm, and can also be used for process dimensions of 14nm and above, and can support the optimization of ultra-large-scale integrated circuits with up to millions of quantities.

[0093] This embodiment does not limit the type of the object to be optimized, including but not limited to logic units, clock gating units, multiplexers, etc., and can be used in any stage of the placement and routing process of physical design, including after placement, after clock synthesis, and after routing.

[0094] When adopting the method of this embodiment, the user can select according to needs: (1) the optimization goal, (2) the way to extract the object to be optimized, and (3) whether to continue running the subsequent netlist transformation method after the current netlist transformation method obtains the optimization effect when traversing and running the combination of netlist transformation methods. According to the above three configurations, the user can select different optimization goals and customize the configuration in terms of running time and optimization effect.

[0095] This embodiment can be used for circuits based on low-power design, aiming at optimizing power consumption, using a combination of netlist transformation methods for area or power; it can also be used for high-frequency circuits with high timing requirements, aiming at wns, using a combination of netlist transformation methods for wns.

[0096] Embodiment 2

[0097] This embodiment provides a physical design optimization system, as Figure 2 shown. The system includes an optimization goal acquisition module 11, an optimization object determination module 12, a method combination acquisition module 13, and an optimization module 14.

[0098] In this embodiment, the optimization goal acquisition module 11 is used to acquire the specified optimization goal; the optimization object determination module 12 is used to determine the object to be optimized that needs to be optimized from the netlist to be optimized based on the optimization goal; the method combination acquisition module 13 is used to acquire the corresponding target netlist transformation method combination based on the optimization goal, where different optimization goals are configured to correspond to different netlist transformation method combinations, and each netlist transformation method combination respectively includes a plurality of netlist transformation methods in a predetermined order; the optimization module 14 is used to traverse all the optimization objects and optimize the currently traversed optimization object by using the target netlist transformation method combination.

[0099] In an implementable manner, the optimization goals include total negative timing slack, worst negative timing slack, area, or power consumption.

[0100] In an implementable manner, the configuration process of the netlist transformation method combinations corresponding to different optimization goals is as follows:

[0101] Based on the optimization goal, select several corresponding netlist transformation methods;

[0102] Based on the optimization goal, combine the selected netlist transformation methods in a predetermined order to obtain the netlist transformation method combination corresponding to the optimization goal.

[0103] In an implementable manner, after selecting the netlist transformation method, it further includes performing fine-grained splitting on the selected part of the netlist transformation method (such as cell size transformation and buffer insertion).

[0104] In an implementable manner, when the optimization objective is the total negative timing margin, the corresponding netlist transformation method combination includes cell re-placement, cell cloning, multi-buffer insertion, cell size up-transformation, cell size down-transformation, single-buffer insertion, buffer insertion for solving high load, and netlist reconstruction methods executed in sequence;

[0105] When the optimization objective is the worst negative timing margin, the corresponding netlist transformation method combination includes pin swapping, cell re-placement, cell size up-transformation, cell size down-transformation, single-buffer insertion, multi-buffer insertion, buffer insertion for solving high load, and netlist reconstruction methods executed in sequence; and / or,

[0106] When the optimization objective is area or power consumption, the corresponding netlist transformation method combination includes cell re-placement, cell size down-transformation, buffer deletion, and netlist reconstruction methods executed in sequence.

[0107] In an implementable manner, when the optimization objective is area or power consumption, the optimization object determination module determines the optimization object from the netlist according to the topological order of the netlist;

[0108] When the optimization objective is the total negative timing margin, the optimization object determination module determines the optimization object from the critical path of the netlist according to the topological order, or determines the bottleneck optimization object from the critical path of the netlist as the optimization object;

[0109] When the optimization objective is the worst negative timing margin, the optimization object determination module determines the optimization object from the netlist according to the topological order of the netlist, or determines the bottleneck optimization object from the critical path of the netlist as the optimization object.

[0110] In an implementable manner, the system further includes an optimization end condition configuration module for configuring the optimization end condition before traversing the optimization object, and the optimization end condition is that all methods are executed, or the current optimization object is optimized successfully;

[0111] When the optimization end condition is that all methods are executed, the optimization module sequentially uses all the netlist transformation methods in the target netlist transformation method combination to optimize the current optimization object;

[0112] When the optimization end condition is that the current optimization object is successfully optimized, the optimization module sequentially optimizes the current optimization object by using the netlist transformation methods in the target netlist transformation method combination until the current optimization object is successfully optimized.

[0113] In this embodiment, different optimization objectives are distinguished, and different netlist transformation method combinations are configured for different optimization objectives. Since various netlist transformation methods can be fused in the combination, and the execution order of each netlist transformation method in the combination can be flexibly configured according to the optimization objective, the optimization method of the present invention can be flexibly adapted to different optimization objectives, has a better optimization effect than the optimization strategies in the prior art, and does not need to adopt the minimum cost network flow algorithm, reducing the time consumption.

[0114] Embodiment 3

[0115] This embodiment provides an electronic device, which can be presented in the form of a computing device (for example, it can be a server device), including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the physical design optimization method provided in Embodiment 1 can be implemented.

[0116] Figure 3 The hardware structure diagram of this embodiment is shown. As Figure 3 shown, the electronic device 30 specifically includes:

[0117] At least one processor 31, at least one memory 32, and a bus 33 for connecting different system components (including the processor 31 and the memory 32), where:

[0118] The bus 33 includes a data bus, an address bus, and a control bus.

[0119] The memory 32 includes volatile memory, such as a random access memory (RAM) 321 and / or a cache memory 322, and may further include a read-only memory (ROM) 323.

[0120] The memory 32 further includes a program / utilities 325 having a set (at least one) of program modules 324. Such program modules 324 include, but are not limited to: an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include the implementation of a network environment.

[0121] The processor 31 executes various functional applications and data processing by running the computer program stored in the memory 32, such as the steps of the physical design optimization method provided in Embodiment 1 of the present invention.

[0122] The electronic device 30 can further communicate with one or more external devices 34 (such as a keyboard, a pointing device, etc.). Such communication can be carried out through the input / output (I / O) interface 35. Also, the electronic device 30 can further communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through the network adapter 36. The network adapter 36 communicates with other modules of the electronic device 30 through the bus 33. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in combination with the electronic device 30, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID (redundant array of independent disks) systems, tape drives, and data backup storage systems, etc.

[0123] It should be noted that, although several units / modules or sub-units / modules of the electronic device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more of the above-described units / modules can be embodied in one unit / modules. Conversely, the features and functions of one unit / modules described above can be further divided and embodied by multiple unit / modules.

[0124] Embodiment 4

[0125] This embodiment provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the steps of the physical design optimization method provided in Embodiment 1 are implemented.

[0126] Among them, the more specific forms that the readable storage medium can adopt can include but not limited to: portable disks, hard disks, random access memories, read-only memories, erasable programmable read-only memories, optical storage devices, magnetic storage devices, or any suitable combination of the above.

[0127] In a possible implementation manner, the present invention can also be implemented in the form of a program product, which includes program code. When the program product runs on a terminal device, the program code is used to cause the terminal device to execute the steps of the physical design optimization method provided in Embodiment 1.

[0128] Among them, the program code for executing the present invention can be written in any combination of one or more programming languages. The program code can be executed entirely on the user device, partially on the user device, executed as an independent software package, partially on the user device and partially on a remote device, or entirely on a remote device.

[0129] Although the specific embodiments of the present invention have been described above, those skilled in the art should understand that this is only an example, and the protection scope of the present invention is defined by the appended claims. Without departing from the principles and essence of the present invention, those skilled in the art can make various changes or modifications to these embodiments, but these changes and modifications all fall within the protection scope of the present invention.

Claims

1. A physical design optimization method, characterized in that Including: Obtain a specified optimization objective; Based on the optimization objective, determine an optimization object to be optimized from the netlist to be optimized; Based on the optimization objective, obtain a corresponding target netlist transformation method combination, wherein different optimization objectives are configured to correspond to different netlist transformation method combinations, and each netlist transformation method combination respectively includes multiple netlist transformation methods in a predetermined order; Traverse all the optimization objects, and use the target netlist transformation method combination to optimize the currently traversed optimization object.

2. The physical design optimization method according to claim 1, wherein The optimization objective includes the total negative timing margin, the worst negative timing margin, area, or power consumption.

3. The physical design optimization method according to claim 2, wherein The configuration process of the netlist transformation method combinations corresponding to different optimization objectives is as follows: Based on the optimization objective, select several corresponding netlist transformation methods; Based on the optimization objective, combine the selected netlist transformation methods in a predetermined order to obtain a netlist transformation method combination corresponding to the optimization objective.

4. The physical design optimization method according to claim 3, characterized in that After selecting the netlist transformation methods, it further includes performing fine-grained splitting on some of the selected netlist transformation methods.

5. The physical design optimization method according to claim 4, characterized in that When the optimization objective is the total negative timing margin, the corresponding netlist transformation method combination includes unit re-placement, unit cloning, multi-buffer insertion, unit size up-transformation, unit size down-transformation, single-buffer insertion, buffer insertion for solving high load, and netlist reconstruction methods executed in sequence; When the optimization objective is the worst negative timing margin, the corresponding netlist transformation method combination includes pin swapping, unit re-placement, unit size up-transformation, unit size down-transformation, single-buffer insertion, multi-buffer insertion, buffer insertion for solving high load, and netlist reconstruction methods executed in sequence; and / or, When the optimization objective is area or power consumption, the corresponding netlist transformation method combination includes unit re-placement, unit size down-transformation, buffer deletion, and netlist reconstruction methods executed in sequence.

6. The physical design optimization method according to claim 2, characterized in that, When the optimization objective is area or power consumption, determine the optimization object from the netlist according to the topological order of the netlist; When the optimization objective is the total negative timing margin, determine the optimization object from the critical path of the netlist according to the topological order, or determine the bottleneck optimization object from the critical path of the netlist as the optimization object; When the optimization objective is the worst negative timing margin, determine the optimization object from the netlist according to the topological order of the netlist, or determine the bottleneck optimization object from the critical path of the netlist as the optimization object.

7. The physical design optimization method according to claim 1, characterized in that Before traversing the optimization objects, the method further includes configuring an optimization end condition, and the optimization end condition is that all methods are executed, or the current optimization object is successfully optimized; When the optimization end condition is that all methods are executed, the optimizing the currently traversed optimization object includes: sequentially using all the netlist transformation methods in the target netlist transformation method combination to optimize the current optimization object; When the optimization end condition is that the current optimization object is successfully optimized, the optimization of the currently traversed optimization object includes: sequentially optimizing the current optimization object by using the netlist transformation methods in the target netlist transformation method combination until the current optimization object is successfully optimized.

8. A physical design optimization system, characterized in that, including: an optimization target acquisition module, configured to acquire a specified optimization target; an optimization object determination module, configured to determine an optimization object to be optimized from the netlist to be optimized based on the optimization target; a method combination acquisition module, configured to acquire a corresponding target netlist transformation method combination based on the optimization target, wherein different optimization targets are configured to correspond to different netlist transformation method combinations, and each netlist transformation method combination respectively includes a plurality of netlist transformation methods in a predetermined order; an optimization module, configured to traverse all the optimization objects and optimize the currently traversed optimization object by using the target netlist transformation method combination.

9. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and capable of running on the processor, characterized in that, When the processor executes the computer program, the steps of the physical design optimization method according to any one of claims 1-7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, the steps of the physical design optimization method according to any one of claims 1 to 7 are implemented.

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