Display panel and display device

Abstract

The invention provides a display panel and a display device.The display panel comprises a plurality of pixel driving circuits and a plurality of reset signal lines, at least one reset signal line is arranged between every two adjacent rows of pixel driving circuits, the reset signal lines are electrically connected to the two adjacent rows of pixel driving circuits, and therefore the reset signal lines are electrically connected to the pixel driving circuits; according to the display panel, the pixel driving circuits are arranged in the row direction, so that the two adjacent rows of pixel driving circuits share the same reset signal line, the number of the reset signal lines extending in the row direction can be reduced, the space occupied by the reset signal lines in the column direction is reduced, more space can be used for arranging the pixel driving circuits, and the pixel density of the display panel can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] With the development of display technologies, display panels have been widely used in people's lives, such as the display panels of mobile phones, computers, and televisions. With the progress of life and the development of technologies, people not only have higher and higher requirements for the display performance of display panels, but also have higher and higher requirements for the resolution of display panels.

[0003] However, in an organic light-emitting diode display panel, since each light-emitting device requires a complex pixel driving circuit to drive, the number of wirings in the organic light-emitting diode display panel is larger and more dense, resulting in a lower pixel density of the organic light-emitting diode display panel.

[0004] Therefore, it is necessary to provide a display panel and a display device to improve this defect. Summary of the Invention

[0005] Embodiments of the present application provide a display panel and a display device, which can improve the pixel density of the display panel.

[0006] To achieve the above object, according to a first aspect of the present application, a display panel is provided, including a plurality of pixel driving circuits, a plurality of reset signal lines, a first power supply signal line, a second power supply signal line, and a light-emitting device. The reset signal line has a fixed potential. The plurality of reset signal lines include a first reset signal line, a second reset signal line, and a third reset signal line. The pixel driving circuit includes:

[0007] A driving transistor, the driving transistor and the light-emitting device are connected in series between the first power supply signal line and the second power supply signal line;

[0008] A first reset transistor, electrically connected between the driving gate of the driving transistor and the first reset signal line;

[0009] A second reset transistor, electrically connected between the first electrode of the driving transistor and the second reset signal line; and

[0010] A third reset transistor, electrically connected between the second electrode of the driving transistor and the third reset signal line;

[0011] Wherein, at least one of the first reset signal line, the second reset signal line, and the third reset signal line is disposed between adjacent two rows of the pixel driving circuits and is electrically connected to the adjacent two rows of the pixel driving circuits.

[0012] Optionally, at least two of the first reset signal line, the second reset signal line, and the third reset signal line are disposed between the same adjacent two rows of the pixel driving circuits.

[0013] Optionally, the first reset signal line and the second reset signal line are respectively disposed between different adjacent two rows of the pixel driving circuits, and the second reset signal line and the third reset signal line are disposed between the same adjacent two rows of the pixel driving circuits.

[0014] Optionally, the first reset signal line (VI_GATE) is disposed between the (2n)th row of pixel driving circuits and the (2n + 1)th row of pixel driving circuits, and the second reset signal line and the third reset signal line are disposed between the (2n - 1)th row of pixel driving circuits and the 2nth pixel driving circuit, where n is an integer greater than or equal to 1.

[0015] Optionally, the distance between the second reset signal line and the nearest third reset signal line is less than the distance between two adjacent second reset signal lines.

[0016] Optionally, the adjacent two rows of pixel driving circuits electrically connected to the same reset signal line are symmetrically disposed.

[0017] Optionally, the adjacent two rows of pixel driving circuits electrically connected to the same reset signal line are connected by a connecting portion, and the connecting portion is asymmetrically disposed with respect to the reset signal line.

[0018] Optionally, the adjacent two rows of pixel driving circuits electrically connected to the same second reset signal line are symmetrically disposed with respect to the second reset signal line;

[0019] Alternatively, the adjacent two rows of pixel driving circuits electrically connected to the same third reset signal line are symmetrically disposed with respect to the third reset signal line.

[0020] Optionally, the display panel includes an active layer, and the active layer includes a second reset active portion of the second reset transistor, a third reset active portion of the third reset transistor, a first connecting portion, and a second connecting portion;

[0021] Wherein, the second reset active part of the second reset transistor is connected to the second reset active part of the second reset transistor in the adjacent row of the pixel driving circuit through the first connection part, and the two second reset active parts and the first connection part are connected to each other to be continuously arranged; the third reset active part of the third reset transistor is connected to the third reset active part of the third reset transistor in the adjacent row of the pixel driving circuit through the second connection part, and the two third reset active parts and the second connection part are connected to each other to be continuously arranged.

[0022] Optionally, the display panel includes multiple conductive layers, and multiple first reset signal lines are respectively arranged in at least two of the conductive layers, and the first reset signal lines located in different conductive layers are connected in parallel; multiple second reset signal lines are respectively arranged in at least three of the conductive layers, and the second reset signal lines located in different conductive layers are connected in parallel; multiple third reset signal lines are respectively arranged in at least two of the conductive layers, and the third reset signal lines located in different conductive layers are connected in parallel;

[0023] Wherein, the number of the conductive layers provided with the first reset signal lines is less than the number of the conductive layers provided with the second reset signal lines; the number of the conductive layers provided with the third reset signal lines is less than the number of the conductive layers provided with the second reset signal lines.

[0024] Optionally, the multiple conductive layers include:

[0025] A first gate layer, disposed on the active layer;

[0026] A second gate layer, disposed on the first gate layer;

[0027] A first source-drain layer, disposed on the second gate layer;

[0028] Wherein, the second gate layer includes multiple second reset signal lines, the first source-drain layer includes the first reset signal line, multiple second reset signal lines and the third reset signal line, and the first reset signal line, the second reset signal line and the third reset signal line are arranged at intervals along the column direction.

[0029] Optionally, both the second reset active part and the third reset active part extend in a direction perpendicular to the extension direction of the first reset signal line, and along the thickness direction of the display panel, the second reset active part partially overlaps with the third reset signal line, and the third reset active part partially overlaps with the second reset signal line.

[0030] Optionally, the pixel driving circuit further includes a capacitor. A first electrode plate of the capacitor is electrically connected to the first power signal line, a second electrode plate of the capacitor is electrically connected to a driving gate of the driving transistor, and the second gate layer includes the second electrode plate;

[0031] Among them, in two adjacent pixel driving circuits, the second electrode plates in one of the pixel driving circuits are arranged to be disconnected from the second electrode plates in the other pixel driving circuit.

[0032] Optionally, the first source-drain layer includes the first power signal line. The first power signal line includes a plurality of first horizontal portions and a first inclined portion connected between two adjacent first horizontal portions. The first horizontal portions are arranged parallel to the extending direction of the first reset signal line, and the first inclined portion forms an obtuse angle with the first horizontal portion.

[0033] Optionally, the display panel further includes a first scan signal line and a second scan signal line. The pixel driving circuit further includes a switching transistor. The first scan signal line is electrically connected to a second reset gate of the second reset transistor, and the second scan signal line is electrically connected to a switching gate of the switching transistor;

[0034] Among them, the first source-drain layer includes the second scan signal line. The second scan signal line includes a plurality of second horizontal portions and a second inclined portion connected between two adjacent second horizontal portions. The second horizontal portions are arranged parallel to the extending direction of the first reset signal line, and the second inclined portion forms an obtuse angle with the second horizontal portion.

[0035] According to a second aspect of the present application, a display device is provided, including the display panel as described above.

[0036] In the display panel of the embodiment of the present application, by arranging at least one of the first reset signal line, the second reset signal line, and the third reset signal line between two adjacent rows of pixel driving circuits and electrically connecting it to two adjacent rows of pixel driving circuits, so that two adjacent rows of pixel driving circuits share the same reset signal line, in this way, the number of reset signal lines extending in the row direction can be reduced, thereby reducing the space occupied by the reset signal lines in the column direction. Therefore, there can be more space for arranging pixel driving circuits, and thus the pixel density of the display panel can be improved.

[0037] Other features and advantages of the present application will be described in detail in the subsequent specific implementation part. Description of the Drawings

[0038] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0039] To more comprehensively understand the present application and its beneficial effects, the following description will be made in conjunction with the drawings, where the same reference numerals in the following description represent the same parts.

[0040] Figure 1 Top view of the display panel provided by the embodiment of the present application;

[0041] Figure 2 Schematic layout diagram of the pixel driving circuit and signal lines in the display panel provided by the embodiment of the present application;

[0042] Figure 3 Circuit diagram of the pixel driving circuit provided by the embodiment of the present application;

[0043] Figure 4 Schematic diagram of the film layer structure of the display panel provided by the embodiment of the present application;

[0044] Figure 5 Film layer diagram of the active layer in the display panel provided by the embodiment of the present application;

[0045] Figure 6 Film layer diagram of the first gate layer in the display panel provided by the embodiment of the present application;

[0046] Figure 7 Stacked layer diagram of the active layer and the first gate layer in the display panel of the present application;

[0047] Figure 8 Film layer diagram of the second gate layer in the display panel provided by the embodiment of the present application;

[0048] Figure 9 Stacked layer diagram of the active layer, the first gate layer and the second gate layer in the display panel of the present application;

[0049] Figure 10 Film layer diagram of the first source-drain layer in the display panel provided by the embodiment of the present application;

[0050] Figure 11 Stacked layer diagram of the active layer, the first gate layer, the second gate layer and the first source-drain layer in the display panel of the present application;

[0051] Figure 12 Schematic diagram of the symmetric arrangement of the pixel driving circuit in the display panel provided by the embodiment of the present application;

[0052] Figure 13 Schematic diagram of the display device provided for the embodiment of the present application. Specific embodiments

[0053] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present application.

[0054] The embodiments of the present application provide a display panel and a display device. The display panel includes a plurality of pixel driving circuits and a plurality of reset signal lines. The display panel includes a plurality of pixel driving circuits, a plurality of reset signal lines, a first power supply signal line, a second power supply signal line, and a light-emitting device. The plurality of pixel driving circuits are arranged in an array in the row direction and the column direction. The reset signal lines extend in the row direction. The reset signal lines have a fixed potential. The plurality of reset signal lines include a first reset signal line, a second reset signal line, and a third reset signal line. The pixel driving circuit includes: a driving transistor, the driving transistor and the light-emitting device are connected in series between the first power supply signal line and the second power supply signal line; a first reset transistor, electrically connected between the driving gate of the driving transistor and the first reset signal line; a second reset transistor, electrically connected between the first electrode of the driving transistor and the second reset signal line; and a third reset transistor, electrically connected between the second electrode of the driving transistor and the third reset signal line. At least one of the first reset signal line, the second reset signal line, and the third reset signal line is disposed between adjacent two rows of pixel driving circuits and is electrically connected to the adjacent two rows of pixel driving circuits.

[0055] In the embodiments of the present application, by disposing at least one of the first reset signal line, the second reset signal line, and the third reset signal line between adjacent two rows of pixel driving circuits and electrically connecting the reset signal line to the adjacent two rows of pixel driving circuits, so that the adjacent two rows of pixel driving circuits share the same reset signal line, thus the number of reset signal lines extending in the row direction can be reduced, thereby reducing the space occupied by the reset signal lines in the column direction. Therefore, more space can be used to arrange the pixel driving circuits, and thus the pixel density of the display panel can be improved.

[0056] Please refer to Figure 1 , Figure 1A top view of a display panel provided by an embodiment of the present application. The display panel 100 includes a display area AA and a border area NA, and the border area NA is disposed around the display area AA. The display panel includes a plurality of sub-pixels, and each sub-pixel includes a light-emitting device and a pixel driving circuit electrically connected to the light-emitting device. Both the light-emitting device and the pixel driving circuit are disposed in the display area AA.

[0057] Please refer to Figure 2 , Figure 2 A schematic layout diagram of pixel driving circuits and signal lines in the display panel provided by an embodiment of the present application. A plurality of pixel driving circuits 10 are arranged in an array along the row direction X and the column direction Y. The reset signal line VI extends along the row direction X, and a plurality of reset signal lines VI are arranged at intervals along the column direction Y.

[0058] It should be noted that in the following embodiments, the included angle between the row direction X and the column direction Y is greater than 0° and less than or equal to 90°. For example, the row direction X is horizontal and the column direction Y is vertical.

[0059] Please refer to Figure 2 , at least one reset signal line VI is disposed between two adjacent rows of pixel driving circuits 10 and is electrically connected to two non-adjacent rows of pixel driving circuits 10, so that two adjacent rows of pixel driving circuits 10 share the same reset signal line VI. In this way, the number of reset signal lines VI extending along the row direction X can be reduced, thereby reducing the space occupied by the reset signal lines VI in the column direction Y. Therefore, more space can be used to dispose the pixel driving circuits 10 and the light-emitting devices EL, and thus the pixel density of the display panel can be improved and the display effect of the display panel can be improved.

[0060] In some embodiments, the reset signal line VI has a fixed potential, the signal line VI is a DC signal line, and the level of the DC signal line is constant. By sharing the same DC signal line between two adjacent rows of pixel driving circuits 10, the driving timing of the pixel driving circuit does not need to be changed. Thus, the pixel density of the display panel can be improved and the display effect of the display panel can be improved while reducing the design difficulty and manufacturing cost of the display panel.

[0061] Please refer to Figure 3 , Figure 3The circuit diagram of the pixel driving circuit provided by the embodiment of the present application. The reset signal line VI includes a first reset signal line VI_GATE. The pixel driving circuit 10 includes a driving transistor T1 and a first reset transistor T4. The first electrode of the driving transistor T1 is electrically connected to the first node A, the second electrode of the driving transistor T1 is electrically connected to the second node B, and the driving gate of the driving transistor T1 is electrically connected to the third node Q. The first electrode of the first reset transistor T4 is electrically connected to the first reset signal line VI_GATE, the second electrode of the first reset transistor T4 is electrically connected to the third node Q, and the first reset gate of the first reset transistor T4 is electrically connected to the reset control signal line RST.

[0062] Please refer to Figure 2 and Figure 3 , the first reset signal line VI_GATE is electrically connected to the first electrodes of the first reset transistors T4 in two adjacent rows of pixel driving circuits 10. By electrically connecting the first electrodes of the first reset transistors T4 in two adjacent rows of pixel driving circuits 10 to the same first reset signal line VI_GATE, the number of first reset signal lines VI_GATE can be reduced, so that the space occupied by the first reset signal line VI_GATE in the column direction Y can be reduced. Therefore, more space can be used to arrange the pixel driving circuit 10 and the light-emitting device, thereby improving the pixel density of the display panel and the display effect of the display panel.

[0063] It should be noted that in the embodiment of the present application, the first electrode of the transistor is one of the source electrode and the drain electrode, the second electrode is the other of the source electrode and the drain electrode, and the first electrode and the second electrode of each transistor can be the same or different.

[0064] In some embodiments, please refer to Figure 3, the display panel includes a first scan signal line Scan1 and a second scan signal line Scan2. The pixel driving circuit has a fourth node C. The reset signal line VI includes a second reset signal line VI_ANO and a third reset signal line VI_T8. The pixel driving circuit 10 includes a second reset transistor T7 and a third reset transistor T8. The first electrode of the second reset transistor T7 is electrically connected to the second reset signal line VI_ANO. The second electrode of the second reset transistor T7 is electrically connected to the fourth node C. The second reset gate of the second reset transistor T7 is electrically connected to the first scan signal line Scan1. The first electrode of the third reset transistor T8 is electrically connected to the third reset signal line VI_T8. The second electrode of the third reset transistor T8 is electrically connected to the first node A. The third reset gate of the third reset transistor VI_T8 is electrically connected to the first scan signal line Scan1. In some other embodiments, the third reset gate of the third reset transistor VI_T8 may also be electrically connected to the second scan signal line Scan2.

[0065] Please refer to Figure 2 and Figure 3 , the second reset signal line VI_ANO is electrically connected to the first electrodes of the second reset transistors T7 in two adjacent rows of the pixel driving circuits 10, and the third reset signal line VI_T8 is electrically connected to the first electrodes of the third reset transistors T8 in two adjacent rows of the pixel driving circuits 10. By electrically connecting the first electrodes of the second reset transistors T7 in two adjacent rows of the pixel driving circuits 10 to the same second reset signal line VI_ANO, and electrically connecting the first electrodes of the third reset transistors T8 in two adjacent rows of the pixel driving circuits 10 to the same third reset signal line VI_T8, the number of the second reset signal line VI_ANO and the third reset signal line VI_T8 can be reduced, so that the space in the column direction Y occupied by the second reset signal line VI_ANO and the third reset signal line VI_T8 can be reduced. Therefore, more space can be used to arrange the pixel driving circuits 10 and the light-emitting devices, and thus the pixel density of the display panel can be further increased, and the display effect of the display panel can be improved.

[0066] In some embodiments, please refer to Figure 3, the pixel driving circuit 10 further includes a switching transistor T2, a compensating transistor T3, a first light-emitting control transistor T5 and a second light-emitting control transistor T6, and a capacitor C1. A first electrode of the switching transistor T2 is electrically connected to the data signal line DATA, a second electrode of the switching transistor T2 is electrically connected to the first node A, and a switching gate of the switching transistor T2 is electrically connected to the second scan signal line Scan2; a first electrode of the compensating transistor T3 is electrically connected to the third node Q, a second electrode of the compensating transistor T3 is electrically connected to the second node B, and a compensating gate of the compensating transistor T3 is electrically connected to the second scan signal line Scan2; a first electrode of the first light-emitting control transistor T5 is electrically connected to the first power supply signal line VDD, a second electrode of the first light-emitting control transistor T5 is electrically connected to the first node A, and a first light-emitting control gate of the first light-emitting control transistor T5 is electrically connected to the light-emitting control signal line EM; a first electrode of the second light-emitting control transistor T6 is electrically connected to the second node B, a second electrode of the second light-emitting control transistor T6 is electrically connected to the fourth node C, and a second light-emitting control gate of the second light-emitting control transistor T6 is electrically connected to the light-emitting control signal line EM; a first plate of the capacitor C1 is electrically connected to the first power supply signal line VDD, and a second plate of the capacitor C is electrically connected to the third node Q.

[0067] In some embodiments, referring to Figure 3 , the display panel 100 further includes a light-emitting device EL. An anode of the light-emitting device EL is electrically connected to the fourth node C, and a cathode of the light-emitting device EL is electrically connected to the second power supply signal line VSS.

[0068] In an embodiment of the present application, the first power supply signal line VDD is used to provide a constant voltage high-level signal to the pixel driving circuit 10, and the second power supply signal line VSS is used to provide a constant voltage low-level signal to the pixel driving circuit 10.

[0069] In some embodiments, at least two of the first reset signal line VI_GATE, the second reset signal line VI_ANO, and the third reset signal line VI_T8 are disposed between the same adjacent two rows of pixel driving circuits 10. For example, the first reset signal line VI_GATE, the second reset signal line VI_ANO, and the third reset signal line VI_T8 are all disposed between the same adjacent two rows of pixel driving circuits 10, that is, the first reset signal line VI_GATE, the second reset signal line VI_ANO, and the third reset signal line VI_T8 are simultaneously disposed between the adjacent two rows of pixel driving circuits 10; or, the first reset signal line VI_GATE and the second reset signal line VI_GATE are disposed between one adjacent two rows of pixel driving circuits 10, and the third reset signal line VI_T8 is disposed between another adjacent two rows of pixel driving circuits 10. In this way, the space in the column direction Y occupied by the first reset signal line VI_GATE, the second reset signal line VI_ANO, and the third reset signal line VI_T8 can be reduced simultaneously. Therefore, more space can be used to dispose the pixel driving circuits 10 and the light-emitting devices, thereby further improving the pixel density of the display panel and the display effect of the display panel.

[0070] In some embodiments, the first reset signal line VI_GATE and the second reset signal line VI_ANO are respectively disposed between different adjacent two rows of pixel driving circuits, and the second reset signal line VI_ANO and the third reset signal line VI_T8 are disposed between the same adjacent two rows of pixel driving circuits.

[0071] In some embodiments, as Figure 2 shown, the first reset signal line VI_GATE is disposed between the (2n)-th row of pixel driving circuits and the (2n + 1)-th row of pixel driving circuits, and the second reset signal line VI_ANO and the third reset signal line VI_T8 are disposed between the (2n - 1)-th row of pixel driving circuits and the (2n)-th row of pixel driving circuits, where n is an integer greater than or equal to 1. That is, the first reset signal line VI_GATE is disposed between the odd-numbered row and the even-numbered row of pixel driving circuits and is electrically connected to the even-numbered row and the odd-numbered row of pixel driving circuits. The second reset signal line VI_ANO and the third reset signal line VI_T8 are disposed between the odd-numbered row and the even-numbered row of pixel driving circuits and are electrically connected to the odd-numbered row and the even-numbered row of pixel driving circuits. In this way, the space in the column direction Y occupied by the first reset signal line VI_GATE, the second reset signal line VI_ANO, and the third reset signal line VI_T8 can also be reduced simultaneously. Therefore, more space can be used to dispose the pixel driving circuits 10 and the light-emitting devices, thereby further improving the pixel density of the display panel and the display effect of the display panel.

[0072] Next, for Figure 3The structure shown describes the film stack structure of the pixel driving circuit of the present application.

[0073] In some embodiments, refer to Figure 4 , Figure 4 which is a schematic diagram of the film stack structure of the display panel provided by the embodiment of the present application. The display panel 100 includes a substrate 101, a barrier layer 15 disposed on the substrate 101, a buffer layer 16 disposed on the barrier layer 15, an active layer 11 disposed on the buffer layer 16, a first gate insulating layer 17 disposed on the active layer 11, a first gate layer 12 disposed on the first gate insulating layer 17, a second gate insulating layer 18 disposed on the first gate layer 12, a second gate layer 13 disposed on the second gate insulating layer 18, a first interlayer dielectric layer 19 disposed on the second gate layer 13, a first source / drain layer 14 disposed on the first interlayer dielectric layer 19, a second interlayer dielectric layer 20 disposed on the first source / drain layer 14, a second source / drain layer 21 disposed on the second interlayer dielectric layer 20, and a planarization layer 22 disposed on the second source / drain layer 21.

[0074] In some embodiments, refer to Figure 4 , the substrate 101 may be a single-layer substrate formed of an organic material or an inorganic material, or the substrate 101 may also be a double-layer or multi-layer substrate formed of at least one of an organic material and an inorganic material. Among them, the organic material may be, but is not limited to, polyimide, and the inorganic material may be, but is not limited to, glass.

[0075] As Figure 4 shown, the barrier layer 15 is disposed on the substrate 101, and the buffer layer 16 is disposed on the barrier layer 15. Both the barrier layer 15 and the buffer layer 16 may be a single-layer structure or a stacked structure formed of at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0076] As Figure 4 shown, the active layer 11 is disposed on the buffer layer 16. The material of the active layer 11 includes a metal oxide semiconductor material or a silicon semiconductor material. The metal oxide semiconductor material may specifically be indium gallium zinc oxide, and the silicon semiconductor material may specifically be amorphous silicon or low-temperature polycrystalline silicon.

[0077] In the embodiment of the present application, the material of the active layer 11 includes low-temperature polycrystalline silicon.

[0078] As Figure 4As shown, a first gate insulating layer 17, a second gate insulating layer 18, a first interlayer dielectric layer 19, and a second interlayer dielectric layer 20 are respectively disposed on corresponding metal layers or active layers, so that the metal layers or active layers of different layers are separated and insulated. The first gate insulating layer 17, the second gate insulating layer 18, the first interlayer dielectric layer 19, and the second interlayer dielectric layer 20 may be a single-layer structure or a stacked structure formed by at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0079] As Figure 4 shown, a first gate layer 12, a second gate layer 13, a first source / drain layer 14, and a second source / drain layer 21 are respectively disposed on corresponding insulating layers or interlayer dielectric layers. The first gate layer 12, the second gate layer 13, the first source / drain layer 14, and the second source / drain layer 21 may be a single-layer structure formed by at least one of copper, molybdenum, titanium, aluminum, silver, etc., or may be a stacked structure of two or more layers formed by the above at least two metal materials.

[0080] As Figure 4 shown, a planarization layer 22 is disposed on the second source / drain layer 21. The material of the planarization layer 22 may be at least one inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride, or may be an organic insulating material having leveling properties.

[0081] As Figure 4 shown, the display panel further includes a light-emitting device layer 30. The light-emitting device layer 30 is disposed on a side of the planarization layer 22 away from the second source / drain layer 21. The light-emitting device layer 30 includes an anode layer 31 disposed on the planarization layer 22, a pixel definition layer 32 disposed on the anode layer 31, a spacer layer 33 disposed on the pixel definition layer 32, a light-emitting material layer disposed on the pixel definition layer 32, and a cathode layer (not shown in the figure).

[0082] Please refer to Figure 5 , Figure 5 which is a film layer diagram of the active layer in the display panel provided by the embodiment of the present application. The active layer 11 includes a driving active part T1A of a driving transistor T1A, a switching active part T2A of a switching transistor T2, a compensating active part T3A of a compensating transistor T3, a first reset active part T4A of a first reset transistor T4, a first light-emitting control active part T5A of a first light-emitting control transistor T5, a second light-emitting control active part T6A of a second light-emitting control transistor T6, a second reset active part T7A of a second reset transistor T7, and a third reset active part T8A of a third reset transistor T8.

[0083] As Figure 5As shown, the driving active part T1A, the switching active part T2A, the compensating active part T3A, the first reset active part T4A, the first light-emitting control active part T5A, the second light-emitting control active part T6A, and the second reset active part T7A are connected to each other, and the third reset active part T8A is separately arranged from other active parts. The switching active part T2A, the first light-emitting control active part T5A, the second light-emitting control active part T6A, and the second reset active part T7A are all strip-shaped and extend along the column direction Y. The driving active part T1A is in a "ji" shape and is arranged between the first light-emitting control active part T5A and the second light-emitting control active part T6A. The first end of the switching active part TA2, the first end of the driving active part T1A, and the first end of the first light-emitting control transistor T5A are all connected to the first connection point P1. The second end of the driving active part T1A is connected to the first end of the second light-emitting control active part T6A at the second connection point P2. The second end of the first light-emitting control active part T5A is connected to the second end of the second light-emitting control active part T6A at the third connection point P3.

[0084] In this embodiment, the first connection point P1 is the first node A, the second connection point P2 is the second node B, and the third connection point P3 is the position where the anode of the light-emitting device EL is located, that is, the third connection point P3 is the fourth node C.

[0085] As Figure 5 shown, the active layer 11 further includes a first connection part 111 and a second connection part 112. The second reset active part T7A of the second reset transistor T7 is connected to the second reset active part T7A of the second reset transistor T7 in an adjacent row of pixel driving circuits through the first connection part 111. The two second reset active parts T7A and the first connection part 111 are connected to each other to be continuously arranged. The third reset active part T8A of the third reset transistor T8 is connected to the third reset active part T8A of the third reset transistor T8 in an adjacent row of pixel driving circuits through the second connection part 112. The two third reset active parts T8A and the second connection part 112 are connected to each other to be continuously arranged.

[0086] It should be noted that by sharing a second reset signal line VI_ANO and a third reset signal line VI_T8 between adjacent two rows of pixel driving circuits, adjacent two second reset active parts T7A in the adjacent two rows of pixel driving circuits are directly connected, and adjacent two third reset active parts T8A in the adjacent two rows of pixel driving circuits are directly connected. In this way, only one via hole is needed to electrically connect the second reset active part T7A of two second reset transistors T7 in adjacent two rows to the second reset signal line VI_ANO; similarly, only one via hole is needed to electrically connect the third reset active part T8A of two third reset transistors T8 in adjacent two rows to the third reset signal line VI_T8. Therefore, the number of via holes in the pixel driving circuit can be reduced, which can not only improve the yield of the display panel, improve the stability of the display panel, but also help to reduce the area of the pixel driving circuit, thereby improving the pixel density of the display panel.

[0087] Please refer to Figure 6 , Figure 6 which is a layer diagram of the first gate layer in the display panel provided by the embodiment of the present application. The first gate layer 12 includes a driving gate T1G of a driving transistor T1, a switching gate T2G of a switching transistor T2, a compensation gate T3G of a compensation transistor T3, a first reset gate T4G of a first reset transistor T4, a first light-emitting control gate T5G of a first light-emitting control transistor T5, a second light-emitting control gate T6G of a second light-emitting control transistor T6, a second reset gate T7G of a second reset transistor T7, a third reset gate T8G of a third reset transistor T8, a first electrode plate C11 of a capacitor C1, a reset control signal line RST, a first scan signal line Scan1, and a light-emitting control signal line EM.

[0088] As Figure 6 shown, both the first scan signal line Scan1 and the light-emitting control signal line EM extend along the row direction X. The first scan signal line Scan1 and the light-emitting control signal line EM are arranged at intervals along the column direction Y. The driving gate T1G and the first electrode plate C11 are both arranged on the side of the light-emitting control signal line EM away from the first scan signal line Scan1. The first light-emitting control gate T5G is connected to the second light-emitting control gate T6G and the light-emitting control signal line EM. The switching gate T2G is connected to the second reset gate T7G and the first scan signal line Pscan1.

[0089] In this embodiment, the driving gate T1G can be reused as the first electrode plate C11 of the capacitor C1, the light-emitting control signal line EM can directly serve as the first light-emitting control gate T5G and the second light-emitting control gate T6G, and the first scan signal line Scan1 can directly serve as the second reset gate T7G and the third reset gate T8G.

[0090] As shown in Figure 7 the figure, Figure 7 is a stacked diagram of the active layer and the first gate layer in the display panel of the present application. The driving gate T1G partially overlaps with the driving active part T1A. The overlapping part of the driving gate T1G and the active part T1A is the channel of the driving active part T1A; the switching gate T2G partially overlaps with the switching active part T2A. The overlapping part of the switching gate T2G and the switching active part T2A is the channel of the switching active part T2A; the compensation gate T3G partially overlaps with the compensation active part T3A. The overlapping part of the compensation gate T3G and the compensation active part T3A is the channel of the compensation active part T3A; the first reset gate T4G partially overlaps with the first reset active part T4A. The overlapping part of the first reset gate T4G and the first reset active part T4A is the channel of the first reset active part T4A; the first light-emitting control gate T5G partially overlaps with the first light-emitting control active part T5A. The overlapping part of the first light-emitting control gate T5G and the first light-emitting control active part T5A is the channel of the first light-emitting control active part T5A; the second light-emitting control gate T6G partially overlaps with the second light-emitting control active part T6A. The overlapping part of the second light-emitting control gate T6G and the second light-emitting control active part T6A is the channel of the second light-emitting control active part T6A; the second reset gate T7G partially overlaps with the second reset active part T7A. The overlapping part of the second reset gate T7G and the second reset active part T7A is the channel of the second reset active part T7A; the third reset gate T8G partially overlaps with the third reset active part T8A. The overlapping part of the third reset gate T8G and the third reset active part T8A is the channel of the third reset active part T8A.

[0091] Please refer to Figure 8 , Figure 8 which is a film layer diagram of the second gate layer in the display panel provided by the embodiment of the present application. The second gate layer 13 includes the second electrode plate C12 of the capacitor C1 and the second reset signal line VI_ANO.

[0092] As shown in Figure 8 the figure, the second electrode plate C12 has a block structure, and at least part of the top corners of the second electrode plate C12 can be chamfered. The second reset signal line VI_ANO extends along the row direction X.

[0093] As shown in Figure 8 the figure, in the row direction X, in two adjacent pixel driving circuits, the second electrode plate C12 in one pixel driving circuit is disconnected from the second electrode plate C12 in the other pixel driving circuit. By disconnecting the second electrode plates C12 in two adjacent pixel driving circuits, the overlapping area between the second electrode plate C12 and the conductive patterns in other film layers can be reduced, thereby reducing the parasitic capacitance between the second electrode plate C12 and the conductive patterns in other film layers, and thus the response speed and stability of the pixel driving circuit can be improved.

[0094] Please refer to Figures 7 to 9 , Figure 9 which is a stacked diagram of the active layer, the first gate layer, and the second gate layer in the display panel of this application. The area of the second electrode plate C12 is larger than that of the first electrode plate C11, and the positive projection of the second electrode plate C12 on the first electrode plate C11 covers the first electrode plate C11. Both the second reset active part T7A and the third reset active part T8A are arranged to extend along the column direction Y. Along the thickness direction of the display panel, the third reset active part T8A partially overlaps with the second reset signal line VI_ANO.

[0095] In some examples, please refer to Figure 8 where the second reset signal line VI_ANO includes a first sub-reset signal line VI_ANO1, and the first sub-reset signal line VI_ANO is arranged on the second gate layer 13.

[0096] As Figure 10 shown Figure 10 which is a film layer diagram of the first source-drain layer in the display panel provided by the embodiment of this application. The first source-drain layer 14 includes a first reset signal line VI_GATE, a reset control signal line RST, a second scan signal line Scan2, a first power supply signal line VDD, a second reset signal line VI_ANO, a third reset signal line VI_T8, a third connection part 151, a fourth connection part 152, a fifth connection part 153, a sixth connection part 154, a seventh connection part 155, and an eighth connection part 156.

[0097] As Figure 10 shown, the first reset signal line VI_GATE, the reset control signal line RST, the second scan signal line Scan2, the first power supply signal line VDD, the second reset signal line VI_ANO, and the third reset signal line VI_T8 are all arranged to extend along the row direction X, and the first reset signal line VI_GATE, the reset control signal line RST, the second scan signal line Scan2, the first power supply signal line VDD, the second reset signal line VI_ANO, and the third reset signal line VI_T8 are arranged at intervals along the column direction Y.

[0098] In some embodiments, as Figure 10As shown, the first power supply signal line VDD includes a plurality of first horizontal portions VDD1 and first inclined portions VDD2 connected between two adjacent first horizontal portions VDD1. The first horizontal portions VDD1 are arranged parallel to the extending direction of the first reset signal line VI_GATE. Two adjacent first horizontal portions VDD1 are located on different straight lines. An obtuse angle is formed between the first horizontal portion VDD1 and the first inclined portion VDD2. Two adjacent first inclined portions VDD2 are symmetrically arranged. The plurality of first horizontal portions VDD1 and the plurality of first inclined portions VDD2 are continuously and alternately arranged along the extending direction of the first power supply signal line VDD, so that the first power supply signal line VDD is wavy, thereby avoiding adjacent openings and conductive patterns in other film layers, which is beneficial to improving the pixel density in the display panel.

[0099] In some embodiments, as Figure 10 shown, the second scan signal line Scan2 includes a plurality of second horizontal portions S21 and second inclined portions S22 connected between two adjacent second horizontal portions S21. The second horizontal portions S21 are arranged parallel to the extending direction of the first reset signal line VI_GATE. Two adjacent first horizontal portions VDD1 are located on different straight lines. An obtuse angle is formed between the second inclined portion S22 and the second horizontal portion S21. Two adjacent second inclined portions S22 are symmetrically arranged. The plurality of second horizontal portions S21 and the plurality of second inclined portions S22 are continuously and alternately arranged along the extending direction of the second scan signal line Scan2, so that the second scan signal line Scan2 is wavy, thereby avoiding adjacent openings and conductive patterns or active patterns in other film layers, which is beneficial to improving the pixel density in the display panel.

[0100] In some embodiments, please refer to Figure 10 , the second reset signal line VI_ANO includes a second sub-reset signal line VI_ANO2, and the second sub-reset signal line VI_ANO2 is disposed on the first source-drain layer 14.

[0101] In some embodiments, please refer to Figure 10, the distance between the second reset signal line VI_ANO and the nearest third reset signal line VI_T8 is less than the distance between adjacent second reset signal lines VI_ANO. It should be noted that since adjacent rows of pixel driving circuits are electrically connected to the same second reset signal line VI_ANO and the same third reset signal line VI_T8, the number of second reset signal lines VI_ANO and third reset signal lines VI_T8 can be reduced by half. In this way, there are two rows of pixel driving circuits between adjacent second reset signal lines VI_ANO. Since there is no pixel driving circuit between the second reset signal line VI_ANO and the nearest third reset signal line VI_T8, the distance between the second reset signal line VI_ANO and the adjacent third reset signal line VI_T8 can be made less than the distance between adjacent second reset signal lines VI_ANO. In this way, the number of reset signal lines extending in the row direction can be reduced, thereby reducing the space occupied by the reset signal lines in the column direction. Therefore, there is more space to set up pixel driving circuits, which can improve the pixel density of the display panel.

[0102] Please refer to Figure 11 , Figure 11 is a stacked diagram of the active layer, the first gate layer, the second gate layer, and the first source-drain layer in the display panel of the present application. The driving gate T1G of the driving transistor T1 is connected to the compensation active part T3A of the compensation transistor T3 and the first reset active part T4A of the first reset transistor T4 through the third connection part 151. The switching active part T2A of the switching transistor T2 is connected to the data signal line DATA through the fourth connection part 152. The data signal line DATA is located in the second source-drain layer 21. The driving active part T1A of the driving transistor T1 is connected to the first end of the first light-emitting control active part T5A of the first light-emitting control transistor T5 through the fifth connection part 153. The second end of the first light-emitting control active part T5A is connected to the first power supply signal line VDD through the sixth connection part 154. The second electrode plate C12 is partially overlapped with the first power supply signal line VDD and is connected to the first power supply signal line VDD. The second scan signal line Scan2 is respectively connected to the switching gate T2G of the switching transistor T2 and the compensation gate T3G of the compensation transistor T3. The first reset gate T4G of the first reset transistor T4 is connected to the reset control signal line RST, and one end of the first reset active part T4A is connected to the first reset signal line VI_GATE. One end of the second reset active part T7A of the second reset transistor T7 is connected to the second reset signal line VI_ANO through the seventh connection part 155. The second reset active part T7A is partially overlapped with the third reset signal line VI_T8.

[0103] In some embodiments, adjacent rows of pixel driving circuits 10 electrically connected to the same reset signal line VI are symmetrically arranged.

[0104] Please refer to Figure 11 , adjacent rows of pixel driving circuits 10 electrically connected to the same reset signal line VI are symmetrically arranged with respect to an axis of symmetry parallel to the row direction X. It should be noted that the symmetrical arrangement of the two rows of pixel driving circuits 10 means that the patterns of the respective transistors in the pixel driving circuit 10 are symmetrically arranged in the positive projection on the substrate 101. Taking the driving transistor T1 as an example, the driving gates T1G of the driving transistors T1 in adjacent rows of pixel driving circuits 10 electrically connected to the same reset signal line VI are symmetrically arranged, and the driving active parts T1A of adjacent rows of pixel driving circuits 10 electrically connected to the same reset signal line VI are symmetrically arranged. By analogy, the same is true for other transistors, which will not be elaborated here.

[0105] As Figure 12 shown, Figure 12 is a schematic diagram of the symmetrical arrangement of pixel driving circuits in the display panel provided by the embodiment of the present application. The adjacent rows of pixel driving circuits electrically connected to the same reset signal line are represented by a positive "A" and an inverted "A" respectively. The adjacent rows of pixel driving circuits electrically connected to the same reset signal line are symmetrically arranged, so that the electrical characteristics of the driving transistors T1 and other transistors in the pixel driving circuits of odd rows and even rows can be guaranteed to be consistent, thereby improving the uniformity of the display brightness of odd rows and even rows, and avoiding the occurrence of horizontal stripes in the display screen due to the large brightness difference between odd rows and even rows, so as to improve the display effect of the display panel.

[0106] In some embodiments, adjacent rows of pixel driving circuits 10 electrically connected to the same second reset signal line VI_ANO and the third reset signal line VI_T8 are symmetrically arranged with respect to the second reset signal line VI_ANO, that is, the second reset signal line VI_ANO serves as the axis of symmetry of adjacent rows of pixel driving circuits 10 electrically connected to the same second reset signal line VI_ANO and the third reset signal line VI_T8. In this way, the electrical characteristics of the driving transistors T1 and other transistors in the pixel driving circuits of odd rows and even rows can also be guaranteed to be consistent, thereby improving the uniformity of the display brightness of odd rows and even rows, and avoiding the occurrence of horizontal stripes in the display screen due to the large brightness difference between odd rows and even rows, so as to improve the display effect of the display panel.

[0107] In some embodiments, adjacent rows of pixel driving circuits 10 electrically connected to the same second reset signal line VI_ANO and third reset signal line VI_T8 are symmetrically arranged with respect to the third reset signal line VI_T8. That is, the third reset signal line VI_T8 serves as the axis of symmetry for adjacent rows of pixel driving circuits 10 electrically connected to the same second reset signal line VI_ANO and third reset signal line VI_T8. In this way, the electrical characteristics of the driving transistors T1 and other transistors in the pixel driving circuits of odd rows and even rows can also be ensured to be consistent, thereby improving the uniformity of the display brightness of odd rows and even rows and avoiding the occurrence of horizontal stripes in the display screen due to the large brightness difference between odd rows and even rows, so as to improve the display effect of the display panel.

[0108] In some embodiments, adjacent rows of pixel driving circuits electrically connected to the same reset signal line are connected through a connecting portion, and the connecting portion is asymmetrically arranged with respect to the second reset signal line VI_ANO or the third reset signal line VI_T8.

[0109] As Figure 11 shown, the connecting portion includes a first connecting portion 111 and a second connecting portion 112 located in the active layer 11. Adjacent rows of pixel driving circuits electrically connected to the same reset signal line are connected through the first connecting portion 111 and the second connecting portion 112. The first connecting portion 111 is asymmetrically arranged with respect to the second reset signal line or the third reset signal line, and the second connecting portion 112 is asymmetrically arranged with respect to the second reset signal line or the third reset signal line.

[0110] In some embodiments, the display panel 100 includes multiple conductive layers. Multiple first reset signal lines VI_GATE are respectively arranged in at least two conductive layers, and the first reset signal lines VI_GATE located in different conductive layers are connected in parallel. Multiple second reset signal lines VI_ANO are respectively arranged in at least three conductive layers, and the second reset signal lines VI_ANO located in different conductive layers are connected in parallel; multiple third reset signal lines VI_T8 are respectively arranged in at least two conductive layers, and the third reset signal lines VI_T8 located in different conductive layers are connected in parallel.

[0111] In some embodiments, the number of conductive layers provided with the first reset signal line VI_GATE is less than the number of conductive layers provided with the second reset signal line VI_ANO; the number of conductive layers provided with the third reset signal line VI_T8 is less than the number of conductive layers provided with the second reset signal line VI_ANO.

[0112] It should be noted that the second reset signal line VI_ANO is used to reset the anodes of the light-emitting devices corresponding to two adjacent rows of pixel driving circuits. The second reset signal line VI_ANO needs to provide a stable voltage to eliminate the afterimage of the previous frame display image. Sharing the second reset signal line VI_ANO with two adjacent rows of pixel driving circuits may cause fluctuations in the anode reset voltage due to the load differences of different row pixel driving circuits. In this embodiment, by increasing the number of conductive layers provided with the second reset signal line VI_ANO, the impedance of the second reset signal line VI_ANO is reduced, thereby further reducing the risk of generating afterimages.

[0113] In some embodiments, the conductive layer includes the first gate layer 12, the second gate layer 13, the first source-drain layer 14, and the second source-drain layer 21 as described above. The first reset signal line VI_GATE can be disposed in at least two of the first gate layer 12, the second gate layer 13, the first source-drain layer 14, and the second source-drain layer 21. The second reset signal line VI_ANO can be disposed in at least three of the first gate layer 12, the second gate layer 13, the first source-drain layer 14, and the second source-drain layer 21. The third reset signal line VI_T8 can be disposed in at least two of the first gate layer 12, the second gate layer 13, the first source-drain layer 14, and the second source-drain layer 21. In this way, the existing conductive layers in the display panel can be utilized to place each reset signal line, avoiding adding other film layer structures and corresponding manufacturing processes, thereby reducing the impedance of each reset signal line and increasing the pixel density of the display panel.

[0114] According to the display panel provided in the above embodiments of the present application, the embodiments of the present application further provide a display device. Please refer to Figure 13 , Figure 13 is a schematic diagram of the display device provided in the embodiments of the present application. The display device 1000 includes a display panel 100 and a housing 200. The display panel 100 is disposed on the housing 200. The display panel 100 can be the display panel provided in any of the above embodiments. The display device provided in the embodiments of the present application can achieve the same technical effects as the display panel provided in any of the above embodiments, which will not be elaborated here.

[0115] Advantages of the embodiments of the present application: The embodiments of the present application provide a display panel and a display device. The display panel includes a plurality of pixel driving circuits and a plurality of reset signal lines. The plurality of pixel driving circuits are arranged in an array in the row direction and the column direction. The reset signal lines extend in the row direction. The reset signal lines have a fixed potential. At least one of the first reset signal line, the second reset signal line, and the third reset signal line is disposed between two adjacent rows of pixel driving circuits and is electrically connected to the two adjacent rows of pixel driving circuits. In the embodiments of the present application, by disposing at least one of the first reset signal line, the second reset signal line, and the third reset signal line between two adjacent rows of pixel driving circuits and electrically connecting the reset signal line to the two adjacent rows of pixel driving circuits, the two adjacent rows of pixel driving circuits share the same reset signal line. In this way, the number of reset signal lines extending in the row direction can be reduced, thereby reducing the space occupied by the reset signal lines in the column direction. Therefore, more space can be used to arrange the pixel driving circuits, and thus the pixel density of the display panel can be improved.

[0116] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more such features. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0117] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0118] The embodiments, implementation manners, and related technical features of the present application can be combined and replaced with each other without conflict.

[0119] The above are only the preferred embodiments of the present application and do not impose any form of limitation on the present application. However, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that, It includes a plurality of pixel driving circuits, a plurality of reset signal lines, a first power supply signal line, a second power supply signal line, and a light-emitting device. The reset signal lines have a fixed potential. The plurality of reset signal lines include a first reset signal line, a second reset signal line, and a third reset signal line. The pixel driving circuit includes: A driving transistor, which is connected in series with the light-emitting device between the first power supply signal line and the second power supply signal line; A first reset transistor, which is electrically connected between the driving gate of the driving transistor and the first reset signal line; A second reset transistor, which is electrically connected between the first electrode of the driving transistor and the second reset signal line; and A third reset transistor, which is electrically connected between the second electrode of the driving transistor and the third reset signal line; Wherein, at least one of the first reset signal line, the second reset signal line, and the third reset signal line is disposed between adjacent two rows of the pixel driving circuits and is electrically connected to the adjacent two rows of the pixel driving circuits.

2. The display panel according to claim 1, wherein At least two of the first reset signal line, the second reset signal line, and the third reset signal line are disposed between the same adjacent two rows of the pixel driving circuits.

3. The display panel according to claim 2, characterized in that, The first reset signal line and the second reset signal line are respectively disposed between different adjacent two rows of the pixel driving circuits, and the second reset signal line and the third reset signal line are disposed between the same adjacent two rows of the pixel driving circuits.

4. The display panel according to claim 3, characterized in that, The first reset signal line is disposed between the (2n)-th row of pixel driving circuits and the (2n + 1)-th row of pixel driving circuits, and the second reset signal line and the third reset signal line are disposed between the (2n - 1)-th row of pixel driving circuits and the 2n-th pixel driving circuits, where n is an integer greater than or equal to 1.

5. The display panel according to claim 1, wherein The distance between the second reset signal line and the nearest third reset signal line is less than the distance between adjacent two second reset signal lines.

6. The display panel according to claim 1, wherein, The adjacent two rows of pixel driving circuits electrically connected to the same reset signal line are symmetrically disposed.

7. The display panel according to claim 6, wherein The adjacent two rows of pixel driving circuits electrically connected to the same reset signal line are connected by a connecting portion, and the connecting portion is asymmetrically disposed with respect to the reset signal line.

8. The display panel according to claim 6, wherein The adjacent two rows of pixel driving circuits electrically connected to the same second reset signal line are symmetrically disposed with respect to the second reset signal line; Or, the adjacent two rows of pixel driving circuits electrically connected to the same third reset signal line are symmetrically disposed with respect to the third reset signal line.

9. The display panel according to claim 1, wherein The display panel includes an active layer, and the active layer includes a second reset active portion of the second reset transistor, a third reset active portion of the third reset transistor, a first connecting portion, and a second connecting portion; Wherein, the second reset active part of the second reset transistor is connected to the second reset active part of the second reset transistor in the adjacent row of the pixel driving circuit through the first connection part, and the two second reset active parts and the first connection part are connected to each other to be continuously arranged; the third reset active part of the third reset transistor is connected to the third reset active part of the third reset transistor in the adjacent row of the pixel driving circuit through the second connection part, and the two third reset active parts and the second connection part are connected to each other to be continuously arranged.

10. The display panel according to claim 9, wherein The display panel includes multiple conductive layers, and multiple first reset signal lines are respectively arranged in at least two of the conductive layers, and the first reset signal lines in different conductive layers are connected in parallel; multiple second reset signal lines are respectively arranged in at least three of the conductive layers, and the second reset signal lines in different conductive layers are connected in parallel; multiple third reset signal lines are respectively arranged in at least two of the conductive layers, and the third reset signal lines in different conductive layers are connected in parallel; Wherein, the number of the conductive layers provided with the first reset signal lines is less than the number of the conductive layers provided with the second reset signal lines; the number of the conductive layers provided with the third reset signal lines is less than the number of the conductive layers provided with the second reset signal lines.

11. The display panel according to claim 10, wherein The multiple conductive layers include: A first gate layer, arranged on the active layer; A second gate layer, arranged on the first gate layer; A first source-drain layer, arranged on the second gate layer; Wherein, the second gate layer includes multiple second reset signal lines, and the first source-drain layer includes the first reset signal line, multiple second reset signal lines and the third reset signal line.

12. The display panel according to claim 11, wherein The second reset active part and the third reset active part both extend in a direction perpendicular to the extension direction of the first reset signal line. Along the thickness direction of the display panel, the second reset active part partially overlaps with the third reset signal line, and the third reset active part partially overlaps with the second reset signal line.

13. The display panel according to claim 11, wherein The pixel driving circuit further includes a capacitor, the first electrode plate of the capacitor is electrically connected to the first power signal line, the second electrode plate of the capacitor is electrically connected to the driving gate of the driving transistor, and the second gate layer includes the second electrode plate; Wherein, in two adjacent pixel driving circuits, the second electrode plate in one of the pixel driving circuits is arranged to be disconnected from the second electrode plate in the other pixel driving circuit.

14. The display panel according to claim 11, wherein The first source-drain layer includes the first power signal line, the first power signal line includes multiple first horizontal parts and a first inclined part connected between two adjacent first horizontal parts, the first horizontal part is arranged parallel to the extension direction of the first reset signal line, and the first inclined part forms an obtuse angle with the first horizontal part.

15. The display panel according to claim 11, wherein The display panel further includes a first scanning signal line and a second scanning signal line, and the pixel driving circuit further includes a switching transistor. The first scanning signal line is electrically connected to a second reset gate of the second reset transistor, and the second scanning signal line is electrically connected to a switching gate of the switching transistor; Wherein, the first source-drain layer includes the second scanning signal line, and the second scanning signal line includes a plurality of second horizontal portions and second inclined portions connected between two adjacent second horizontal portions. The second horizontal portions are arranged parallel to the extending direction of the first reset signal line, and the second inclined portions are arranged at an obtuse angle with respect to the second horizontal portions.

16. A display device, characterized in that, A display panel according to any one of claims 1 to 15.

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