Tcon liquid crystal logic on-board ceramic capacitor howling reduction method

Abstract

The application belongs to the technical field of liquid crystal screens, and provides a TCON liquid crystal logic board ceramic capacitor howling reduction method, which comprises the following steps: in each frame working scanning area of the TCON liquid crystal logic board, a GOA circuit is used to open a thin film transistor (TFT) through row-by-row scanning by means of a CLK signal, and a DATA electric field is provided to a liquid crystal unit by means of a Source driver, and an AVDD and a VGH power supply are driven to provide a capacitive load pulse current; and each frame of the TCON liquid crystal logic board is blanked; and the application can solve the problem of howling caused by great variation of chip power supply load in the prior art.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of liquid crystal screen, and particularly relates to a method for reducing ceramic capacitor howling on a TCON liquid crystal logic board. BACKGROUND

[0002] FT liquid crystal screens are widely used in display devices, and the driving thereof mainly depends on a TCON (related controller) liquid crystal logic control board. The TCON liquid crystal logic control board supplies power to a source driver and a GOA (gate on array) circuit through AVDD (analog power supply voltage) and VGH (high gate voltage) power supplies to control the display of pixels. However, in actual application, a multi-layer ceramic capacitor (MLCC) of the TCON liquid crystal logic control board often generates mechanical vibration due to the inverse piezoelectric effect, resulting in howling. The howling mainly occurs between a scanning working area and a BLANK (blank) area of each frame, because the load of the AVDD and VGH power supplies changes from heavy load to no load, and the response speed of a power supply chip is insufficient, resulting in a voltage ripple peak. The peak frequency (usually 60 Hz to 288 Hz) is within the audible range of human ears, triggers the vibration of the MLCC, and affects the user experience.

[0003] In the prior art, methods for solving the MLCC howling problem mainly include the following:

[0004] 1. Using tantalum capacitors to replace MLCCs: Tantalum capacitors have low voltage resistance and high unit price. To achieve the same capacity and voltage resistance, the cost is several times higher than that of MLCCs, and the volume is increased, which is not conducive to PCB layout.

[0005] 2. Using electrolytic capacitors to replace ceramic multilayer capacitors (MLCCs): If the electrolytic capacitors need to meet the parameters of high frequency, low ESR and long service life, the volume is large and the height is too high. The height of a single capacitor is prominent on the PCBA board, which is not conducive to packaging and transportation, and the height of the whole machine mechanism is limited, and the universality is low.

[0006] 3. Using special MLCCs: Such capacitors are expensive, and the procurement cycle is long, the supply cost is lacking, and it is difficult to meet the production demand.

[0007] 4. Placing capacitors of the same specification on the front and back surfaces of the PCB: correcting noise by using vibration surface difference, but double-sided mounting is required, which increases production cost, and the whole machine assembly setting (such as mounting the iron back plate on the back surface of the PCB).

[0008] In this method, there are significant defects: tantalum capacitors and special MLCCs have high cost and are difficult to supply; electrolytic capacitors have large volume and low universality; and the PCB front and back surface mounting process is complex and has assembly restrictions. These problems limit the performance of the prior art in terms of cost, efficiency and applicability, and it is difficult to effectively solve the MLCC howling problem of the TCON liquid crystal logic. Therefore, a method with high efficiency and easy implementation is needed, which reduces the howling caused by large changes in power supply load by optimizing the TCON control and logic circuit design, while taking into account power consumption and whole machine assembly requirements. SUMMARY

[0009] In view of the above technical problems, the present application provides a TCON liquid crystal logic board ceramic capacitor howling reduction method to solve the problem of chip power supply load variation too large causing howling in the prior art.

[0010] Other features and advantages of the present disclosure will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, or some of the features and advantages will be learned by practice of the present disclosure.

[0011] The present application discloses a TCON liquid crystal logic board ceramic capacitor howling reduction method, the method comprising:

[0012] In each frame of the TCON liquid crystal logic board, the GOA circuit is used to open the thin film transistor TFT by row scanning through the CLK signal, and the DATA electric field is provided to the liquid crystal unit through the Source driver, and the AVDD and VGH power supplies are driven to provide pulsed current for the capacitive load;

[0013] In each frame of the TCON liquid crystal logic board, the GOA circuit is used to open the thin film transistor TFT by row scanning through the CLK signal, and the DATA electric field is provided to the liquid crystal unit through the Source driver, and the AVDD and VGH power supplies are driven to provide pulsed current for the capacitive load;

[0014] Further, in the load control circuit template, the switch tube of the first load module is a first PMOS tube, the first load module includes a first control voltage dividing resistor and a second control voltage dividing resistor connected to the VGH and the AVDD respectively, the common end of the first control voltage dividing resistor and the second control voltage dividing resistor is connected to the source of the first PMOS tube and a first branch voltage dividing resistor respectively, the first branch voltage dividing resistor is also connected to the gate of the first PMOS tube and one end of a first auxiliary voltage dividing resistor, the drain of the first PMOS tube is connected to a first load resistor, the common end of the first branch voltage dividing resistor and the first auxiliary voltage dividing resistor is also connected to one end of a voltage dividing adjustment resistor, the voltage dividing adjustment resistor is connected to the output end of the identification module through a short auxiliary resistor, and a first isolation diode is connected in parallel to the short auxiliary resistor.

[0015] The switch tube of the second load module is a second PMOS tube, the source of the second PMOS tube is connected to the VGH and one end of a second branch voltage dividing resistor, the other end of the second branch voltage dividing resistor is connected to the gate of the second PMOS tube and one end of a second auxiliary voltage dividing resistor, the drain of the second PMOS tube is connected to a second load resistor, and the common end of the second branch voltage dividing resistor and the second auxiliary voltage dividing resistor is also connected to the output end of the identification module through a second isolation diode.

[0016] The identification module comprises a plurality of input ports, and a plurality of CLK signals of the working scanning area are input into the plurality of input ports.

[0017] Further, according to the protection requirements of the AVDD and the VGH on different liquid crystal logic boards, when only the AVDD needs to be loaded, the second load module in the load control circuit template is removed, the first isolation diode and the first control voltage dividing resistor are removed, the second control voltage dividing resistor and the short-circuit auxiliary resistor are replaced by 0-ohm resistors, and the resistance values of the voltage dividing adjustment resistor, the first branch voltage dividing resistor and the first auxiliary voltage dividing resistor are matched according to the voltage specifications of the VGH and the AVDD, so that the first PMOS tube is cut off in the working scanning area, and the first PMOS tube is turned on in the BLANK blanking area.

[0018] Further, according to the protection requirements of the AVDD and the VGH on different liquid crystal logic boards, when only the VGH needs to be loaded, the second load module in the load control circuit template is removed, the first isolation diode and the second control voltage dividing resistor are removed, and the voltage dividing adjustment resistor, the first control voltage dividing resistor and the short-circuit auxiliary resistor are replaced by 0-ohm resistors.

[0019] Further, according to the protection requirements of the AVDD and the VGH on different liquid crystal logic boards, when the VGH and the AVDD both need to be loaded, the elements of the second load module are maintained, the short-circuit auxiliary resistor and the first control voltage dividing resistor are removed, and the second control voltage dividing resistor is replaced by a 0-ohm resistor.

[0020] The technical scheme of the present disclosure has the following beneficial effects:

[0021] The present application automatically loads the AVDD or the VGH in the BLANK blanking area by using the load control circuit template, thereby effectively reducing the voltage ripple caused by the instantaneous mutation of the load, and the load circuit does not work in the normal working scanning area, so that the power consumption and the noise reduction problem are considered. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 This is a flowchart of a method for reducing the squealing of ceramic capacitors on the TCON liquid crystal logic board in the embodiments of this specification.

[0023] Figure 2 This is a simplified schematic diagram illustrating the control of the liquid crystal GOA gate signal and source data in the embodiments of this specification.

[0024] Figure 3 This is a schematic diagram of the GOA circuit in the embodiments of this specification;

[0025] Figure 4 This is a schematic diagram of the GOA control timing and BLACK region control pulses in the embodiments of this specification;

[0026] Figure 5 This is a schematic diagram of the load control circuit template in the embodiments of this specification. Detailed Implementation

[0027] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure may be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., may be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0028] like Figure 1 As shown in the embodiments of this specification, a method for reducing the squealing of ceramic capacitors on a TCON liquid crystal logic board is provided. The method specifically includes steps S101-102:

[0029] In step S101, within each frame of the working scan area of ​​the TCON liquid crystal logic board, the GOA circuit is used to scan and turn on the thin film transistor TFT line by line through the CLK signal. At the same time, the DATA electric field is applied to the liquid crystal cell through the Source driver to drive the AVDD and VGH power supplies to provide the pulsed current of the capacitive load.

[0030] In step S102, in each frame BLANK blanking area of the TCON liquid crystal logic board, a load is applied to the AVDD or / and the VGH based on a pre-designed load control circuit template, the load control circuit template includes an identification module, and further includes a first load module or / and a second load module, the identification module is used to output a high level in the working scanning area and output a low level in the BLANK blanking area, the first load module is used to provide a load for the AVDD or / and the VGH, and the second load module is used to provide a load for the VGH, the first load module and the second load module each include a load resistor and a switch tube, and the switch tube is controlled to be turned on by the identification module.

[0031] As shown in Figure 2 , Figure 2 is a simplified working diagram of liquid crystal GOA gate signal and source data control, in Figure 2 , Gn (corresponding to the CLK signal of the GOA circuit, GOA is gate on panel technology) is a gate control signal (gate signal), Gn is high to open the corresponding row data control thin film transistor TFT, the source data applies an electric field to the liquid crystal unit to adjust the light transmission process, and the liquid crystal flip angle is controlled according to the electric field in the source data to control the light passing amount, and the R / G / B three primary colors pass through spatial color mixing to finally obtain the required display color and brightness.

[0032] As shown in Figure 3 , Figure 3 is a simplified GOA circuit diagram, which includes four transistors (Q8, Q9, Q10, Q11) and a parasitic capacitor, and the GOA circuit is used to generate a gate control signal (Gn) to drive the pixels of the TFT liquid crystal screen row by row. Specifically, the GOA integrates the gate drive circuit in the panel, and realizes row-by-row scanning through a clock signal (CLK) and a start signal (STV). Through circuit control, it is ensured that the TFT of each pixel row is turned on at the correct time, and the data signal is transmitted to the liquid crystal unit. The working principle of the GOA circuit is:

[0033] 1. The STV signal starts a frame, and the transistors Q8 and Q9 are pre-opened. Among them, STV (Start Vertical) is a gate start signal for starting a frame, which is a high level pulse (H), which triggers the start of a new frame scanning. When STV is high (H), Q8 is turned on, and the subsequent signal is transmitted to the circuit through the conduction of Q8. After Q8 is turned on, the voltage of its drain or source rises, so that the induction (GATE) of Q9 reaches a high level. Q9 enters a pre-opened state, but has not yet completely turned on, and waits for the next signal. This step is to prepare for the generation of the next stage gate signal.

[0034] 2、CLK1 and G(n-1) signal, Q26 open to transmit data. CLK1 is one of the clock signals of GOA circuit, when CLK1 becomes high (H), the drive circuit enters the next stage. G(n-1) is the gate signal of the last row (high level), generated by the last stage GOA unit, which acts as a control signal to affect the operation of the current unit. G(n-1) high level makes the induction of Q26 active, Q26 is turned on, and the conduction of Q26 transmits the voltage signal (Data) of the source data line (Source) to the liquid crystal electrode. The data signal represents the gray level (voltage value) applied to the liquid crystal electrode, controls the deflection angle of the liquid crystal molecule, adjusts the amount of light passing through the corresponding primary color (R / G / B), and determines the brightness and color of the pixel. This step completes the pixel charging: G(n-1) transmits signals from the last row, CLK1 provides related signals, Q26 sends data signals to the pixel, and the liquid crystal starts to display. At this time, the STV signal is a "start switch" that triggers the pre-charge of Q9 through Q8, ensuring that the circuit is ready to receive the clock signal.

[0035] 3、G(n-1) is submitted to the next stage, G(n) is generated and reset. Among them, G(n-1) is not only used for the current row, but also as an opening signal to pass to Q12 of the next stage GOA unit. Q12 receives this signal, making Q13 enter the pre-opening state, preparing to generate the gate signal G(n) of the next row. When CLK5 (another clock signal) reaches high level, Q13 is turned on, and the conduction of Q13 makes G(n) reach high level, activating the TFT of the current row (through Q27), allowing the data signal to trigger. After G(n) high level is generated, it is fed back to the last stage GOA unit at the same time, triggering the reset process. G(n) signal makes Q10 and Q11 conduct through the feedback circuit. The conduction of Q10 and Q11 pulls the GATE of Q9 and Q26 to VSS (ground voltage or low level).

[0036] In summary, as Figure 4 shown, Figure 4 the Level Shift GOA control timing and BLACK area control pulse diagram, for the GOA control timing of 3840*2160 resolution, each frame single channel CLK output 270 endurance, and then enter the BLANK area.

[0037] TFT liquid crystal screen consists of millions to tens of millions of pixels, each pixel contains a thin film transistor (TFT) and a liquid crystal unit. Liquid crystal unit by applying Data electric field to adjust the degree of light transmission, so as to control the brightness and color of the pixel. TFT as a switching element, responsible for controlling the voltage signal of each pixel, to achieve accurate display of the image. TFT liquid crystal screen drive is mainly divided into two parts of the row driver and column driver. Row driver is responsible for selecting the line to be updated, usually in a loop to refresh the entire display area. Column driver for each row of pixels selected to provide the corresponding voltage signal, control the brightness and color of each pixel. This row-column driving method makes TFT liquid crystal screen can achieve high resolution, fast response and stable display effect.

[0038] VGH voltage: for Level Shift level converter, through the Level Shift process to the liquid crystal screen GOA control unit circuit, through the CLK open each row

[0039] Thin film transistor TFT, CLK signal negative for capacitive load characteristics, load current for pulse current;

[0040] AVDD voltage: for supply Source drive, provide DATA electric field to the liquid crystal unit, liquid crystal unit for capacitive load characteristics, load current for pulse current; AVDD for multiple module unit power supply: such as VGH BOOST boost circuit unit module, VCOM and GAMMA unit module, HAVDD unit module.

[0041] Scan working area and BLANK blank area current analysis:

[0042] In each frame scanning working area, because the Level Shifter GOA circuit through the CLK signal scanning open thin film transistor TFT row by row, DATA electric field to the liquid crystal unit, CLK and DATA signal are capacitive load, so in the scanning working area VGH and AVDD current are large;

[0043] In the BLANK blank area, this area GOA part of the CLK signal stop output no load, at the same time CLK control thin film transistor TFT cut off, DATA signal also no load, at this time AVDD and VGH almost no load, because the industry existing power management chip response speed limit, from heavy load to no load change moment will produce voltage mutation ripple peak, and this frequency is equal to the frame frequency, according to the refresh rate is different, generally have 60HZ-288HZ, all in the frequency range that can be heard by human ear, this periodic mutation ripple peak makes MLCC ceramic capacitor inverse piezoelectric effect lead to mechanical vibration produces whistling.

[0044] Among them, such as Figure 5As shown in the load control circuit template, the switch tube of the first load module 201 is a first PMOS tube Q3, the first load module includes a first control voltage dividing resistor R198 and a second control voltage dividing resistor R197 connected to the VGH and the AVDD respectively, the common end of the first control voltage dividing resistor R198 and the second control voltage dividing resistor R197 is connected to the source of the first PMOS tube Q3 and a first branch voltage dividing resistor R190 respectively, the first branch voltage dividing resistor R190 is also connected to the gate of the first PMOS tube Q3 and one end of a first auxiliary voltage dividing resistor R191, the drain of the first PMOS tube Q3 is connected to a first load resistor R189, the common end of the first branch voltage dividing resistor R190 and the first auxiliary voltage dividing resistor R191 is also connected to one end of a voltage dividing adjustment resistor R192, the voltage dividing adjustment resistor R192 is connected to the output end of the identification module through a short auxiliary resistor, and the short auxiliary resistor is connected in parallel with a first isolation diode D8.

[0045] The switch tube of the second load module 202 is a second PMOS tube Q30, the source of the second PMOS tube Q30 is connected to the VGH and one end of a second branch voltage dividing resistor R193, the other end of the second branch voltage dividing resistor R193 is connected to the gate of the second PMOS tube Q30 and one end of a second auxiliary voltage dividing resistor R196, the drain of the second PMOS tube Q30 is connected to a second load resistor R194, and the common end of the second branch voltage dividing resistor R193 and the second auxiliary voltage dividing resistor R196 is also connected to the output end of the identification module through a second isolation diode D9.

[0046] The identification module 203 includes a plurality of input ports, and a plurality of the input ports input CLK signals of the working scanning area, and the CLK signals are inputted through diodes to realize an OR gate function.

[0047] Among them, please continue to refer to Figure 5 , the CLK1 to CLK8 signals of the working scanning area realize an OR gate function through diodes, and the ctrl is high as long as any one CLK is high, the adjacent CLK signals are spaced by 1 row, so as to ensure that the ctrl is always high (high = VGH voltage) in the working scanning area. The high level VGH at the ctrl of the working area is sent to the GATE of the first PMOS tube Q3 to make it cut off, and the GATA of the first PMOS tube Q3 is in a conductive state through an external resistance voltage dividing, and the first load module 201 is turned on.

[0048] In a specific implementation, according to different AVDD and VGH protection requirements on the liquid crystal logic board, when only the AVDD needs to be loaded, the second load module 202 in the load control circuit template as a finished product is removed, all circuits in the second load module 202 are not turned on, the first isolation diode D8 and the first control voltage dividing resistor R198 are removed, the positions of the original first isolation diode D8 and the first control voltage dividing resistor R198 in the circuit are not turned on, the second control voltage dividing resistor R197 and the short auxiliary resistor are replaced by 0 ohm resistors, conduction is realized through the 0 ohm resistors, and the resistance values of the voltage dividing adjustment resistor R192, the first branch voltage dividing resistor R190 and the first auxiliary voltage dividing resistor R191 are matched according to the voltage specifications of the VGH and the AVDD, so that the first PMOS tube Q3 is cut off in the working scanning area, and the first PMOS tube Q3 is turned on in the BLANK blanking area, that is, even if the high level VGH at the ctrl in the working scanning area is sent to the GATE electrode of the first PMOS tube Q3, Q3 is guaranteed to be cut off, and it is guaranteed that the VGS voltage resistance is not exceeded; when the Blank blanking area, the ctrl is similar to being suspended, at this time, the GATA voltage of Q3 is the voltage dividing of R190 and R191 on AVDD, which satisfies the VGS conduction voltage, Q3 is turned on to automatically increase the R189 load of AVDD in the Blank blanking area.

[0049] In another embodiment, according to different AVDD and VGH protection requirements on the liquid crystal logic board, when only the VGH needs to be loaded, the second load module in the load control circuit template is removed, the first isolation diode D8, the second control voltage dividing resistor R197 are removed, and the voltage dividing adjustment resistor R192, the first control voltage dividing resistor R198 and the short auxiliary resistor are replaced by 0 ohm resistors. In this way, the high level VGH at the ctrl in the working scanning area is directly added to the GATE electrode of Q3 to make Q3 cut off; when the Blank blanking area, the ctrl is similar to being suspended, at this time, the GATA voltage of Q3 is the voltage dividing of R190 and R191 on VGH, which satisfies the VGS conduction voltage, then Q3 is turned on to automatically increase the R189 load of VGH in the Blank blanking area.

[0050] In another embodiment, according to different AVDD and VGH protection requirements on the liquid crystal logic board, when the VGH and the AVDD both need to be loaded, wherein:

[0051] VGH load: maintain the elements of the second load module, then the work scan area in the control of the high level VGH directly to the second PMSO tube Q30 GATE, Q30 off; Blank blanking area when the control is similar to suspended, at this time the Q30 GATA voltage for R193 and R196 VGH voltage divider meet the VGS conduction voltage, Q30 conduction open to VGH in the Blank area automatically increase R194 load.

[0052] AVDD load: remove the short auxiliary resistor, the first control voltage dividing resistor R198, and the second control voltage dividing resistor R197 is replaced by 0 ohm resistor. According to the corresponding screen VGH and AVDD voltage specification selection R192, R190, R191 suitable resistance value of voltage divider, work scan area in the control of the high level VGH sent to Q3 GATE, ensure Q3 off and ensure not to exceed VGS voltage; Blank blanking area when the control is similar to suspended, at this time the Q3 GATA voltage for R190 and R191 AVDD voltage divider meet the VGS conduction voltage, Q3 conduction open to AVDD in the Blank area automatically increase R189 load;

[0053] Among them, the first isolation diode D8 and the second isolation diode D9 play a reverse isolation role in the circuit, avoiding the influence of Q3 and Q30 GATE voltage through external other resistance connection in the Blank blanking area.

[0054] The above R190, R189, R192, R191, R194 are adjustable resistance, to facilitate the application in different LCD screen when adjusting the resistance value, to realize the voltage divider to meet the conduction or cutoff of the switch tube, and meet the load supply of AVDD and VGH.

[0055] Through Figure 5 The load control circuit template, in each frame in the BLANK area control Q3 and Q30 conduction to make AVDD and VGH in the BLANK area R189 and R194 load, avoid sudden empty load to reduce the peak ripple mutation, reduce the MLCC ceramic capacitor generated by the inverse piezoelectric effect caused by mechanical vibration of the howling. Different brands and different size of LCD screen due to process and TFT characteristics and other reasons, according to the actual power ripple and MLCC howling situation flexible selection of the above load automatic identification control circuit on the piece to realize the function of reducing the peak ripple mutation.

[0056] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A TCON liquid crystal logic on board ceramic capacitor howling reduction method, characterized in that, The method comprises: In each frame of the working scanning area of the TCON liquid crystal logic board, the GOA circuit is used to open the TFT through the CLK signal row by row, and the DATA electric field is provided to the liquid crystal unit through the Source driver, the AVDD and VGH power supplies are driven to provide the pulsed current of the capacitive load; In each frame of the BLANK blanking area of the TCON liquid crystal logic board, a load is applied to the AVDD and / or the VGH based on a pre-designed load control circuit template, the load control circuit template comprises an identification module, a first load module and / or a second load module, the identification module is used to output a high level in the working scanning area and a low level in the BLANK blanking area, the first load module is used to provide a load for the AVDD and / or the VGH, and the second load module is used to provide a load for the VGH, the first load module and the second load module each comprise a load resistor and a switch tube, and the switch tube is controlled to be turned on by the identification module; In the load control circuit template, the switch tube of the first load module is a first PMOS tube, the first load module comprises a first control voltage dividing resistor and a second control voltage dividing resistor connected to the VGH and the AVDD respectively, the common end of the first control voltage dividing resistor and the second control voltage dividing resistor is connected to the source of the first PMOS tube and a first branch voltage dividing resistor, the first branch voltage dividing resistor is also connected to the gate of the first PMOS tube and one end of a first auxiliary voltage dividing resistor, the drain of the first PMOS tube is connected to a first load resistor, and the common end of the first branch voltage dividing resistor and the first auxiliary voltage dividing resistor is also connected to one end of a voltage dividing adjustment resistor, the voltage dividing adjustment resistor is connected to the output end of the identification module through a short auxiliary resistor, and a first isolation diode is connected in parallel to the short auxiliary resistor; The switch tube of the second load module is a second PMOS tube, the source of the second PMOS tube is connected to the VGH and one end of a second branch voltage dividing resistor, the other end of the second branch voltage dividing resistor is connected to the gate of the second PMOS tube and one end of a second auxiliary voltage dividing resistor, the drain of the second PMOS tube is connected to a second load resistor, and the common end of the second branch voltage dividing resistor and the second auxiliary voltage dividing resistor is also connected to the output end of the identification module through a second isolation diode; The identification module comprises a plurality of input ports, and a plurality of the input ports input the CLK signal of the working scanning area, and the diode realizes an OR function after the CLK signal is input.

2. The TCON liquid crystal logic on board ceramic capacitor howling reduction method according to claim 1, characterized in that, According to the AVDD and VGH protection requirements on different liquid crystal logic boards, when only the AVDD needs to be loaded, the second load module in the load control circuit template is removed, the first isolation diode and the first control voltage dividing resistor are removed, the second control voltage dividing resistor and the short auxiliary resistor are replaced by 0 ohm resistors, and the resistance values of the voltage dividing adjustment resistor, the first branch voltage dividing resistor and the first auxiliary voltage dividing resistor are matched according to the voltage specifications of the VGH and the AVDD, so that the first PMOS transistor is cut off in the working scanning area, and the first PMOS transistor is turned on in the BLANK blanking area. 3.The TCON liquid crystal logic on-glass ceramic capacitor howling reduction method of claim 1, wherein, According to the AVDD and VGH protection requirements on different liquid crystal logic boards, when only the VGH needs to be loaded, the second load module in the load control circuit template is removed, the first isolation diode, the second control voltage dividing resistor are removed, and the voltage dividing adjustment resistor, the first control voltage dividing resistor, and the short auxiliary resistor are replaced by 0 ohm resistors.

4. The TCON liquid crystal logic on board ceramic capacitor howling reduction method of claim 1, wherein, According to the AVDD and VGH protection requirements on different liquid crystal logic boards, when the VGH and the AVDD both need to be loaded, the elements of the second load module are maintained, the short auxiliary resistor and the first control voltage dividing resistor are removed, and the second control voltage dividing resistor is replaced by a 0 ohm resistor.

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