Memory device and test method for memory device

Abstract

A memory device includes: a memory core including a memory cell array, the memory cell array including a plurality of memory cells, the memory cell array being divided into a plurality of memory banks; a built-in self-test (BIST) circuit configured to select a target memory bank from the plurality of memory banks and perform a parallel test on the target memory bank; and a control circuit configured to control the parallel test. The BIST circuit may determine at least one defective memory cell that outputs a defective bit among target memory cells included in a target memory bank, and may determine whether the defective memory cell is a single defective memory cell or an adjacent dual defective memory cell, and when the defective memory cell is not a single defective memory cell and an adjacent dual defective memory cell, the control circuit can determine the target memory bank as a defective memory bank.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10 - 2024 - 0011162, filed on January 24, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to a memory device and a test method for a memory device. Background art

[0004] Semiconductor memory devices are fabricated through semiconductor manufacturing processes and are then tested by test equipment in wafer, die, or package states. Through testing, defective memory devices can be identified, and when some memory cells are defective, a repair operation can be performed to repair the memory device. As micro - processing progresses, the likelihood of errors occurring during the manufacturing process of memory devices such as dynamic random access memories (DRAMs) increases. Errors during the manufacturing process may result in defective memory devices. Additionally, errors may occur during the operation of defective memory devices. Defective memory devices may not be identified during the initial test phase before their operation. Therefore, the importance of built - in self - test (BIST) of memory devices is increasing. Summary of the invention

[0005] One aspect of the present disclosure is to provide a memory device and a test method for a memory device that determine a defective memory bank when a single memory cell is defective or both of a pair of adjacent memory cells are defective in a memory bank including defective memory cells.

[0006] According to one aspect of the present disclosure, a memory device may include: a memory core including a memory cell array, the memory cell array including a plurality of memory cells, the memory cell array being divided into a plurality of memory banks; a built - in self - test (BIST) circuit for selecting a target memory bank from the plurality of memory banks and performing a parallel test on the target memory bank; and a control circuit for controlling the parallel test, wherein the BIST circuit may determine at least one defective memory cell among target memory cells included in the target memory bank that outputs a defective bit, and may determine whether the defective memory cell is a single defective memory cell or an adjacent double - defective memory cell, and when the defective memory cell is not a single defective memory cell and an adjacent double - defective memory cell, the control circuit may determine the target memory bank as a defective memory bank.

[0007] According to one aspect of the present disclosure, a memory device may include: a memory core including a memory cell array having a plurality of memory cells, the memory cell array being divided into a plurality of memory banks; a BIST circuit for selecting a target memory bank from the plurality of memory banks and performing a parallel test on the target memory bank; and a control circuit for controlling the parallel test, wherein the BIST circuit may include: a first test circuit for determining defective memory cells among target memory cells included in the target memory bank and outputting a first output signal; a second test circuit for determining whether the defective memory cells are single defective memory cells and outputting a second output signal; and a third test circuit for determining whether the defective memory cells are adjacent double defective memory cells and outputting a third output signal, and the control circuit may determine the target memory bank as a defective memory bank using the first output signal to the third output signal when the defective memory cells are not single defective memory cells and adjacent double defective memory cells.

[0008] According to one aspect of the present disclosure, a test method for a memory device including a plurality of memory banks may include: selecting a target memory bank from the plurality of memory banks, and determining defective memory cells among target memory cells included in the target memory bank that output a logical state different from an input bit; when defective memory cells are determined among the target memory cells, determining whether the defective memory cells are single defective memory cells or adjacent double defective memory cells; and when the defective memory cells are not single defective memory cells and adjacent double defective memory cells, determining the target memory bank as a defective memory bank.

[0009] According to an exemplary embodiment of the present disclosure, in a memory bank in which defective memory cells are determined among a plurality of memory cells included in a memory block, it may be determined whether a single memory cell is defective or whether both of a pair of adjacent memory cells are defective. When the defective memory cells are a single memory cell or a pair of adjacent memory cells, it may be determined that the memory bank is normal and a repair operation may not be performed on the memory bank. Accordingly, consumption of memory cells to be replaced by a repair operation may be reduced to improve a yield of the memory device.

[0010] Advantages and effects of the present application are not limited to the foregoing, and may be more easily understood during a process of describing specific exemplary embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a view schematically showing a host memory system according to an exemplary embodiment of the present disclosure;

[0013] Figure 2 is a view schematically showing a memory device according to an exemplary embodiment of the present disclosure;

[0014] Figure 3 is a flowchart showing a process of selecting a defective memory bank in a memory device according to an exemplary embodiment of the present disclosure;

[0015] Figure 4 is a flowchart showing a process of performing a parallel test on a target memory bank and determining whether the target memory bank is defective according to an exemplary embodiment of the present disclosure;

[0016] Figure 5 is a view showing a third test circuit according to an exemplary embodiment of the present disclosure;

[0017] Figure 6 and Figure 7 is a view showing signals of the third test circuit according to an exemplary embodiment of the present disclosure;

[0018] Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12A and Figure 12B is a diagram showing output signals according to execution of a target memory bank and a parallel test according to an exemplary embodiment of the present disclosure; and

[0019] Figure 13 is a view showing a system to which a memory device is applied according to an exemplary embodiment of the present disclosure. Detailed Description of Specific Embodiments

[0020] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0021] Figure 1 is a view schematically showing a host memory system according to an exemplary embodiment of the present disclosure.

[0022] Refer to Figure 1, the host memory system 10 may be a data center composed of dozens of host devices or servers. According to some example embodiments, the host memory system 10 may be, for example, a laptop computer, a desktop computer, a server computer, a workstation, a portable communication terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), a smart phone, a tablet PC, and any other suitable computer, virtual machine, or its virtual computing device. Alternatively, the host memory system 10 may be some of the components included in a computing system, such as a graphics card.

[0023] The host memory system 10 is shown to have several hardware configurations that will be described in more detail below with reference to Figure 1 but the present disclosure is not limited thereto. The host memory system 10 may include a host device 100 and a memory system 200. The host device 100 and the memory system 200 may be connected according to various standard interfaces.

[0024] The host device 100 may include a processor 102 and may execute an operating system (OS) and / or various applications. The processor 102 may be communicatively connected to the memory system 200. The memory system 200 connected to the processor 102 may be referred to as system memory.

[0025] The processor 102 is a functional block for performing general computer operations in the host memory system 10, and may be a central processing unit (CPU), a digital signal processor (DSP), a network processor, an application processor (AP), or any type of processor such as another device for executing code. The processor 102 may be configured to execute one or more machine-executable instructions or several pieces of software, firmware, or a combination thereof. The processor 102 may include any number of processor cores. For example, the processor 102 may include a single core, or may include multiple cores, such as dual-core, quad-core, or six-core. Although Figure 1 the host memory system 10 is shown including one processor 102, according to example embodiments, the host memory system 10 may include multiple processors.

[0026] The memory system 200 may include a memory controller 210, a memory device 220, and a memory interface 230. The memory controller 210 may control the memory access operations (e.g., write operations or read operations) of the memory device 220 in response to requests from the host device 100 connected to the memory system 200. The memory device 220 may be used as a working memory for recording or loading data used in the operations of the processor 102. Although Figure 1The memory system 200 is shown to include one memory device 220, but according to an example embodiment, the memory system 200 may include multiple memory devices.

[0027] For simplicity, the memory interface 230 is shown as being connected by a single signal line between the memory controller 210 and the memory device 220, and may actually be connected via multiple signal lines. The memory interface 230 may include a connector for connecting the memory controller 210 and the memory device 220, and the connector may be implemented as pins, balls, signal lines, or other hardware components. For example, a clock signal (CLK), a command / address signal (CMD / ADDR), data (DQ), etc. may be transmitted and received between the memory controller 210 and the memory device 220 through the memory interface 230. The memory interface 230 may be implemented with a single channel including multiple signal lines, or may be implemented with multiple channels. The memory interface 230 may be referred to as a channel, and in the following example embodiments, the terms "memory interface 230" and "channel" may be used interchangeably.

[0028] The memory controller 210 may access the memory device 220 in response to a memory request from the processor 102, and may provide a system physical address for memory access. The memory controller 210 may include a memory physical layer interface, i.e., a memory PHY 212, for memory docking, such as selecting rows and columns corresponding to memory cells, programming data into the memory cells, or reading the written data.

[0029] The memory PHY 212 may have various forms of actual physical implementations of the memory controller 210 for performing the functions shown above. For example, the memory controller 210 may include physical components for exchanging data with the memory device 220, and may include at least one transmitter and at least one receiver. The memory controller 210 may be implemented with one or more hardware components (e.g., analog circuits or logic circuits), software, and / or firmware program code. The memory controller 210 may be integrally integrated into the processor 102 to ensure consistent access of the processor 102 to the memory device 220.

[0030] The memory device 220 may be a DRAM device. However, the memory device 220 is not limited to a DRAM device, and the memory device 220 may be one of volatile memory devices such as synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), low power double data rate SDRAM (LPDDR SDRAM), graphics double data rate SDRAM (GDDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, wide I / O DRAM, high bandwidth memory (HBM), and hybrid memory cube (HMC). According to another exemplary embodiment, the memory device 220 may be one of a plurality of memory devices mounted on a memory module. The memory module may be implemented as an unbuffered dual in-line memory module (UDIMM), a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM), a fully buffered DIMM (FBDIMM), and a small outline DIMM (SODIMM).

[0031] The memory device 220 may include a memory core 222, a built-in self-test (BIST) circuit 224, a control circuit 226, and an error correction circuit (ECC) 228.

[0032] The memory core 222 may include a plurality of memory cell arrays. Each of the plurality of memory cell arrays may be divided into a plurality of memory banks. Each of the plurality of memory cells may be a DRAM cell composed of one access transistor and one storage capacitor.

[0033] The control circuit 226 may control access to the memory core 222 based on commands and addresses received by the memory device 220. For example, the control circuit 226 may control read, write, and refresh operations of the memory core 222 based on commands and addresses received from the memory controller 210 through the memory interface 230. Additionally, the control circuit 226 may control testing of the memory device 220 by using the BIST circuit 224.

[0034] The BIST circuit 224 may perform testing of the memory device 220. Specifically, the BIST circuit 224 may test whether memory banks of the memory core 222 and / or memory cells of the memory banks are defective. For example, the BIST circuit 224 may perform testing by writing test data to the memory core 222 and reading the written data. The BIST circuit 224 may compare the written data with the test data before the write operation and determine whether the memory cells and / or the memory banks are defective.

[0035] According to some embodiments, the BIST circuit 224 may select a target memory bank from multiple memory banks and perform parallel tests on the multiple memory banks to determine whether the target memory bank among the multiple memory banks is defective. For example, the parallel test may be a test for determining whether the target memory bank among the multiple memory banks is defective based on whether the logical state input to the target memory bank matches the logical states input to the multiple memory banks. More specifically, by recording input bits of the same logical state into the multiple memory banks and comparing the input bits of the same logical state with the corresponding output bits output from the target memory bank, the BIST circuit 224 can determine whether the target memory bank is defective. However, the present disclosure is not limited thereto, and input bits having a specific pattern may be recorded in the target memory bank.

[0036] Specifically, among the target memory cells included in the target memory bank, when a single memory cell outputs a logical state different from the input bit, or a pair of adjacent memory cells output logical states different from the input bit, it can be determined that the target memory bank is not defective. In other words, in this case, the target memory bank can be determined to be a normal memory bank, and a repair operation may not be performed. In other words, the BIST circuit 224 may not determine a single-bit error and an adjacent double-bit error occurring in the memory bank as defective because the error correction circuit (ECC) 228 included in the storage device 220 can perform error correction operations on single-bit errors (e.g., SEC) and / or adjacent double-bit errors (e.g., SE2C). Therefore, the BIST circuit 224 may not need to perform a repair operation on defective memory cells that can be corrected by the ECC circuit 228. Here, the term adjacent double-bit error may refer to an error occurring in two memory cells adjacent to each other among multiple memory cells (i.e., two adjacent memory cells). The two adjacent memory cells may correspond to double-defective memory cells connected to the same word line and a pair of adjacent bit lines. However, since single-bit errors and adjacent double-bit errors may not necessarily occur due to the strength of the memory cells, it may be necessary to test the strength or integrity of the memory cells to determine whether one or more of these memory cells are defective.

[0037] When the BIST circuit 224 only determines the case where a single memory cell among the target memory cells included in the target memory bank outputs a logical state different from the input bit, the control circuit 226 can determine that the memory bank in which a pair of adjacent memory cells output logical states different from the input bit is defective. Additionally, unnecessary repair operations may be performed.

[0038] According to an exemplary embodiment of the present disclosure, the BIST circuit 224 may distinguish and determine a case where a logic state in which outputs of a pair of adjacent memory cells are different from an input bit. In this case, the control circuit 226 may determine the target memory bank as a normal memory bank. Accordingly, the yield may be improved by reducing consumption of repair memory cells to be replaced. For example, the repair memory cells may be supplementary memory cells manufactured in a memory device and used to replace defective memory cells. In other words, the BIST circuit 224 may not need to use the repair memory cells to replace one or more memory cells having a single-bit error or adjacent double-bit errors correctable by the ECC circuit 228, thereby saving the repair memory cells.

[0039] Figure 2 is a view schematically showing a memory device according to an exemplary embodiment of the present disclosure.

[0040] Figure 2 The memory device 300 may correspond to the memory device 220 described with reference to Figure 1 The memory device 300 may include a memory core 310, a read / write (RW) bus 320, a BIST circuit 330, and a control circuit 340.

[0041] The memory core 310 may include a plurality of memory banks 310a to 310d. In other words, the memory core 310 may include a memory cell array, and the memory cell array may be divided into a plurality of memory banks 310a to 310d.

[0042] Each of the plurality of memory banks 310a to 310d may include a plurality of memory cells, a row decoder (R / D), a column decoder (C / D), and sense amplifiers. Each of the plurality of memory banks 310a to 310d may include a plurality of word lines and a plurality of bit lines, and the plurality of memory cells may be connected to the plurality of word lines and the plurality of bit lines.

[0043] Figure 2 The memory core 310 in the exemplary embodiment shown in may include four memory banks 310a to 310d, but the number of memory banks is not limited thereto.

[0044] The read / write bus 320 may provide a data path between the plurality of memory banks 310a to 310d and a memory interface. Figure 2 Data lines DQ between the read / write bus 320 and the plurality of memory banks 310a to 310d are shown. The BIST circuit 330 may provide read and write commands (CMD) to test data paths of the plurality of memory banks 310a to 310d.

[0045] According to an exemplary embodiment of the present disclosure, the BIST circuit 330 may select a target memory bank from among a plurality of memory banks 310a to 310d and perform a parallel test on the plurality of memory banks 310a to 310d. Based on the parallel test, the BIST circuit 330 may determine that one or more defective memory cells in the target memory bank output one or more output bits having a logic state different from the input bit, and may determine whether the error is a single-bit error and / or an adjacent double-bit error.

[0046] According to an exemplary embodiment of the present disclosure, the BIST circuit 330 may include a first test circuit 332, a second test circuit 334, and a third test circuit 336.

[0047] The first test circuit 332 may determine whether there are defective memory cells in the target memory bank.

[0048] The second test circuit 334 may determine whether the defective memory cell is a single defective memory cell. Among the target memory cells, when a single memory cell outputs a logic state different from the input bit and the remaining memory cells output a logic state the same as the input bit, the single memory cell may be determined as a single defective memory cell.

[0049] The third test circuit may determine whether the defective memory cells are adjacent double-defective memory cells. Among the target memory cells, when a pair of adjacent memory cells output a logic state different from the input bit and the remaining memory cells output a logic state the same as the input bit, the pair of memory cells may be determined as adjacent double-defective memory cells. As described herein, "a pair of adjacent memory cells" may refer to a pair of memory cells connected to the same word line and having no other memory cells therebetween.

[0050] According to an exemplary embodiment of the present disclosure, the first to third test circuits 332, 334, and 336 may send the parallel test results to the control circuit 340. The parallel test results may include output signals (OUT1 to OUT3, OUT) and address information (ADD1 to ADD3, ADD) of the first to third test circuits 332, 334, and 336.

[0051] For example, the first output signal OUT1 of the first test circuit 332 may indicate whether defective memory cells have been determined for the target memory bank. The first address information ADD1 of the first test circuit 332 may correspond to the address information of the defective memory cell.

[0052] For example, the second output signal OUT2 of the second test circuit 334 may indicate whether the defective memory cell is a single defective memory cell. The second address information ADD2 of the second test circuit 334 may correspond to the address information of the single defective memory cell.

[0053] For example, the third output signal OUT3 of the third test circuit 336 may indicate whether the defective memory cell is an adjacent double defective memory cell. The third address information ADD3 of the third test circuit 336 may correspond to the address information of the adjacent double defective memory cell.

[0054] According to an exemplary embodiment of the present disclosure, the control circuit 340 may control the execution of the parallel test of the BIST circuit 330. Additionally, when the defective memory cell is not a single defective memory cell and an adjacent double defective memory cell, the control circuit 340 may determine the target memory bank as a defective memory bank. In this case, the control circuit 340 may use the first to third output signals (OUT) or the first to third address information (ADD).

[0055] The control circuit 340 may send the test result to the memory controller 210 (see Figure 1 ). The test result may include whether the target memory bank is defective and / or the first to third addresses (ADD1 to ADD3). The memory controller may perform a repair operation on the defective memory cell included in the defective memory bank. For example, through the repair operation, the defective memory cell may be replaced with another memory cell, the word line to which the defective memory cell is connected may be mapped to another word line, or the bit line to which the defective memory cell is connected may be mapped to another bit line. However, the present disclosure is not limited thereto.

[0056] When the defective memory cell is not a single defective memory cell and an adjacent double defective memory cell, the memory device 300 according to an exemplary embodiment of the present disclosure may determine the target memory bank as a defective memory bank. In other words, when the defective memory cell is an adjacent double defective memory cell, the target memory bank may be determined as a normal memory bank without performing a repair operation on the target memory bank.

[0057] Figure 3 is a flowchart illustrating a process of selecting a defective memory bank in a selective memory device according to an exemplary embodiment of the present disclosure.

[0058] In an exemplary embodiment of the present disclosure, a host memory system may include a host device and a memory system. The host device and the memory system may be connected according to various standard interfaces. The memory system may include a memory controller, a memory device, and a memory interface. A specific embodiment of the host memory system may be similar to Figure 1 those described in

[0059] In an exemplary embodiment of the present disclosure, the memory device may include a memory core, a BIST circuit, and a control circuit. The memory core may include a plurality of memory banks, and each of the plurality of memory banks may include a plurality of memory cells. The BIST circuit may select a target memory bank from the plurality of memory banks and may perform a parallel test on the target memory bank. The control circuit may control the execution of the parallel test of the BIST circuit. A specific embodiment of the memory device may be similar to Figure 2 those described in

[0060] The memory device may perform a parallel test on each of the plurality of included memory banks. Through the parallel test, a defective memory bank may be selected, and when the memory bank is defective, a repair operation may be performed to save the memory device. Hereinafter, a process for selecting a defective memory bank in a memory device according to an exemplary embodiment of the present disclosure will be described.

[0061] The memory device may receive a test command from the host device (S100). In other words, the host device may issue a test command to the memory device. The memory controller may issue a test command to the memory device to detect a memory cell that outputs a logic state different from the input bit (S110).

[0062] The memory device may perform a parallel test operation on each of the plurality of memory banks in response to the received test command. For example, the memory device may sequentially perform a parallel test operation on all memory banks. The BIST circuit may select a target memory bank from the plurality of memory banks (S120).

[0063] The BIST circuit may perform a parallel test on the target memory bank (S130). The BIST circuit may provide read and write commands to a read / write bus to perform a parallel test. The same data may be written to each target memory cell included in the target memory bank through a write command. The data written to each target memory cell may be read through a read command. Specific embodiments may be similar to Figure 2 those described in the embodiments

[0064] According to an exemplary embodiment of the present disclosure, the BIST circuit may determine whether the read data of a target memory cell is the same as the written data. In other words, the BIST circuit may determine whether the output bit output from the target memory cell is the same as the logical state of the input bit. In this case, the BIST circuit may determine that the target memory cell among the target memory cells that outputs a different logical state from the input bit is a defective memory cell.

[0065] In the target memory bank in which a defective memory cell is identified, the BIST circuit may determine whether the defective memory cell is a single memory cell or a pair of adjacent memory cells. In addition, the BIST circuit may send the parallel test result to the control circuit. The parallel test result may include an output signal and address information, and a specific embodiment may be similar to Figure 2 the embodiment described in

[0066] The control circuit may determine whether the target memory bank is defective (S140). When the defective memory cell is not defective (No in S140), the control circuit may determine that the target memory bank is a normal memory bank (S150). When the defective memory cell is defective (Yes in S140), the control circuit may determine that the target memory bank is a defective memory bank (S160).

[0067] The control circuit may send the test result to the memory controller, and the memory controller may perform a repair operation on the defective memory bank (S170). For example, through the repair operation, a defective memory cell may be replaced with another memory cell, the word line to which the defective memory cell is connected may be mapped to another word line, or the bit line to which the defective memory cell is connected may be mapped to another bit line. However, the present disclosure is not limited thereto.

[0068] Hereinafter, the process in which the BIST circuit performs a parallel test on the target memory bank and the control circuit determines whether the target memory bank is defective (S120 and S130) will be described in detail.

[0069] Figure 4 is a flowchart showing a process of performing a parallel test on a target memory bank and determining whether the target memory bank is defective according to an exemplary embodiment of the present disclosure.

[0070] In an exemplary embodiment of the present disclosure, a host memory system may include a host device and a memory system. The memory system may include a memory controller, a memory device, and a memory interface. The memory device may include a memory core, a BIST circuit, and a control circuit. The memory core may include a plurality of memory banks, and each of the plurality of memory banks may include a plurality of memory cells.

[0071] According to an exemplary embodiment of the present disclosure, the BIST circuit may include a first test circuit, a second test circuit, and a third test circuit, and may perform a parallel test on a target memory bank. The control circuit may control the parallel test performed by the BIST circuit. Specific embodiments of the host memory system and the memory device may be similar to Figures 1 to 3 those described in

[0072] First, the BIST circuit may activate the first test circuit (S200). The first test circuit may determine defective memory cells among target memory cells included in the target memory bank. The first test circuit may determine at least one memory cell that outputs a logic state different from the input bit among the target memory cells as a defective memory cell.

[0073] When no defective memory cells are determined among the target memory cells (No in S210), the target memory bank may be determined as a normal memory bank (S270). When defective memory cells are determined among the target memory cells (Yes in S210), the BIST circuit may determine whether the defective memory cells are single defective memory cells or adjacent double defective memory cells (S220 to S250).

[0074] Specifically, when defective memory cells are determined among the target memory cells (Yes in S210), the BIST circuit may activate the second test circuit and the third test circuit (S220 and S240).

[0075] The second test circuit may determine whether the defective memory cells are single defective memory cells (S230). Among the target memory cells, when a single memory cell outputs a logic state different from the input bit and the remaining memory cells output a logic state the same as the input bit, the single memory cell may be determined as a single defective memory cell.

[0076] The third test circuit can determine whether a defective memory cell is an adjacent double-defective memory cell (S250). Among the target memory cells, when a pair of adjacent memory cells output a logic state different from the input bit and the remaining memory cells output the same logic state as the input bit, the pair of memory cells can be determined as adjacent double-defective memory cells.

[0077] The control circuit can determine whether a defective memory cell is a single-defective memory cell or an adjacent double-defective memory cell (S260). In this case, the control circuit can use the output signals of the first to third test circuits.

[0078] When the defective memory cell is a single-defective memory cell or an adjacent double-defective memory cell (Yes in S260), the control circuit can determine the target memory bank as a normal memory bank (S270). No repair operation needs to be performed on the normal memory bank.

[0079] When the defective memory cell is not a single-defective memory cell and an adjacent double-defective memory cell (No in S260), the control circuit can determine the target memory bank as a defective memory bank (S280). The control circuit can send the test result including information about the defective memory bank to the memory controller, and the memory controller can perform a repair operation on the defective memory bank. For example, as discussed above, through the repair operation, a defective memory cell can be replaced with another memory cell (e.g., a repair memory cell), the word line to which the defective memory cell is connected can be mapped to another word line, or the bit line to which the defective memory cell is connected can be mapped to another bit line. However, the present disclosure is not limited thereto.

[0080] The BIST circuit according to an exemplary embodiment of the present disclosure can determine a memory bank in which the defective memory cell is a single-defective memory cell and an adjacent double-defective memory cell as a normal memory bank, and thus, unnecessary repair operations do not need to be performed on the single-defective memory cell and the adjacent double-defective memory cell.

[0081] Figure 5 FIG. is a view showing a third test circuit according to an exemplary embodiment of the present disclosure.

[0082] In an exemplary embodiment of the present disclosure, a memory device may include a memory core, a BIST circuit, and a control circuit. The memory core may include a plurality of memory banks, and each of the plurality of memory banks may include a plurality of memory cells. The BIST circuit may select a target memory bank from the plurality of memory banks and may perform a parallel test on the target memory bank. The control circuit may control the execution of the parallel test of the BIST circuit. A specific embodiment of the memory device may be similar to Figures 1 to 4 those described in

[0083] According to an exemplary embodiment of the present disclosure, the BIST circuit may include first to third test circuits. When a pair of adjacent memory cells among the target memory cells included in the target memory bank output defective bits, the third test circuit may determine the pair of memory cells as adjacent double-defective memory cells. In other words, the third test circuit may determine whether a defective memory cell that outputs a logical state different from the input bit among the target memory cells is an adjacent double-defective memory cell.

[0084] Each of the plurality of memory banks may include a plurality of word lines and a plurality of bit lines, and the plurality of memory cells may be connected to the plurality of word lines and the plurality of bit lines. A pair of memory cells may be connected to one of the plurality of word lines and a pair of adjacent bit lines among the plurality of bit lines. In this case, the pair of bit lines may be determined by the control circuit.

[0085] First, referring to Figure 5 , the third test circuit 400 may include an input unit 500, a logic unit 600, and an output unit 700. The input unit 500 may receive a selection signal S from the first test circuit and bit determination signals A0 to A7 from the control circuit. The bit determination signals A0 to A7 may indicate whether the 0th to seventh target memory cells output defective bits. The 0th to seventh target memory cells may correspond to all or some of the target memory cells.

[0086] The 0th to seventh target memory cells may be connected to one of the plurality of word lines and adjacent bit lines among the plurality of bit lines. In this case, the number of adjacent bit lines to each other may be equal to the number of the 0th to seventh target memory cells. As used herein, "adjacent bit lines to each other" may refer to a pair of adjacent bit lines, where no other bit lines are provided between the pair of bit lines. Therefore, "adjacent bit lines to each other" may refer to a pair of directly adjacent bit lines.

[0087] The 0th to 7th target memory cells may be divided into first to fourth pairs of memory cells adjacent to each other. Accordingly, bit determination signals A0 to A7 may also be divided into first to fourth pairs of bit determination signals. For example, the first pair of memory cells may be connected to a word line and a pair of adjacent bit lines. In this case, the pair of bit lines may be determined by a selection signal S.

[0088] According to an exemplary embodiment of the present disclosure, the input unit 500 may include a plurality of multiplexers (511-514; 510), and each of the plurality of multiplexers 510 may include an inverter and a transmission gate connected in parallel. The input unit 500 may output a pair of bit determination signals corresponding to a pair of memory cells among the bit determination signals A0 to A7 to the logic unit 600. Specifically, the pair of bit determination signals may be output to a plurality of half adders (621-624; 620) included in the logic unit 600.

[0089] According to an exemplary embodiment of the present disclosure, the input unit 500 may receive a selection signal S and the (2n-2)th to (2n)th bit determination signals. In this case, n corresponds to a natural number of 1 or greater, and may be the same hereinafter. The input unit 500 may output the (2n-1)th bit determination signal to the nth half adder among the plurality of half adders 621 to 624.

[0090] The selection signal S, and the (2n-2)th bit determination signal and the (2n)th bit determination signal may be input to the nth multiplexer among the plurality of multiplexers 510. The nth multiplexer may output one of the (2n-2)th and (2n)th bit determination signals to the nth half adder according to the selection signal S. When the selection signal S is in the first state (high), the nth multiplexer may output the (2n-2)th bit determination signal, and when the selection signal S is in the second state (low), the nth multiplexer may output the (2n)th bit determination signal.

[0091] In an exemplary embodiment, the input unit 500 may receive a selection signal S and the 0th to 2nd bit determination signals A0 to A2, and may output the 1st bit determination signal A1 to the first half adder 621. The selection signal S, and the 0th and 2nd bit determination signals (A0 and A2) may be input to the first multiplexer 511.

[0092] In an embodiment of the present disclosure, when the selection signal S is in the first state (high), the first multiplexer 511 may output the 0th bit determination signal A0 to the first half adder 621. That is, the 0th and 1st target memory cells may correspond to a pair of adjacent memory cells.

[0093] In another exemplary embodiment of the present disclosure, when the selection signal S is in the second state (low), the first multiplexer 511 may output the first bit determination signal A1 to the first half adder 621. That is, the first and second target memory cells may correspond to a pair of adjacent memory cells to each other.

[0094] According to an exemplary embodiment of the present disclosure, the logic unit 600 may output the first internal signal IS1 to the third internal signal IS3 using the output of the input unit 500. The logic unit 600 may include a first logic unit (621-624; 620), a second logic unit (641-642; 640), and a third logic unit 660.

[0095] The first logic unit 620 may include a plurality of half adders 621 to 624. The plurality of half adders 621 to 624 may perform a NAND logic operation and an XNOR logic operation on the bit determination signals corresponding to a pair of memory cells.

[0096] The second logic unit 640 may include a plurality of second logic circuits 641 and 642. The second logic circuits 641 and 642 may perform a first NAND logic operation, a second NAND logic operation, and an XOR logic operation on the outputs of a pair of adjacent half adders among the plurality of half adders 621 to 624.

[0097] The third logic unit 660 may include at least one third logic circuit. The third logic circuit may perform a NAND logic operation, an AND logic operation, and a NOR logic operation on the output of the second logic unit 640 to output the first internal signal IS1 to the third internal signal IS3.

[0098] The first internal signal IS1 may indicate whether, among the first to fourth pairs of output bits output from the first to fourth pairs of adjacent memory cells among the target memory cells, the first pair of output bits are defective bits, or whether the second to fourth pairs of output bits are defective bits.

[0099] Among the first to fourth pairs of output bits output from the first to fourth pairs of adjacent memory cells among the target memory cells, the second internal signal IS2 may indicate whether there are no defective bits or a pair of output bits are defective bits among the first and second pairs of output bits, and whether there are no defective bits or a pair of output bits are defective bits among the third and fourth pairs of output bits.

[0100] The third internal signal IS3 may indicate whether each of the first to fourth pairs of output bits output from the first to fourth pairs of adjacent memory cells among the target memory cells are all defective bits or normal bits.

[0101] The output unit 700 may output a third output signal OUT3 indicating whether a pair of memory cells are adjacent double - defective memory cells by using the first internal signal IS1 to the third internal signal IS3. For example, the output unit 700 may perform an AND logic operation on the first internal signal IS1 to the third internal signal IS3 and may output the third output signal OUT3. The third output signal OUT3 may indicate whether the defective memory cells included in the target memory cells are adjacent double - defective memory cells.

[0102] Hereinafter, the third output signal OUT3 output from the third test circuit 400 according to an exemplary embodiment of the present disclosure will be described in detail.

[0103] Figure 6 and Figure 7 is a view showing signals of a third test circuit according to an exemplary embodiment of the present disclosure.

[0104] A memory device according to an exemplary embodiment of the present disclosure may include a memory core, a BIST circuit, and a control circuit, and the BIST circuit may include a first test circuit to a third test circuit. When a pair of adjacent memory cells in a target memory cell output defective bits, the third test circuit may determine the pair of memory cells as adjacent double - defective memory cells. Specific embodiments of the memory device and the BIST circuit may be similar to Figures 1 to 5 those described in

[0105] Figure 6 and Figure 7 may show the first internal signal IS1 to the third internal signal IS3 and the third output signal OUT3 of the third test circuit.

[0106] First, referring to Figure 6 , the selection signal received by the third test circuit corresponds to the first state (high), and the 0th and first, second and third... bit determination signals (A0 and A1, A2 and A3,...) may correspond to the bit determination signals corresponding to a pair of memory cells. In other words, each of the 0th and first, second and third... target memory cells may correspond to a pair of adjacent memory cells and may correspond to the first to fourth pairs of memory cells. Specific embodiments may be similar to Figure 5 those described in

[0107] The bit determination signals A0 to A7 may be divided into the first to sixth cases CASE1 to CASE6, and the bit determination signals A0 to A7 may have various combinations of values. A normal bit may indicate that the output bit output from the target memory cell is in the same logical state as the input bit, and a defective bit may indicate that the output bit is in a different logical state from the input bit.

[0108] A "0" in the bit determination signal may indicate that a target memory cell corresponding to the bit determination signal outputs a normal bit, and the target memory cell may correspond to a normal memory cell. A "1" in the bit determination signal may indicate that a target memory cell corresponding to the bit determination signal outputs a defective bit, and the target memory cell may correspond to a defective memory cell.

[0109] The first case, CASE1, may correspond to a case where all of the first to fourth pairs of target memory cells output defective bits because all of the 0th to 7th bit determination signals A0 to A7 have the value 1. Since the first case, CASE1, does not correspond to a case where the first pair of output bits are defective bits or the second to fourth pairs of output bits are defective bits, the first internal signal IS1 may correspond to the second state L. Since two pairs of output bits among the first and second pairs of output bits are defective bits and two pairs of output bits among the third and fourth pairs of output bits are defective bits, the second internal signal IS2 may correspond to the second state L. However, since each of the first to fourth pairs of output bits is the same as the defective bit, the third internal signal IS3 may correspond to the first state H. When an AND logic operation is performed on the first internal signal IS1 to the third internal signal IS3, the third output signal OUT3 may correspond to the second state L. That is, in case 1 of the first case, it can be determined that the defective memory cells are not adjacent double-defective memory cells.

[0110] The second case, CASE2, may correspond to a case where the first to third pairs of target memory cells may output defective bits because the 0th to 5th bit determination signals A0 to A5 may have the value 1 and the 6th and 7th bit determination signals A6 and A7 may have the value 0. Since the first to third pairs of output bits are defective bits, the first internal signal IS1 may correspond to the first state H. Since two pairs of output bits among the first pair of output bits and the second pair of output bits are defective bits, the second internal signal IS2 may correspond to the second state L. Since each of the first to third pairs of output bits is the same as the defective bit and each of the fourth pair of output bits is the same as the normal bit, the third internal signal IS3 may correspond to the first state H. When an AND logic operation is performed on the first internal signal IS1 to the third internal signal IS3, the third output signal OUT3 may correspond to the second state L. That is, in case 2 of the second case, it can be determined that the defective memory cells are not adjacent double-defective memory cells.

[0111] The third case, CASE3, can correspond to the case where the first and second pairs of target memory cells output defective bits, because the bit determination signals A0 to A3 for the 0th to 3rd bits can have the value 1, and the bit determination signals A4 to A7 for the 4th to 7th bits can have the value 0. Since the third case, CASE3, does not correspond to the case where the first pair of output bits are defective bits or the second to fourth pairs of output bits are defective bits, the first internal signal IS1 can correspond to the second state L. Since two pairs of output bits among the first and second pairs of output bits are defective bits, the second internal signal IS2 can correspond to the second state L. Since each of the first and second pairs of output bits is the same as the defective bit, and each of the third and fourth pairs of output bits is the same as the normal bit, the third internal signal IS3 can correspond to the first state H. When performing an AND logic operation on the first internal signal IS1 to the third internal signal IS3, the third output signal OUT3 can correspond to the second state L. That is, in the third case 3, it can be determined that the defective memory cell is not an adjacent double-defective memory cell.

[0112] The fourth case, CASE4, can correspond to the case where the first and third pairs of target memory cells can output defective bits and the second and fourth pairs of target memory cells can output normal bits. Since the fourth case, CASE4, does not correspond to the case where the first pair of output bits are defective bits or the second to fourth pairs of output bits are defective bits, the first internal signal IS1 can correspond to the second state L. Since the first pair of output bits among the first and second pairs of output bits are defective bits, and the third pair of output bits among the third and fourth pairs of output bits are defective bits, the second internal signal IS2 can correspond to the first state H. Since each of the first to fourth pairs of output bits equally outputs defective bits or normal bits, the third internal signal IS3 can correspond to the first state H. When performing an AND logic operation on the first internal signal IS1 to the third internal signal IS3, the third output signal OUT3 can correspond to the second state L. That is, in the fourth case, case 4, it can be determined that the defective memory cell is not an adjacent double-defective memory cell.

[0113] The fifth case, CASE5, can correspond to a case where the first pair of target memory cells can output defective bits and the second to fourth pairs of target memory cells can output normal bits. Since the first pair of output bits are defective bits, the first internal signal IS1 can correspond to the first state H. Since the first pair of output bits among the first and second pairs of output bits are defective bits and there are no defective bits among the third and fourth pairs of output bits, the second internal signal IS2 can correspond to the first state H. Since each of the first to fourth pairs of output bits equally outputs defective bits or normal bits, the third internal signal IS3 can correspond to the first state H. When an AND logic operation is performed on the first internal signal IS1 to the third internal signal IS3, the third output signal OUT3 can correspond to the first state H. That is, in the fifth case 5, the third test circuit can determine the first pair of memory cells as adjacent double-defective memory cells.

[0114] The sixth case, CASE6, can correspond to a case where all the first to fourth pairs of target memory cells output normal bits. Since the sixth case, CASE6, does not correspond to a case where the first pair of output bits are defective bits or the second to fourth pairs of output bits are defective bits, the first internal signal IS1 can correspond to the second state L. Since there are no defective bits among the first and second pairs of output bits and there are no defective bits among the third and fourth pairs of output bits, the second internal signal IS2 can correspond to the first state H. Since each of the first to fourth pairs of output bits equally outputs normal bits, the third internal signal IS3 can correspond to the first state H. When an AND logic operation is performed on the first internal signal IS1 to the third internal signal IS3, the third output signal OUT3 can correspond to the second state L. That is, in the sixth case, CASE6, the defective memory cells can be determined not to be adjacent double-defective memory cells.

[0115] Reference Figure 7 , in the case where the selection signal received by the third test circuit is in the second state (low), the first and second, third and fourth,... bit determination signals (A1 and A2, A3 and A4,...) can correspond to the bit determination signals corresponding to a pair of memory cells. In other words, the first and second, third and fourth,... target memory cells each correspond to a pair of adjacent memory cells and can correspond to the first to fourth pairs of memory cells. Specific embodiments can be similar to Figure 5 those described in

[0116] The bit determination signals A1 to A0 can be divided into first to sixth cases CASE1 to CASE6. Specific embodiments for determining the first internal signal IS1 to the third internal signal IS3 and the third output signal OUT3 can be similar to those previously referred to Figure 6 described ones.

[0117] Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A and Figure 12B are diagrams showing output signals according to a target memory bank and parallel testing according to an exemplary embodiment of the present disclosure.

[0118] Specific embodiments of a memory device and a BIST circuit according to an exemplary embodiment of the present disclosure can be similar to those Figures 1 to 7 described in. The BIST circuit of the exemplary embodiment of the present disclosure can include a first test circuit to a third test circuit. The first test circuit to the third test circuit can determine target memory cells included in a target memory bank.

[0119] The first test circuit can determine defective memory cells and output a first output signal OUT1 and / or the addresses of the defective memory cells. The second test circuit determines whether the defective memory cells are single defective memory cells, and can output a second output signal OUT2 and / or the addresses of the single defective memory cells. The third test circuit can determine whether the defective memory cells are adjacent double defective memory cells, and can output a third output signal OUT3 and / or the addresses of the adjacent double defective memory cells.

[0120] The control circuit can use the outputs of the first test circuit to the third test circuit to determine whether the defective memory cells are single defective memory cells or adjacent double defective memory cells. When the defective memory cells are not single defective memory cells and adjacent double defective memory cells, the control circuit can determine the target memory bank as a defective memory bank.

[0121] Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A can represent a target memory bank and bit determination signals according to an exemplary embodiment of the present disclosure. Figure 8B , Figure 9B , Figure 10B ,Figure 11B and Figure 12B may represent the first output signal OUT1 to the third output signal OUT3 according to an exemplary embodiment of the present disclosure.

[0122] Referring to Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A and Figure 12A , the target memory bank may include a plurality of word lines WL0 to WL7 and a plurality of bit lines BL0 to BL7. However, the present disclosure is not limited thereto, and may include a plurality of bit lines BL0 to BL15. The target memory cells may be connected to the plurality of word lines WL0 to WL7 and the plurality of bit lines BL0 to BL7. It can be understood that Figure 8A 、 Figure 9A 、 Figure 10A 、 11A and Figure 12A the rectangular regions in correspond to the target memory cells.

[0123] According to an exemplary embodiment of the present disclosure, the target memory cells may be divided into a plurality of regions. Each of the plurality of regions may include target memory cells connected to the same word line among the plurality of word lines WL0 to WL7 and the plurality of bit lines BL0 to BL7. For example, one of the plurality of regions may include target memory cells connected to the 0th word line (i.e., WL0) and the plurality of bit lines BL0 to BL7.

[0124] According to an exemplary embodiment of the present disclosure, target memory cells connected to the same word line among the plurality of word lines WL0 to WL7 and a pair of adjacent bit lines among the plurality of bit lines BL0 to BL7 may correspond to a pair of adjacent memory cells. This may be determined according to the selection signal received by the third test circuit, and a specific embodiment may be similar to those described in Figures 5 to 7 .

[0125] In Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A and Figure 12A shown target memory bank, target memory cells connected to the same word line and a pair of adjacent bit lines (BL0 and BL1, BL2 and BL3,...) may correspond to a pair of memory cells. For example, target memory cells connected to the 0th word line WL0 and the 0th bit line BL0 and the first bit line BL1 may correspond to a pair of adjacent memory cells. As another example, target memory cells connected to the 0th word line WL0 and the first bit line BL1 and the second bit line BL2 may correspond to a pair of adjacent memory cells.

[0126] Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A Each of the bit determination signals shown in can correspond to a target memory cell. A "0" in the bit determination signal can indicate that the target memory cell corresponding to the bit determination signal outputs a normal bit, and the target memory cell can correspond to a normal memory cell. A "1" in the bit determination signal can indicate that the target memory cell corresponding to the bit determination signal outputs a defective bit, and the target memory cell can correspond to a defective memory cell.

[0127] Referring to Figure 8B , Figure 9B , Figure 10B , Figure 11B and Figure 12B , in order to determine whether the target memory bank is defective, the BIST circuit can output a first output signal OUT1 to a third output signal OUT3 for each of a plurality of regions included in the target memory bank.

[0128] The first test circuit can determine at least one memory cell among the target memory cells that outputs a defective bit as a defective memory cell, and can output the first output signal OUT1 in a second state L for a region among the plurality of regions that includes the defective memory cell. In addition, the second test circuit and the third test circuit can be activated only when the defective memory cell is determined in the first test circuit.

[0129] When one of the target memory cells outputs a defective bit, the second test circuit can determine the one memory cell as a single defective memory cell. That is, the defective memory cell can be a single defective memory cell. The second output signal OUT2 can be output in a first state H for a region among the plurality of regions that includes the single defective memory cell.

[0130] When a pair of adjacent memory cells among the target memory cells output defective bits, the third test circuit can determine the pair of memory cells as adjacent double defective memory cells. That is, the defective memory cells can be adjacent double defective memory cells. The third output signal OUT3 can be output in a first state H for a region among the plurality of regions that includes the adjacent double defective memory cells.

[0131] For example, for at least one region among the plurality of regions that outputs the first output signal OUT1 in the second state L, when the second output signal OUT2 and the third output signal OUT3 are output in the second state L, the control circuit can determine the target memory bank as a defective memory bank.

[0132] As another example, in at least one region among multiple regions that outputs the first output signal OUT1 in the second state L, when the second output signal OUT2 or the third output signal OUT3 is output in the first state H, the control circuit may determine the target memory bank as a normal memory bank.

[0133] Reference Figure 8A , this may correspond to the case where all bit determination signals have a value of 0. In other words, all target memory cells may correspond to normal memory cells that output normal bits. Refer to Figure 8B , since there is no region including defective memory cells among the multiple regions, the first output signal OUT1 for the multiple regions is all output in the first state H, and the second and third test circuits may not be activated. That is to say, the control circuit may determine the target memory bank as a normal memory bank.

[0134] Reference Figure 9A , this may correspond to the case where one bit determination signal has a value of 1. In other words, since one memory cell among the target memory cells outputs a defective bit, the target memory cell corresponding to one bit determination signal may correspond to a defective memory cell or a single defective memory cell.

[0135] Reference Figure 9B , the first test circuit may output the first output signal OUT1 in the second state L for the region including defective memory cells among the multiple regions. The second test circuit may output the second output signal OUT2 in the first state H for the region including a single defective memory cell among the multiple regions. The third test circuit may output all the third output signals OUT3 for the multiple regions in the second state L.

[0136] This may correspond to the case where the second output signal OUT2 is output in the first state H for the region among the multiple regions that outputs the first output signal OUT1 in the second state L. Therefore, the control circuit may determine the target memory bank as a normal memory bank.

[0137] Refer to Figure 10A , this may correspond to the case where a pair of adjacent bit determination signals have a value of 1. In other words, since a pair of adjacent memory cells among the target memory cells output defective bits, the pair of target memory cells corresponding to this pair of bit determination signals may correspond to defective memory cells and adjacent double-defective memory cells.

[0138] Refer to Figure 10B, the first test circuit can output a first output signal OUT1 in a second state L for a region among multiple regions that includes a defective memory cell. The second test circuit can output second output signals OUT2 for all of the multiple regions in the second state L. The third test circuit can output a third output signal OUT3 in a first state H for a region among the multiple regions that includes adjacent double-defective memory cells.

[0139] This can correspond to a case where the third output signal OUT3 is output in the first state H for a region that outputs the first output signal OUT1 in the second state L among the multiple regions. Therefore, the control circuit can determine the target memory bank as a normal memory bank.

[0140] Reference Figure 11A , target memory cells corresponding to the bit determination signal having a value of 1 may not be adjacent to each other. In other words, the target memory cells correspond to defective memory cells, but may not be adjacent double-defective memory cells.

[0141] Reference Figure 11B , the first test circuit can output a first output signal OUT1 in a second state L for a region among multiple regions that includes a defective memory cell. The second test circuit and the third test circuit can output both the second output signal OUT2 and the third output signal OUT3 for the multiple regions in the second state L.

[0142] This can be a case where the second output signal OUT2 and the third output signal OUT3 are output in the second state L for a region that outputs the first output signal OUT1 in the second state L among the multiple regions. Therefore, the control circuit can determine the target memory bank as a defective memory bank.

[0143] Reference Figure 12A , since there are a total of three target memory cells corresponding to the bit determination signal having a value of 1, the target memory cells correspond to defective memory cells, but may not be single-defective memory cells and adjacent double-defective memory cells.

[0144] Reference Figure 12B , the first test circuit can output a first output signal OUT1 in a second state L for a region among multiple regions that includes a defective memory cell. The second test circuit and the third test circuit can output both the second output signal OUT2 and the third output signal OUT3 for the multiple regions in the second state (L).

[0145] This may correspond to a case where the second output signal OUT2 and the third output signal OUT3 are output in the second state L for a region that outputs the first output signal OUT1 in the second state L among a plurality of regions. Accordingly, the control circuit may determine the target memory bank as a defective memory bank.

[0146] In another exemplary embodiment of the present disclosure, the control circuit may use the address of the memory cell to determine whether the target memory bank is defective.

[0147] The first test circuit may identify defective memory cells among the target memory cells and may output the first address of the defective memory cells to the control circuit. When the defective memory cell is a single defective memory cell, the second test circuit may output the second address of the single defective memory cell to the control circuit. When the defective memory cells are adjacent double defective memory cells, the third test circuit may output the third address of the adjacent double defective memory cells to the control circuit.

[0148] When the first address matches the second or third address, the control circuit may determine the target memory bank as a normal memory bank. When the first address does not match the second address and the third address, the control circuit may determine the target memory bank as a defective memory bank.

[0149] Figure 13 is a view showing a system to which a memory device is applied according to an exemplary embodiment of the present disclosure.

[0150] Referring to Figure 13 , the system 1000 may include a camera 1100, a display 1200, an audio processing unit 1300, a modem 1400, DRAMs 1500a and 1500b, flash memory devices 1600a and 1600b, I / O devices 1700a and 1700b, and an application processor 1800 (hereinafter referred to as “AP”). Each of the flash memory devices 1600a and 1600b may include a controller 1610 and a flash memory 1620. The AP 1800 may include a controller 1810, an accelerator chip 1820, and an interface 1830. The system 1000 may be implemented as a laptop computer, a mobile phone, a smart phone, a tablet personal computer, a wearable device, a healthcare device, or an Internet of Things (IoT) device. Additionally, the system 1000 may be implemented as a server or a personal computer.

[0151] The camera 1100 can capture still images or moving images under user control and can store or transmit the captured image / video data to the display 1200. The audio processing unit 1300 can process the audio data or network content included in the flash devices 1600a and 1600b. The modem 1400 can modulate and transmit signals for wired / wireless data transmission and reception and can perform demodulation to recover the original signal on the receiving side. The I / O devices 1700a and 1700b can include devices for providing digital input / output functions, such as a universal serial bus (USB) or a storage device, a digital camera, a secure digital (SD) card, a digital versatile disc (DVD), a network adapter, a touch screen, and the like.

[0152] The AP 1800 can control the overall operation of the system 1000. The AP 1800 can control the display 1200 such that a part of the content stored in the flash devices 1600a and 1600b is displayed on the display 1200. When the AP 1800 receives a user input through the I / O devices 1700a and 1700b, it can perform a control operation corresponding to the user input. The AP 1800 can include an accelerator block, which is a dedicated circuit for artificial intelligence (AI) data calculation, or an accelerator chip 1820 separated from the AP 1800 can be provided. The DRAM 1500b can be additionally mounted on the accelerator block or the accelerator chip 1820. The accelerator is a functional block for professionally performing a specific function of the AP 1800, and the accelerator can include a GPU as a functional block for professionally performing graphic data processing, a neural processing unit (DPU) as a block for professionally performing AI calculation and inference, and a data processing unit (DPU) as a block for professionally performing data transmission.

[0153] The system 1000 can include multiple DRAMs 1500a and 1500b. The AP 1800 can control the DRAMs 1500a and 1500b through commands and mode register (MRS) settings that meet the standards of the Joint Electron Device Engineering Council (JEDEC), and can allow communication by setting the DRAM interface protocol to use company-specific functions such as low voltage / high speed / reliability and cyclic redundancy check (CRC) / error correction code (ECC) functions. For example, the AP 1800 can communicate with the DRAM 1500a through an interface that complies with JEDEC standards, such as LPDDR4 and LPDDR5, and the accelerator block or the accelerator chip 1820 can control the accelerator DRAM 1500b, which has a higher bandwidth than the DRAM 1500a, to perform communication by setting a new DRAM interface protocol.

[0154] Figure 13Only DRAMs 1500a and 1500b are shown, but the present disclosure is not limited thereto, and any memory, including PRAM, SRAM, MRAM, RRAM, FRAM, or hybrid RAM, may be used when the AP 1800 or the accelerator chip 1820 meets the bandwidth, response speed, and voltage conditions. DRAMs 1500a and 1500b have relatively smaller latency and bandwidth than the I / O devices 1700a and 1700b or the flash devices 1600a and 1600b. When the system 1000 is powered on, DRAMs 1500a and 1500b may be initialized, and since the operating system and application data are loaded, DRAMs 1500a and 1500b may be used as a temporary storage location for the operating system and application data or as an execution space for various software codes.

[0155] In DRAMs 1500a and 1500b, arithmetic operations such as addition / subtraction / multiplication / division, vector operations, address operations, or fast Fourier transform (FFT) operations may be performed. Additionally, functions for inferring performance used in inference may be executed within DRAMs 1500a and 1500b. Here, an artificial neural network may be used to perform inference in a deep learning algorithm. The deep learning algorithm may include a training operation of learning a model through various data and an inference operation of identifying data using the learned model. As an example, an image captured by the camera 1100 is signal-processed and stored in DRAM 1500b, and the accelerator block or the accelerator chip 1820 may perform AI data operations to identify data using the data stored in DRAM 1500b and the functions for inference.

[0156] DRAMs 1500a and 1500b may include a plurality of memory banks, and may include a BIST circuit and a control circuit as described with reference to Figures 1 to 1 FIG. 2. DRAMs 1500a and 1500b may perform a parallel test on a target memory bank among the plurality of memory banks. When at least one defective memory cell that outputs a logic state different from the input bit is a single defective memory cell or an adjacent double defective memory cell, DRAMs 1500a and 1500b may determine that the memory bank is normal.

[0157] System 1000 may include a plurality of memory devices having a larger capacitance than DRAM 1500a and 1500b or a plurality of flash memory devices 1600a and 1600b. The accelerator block or accelerator chip 1820 may use the flash memory devices 1600a and 1600b to perform training operations and AI data operations. In an example embodiment, the flash memory devices 1600a and 1600b may use arithmetic devices provided in the memory controller 1610 to more efficiently perform the training operations and inference AI data operations performed by the AP 1800 and / or the accelerator chip 1820. The flash memory devices 1600a and 1600b may store photos captured by the camera 1100 or store data transmitted over a data network. For example, augmented reality / virtual reality, high definition (HD) or ultra-high definition (UHD) content may be stored.

[0158] The present disclosure is not limited to the above embodiments and drawings, but is defined by the appended claims. Accordingly, those of ordinary skill in the art can make various substitutions, modifications or changes without departing from the scope of the present disclosure defined by the appended claims, and such substitutions, modifications or changes should be construed as being included within the scope of the present disclosure.

Claims

1. A memory device, comprising: A memory core including a memory cell array, the memory cell array including a plurality of memory cells, and the memory cell array being arranged as a plurality of memory banks; A built-in self-test (BIST) circuit configured to select a target memory bank from the plurality of memory banks and perform a parallel test on the target memory bank among the plurality of memory banks; And A control circuit configured to control the parallel test, Wherein, the BIST circuit is configured to determine one or more defective memory cells among the plurality of memory cells in the target memory bank that output defective bits, and determine whether the defective memory cells are single defective memory cells or adjacent double defective memory cells, and When the defective memory cells are not the single defective memory cells and the adjacent double defective memory cells, the control circuit is configured to determine the target memory bank as a defective memory bank.

2. The memory device according to claim 1, wherein, The BIST circuit is configured to determine, among the output bits output from the target memory cells, the output bits that are in a different logical state from the input bits as the defective bits.

3. The memory device according to claim 2, wherein, The BIST circuit includes a first test circuit configured to determine the defective memory cells, a second test circuit configured to determine whether the defective memory cells are the single defective memory cells, and a third test circuit configured to determine whether the defective memory cells are the adjacent double defective memory cells.

4. The memory device according to claim 3, wherein, When one of the target memory cells outputs the defective bit, the second test circuit determines the one memory cell as the single defective memory cell, and When a pair of adjacent memory cells among the target memory cells output the defective bits, the third test circuit determines the pair of adjacent memory cells as the adjacent double defective memory cells.

5. The memory device according to claim 4, wherein, Each of the plurality of memory banks includes a plurality of word lines and a plurality of bit lines, and the plurality of memory cells are connected to the plurality of word lines and the plurality of bit lines, and The pair of adjacent memory cells are connected to one of the plurality of word lines and a pair of adjacent bit lines among the plurality of bit lines.

6. The memory device according to claim 5, wherein, The pair of adjacent bit lines are determined by the control circuit.

7. The memory device according to claim 6, wherein, The third test circuit includes an input unit, a logic unit including a plurality of half adders, and an output unit for outputting an output signal, Wherein, the input unit is configured to receive a selection signal for determining the pair of adjacent bit lines from the control circuit, receive a bit determination signal indicating whether each of the output bits is a defective bit from the first test circuit, and output the bit determination signals corresponding to the pair of adjacent memory cells among the bit determination signals to each of the plurality of half adders, The logic unit is configured to output first to third internal signals using the bit determination signals corresponding to the pair of adjacent memory cells to each other, and The output unit is configured to output an output signal indicating whether the pair of adjacent memory cells to each other are the adjacent double defective memory cells using the first to third internal signals.

8. The memory device according to claim 7, wherein, The input unit is configured to output a (2n - 1)-th bit determination signal to an n-th half adder and includes a plurality of multiplexers, and An n-th multiplexer among the plurality of multiplexers is configured to output one of a (2n - 2)-th bit determination signal and a (2n)-th bit determination signal to the n-th half adder according to the selection signal, where n corresponds to a natural number of 1 or greater.

9. The memory device according to claim 8, wherein, When the selection signal is in a first state, the n-th multiplexer is configured to output the (2n - 2)-th bit determination signal to the n-th half adder, and when the selection signal is in a second state, the n-th multiplexer is configured to output the (2n)-th bit determination signal to the n-th half adder.

10. The memory device according to claim 7, wherein, The logic unit includes a first logic unit, a second logic unit, and a third logic unit, wherein the first logic unit includes the plurality of half adders, and each of the plurality of half adders is configured to perform a NAND logic operation and an XNOR logic operation on the bit determination signals corresponding to the pair of adjacent memory cells to each other, The second logic unit includes a plurality of second logic circuits, and each of the plurality of second logic circuits is configured to perform a first NAND logic operation, a second NAND logic operation, and an XOR logic operation on the outputs of a pair of adjacent half adders among the plurality of half adders, and The third logic unit includes at least one third logic circuit, and the third logic circuit is configured to perform a NAND logic operation, an AND logic operation, and a NOR logic operation on the output of the second logic unit to output the first to third internal signals.

11. The memory device according to claim 10, wherein, The first internal signal indicates whether, among first to fourth pairs of output bits output from first to fourth pairs of adjacent memory cells among the target memory cells, the first pair of output bits are defective bits or the second to fourth pairs of output bits are defective bits.

12. The memory device according to claim 10, wherein, The second internal signal indicates whether, among first to fourth pairs of output bits output from first to fourth pairs of adjacent memory cells among the target memory cells, there are no defective bits or a pair of output bits are defective bits among the first and second pairs of output bits, and whether there are no defective bits or a pair of output bits are defective bits among the third and fourth pairs of output bits.

13. The memory device according to claim 10, wherein, The third internal signal indicates whether each of the first to fourth pairs of output bits output from the first pair of adjacent memory cells to the fourth pair of adjacent memory cells among the target memory cells is the same as a defective bit or a normal bit.

14. The memory device according to claim 10, wherein, The output unit is configured to output the output signal by performing an AND logic operation on the first to third internal signals.

15. A memory device, comprising: A memory core including a memory cell array, the memory cell array including a plurality of memory cells, and the memory cell array being divided into a plurality of memory banks; A BIST circuit configured to select a target memory bank from the plurality of memory banks and perform a parallel test on the target memory bank among the plurality of memory banks; And A control circuit configured to control the parallel test, wherein the BIST circuit includes a first test circuit configured to determine a defective memory cell and output a first output signal for target memory cells included in the target memory bank, a second test circuit configured to determine whether the defective memory cell is a single defective memory cell and output a second output signal, and a third test circuit configured to determine whether the defective memory cell is an adjacent double-defective memory cell and output a third output signal, and wherein when the defective memory cell is not the single defective memory cell and the adjacent double-defective memory cell, the control circuit is configured to determine the target memory bank as a defective memory bank using the first to third output signals.

16. The memory device according to claim 15, wherein, The target memory cells are divided into a plurality of regions, and the BIST circuit is configured to output the first to third output signals for each of the plurality of regions.

17. The memory device according to claim 16, wherein, The first test circuit determines at least one memory cell having a logical state in which the output among the target memory cells is different from the input bit as the defective memory cell, and outputs the first output signal in a second state for the region including the defective memory cell among the plurality of regions.

18. The memory device according to claim 17, wherein, When one memory cell among the target memory cells outputs the logical state different from the input bit, the second test circuit determines the one memory cell as the single defective memory cell, and outputs the second output signal in a first state for the region including the single defective memory cell among the plurality of regions, and when a pair of adjacent memory cells among the target memory cells output the logical state different from the input bit, the third test circuit determines the pair of adjacent memory cells as the adjacent double-defective memory cells, and outputs the third output signal in a first state for the region including the adjacent double-defective memory cells among the plurality of regions.

19. The memory device according to claim 18, wherein, For at least one region among the multiple regions that outputs the first output signal in the second state, when the second output signal and the third output signal are not output in the first state, the control circuit determines the target memory bank as a defective memory bank.

20. A test method for a memory device including a plurality of memory banks, the method comprising: selecting a target memory bank from the plurality of memory banks and determining defective memory cells that output a logical state different from the input bit among target memory cells included in the target memory bank; when determining the defective memory cells among the target memory cells, determining whether the defective memory cells are single defective memory cells or adjacent double defective memory cells; and when the defective memory cells are not the single defective memory cells and the adjacent double defective memory cells, determining the target memory bank as a defective memory bank.

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