Decoding method and storage device

Abstract

The invention provides a decoding method and a storage device. The method comprises the following steps: in response to a reading instruction for reading first data from the memory module, reading the first data and a first error correction code corresponding to a first logic unit; determining first sub-data from the first data; according to preset bit information, executing a first data detection operation on the first sub-data so as to correct an error in the first sub-data; and after executing the first data detection operation on the first sub-data, executing a decoding operation on the first data according to the first error correction code. Therefore, the decoding capability of the storage device can be effectively improved on the premise that the overall operation burden is not obviously improved (even reduced).

Description

Technical Field

[0001] The present invention relates to the field of storage technologies, and particularly to a decoding method and a storage device. Background Art

[0002] In a solid-state storage device (SSD), due to its internal characteristics based on flash memory technology, data is prone to various types of errors during storage, especially bit flip errors. This requires the SSD controller to integrate an error checking and correction (ECC) circuit to ensure data integrity.

[0003] In a solid-state drive (SSD), an error correction code (ECC) circuit is a key component for detecting and correcting bit errors that occur within storage cells. The ECC adds redundant information to the original data, enabling the SSD controller to detect and repair a certain number of bit errors when reading the data, thereby maintaining the integrity and reliability of the data. Although the ECC can significantly improve data reliability, its correction ability has an upper limit, that is, the ECC can only correct a specific range of error bits. If the errors that occur in a certain storage block exceed the maximum error rate that the ECC algorithm can tolerate (usually referred to as the "erasable and correctable ability" of the erasure code), then even with the ECC mechanism, the data in that block cannot be recovered, which will lead to the situation of irrecoverable data loss.

[0004] In view of this, how to effectively manage NAND flash memory has become one of the core topics that engineers in the industry are currently concerned about. Summary of the Invention

[0005] The present invention provides a decoding method and a storage device, which can improve the decoding efficiency of the storage device.

[0006] An embodiment of the present invention provides a decoding method for a storage device, where the storage device includes a memory module, and the decoding method includes: in response to a read instruction for reading first data from the memory module, reading the first data corresponding to a first logical unit and a first error correction code; determining first sub-data from the first data; performing a first data detection operation on the first sub-data according to preset bit information to correct errors in the first sub-data; and after performing the first data detection operation on the first sub-data, performing a decoding operation on the first data according to the first error correction code.

[0007] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module, and a memory controller. The memory controller is connected to the connection interface and the memory module. The memory controller is configured to: in response to a read instruction for reading first data from the memory module, read first data corresponding to a first logical unit and a first error correction code; determine first sub-data from the first data; perform a first data detection operation on the first sub-data according to preset bit information to correct an error in the first sub-data; and after performing the first data detection operation on the first sub-data, perform a decoding operation on the first data according to the first error correction code.

[0008] Based on the above, in response to a read instruction for reading first data, first data corresponding to a first logical unit and a first error correction code can be read, and first sub-data can be determined from the first data. According to preset bit information, a first data detection operation can be first performed on the first sub-data to correct an error in the first sub-data. After performing the first data detection operation on the first sub-data, a decoding operation can be further performed on the first data according to the first error correction code. Thus, the decoding ability of the storage device can be effectively improved without significantly increasing (or even reducing) the overall operation burden. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of a data storage system shown according to an embodiment of the present invention;

[0010] Figure 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention;

[0011] Figure 3 is a schematic diagram of a managed memory module shown according to an embodiment of the present invention;

[0012] Figure 4 is a schematic diagram of a variable sampling window and a target bit interval shown according to an embodiment of the present invention;

[0013] Figure 5 is a schematic diagram of a first data detection operation shown according to an embodiment of the present invention;

[0014] Figure 6 is a schematic diagram of an operation scenario of a decoding method shown according to an embodiment of the present invention;

[0015] Figure 7 is a flowchart of a decoding method shown according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used in the drawings and the description to refer to the same or like parts.

[0017] Figure 1 is a schematic diagram of a data storage system shown according to an embodiment of the present invention. Please refer to Figure 1 , the data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system disposed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 can include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0018] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support an embedded Multi-Media Card (eMMC), a Universal Flash Storage (UFS), a Peripheral Component Interconnect Express (PCI Express), a Non-Volatile Memory Express (NVM express), a Serial Advanced Technology Attachment (SATA), a Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 (such as exchanging signals, instructions, and / or data) via the connection interface 121.

[0019] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more arrays of memory cells. The memory cells in the memory cell array store data in the form of voltages (also referred to as threshold voltages). For example, the memory module 122 may include a single-level cell (SLC) NAND flash memory module, a multi-level cell (MLC) NAND flash memory module, a triple-level cell (TLC) NAND flash memory module, a quad-level cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0020] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the overall or partial operation of the storage device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices, or a combination of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0021] The memory controller 123 may send a sequence of instructions to the memory module 122 to access the memory module 122. For example, the memory controller 123 may send a sequence of write instructions to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 may send a sequence of read instructions to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 may send a sequence of erase instructions to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 may also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited in the present invention. The memory module 122 may receive the instruction sequence from the memory controller 123 and access the storage units inside the memory module 122 according to this instruction sequence.

[0022] Figure 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention. Please refer to Figure 1 and Figure 2 , the memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0023] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can be used to control or manage the overall or partial operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is the same as the description of the memory controller 123.

[0024] In an embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and is used to cache data. For example, the buffer memory 24 can be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0025] In one embodiment, the memory controller 123 may further include an error correction circuit 25. The error correction circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on data to ensure the correctness of the data. For example, the error correction circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 may further include various other types of circuit modules (such as a power management circuit, etc.), which are not limited in the present invention.

[0026] Figure 3 is a schematic diagram of managing a memory module shown according to an embodiment of the present invention. Please refer to Figures 1 to 3 , the memory module 122 includes a plurality of physical units 301(1) to 301(B). Each physical unit includes a plurality of memory cells and is used to store data non-volatilely.

[0027] In one embodiment, a physical unit may include a physical programming unit. In one embodiment, a physical programming unit may include a plurality of physical sectors. For example, the data capacity of a physical sector may be 512 bytes (Bytes, B), and a physical programming unit may include 32 physical sectors. However, both the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can be adjusted according to practical requirements, which are not limited in the present invention. In one embodiment, a physical programming unit can be regarded as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0028] In one embodiment, a physical programming unit is the smallest unit for synchronously writing data in the memory module 122. For example, when performing a programming operation (also referred to as a write operation) on a physical programming unit to write data into this physical programming unit, multiple memory cells in this physical programming unit can be programmed synchronously to store the corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to this physical programming unit to change the threshold voltage of at least some of the memory cells in this physical programming unit. For example, the threshold voltage of a memory cell can reflect the bit data stored in this memory cell.

[0029] In one embodiment, an entity erasure unit may include a plurality of entity programming units. The plurality of entity programming units in an entity erasure unit may be synchronously erased. For example, when an erasure operation is performed on an entity erasure unit, an erasure voltage may be applied to the plurality of entity programming units in this entity erasure unit to change the threshold voltages of at least some of the storage units in these entity programming units. By performing an erasure operation on an entity erasure unit, the data stored in this entity erasure unit can be cleared. In one embodiment, an entity erasure unit may be regarded as an entity block.

[0030] In one embodiment, the memory control circuit 23 may logically associate the entity units 301(1) to 301(A) and 301(A + 1) to 301(B) with the data area 31 and the idle area 32 respectively. The entity units 301(1) to 301(A) in the data area 31 all store data (also referred to as user data) from the host system 11. For example, any one of the entity units in the data area 31 may store valid data and / or invalid data. In addition, the entity units 301(A + 1) - 301(B) in the idle area 32 do not store data (such as valid data).

[0031] In one embodiment, if a certain entity unit does not store valid data, this entity unit may be associated with the idle area 32. In addition, the entity units in the idle area 32 may be erased to clear the data in these entity units. In one embodiment, the entity units in the idle area 32 are also referred to as idle entity units. In one embodiment, the idle area 32 is also referred to as a free pool.

[0032] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more entity units from the idle area 32 and instruct the memory module 122 to store the data in the selected entity units. After the data is stored in this entity unit, this entity unit may be associated with the data area 31. In other words, one or more entity units may be alternately used between the data area 31 and the idle area 32.

[0033] In one embodiment, the memory control circuit 23 may configure a plurality of logic units 302(1) to 302(C) to map the entity units in the data area 31 (i.e., the entity units 301(1) to 301(A)). For example, one logic unit may correspond to one logical block address (LBA) or other logical management units. One logic unit may be mapped to one or more entity units.

[0034] In one embodiment, if a certain physical unit is currently mapped by any logical unit, the memory control circuit 23 may determine that the data currently stored in this physical unit includes valid data. Conversely, if a certain physical unit is not currently mapped by any logical unit, the memory control circuit 23 may determine that this physical unit does not currently store any valid data.

[0035] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in at least one management table (also referred to as the logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may, according to the information in this management table (i.e., the logical-to-physical mapping table), instruct the memory module 122 to perform operations such as data reading, writing, or erasing.

[0036] In one embodiment, the memory control circuit 23 may obtain a read instruction from the host system 11. The read instruction is used to indicate reading data (also referred to as first data) from the memory module 122. For example, the read instruction may carry an instruction code indicating the logical unit (also referred to as the first logical unit) to which the first data belongs. For example, the first logical unit may include Figure 3 at least one of the logical units 302(1) to 302(C).

[0037] In one embodiment, in response to the read instruction, the memory control circuit 23 may read the first data corresponding to the first logical unit and the error correction code corresponding to the first data (also referred to as the first error correction code) from the memory module 122. For example, the first error correction code can be used to correct errors (also referred to as error bits) in the first data.

[0038] Specifically, the first data may include data from the host system 11 (such as user data), program code (also referred to as firmware code) for running the storage device 12, and / or data for managing the storage device 12 (also referred to as system data). User data refers to data that a user wants to save, such as documents, images, video files, etc. In addition, the program code for running the storage device 12 may include firmware code.

[0039] In one embodiment, the system data includes one or more management data for the file system of storage device 12. For example, the system data may include management data of various file systems such as FAT32, exFAT (Extended File Allocation Table), NTFS, ext4, F2FS (Flash-Friendly File System), YAFFS, APFS (Apple File System), Btrfs, or ZFS. The system data is crucial for managing and maintaining the file system and its structure of storage device 12. Different types of storage devices 12 may use different file systems, and the internal data structures of different types of file systems will also vary.

[0040] FAT32 was the most commonly used file system for early USB flash drives. It has broad compatibility, and almost all operating systems can read and write USB flash drives in FAT32 format. However, FAT32 has a limitation that the size of a single file cannot exceed 4GB. exFAT was developed by Microsoft to address the limitations of FAT32, especially the support for large files. exFAT supports larger files and has good support in both Windows and MAC OS, and has gradually become the new standard for USB flash drives. NTFS is mainly used in Windows operating systems. Although some USB flash drives may also use NTFS, its cross-platform compatibility is not as good as FAT32 or exFAT. ext4 is commonly found in eMMC storage in Android devices. ext4 is a journaling file system that provides better data integrity and recovery capabilities and is widely used in Linux systems. F2FS is a file system optimized for flash memory and is mainly used in Android devices to improve performance and extend the lifespan of flash memory. YAFFS was once used as the file system for embedded systems, especially on early kernel versions of Android devices. Btrfs is an advanced file system designed for Linux that supports functions such as replication, snapshots, and checksums. Although it is still under development, it has been adopted in some scenarios. ZFS is another advanced file system that was initially developed by Sun Microsystems and can now be found in many systems. It provides functions such as data redundancy, compression, and snapshots, and is very suitable for data center environments.

[0041] Among them, the situation where the above products share some file systems is as follows:

[0042] FAT32 and exFAT: These two file systems are commonly used in various types of removable storage devices, including USB flash drives and SSDs (when used as external drives), due to their wide compatibility. ext4: Although mainly used in the Linux operating system, it can be found on various storage media such as eMMC, UFS, and SSDs, especially in Android devices and Linux servers. F2FS: Primarily used for eMMC and UFS storage on mobile devices to adapt to the characteristics and requirements of flash memory.

[0043] In one embodiment, the system data includes File Allocation Table (FAT) data. In the storage field, FAT data is part of the file system. When writing FAT data to the memory module 122, the FAT data exhibits different characteristics from the writing of user data. These differences are mainly reflected in the distribution characteristics of the data and the distribution requirements for "1" and "0".

[0044] FAT data is a type of structured metadata used to record the allocation of files in the file system. Each FAT entry (usually 16 bits or 32 bits) indicates the location of the next cluster of a file's cluster, or flags whether the cluster is unused. Unused clusters are usually marked with a specific value (such as all "0"), while clusters allocated to a file contain the address of the next cluster in the chain. This structured data usually has a relatively high degree of regularity, that is, the distribution of "1" and "0" in the FAT data follows certain rules. For example, unused cluster entries are all "0", while entries pointing to other clusters show a mixed distribution of "1" and "0".

[0045] On the other hand, user data is usually unstructured and can be any form of data, including text, images, videos, etc. The distribution of user data is usually random. In fact, to reduce the risk of bit flip errors, user data is randomized before being written to the memory module 122. For example, the data with the best randomization effect can be selected and written to the memory module 122. Therefore, in user data, the state ("1" or "0") of each bit has no obvious regularity.

[0046] In one embodiment, for the FAT32 file system, taking a USB flash drive with a size of 8GB as an example, the calculation method for the maximum possible number of bytes occupied by its FAT data (i.e., the size of a single FAT data table) is as follows:

[0047] The FAT data size of the FAT32 file system depends on the total number of clusters and the size of each FAT entry. For FAT32, each FAT entry occupies 4 bytes (32 bits) because FAT32 can manage larger disk spaces and more clusters.

[0048] To calculate the maximum capacity of the FAT data on an 8GB USB drive, assume that the maximum volume size supported by FAT32 is 2TB. The cluster size in FAT32 is usually between 512 bytes and 32KB, depending on the total size of the volume. For an 8GB USB drive, a common cluster size is 4KB (4096 bytes). For an 8GB USB drive, assuming a cluster size of 4KB (4096 bytes) and each FAT entry occupying 4 bytes, the size of the FAT data can be calculated as follows:

[0049] 2097152 × 4 (bytes) = 8388608 bytes = 8MB

[0050] Furthermore, the maximum possible value of the number of bytes occupied by the FAT data (i.e., the size of a single FAT data) can be represented in hexadecimal as follows:

[0051] 2 × 1024 × 1024 clusters = 0x0020000

[0052] Alternatively, it can be converted to binary representation as follows: 0000 0000 0010 0000 0000 0000 0000 0000

[0054] As described above, if a FAT data is represented in binary, the first 10 bits in this FAT data can be regarded as partial data with a structured feature (i.e., 10 consecutive "0"s), while the remaining bits in this FAT data do not have the said structured feature. However, other types of management data may have their respective corresponding and / or different forms of structured features, which are not restricted by the present invention.

[0055] For example, in the exFAT file system, the management data with structured features may include FAT data and Cluster Bitmap data. This FAT data is used to track the allocation status of clusters. In addition, the Cluster Bitmap data is used to record which clusters have been used and / or which clusters are free. Alternatively, in the ext4 file system, the management data with structured features may include Block Bitmap data. The Block Bitmap data is used to track whether the blocks on the disk are allocated. Alternatively, in the F2FS file system, the management data with structured features may include management data for Node Segment data and Data Segment, which is used to manage the allocation of metadata and user data. This mechanism helps to improve read / write efficiency and reduce fragmentation. Alternatively, in the XFS file system, the management data with structured features may include Allocation Groups data, which contains metadata, such as space allocation data, and provides a more flexible way to manage and recover file allocation information. In addition, more other types of management data may also have the foregoing or similar structured features, which will not be elaborated one by one herein.

[0056] In one embodiment, after reading the first data from the memory module 122, the memory control circuit 23 may determine specific data (also referred to as the first sub-data) from the first data. For example, the first sub-data contains a part of the data in the first data, and the data volume of the first sub-data is less than the total data volume of the first data.

[0057] In one embodiment, the first sub-data is the data in the first data with structured features. The structured features may be a bit sequence distributed according to a specific rule (e.g., "0" and / or "1" distributed according to a specific rule). For example, some types of system data may have the foregoing structured features.

[0058] In one embodiment, the memory control circuit 23 may determine the type of the first data. For example, the memory control circuit 23 may determine that the type of the first data is data with structured features (e.g., one or more of the foregoing management data) or data without the structured features (e.g., user data or firmware data).

[0059] In one embodiment, if the type of the first data is data with structured features, the memory control circuit 23 may further confirm the type of the first data. For example, the memory control circuit 23 may confirm which one of the aforementioned one or more management data the first data belongs to. For example, the memory control circuit 23 may confirm that the type of the first data belongs to the management data for various file systems such as FAT32, exFAT, NTFS, ext4, F2FS, YAFFS, APFS, Btrfs, or ZFS. In addition, the type of the data with structured features may also be adjusted or expanded according to practical requirements, and the present invention does not limit it.

[0060] In one embodiment, the memory control circuit 23 may determine a sampling window (also referred to as a variable sampling window) according to the type of the first data. The number of the variable sampling windows may be one or more. The memory control circuit 23 may determine at least one bit interval (also referred to as a target bit interval) in the first data according to the variable sampling window. For example, one target bit interval may correspond to one variable sampling window. Then, the memory control circuit 23 may determine the (all) bit data in the first data located within the target bit interval as the first sub-data.

[0061] In one embodiment, if the type of the first data is a certain type (also referred to as the first type), the memory control circuit 23 may determine a certain sampling window (also referred to as the first candidate sampling window) as the variable sampling window. Or, if the type of the first data is another type (also referred to as the second type), the memory control circuit 23 may determine another sampling window (also referred to as the second candidate sampling window) as the variable sampling window. It should be noted that according to the first candidate sampling window, the bit interval (also referred to as the first target bit interval) determined by the memory control circuit 23 in the first data may be different from the bit interval (also referred to as the second target bit interval) determined in the first data according to the second candidate sampling window.

[0062] Figure 4 is a schematic diagram of the variable sampling window and the target bit interval shown in the embodiment of the present invention. Please refer to Figure 4 In one embodiment, the first data includes data 41. According to the type of the data 41, the memory control circuit 23 may determine the variable sampling window W(1). The variable sampling window W(1) corresponds to the bit interval R(1) in the data 41. Therefore, the memory control circuit 23 may determine the sub-data 401 in the data 41 located within the bit interval R(1) as the first sub-data.

[0063] In one embodiment, the first data includes data 42. According to the type of data 42, the memory control circuit 23 can determine a variable sampling window W(2). The variable sampling window W(2) corresponds to the bit interval R(2) in data 42. Therefore, the memory control circuit 23 can determine the sub-data 402 located within the bit interval R(2) in data 42 as the first sub-data.

[0064] In one embodiment, the first data includes data 43. According to the type of data 43, the memory control circuit 23 can determine a variable sampling window W(3). The variable sampling window W(3) corresponds to the bit interval R(3) in data 43. Therefore, the memory control circuit 23 can determine the sub-data 403 located within the bit interval R(3) in data 43 as the first sub-data.

[0065] In one embodiment, the first data includes data 44. According to the type of data 44, the memory control circuit 23 can determine variable sampling windows W(4) and W(5). The variable sampling windows W(4) and W(5) respectively correspond to the bit intervals R(4) and R(5) in data 44. Therefore, the memory control circuit 23 can determine the sub-data 404 and 405 located within the bit intervals R(4) and R(5) in data 42 as the first sub-data.

[0066] It should be noted that in Figure 4 the embodiment, the positions and / or coverage ranges of the variable sampling window W(i) and R(i) in the corresponding data can be adjusted according to practical requirements. In Figure 4 the embodiment, i can be 1 to 5, but the present invention is not limited thereto. In addition, the number of the variable sampling windows W(i) and the number of R(i) can also be adjusted according to practical requirements.

[0067] In one embodiment, after reading the first data, the memory control circuit 23 can obtain preset bit information corresponding to the first data. The preset bit information can reflect the preset data format of the first sub-data. In one embodiment, the preset data format can match the structural characteristics of the first sub-data. For example, the preset data format can reflect the structural characteristics of the first sub-data. For example, the preset data format can reflect that the structural characteristics of the first sub-data are bit sequences distributed according to a specific rule (such as "0" and / or "1" distributed according to a specific rule).

[0068] In one embodiment, the memory control circuit 23 may determine the preset bit information according to the type of the first data. For example, if the type of the first data is a certain type (e.g., the first type), the memory control circuit 23 may determine a certain bit information (also referred to as the first candidate bit information) as the preset bit information. Or, if the type of the first data is another type (e.g., the second type), the memory control circuit 23 may determine another bit information (also referred to as the second candidate bit information) as the preset bit information. It should be noted that the preset data format (also referred to as the first preset data format) reflected by the first candidate bit information may be different from the preset data format (also referred to as the second preset data format) reflected by the second candidate bit information.

[0069] In one embodiment, the first preset data format may reflect that the structural feature of the first sub-data is a bit sequence (also referred to as the first bit sequence) distributed according to a certain rule (also referred to as the first rule). The second preset data format may reflect that the structural feature of the first sub-data is a bit sequence (also referred to as the second bit sequence) distributed according to another rule (also referred to as the second rule). The first rule is different from the second rule. For example, the distribution of bits "0" and "1" in the first bit sequence may be different from the distribution of bits "0" and "1" in the second bit sequence. In addition, the data length of the first bit sequence may be the same as or different from the data length of the second bit sequence.

[0070] In one embodiment, in response to a data writing event for the first logic unit, the memory control circuit 23 may store the category information corresponding to the first logic unit in the management table. For example, the data writing event may be used to store the data belonging to the first logic unit (i.e., the first data) together with the first error correction code into the memory module 122. The category information may reflect the type of the first data. Then, in response to a data reading event for the first logic unit, the memory control circuit 23 may obtain the category information from the management table, and then determine the preset bit information according to the category information. For example, the data reading event may be used to read the data belonging to the first logic unit (i.e., the first data) and the first error correction code from the memory module 122. Thus, during the subsequent reading of the first data, the memory control circuit 23 may synchronously determine the type of the first data, and then obtain the preset bit information.

[0071] In one embodiment, after obtaining the first sub-data and the preset bit information, the memory control circuit 23 may perform a data detection operation (also referred to as the first data detection operation) on the first sub-data according to the preset bit information to correct the errors (i.e., error bits) in the first sub-data. For example, in the first data detection operation, the memory control circuit 23 may flip at least a part of the bits in the first sub-data (e.g., flip a certain bit from "1" to "0" or from "0" to "1") based on the preset bit information to correct the errors in the first sub-data. It should be noted that the first data detection operation does not involve decoding the first data based on the first error correction code.

[0072] In one embodiment, the memory control circuit 23 may compare the first sub-data with the preset data format reflected by the preset bit information to obtain a comparison result. For example, the comparison result may reflect whether there is at least one bit (i.e., error bit) in the first sub-data that does not match the structural feature of the first sub-data. For example, according to the structural feature of the first sub-data, if the preset bit information reflects that the bit value of a certain bit (also referred to as the first bit) in the first sub-data is preset to be "1", but the actual value of the first bit in the currently obtained first sub-data is "0", then the comparison result may reflect that the first bit is an error bit. Or, according to the structural feature of the first sub-data, if the preset bit information reflects that the bit value of another bit (also referred to as the second bit) in the first sub-data is preset to be "0", but the actual bit value of the second bit in the currently obtained first sub-data is "1", then the comparison result may reflect that the second bit is an error bit. Then, the memory control circuit 23 may flip at least one bit (e.g., the aforementioned first bit and / or second bit) in the first sub-data according to the comparison result. Thus, without involving decoding the first data based on the first error correction code, the errors in the first sub-data can be quickly corrected through the first data detection operation with relatively low computational complexity and / or relatively fast execution speed.

[0073] Figure 5 is a schematic diagram of the first data detection operation shown in the embodiment of the present invention. Please refer to Figure 5 , assuming that the first data includes data 51. After determining the variable sampling window W(i), the sub-data 501 in the data 51 located within the bit interval R(i) can be determined as the first sub-data. In addition, the remaining data in the data 51 that is not located within the bit interval R(i) is not determined as the first sub-data. On the other hand, the memory control circuit 23 may obtain the preset bit information corresponding to the data 51. This preset bit information may reflect the preset data format 502 of the sub-data 501.

[0074] After determining that the sub-data 501 is the first sub-data and the preset data format 502, in the first data detection operation, the memory control circuit 23 can compare the sub-data 501 with the preset data format 502 to obtain a comparison result. For example, the comparison result can reflect whether there is at least one bit (i.e., an error bit) in the sub-data 501 that does not match the structured features of the sub-data 501. If the comparison result reflects that there is such an error bit in the sub-data 501, the memory control circuit 23 can flip this error bit. Or, if the comparison result reflects that there is no at least one bit (i.e., an error bit) in the sub-data 501 that does not match the structured features of the sub-data 501, the memory control circuit 23 may not flip any bit in the sub-data 501.

[0075] In one embodiment, the memory control circuit 23 can detect whether there is at least one bit (i.e., an error bit) in the sub-data 501 that does not match the structured features of the sub-data 501 by performing an exclusive OR (XOR) operation or other logical operations on multiple bits in the sub-data 501 and the preset data format 502 one by one. Or, in one embodiment, the memory control circuit 23 can also compare multiple bits in the sub-data 501 and the preset data format 502 one by one or in batches by other means, and the present invention does not limit this.

[0076] In one embodiment, after performing the first data detection operation on the first sub-data, the memory control circuit 23 can instruct the error correction circuit 25 to further perform a decoding operation on the first data according to the first error correction code. For example, in this decoding operation, the error correction circuit 25 can correct the errors (i.e., error bits) in the first data based on the LDPC or other decoding algorithms in combination with the first error correction code.

[0077] It should be noted that since at least a part (or even all) of the errors in the first sub-data of the first data have been corrected in advance in the first data detection operation, therefore, in the subsequent decoding operation performed by the error correction circuit 25 on the first data, the error correction information carried by the first error correction code can be used as much as possible to decode the remaining data in the first data that does not belong to the first sub-data. Thus, the overall decoding efficiency of the storage device 12 for the first data can be effectively improved.

[0078] In one embodiment, the memory control circuit 23 may update the first sub-data to new data (also referred to as the second sub-data) according to the operation result of the first data detection operation. For example, after flipping some erroneous bits in the first sub-data in the first data detection operation, the corrected first sub-data may be determined as the second sub-data. In particular, the second sub-data may conform to the preset data format reflected by the preset bit information. For example, the bit sequence formed by the multiple bits included in the second sub-data may have the preset data format. Alternatively, from another perspective, the bit sequence formed by the multiple bits included in the second sub-data may be consistent with (e.g., the same as) the distribution and / or order of the bits "1" and / or "0" defined in the preset data format.

[0079] In one embodiment, after determining the second sub-data, the memory control circuit 23 may combine the second sub-data with the remaining data in the first data (also referred to as the third sub-data) into new data (also referred to as the second data). Then, the error correction circuit 25 may perform the decoding operation on the second data according to the first error correction code. Thereafter, the corrected second data may be transmitted to the host system 11 in response to the read command.

[0080] Figure 6 is a schematic diagram of an operation scenario of a decoding method according to an embodiment of the present invention. Figure 6 , assuming that the first data includes data 61. After determining the variable sampling window W(i), the sub-data 602 in the bit interval R(i) of the data 61 can be determined as the first sub-data. In addition, the data 61 also includes the remaining data not in the bit interval R(i), namely, the sub-data 601 and 603.

[0081] After the first data detection operation is performed on sub-data 602, sub-data 602 may be updated to sub-data 621 according to the operation result of the first data detection operation. For example, compared with sub-data 602, at least part of the errors in sub-data 621 have been corrected based on the structural features of sub-data 602. Then, sub-data 621 may be combined with sub-data 601 and 603 to form data 62. For example, data 62 includes sub-data 601, 621, and 603. For example, the second data includes data 62.

[0082] After obtaining the data 62, the error correction circuit 25 can perform a decoding operation on the data 62 according to the first error correction code. For example, according to the execution result of this decoding operation, the data 62 can be updated to the data 63. For example, the data 63 includes sub-data 631, 621, and 632. The sub-data 631 is generated by correcting the error in the sub-data 601 based on the first error correction code. The sub-data 632 is generated by correcting the error in the sub-data 603 based on the first error correction code. Compared with the data 62, the errors originally existing in the data 62 in the data 63 have been corrected based on the first error correction code.

[0083] In particular, in Figure 6 embodiments, since at least some (even all) of the errors in the sub-data 602 have been corrected in advance in the first data detection operation, therefore, in the subsequent decoding operation performed on the data 62, the error correction information carried by the first error correction code can be concentrated as much as possible to correct the errors in the sub-data 601 and 603 to generate the sub-data 631 and 632. Thus, the overall decoding efficiency of the storage device 12 for the first data can be effectively improved.

[0084] From another perspective, in Figure 6 embodiments, first correct the errors in the sub-data 602 based on the structural characteristics of the sub-data 602, and then correct the errors in the sub-data 601 and 603 based on the first error correction code, which can effectively improve the error correction ability of the storage device 12 for the data 61 without significantly increasing the operation burden.

[0085] Figure 7 is a flowchart of the decoding method shown in the embodiments of the present invention. Please refer to Figure 7 , in step S701, in response to a read instruction for reading the first data from the memory module, read the first data corresponding to the first logical unit and the first error correction code. In step S702, determine the first sub-data from the first data. In step S703, perform a first data detection operation on the first sub-data according to the preset bit information to correct the error in the first sub-data. In step S704, after performing the first data detection operation on the first sub-data, perform a decoding operation on the first data according to the first error correction code.

[0086] However, Figure 7 the steps in Figure 7 have been described in detail above and will not be elaborated here. It should be noted that Figure 7 the steps in

[0087] In summary, the decoding method and storage device proposed in the embodiments of the present invention can improve the decoding efficiency of the storage device. In particular, by splitting the data to be decoded into data with structured features and data without structured features, and correcting the data with structured features in the data to be decoded based on the structured features (or preset bit information) before performing the decoding operation on the data to be decoded, the number of error bits that need to be corrected by the decoding operation subsequently can be effectively reduced. Thus, the decoding ability of the storage device can be effectively improved without significantly increasing (or even reducing) the overall operation burden.

[0088] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A decoding method, characterized in that, For a storage device, wherein the storage device includes a memory module, and the decoding method includes: In response to a read instruction to read first data from the memory module, reading the first data corresponding to a first logical unit and a first error correction code; Determining first sub-data from the first data; Performing a first data detection operation on the first sub-data according to preset bit information to correct errors in the first sub-data; and After performing the first data detection operation on the first sub-data, performing a decoding operation on the first data according to the first error correction code.

2. The decoding method according to claim 1, wherein the step of determining the first sub-data from the first data includes: Determining a variable sampling window according to the type of the first data; Determining a target bit interval in the first data according to the variable sampling window; And Determining the bit data in the first data that is within the target bit interval as the first sub-data.

3. The decoding method according to claim 2, wherein the step of determining the variable sampling window according to the type of the first data includes: If the type is a first type, determining a first candidate sampling window as the variable sampling window; And If the type is a second type, determining a second candidate sampling window as the variable sampling window, wherein a first target bit interval determined in the first data according to the first candidate sampling window is different from a second target bit interval determined in the first data according to the second candidate sampling window.

4. The decoding method according to claim 1, wherein the preset bit information reflects a preset data format of the first sub-data.

5. The decoding method according to claim 1, further comprising: Determining the preset bit information according to the type of the first data.

6. The decoding method according to claim 5, wherein the step of determining the preset bit information according to the type of the first data includes: If the type is a first type, determining first candidate bit information as the preset bit information; And If the type is a second type, determining second candidate bit information as the preset bit information, wherein a first preset data format reflected by the first candidate bit information is different from a second preset data format reflected by the second candidate bit information.

7. The decoding method according to claim 5, wherein the step of determining the preset bit information according to the type of the first data includes: In response to a data writing event for the first logical unit, storing category information corresponding to the first logical unit in a management table, wherein the category information reflects the type of the first data; And In response to a data reading event for the first logical unit, obtaining the category information from the management table and determining the preset bit information according to the category information.

8. The decoding method according to claim 1, wherein the step of performing the first data detection operation on the first sub-data according to the preset bit information to correct the errors in the first sub-data includes: Compare the first sub-data with a preset data format reflected by the preset bit information to obtain a comparison result; And According to the comparison result, flip at least one bit in the first sub-data.

9. The decoding method according to claim 1, wherein after performing the first data detection operation on the first sub-data, the step of performing the decoding operation on the first data according to the first error correction code includes: Update the first sub-data to a second sub-data according to the operation result of the first data detection operation; Combine the second sub-data with a third sub-data in the first data to form a second data; And Perform the decoding operation on the second data according to the first error correction code.

10. The decoding method according to claim 9, wherein the second sub-data conforms to the preset data format reflected by the preset bit information.

11. A storage device, characterized in that, Comprising: A connection interface for connecting to a host system; A memory module; And A memory controller connected to the connection interface and the memory module, Wherein the memory controller is configured to: In response to a read instruction for reading first data from the memory module, read the first data corresponding to a first logical unit and a first error correction code; Determine a first sub-data from the first data; Perform a first data detection operation on the first sub-data according to preset bit information to correct errors in the first sub-data; And After performing the first data detection operation on the first sub-data, perform a decoding operation on the first data according to the first error correction code.

12. The storage device according to claim 11, wherein the operation of the memory controller to determine the first sub-data from the first data includes: Determine a variable sampling window according to the type of the first data; Determine a target bit interval in the first data according to the variable sampling window; And Determine the bit data in the first data located within the target bit interval as the first sub-data.

13. The storage device according to claim 12, wherein the operation of the memory controller to determine the variable sampling window according to the type of the first data includes: If the type is the first type, determine a first candidate sampling window as the variable sampling window; And If the type is the second type, determine a second candidate sampling window as the variable sampling window, wherein a first target bit interval determined in the first data according to the first candidate sampling window is different from a second target bit interval determined in the first data according to the second candidate sampling window.

14. The storage device according to claim 11, wherein the preset bit information reflects a preset data format of the first sub-data.

15. The storage device according to claim 11, wherein the memory controller is further configured to: Determine the preset bit information according to the type of the first data.

16. The storage device according to claim 15, wherein the operation of the memory controller to determine the preset bit information according to the type of the first data includes: If the type is the first type, determine the first candidate bit information as the preset bit information; and If the type is the second type, determine the second candidate bit information as the preset bit information, where the first preset data format reflected by the first candidate bit information is different from the second preset data format reflected by the second candidate bit information.

17. The storage device according to claim 15, wherein the operation of the memory controller to determine the preset bit information according to the type of the first data includes: In response to a data write event for the first logical unit, store the category information corresponding to the first logical unit in a management table, where the category information reflects the type of the first data; and In response to a data read event for the first logical unit, obtain the category information from the management table and determine the preset bit information according to the category information.

18. The storage device according to claim 11, wherein the operation of the memory controller to perform the first data detection operation on the first sub-data according to the preset bit information to correct the error in the first sub-data includes: Compare the first sub-data with the preset data format reflected by the preset bit information to obtain a comparison result; and According to the comparison result, flip at least one bit in the first sub-data.

19. The storage device according to claim 11, wherein after the memory controller performs the first data detection operation on the first sub-data, the operation of performing the decoding operation on the first data according to the first error correction code includes: Update the first sub-data to a second sub-data according to the operation result of the first data detection operation; Combine the second sub-data with a third sub-data in the first data to form a second data; and Perform the decoding operation on the second data according to the first error correction code.

20. The storage device according to claim 19, wherein the second sub-data conforms to the preset data format reflected by the preset bit information.

Images