Semiconductor structure and forming method thereof
Through radical etching and digital etching, the shape of the recess and channel layer edges is optimized, and the poor shape caused by silicon germanium diffusion is solved, the device performance and reliability is improved, residue removal and the quality of the epitaxial layer is improved.
Patent Information
- Application Number
- CN202410082497.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-19
- Publication Date
- 2025-07-25
AI Technical Summary
During the process of making the gate device structure, the diffusion of germanium elements in the silicon and silicon germanium stack layers leads to poor shape of the recess and channel layer edges, affecting device performance and reliability, and it is difficult to remove residue after the channel is released.
Using a combination of radical etching and digital etching, the shape of the recess and channel layer edges is optimized, and residues are removed by selective etching, including the first etching process to form arcuate recesses and rounded edges, the second etching process to form rectangular recesses and square corner edges, and the third etching process to remove residues.
The shape of the recess and channel layer edges is optimized, the performance and reliability of the device are improved, the quality of the epitaxial layer is ensured, and the residue after the channel is released is effectively removed.
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Figure CN120376411A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a method for forming the same. Background Art
[0002] During the process of fabricating a Gate All Around (GAA) device structure, it is necessary to perform a lateral etching process on a stacked layer of silicon and silicon germanium to form a recess. In the necessary processes such as deposition and annealing involved in the process before forming the recess, there will inevitably be high-temperature processes. The germanium element in the stacked layer of silicon and silicon germanium will inevitably diffuse to a certain extent, resulting in the formation of a silicon germanium mixed layer with a lower germanium concentration at the interface between silicon and silicon germanium. When performing a lateral etching process on the stacked layer of silicon and silicon germanium to form a recess, the higher the concentration of germanium, the faster its etching rate. Then, different etching rates are presented at the boundary of the silicon germanium layer and the middle of the silicon germanium layer, and finally a recess with an "inward concave" crescent shape is formed, and the edge of the silicon layer presents a rounded shape. This will lead to a reduction in the quality of the subsequently formed epitaxial source and drain and easy short-circuiting, reducing the device reliability.
[0003] In addition, when removing the sacrificial layer to release the channel subsequently, this part of the silicon germanium mixed layer is also more difficult to remove, and residues are easily formed, affecting the quality of the metal layer filled after releasing the channel.
[0004] Therefore, it is necessary to provide a more effective and reliable technical solution to optimize the shape of the recess and the edge of the silicon layer, remove the residues after releasing the channel, and improve the device performance and reliability. Summary of the Invention
[0005] This application provides a semiconductor structure and a method for forming the same, which can optimize the shape of the recess and the edge of the channel layer, remove the residues after releasing the channel, and improve the device performance and reliability.
[0006] One aspect of this application provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, on the surface of which a fin portion and a gate structure are sequentially formed, wherein the fin portion includes a plurality of sacrificial layers and channel layers stacked in sequence; performing a first etching process to etch the sacrificial layer to form recesses on both sides of the sacrificial layer, the recesses are arc-shaped, and the edges of the channel layer exposed by the recesses are rounded, and the etching selectivity of the first etching process for the channel layer and the sacrificial layer is (20:1)-(200:1); performing a second etching process to process the recesses and the edges of the channel layer to make the recesses rectangular and the edges of the channel layer square, and the etching selectivity of the second etching process for the channel layer and the sacrificial layer is (0.01:1)-(500:1).
[0007] In some embodiments of this application, the material of the channel layer is silicon, and the material of the sacrificial layer is silicon germanium.
[0008] In some embodiments of the present application, the process parameters of the first etching process include: the etchant includes any one or more of NF3, H2, CF4, He, and Ar; the etching temperature is -20°C - 100°C; the etching pressure is 100 mT - 3000 mT; the etching time is 6 s - 120 s.
[0009] In some embodiments of the present application, the process parameters of the second etching process include: the etchant includes any one or more of NF3, CF4, He, and Ar; the etching temperature is -20°C - 100°C; the etching pressure is 100 mT - 3000 mT; the etching time is 6 s - 120 s.
[0010] In some embodiments of the present application, after performing the first etching process, the radian of the concave portion is 80 - 90 degrees, and the radian of the rounded corner at the edge of the channel layer is 85 - 90 degrees.
[0011] In some embodiments of the present application, after performing the second etching process, the depth of the concave portion is 6 - 15 nm.
[0012] In some embodiments of the present application, the method for forming the semiconductor structure further includes: forming an inner sidewall in the concave portion; epitaxially growing an epitaxial layer on the semiconductor substrate surfaces on both sides of the fin; removing the sacrificial layer and forming a metal layer at the original position of the sacrificial layer.
[0013] In some embodiments of the present application, after removing the sacrificial layer to form a hollow layer, there are residues on the surface of the channel layer adjacent to the sacrificial layer, and a third etching process is performed to remove the residues.
[0014] In some embodiments of the present application, the process parameters of the third etching process include: the etchant includes any one or more of NF3, CF4, He, and Ar; the etching temperature is -20°C - 100°C; the etching pressure is 100 mT - 3000 mT; the etching time is 6 s - 240 s.
[0015] Another aspect of the present application further provides a semiconductor structure, including: a semiconductor substrate, on the surface of which a fin and a gate structure are sequentially formed, wherein the fin includes a plurality of metal layers and channel layers stacked in sequence, an inner sidewall is formed on the sidewall of the metal layer, and an epitaxial layer is formed on the semiconductor substrate surfaces on both sides of the fin.
[0016] In some embodiments of the present application, the material of the channel layer is silicon.
[0017] In some embodiments of the present application, the thickness of the inner sidewall is 6 - 20 nm.
[0018] The present application provides a semiconductor structure and a method for forming the same, which can optimize the shapes of the concave portion and the edge of the channel layer, and remove the residue after releasing the channel, thereby improving the device performance and reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The following drawings detail exemplary embodiments disclosed in the present application. Wherein the same reference numerals represent similar structures in several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for illustrative and descriptive purposes, and are not intended to limit the scope of the present application. Embodiments in other ways may also achieve the inventive concept in the present application. It should be understood that the drawings are not drawn to scale.
[0020] Wherein:
[0021] Figures 1 to 2 are schematic structural diagrams of each step in a method for forming some semiconductor structures;
[0022] Figures 3 to 10 are schematic structural diagrams of each step in the method for forming the semiconductor structure according to the embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0023] The following description provides specific application scenarios and requirements of the present application, aiming to enable those skilled in the art to manufacture and use the content in the present application. For those skilled in the art, various partial modifications to the disclosed embodiments are obvious, and the general principles defined here can be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the disclosed embodiments, but has the broadest scope consistent with the claims.
[0024] The technical solution of the present invention will be described in detail below with reference to the embodiments and the drawings.
[0025] Figures 1 to 2 are schematic structural diagrams of each step in a method for forming some semiconductor structures.
[0026] Referring to Figure 1 as shown, a semiconductor substrate 100 is provided, and a fin 110 and a gate structure 120 are sequentially formed on the surface of the semiconductor substrate 100. Among them, the fin 110 includes a plurality of sacrificial layers 111 and a channel layer 112 stacked in sequence. Among them, the material of the sacrificial layer 111 is silicon germanium, and the material of the channel layer 112 is silicon.
[0027] Referring to Figure 2As shown, the sacrificial layer 111 is etched to form a recess 113 on the sidewall of the sacrificial layer 111. Since necessary processes such as deposition and annealing involved in the process before forming the recess 113 will inevitably have high-temperature processes, the germanium element in the sacrificial layer 111 will inevitably diffuse to a certain extent, and a silicon-germanium alloy with a lower germanium concentration is formed at the interface between the sacrificial layer 111 and the channel layer 112. When the sacrificial layer 111 is laterally etched to form the recess 113, the higher the concentration of germanium, the faster its etching rate. Then, the etching rate at the boundary of the sacrificial layer 111 is faster, and a part of the channel layer 112 with diffused germanium is also etched, finally forming a crescent-shaped recess 113 with an "inward concave" shape, and causing the edge of the channel layer 112 to present a rounded corner structure. Such a structure will affect the epitaxy of the thickness source and drain, reducing the device reliability.
[0028] In view of the above problems, the present application provides a semiconductor structure and a method for forming the same, which can optimize the shape of the recess and the edge of the channel layer, and remove the residue after releasing the channel, improving the device performance and reliability.
[0029] Figures 3 to 10 It is a schematic structural diagram of each step in the method for forming the semiconductor structure according to the embodiment of the present application. The following will describe in detail the method for forming the semiconductor structure according to the embodiment of the present application with reference to the accompanying drawings.
[0030] Reference Figure 3 As shown, a semiconductor substrate 200 is provided, and a fin 210 and a gate structure 220 are sequentially formed on the surface of the semiconductor substrate 200. Among them, the fin 210 includes a plurality of sacrificial layers 211 and channel layers 212 stacked in sequence.
[0031] In some embodiments of the present application, the material of the semiconductor substrate 200 includes (i) elemental semiconductors, such as silicon or germanium, etc.; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide, etc.; (iii) alloy semiconductors, such as silicon-germanium carbide, silicon-germanium, gallium phosphide arsenide or gallium indium phosphide, etc.; or (iv) a combination of the above.
[0032] In some embodiments of the present application, a plurality of fins 210 may be formed on the semiconductor substrate 200. For the sake of simplicity in this embodiment, only one fin is taken as an example.
[0033] In some embodiments of the present application, the material of the sacrificial layer 211 is silicon-germanium, and the material of the channel layer 212 is silicon.
[0034] In some embodiments of the present application, the number of the sacrificial layer 211 and the channel layer 212 is multiple layers. In this embodiment, only three sacrificial layers 211 and three channel layers 212 are taken as an example.
[0035] In some embodiments of the present application, the gate structure 220 includes a gate oxide layer, a gate layer, a mask layer, and a spacer layer located on the sidewalls of the gate oxide layer, the gate layer, and the mask layer in sequence on the surface of the fin 110, etc.
[0036] Refer to Figure 4 As shown, a first etching process is performed to etch the sacrificial layer 211 to form recesses 213 on both sides of the sacrificial layer 211. The recesses 213 are arc-shaped, and the edges of the channel layer 212 exposed by the recesses 213 are rounded. The etching selectivity of the first etching process for the channel layer 212 and the sacrificial layer 211 is (20:1)-(200:1), for example, 25:1.
[0037] In some embodiments of the present application, after the first etching process, the radian of the recess 213 is 80-90 degrees, for example, 86 degrees. The radian of the rounded corner of the edge of the channel layer 212 is 85-90 degrees, for example, 88 degrees. In the technical solution of the present application, the first etching process is, for example, radical etching (Radical Etch) combined with digital simulation etching (Digital Etching). Different from wet etching in conventional processes, the radical dry etching of the present application provides an appropriate low selectivity ratio of silicon and silicon germanium, which can etch less silicon, making the radian of the rounded corner of the edge of the channel layer 212 smaller than that of the conventional process. It is equivalent to initially shaping the rounded corner morphology and increasing the radian of the recess 213, reducing the sacrificial layer 211 on both the upper and lower sides of the recess 213, facilitating the subsequent removal of this part of the sacrificial layer 211. That is, making the recess 213 sink deeper and the rounded corner of the edge of the channel layer 212 protrude less.
[0038] In some embodiments of the present application, the process parameters of the first etching process include: the etchant includes any one or more of NF3, H2, CF4, He, and Ar; the etching temperature is -20°C - 100°C; the etching pressure is 100mT - 3000mT; the etching time is 6s - 120s. For example, the etchant includes NF3 and H2; the etching temperature is 30°C; the etching pressure is 900mT; the etching time is 20s.
[0039] Refer to Figure 5 As shown, a second etching process is performed on the recess 213 and the edge of the channel layer 212 to make the recess 213 rectangular and the edge of the channel layer 212 square. The etching selectivity of the second etching process for the channel layer 212 and the sacrificial layer 211 is (0.01:1)-(500:1), for example, 30:1.
[0040] In the technical solution of the present application, the second etching process is a dry etching process with a relatively high selectivity for etching silicon and silicon germanium, that is, more silicon is etched. Therefore, first, the rounded corners at the edges of the channel layer 212 can be trimmed to form square corners. Secondly, the sacrificial layers 211 on the upper and lower sides of the concave portion 213 with a higher silicon content can be preferentially etched, so that the concave portion 213 is rectangular.
[0041] In some embodiments of the present application, after the second etching process is performed, the depth of the concave portion 213 is 6-15 nm, for example, 8-10 nm.
[0042] In some embodiments of the present application, the process parameters of the second etching process include: the process parameters of the second etching process include: the etchant includes any one or more of NF3, CF4, He, and Ar; the etching temperature is -20°C - 100°C; the etching pressure is 100 mT - 3000 mT; the etching time is 6 s - 120 s. For example, the etchant includes NF3 and H2; the etching temperature is -10°C; the etching pressure is 200 mT; the etching time is 20 s.
[0043] In the technical solution of the present application, the concave portion and the edges of the channel layer are initially shaped by the first etching process, and then the shapes of the concave portion and the edges of the channel layer are finally optimized by the second etching process, so that the concave portion 213 is rectangular and the edges of the channel layer 212 are square corners, which can improve the quality of subsequent epitaxial source / drain, thereby improving the device performance and reliability.
[0044] Reference Figure 6 As shown, an inner sidewall 230 is formed in the concave portion 213.
[0045] In some embodiments of the present application, the method for forming the inner sidewall 230 includes: depositing a layer of inner sidewall material on the sidewalls of the fin 210, the surface of the semiconductor substrate 200, and the surface and sidewalls of the gate structure 220; then etching away the inner sidewall material outside the concave portion 213 to form the inner sidewall 330 in the concave portion 213.
[0046] In some embodiments of the present application, the material of the inner sidewall 230 is silicon nitride.
[0047] Reference Figure 7 As shown, an epitaxial layer 240 is epitaxially grown on the surfaces of the semiconductor substrate 200 on both sides of the fin 210. The epitaxial layer 240 is the source / drain of the GAA device.
[0048] It should be noted that the technical solution of the present application is not only applicable to the etching morphology modification of the silicon and silicon germanium stacked layer in the GAA device structure, but also applicable to the etching morphology modification of other stacked layers with similar requirements.
[0049] In the technical solution of the present application, since the concave portion 213 is rectangular and the edges of the channel layer 212 are square corners, the quality of the source and drain of the epitaxial layer 240 can be improved, thereby improving the device performance and reliability.
[0050] Reference Figure 8 、 Figure 9 and Figure 10 As shown in
[0051] Reference Figure 8 As shown, in some embodiments of the present application, after removing the sacrificial layer 211 to form the hollow layer 250, there are residues 251 on the surface of the channel layer 212 adjacent to the sacrificial layer 211. Currently, a wet etching process is generally used to remove the sacrificial layer 211. Since the silicon concentration of the part of the sacrificial layer 211 adjacent to the surface of the channel layer 212 is higher, its etching rate is slower. Therefore, this part of the sacrificial layer 211 is difficult to be completely removed and residues 251 are easily formed.
[0052] Reference Figure 9 As shown, due to the existence of the residues 251, a third etching process is performed to remove the residues 251.
[0053] In some embodiments of the present application, the process parameters of the third etching process include: the etchant includes any one or more of NF3, CF4, He, and Ar; the etching temperature is -20°C - 100°C; the etching pressure is 100mT - 3000mT; the etching time is 6s - 240s. For example, the etchant includes NF3 and Ar; the etching temperature is -20°C; the etching pressure is 600mT; the etching time is 240s.
[0054] In the technical solution of the present application, since there are no by-products that are difficult to volatilize in the previous radical etching, the residues 251 are relatively easy to remove. In addition, selecting an etching process with a faster etching rate for germanium can effectively remove the residues 251.
[0055] Reference Figure 10 As shown, a metal layer 260 is formed in the hollow layer 250.
[0056] In some embodiments of the present application, the material of the metal layer 260 includes tungsten.
[0057] The technical solution of this application uses the Radical free radical co-etching method, which can be combined with different Si / SiGe selectivity ratios to Digital Flexibly remove the Si and SiGe intermixing layer. During the free radical etching process, the etching selectivity of Si or SiGe to the low dielectric constant material layer, silicon oxide, and silicon nitride is as high as more than 200, and the etching selectivity of Si / SiGe can be achieved at 0.01 - 100:1.
[0058] This application provides a semiconductor structure and a method for forming the same, which can optimize the shape of the recess and the edge of the channel layer, and remove the residue after releasing the channel, improving the device performance and reliability.
[0059] This application also provides a semiconductor structure, refer to Figure 10 As shown, it includes: a semiconductor substrate 200, on the surface of which a fin 210 and a gate structure 220 are sequentially formed. Among them, the fin 210 includes a plurality of metal layers 260 and a channel layer 212 stacked in sequence. An inner sidewall 230 is formed on the sidewall of the metal layer 260, and an epitaxial layer 240 is formed on the surface of the semiconductor substrate 200 on both sides of the fin 210.
[0060] In some embodiments of this application, the material of the semiconductor substrate 200 includes (i) elemental semiconductors, such as silicon or germanium, etc.; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide, etc.; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium phosphide arsenide, or gallium indium phosphide, etc.; or (iv) a combination of the above.
[0061] In some embodiments of this application, multiple fins 210 may be formed on the semiconductor substrate 200. For the purpose of simplicity in this embodiment, only one fin is taken as an example.
[0062] In some embodiments of this application, the material of the metal layer 260 is, for example, tungsten, and the material of the channel layer 212 is silicon.
[0063] In some embodiments of this application, the number of the metal layer 260 and the channel layer 212 is multiple layers. In this embodiment, only three metal layers 260 and three channel layers 212 are taken as an example.
[0064] In some embodiments of this application, the gate structure 220 includes a gate oxide layer, a gate layer, a mask layer sequentially located on the surface of the fin 110, and a sidewall layer located on the sidewalls of the gate oxide layer, the gate layer, and the mask layer, etc.
[0065] In some embodiments of this application, the inner sidewall 230 is rectangular and the edge of the channel layer 212 is square.
[0066] In some embodiments of the present application, the thickness of the inner wall 230 is 6 - 20 nm, for example, 10 nm.
[0067] In some embodiments of the present application, the material of the inner wall 230 is silicon nitride.
[0068] In some embodiments of the present application, the epitaxial layer 240 serves as the source and drain of the GAA device.
[0069] In the technical solution of the present application, since the inner wall 230 is rectangular and the edges of the channel layer 212 are square - angled, the quality of the source and drain of the epitaxial layer 240 can be improved, thereby improving the device performance and reliability.
[0070] In some embodiments of the present application, the material of the metal layer 260 includes tungsten.
[0071] The present application provides a semiconductor structure and a method for forming the same, which can optimize the shapes of the recess and the edges of the channel layer, and remove the residues after releasing the channel, thereby improving the device performance and reliability.
[0072] In summary, after reading the content of the present application, those skilled in the art can understand that the foregoing application content can be presented only by way of example and may not be restrictive. Although not explicitly stated here, those skilled in the art can understand that the present application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of the present application.
[0073] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may also be an intermediate element.
[0074] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there may also be an intermediate element. In contrast, the term "directly" means without an intermediate element. It should also be understood that the terms "comprise", "comprising", "include", or "including", when used in this application document, specify the presence of the recorded features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their groups.
[0075] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be referred to as a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference designators represent the same elements throughout the specification.
[0076] In addition, the present application specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Thus, differences from the shapes shown due to, for example, manufacturing techniques and / or tolerances are foreseeable. Accordingly, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in the shapes caused by, for example, manufacturing. For example, an etched region shown as rectangular will typically have rounded or curved features. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device nor to limit the scope of the exemplary embodiments.
Claims
1. A method for forming a semiconductor structure, characterized in that Including: Providing a semiconductor substrate, on the surface of which a fin portion and a gate structure are sequentially formed. Among them, the fin portion includes a plurality of sacrificial layers and channel layers stacked in sequence; Performing a first etching process to etch the sacrificial layer to form recesses on both sides of the sacrificial layer. The recesses are arc-shaped, and the edges of the channel layer exposed by the recesses are rounded. The etching selectivity of the first etching process for the channel layer and the sacrificial layer is (20:1)-(200:1); Performing a second etching process to process the recesses and the edges of the channel layer so that the recesses are rectangular and the edges of the channel layer are square. The etching selectivity of the second etching process for the channel layer and the sacrificial layer is (0.01:1)-(500:1).
2. The method for forming a semiconductor structure according to claim 1, wherein, The material of the channel layer is silicon, and the material of the sacrificial layer is silicon germanium.
3. The method for forming a semiconductor structure according to claim 2, wherein, The process parameters of the first etching process include: the etching agent includes any one or more of NF3, H2, CF4, He, and Ar; the etching temperature is -20°C - 100°C; the etching pressure is 100mT - 3000mT; the etching time is 6s - 120s.
4. The method for forming a semiconductor structure according to claim 2, wherein The process parameters of the second etching process include: the etching agent includes any one or more of NF3, CF4, He, and Ar; the etching temperature is -20°C - 100°C; the etching pressure is 100mT - 3000mT; the etching time is 6s - 120s.
5. The method for forming a semiconductor structure as claimed in claim 1, wherein, After performing the first etching process, the radian of the recesses is 80 - 90 degrees, and the radian of the rounded corners of the channel layer edges is 85 - 90 degrees.
6. The method for forming a semiconductor structure according to claim 1, wherein, After performing the second etching process, the depth of the recesses is 6 - 15nm.
7. The method for forming a semiconductor structure according to claim 1, wherein Also including: Forming inner sidewalls in the recesses; Epitaxially growing an epitaxial layer on the surfaces of the semiconductor substrate on both sides of the fin portion; Removing the sacrificial layer and forming a metal layer at the original position of the sacrificial layer.
8. The method for forming a semiconductor structure according to claim 7, wherein, After removing the sacrificial layer to form a hollow layer, there are residues on the surface of the channel layer adjacent to the sacrificial layer. Performing a third etching process to remove the residues.
9. The method for forming a semiconductor structure according to claim 8, wherein, The process parameters of the third etching process include: the etching agent includes any one or more of NF3, CF4, He, and Ar; the etching temperature is -20°C - 100°C; the etching pressure is 100mT - 3000mT; the etching time is 6s - 240s.
10. A semiconductor structure, characterized in that, Including: A semiconductor substrate, on the surface of which a fin portion and a gate structure are sequentially formed. Among them, the fin portion includes a plurality of metal layers and channel layers stacked in sequence. Inner sidewalls are formed on the sidewalls of the metal layers, and epitaxial layers are formed on the surfaces of the semiconductor substrate on both sides of the fin portion.
11. The semiconductor structure according to claim 10, wherein, The material of the channel layer is silicon.
12. The semiconductor structure according to claim 10, wherein The thickness of the inner sidewalls is 6 - 20nm.