Three-dimensional sensing, storing and computing integrated structure and manufacturing method and testing structure thereof

Abstract

The invention relates to a three-dimensional sensing, storing and computing integrated structure and a manufacturing method and a testing structure thereof, belongs to the technical field of semiconductors, and solves the problem that the existing three-dimensional integration method faces the shortage of resource allocation of a rewiring layer. The manufacturing method of the three-dimensional sensing, storing and computing integrated structure comprises the following steps: forming a fan-out packaged processor, a memory and an image sensor through a subsequent process; mounting the fan-out type packaged processor on a substrate in a surface mounting manner; bonding the memory to the upper part of the processor of the fan-out type package; and inverting the image sensor, bonding the image sensor above the memory, and routing the image sensor from the memory to the substrate. According to the manufacturing method of the three-dimensional sensing, storing and computing integrated structure, a manufacturing method of a three-dimensional testability design structure is provided, and joint testing among an image sensor, a memory and a processor is achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a three-dimensional sensing and computing integrated structure, a manufacturing method thereof, and a test structure. Background Art

[0002] The improvement of the performance of vision image sensors has led to a sharp increase in data volume. The cluster processing relying on the data center mode is restricted by transmission delay and bandwidth, and the real-time performance cannot be satisfied. A large amount of generated image data piles up, facing problems such as data processing and storage. The demand for intelligent edge processing of image information is extremely urgent. The manufacturing of image sensors, processors, and memory chips relies on different device structures, circuit designs, and processing technologies. In order to realize a high-performance, miniaturized integrated optoelectronic fusion system chip for sensing and computing, three-dimensional integration is a key technical path and practical method.

[0003] However, the existing three-dimensional integration methods face the problem of tight resource allocation of the re-wiring layer, especially for the bottom-layer processor chips. Since the bottom-layer processor chips adopt the form of circular data transfer, if interconnection is achieved through an interposer, it will be very difficult to allocate resources for the re-wiring layer of the interposer to achieve high-speed communication. Summary of the Invention

[0004] In view of the above analysis, embodiments of the present invention aim to provide a three-dimensional sensing and computing integrated structure, a manufacturing method thereof, and a test structure to solve the problem of tight resource allocation of the re-wiring layer faced by the existing three-dimensional integration methods.

[0005] On the one hand, embodiments of the present invention provide a manufacturing method of a three-dimensional sensing and computing integrated structure, including the following steps:

[0006] Forming a fan-out packaged processor, memory, and image sensor through back-end processes;

[0007] Mounting the fan-out packaged processor on a substrate;

[0008] Bonding the memory above the fan-out packaged processor; and

[0009] Inverting and bonding the image sensor above the memory, and wire-bonding from the memory to the substrate.

[0010] Based on a further improvement of the above method, forming a fan-out packaged processor through back-end processes includes:

[0011] Placing one or more processor chips on a carrier plate with bonding glue and fabricating copper pillars;

[0012] Covering the one or more processor chips and the copper pillars with a molding material;

[0013] Grind the encapsulation material flat by chemical mechanical polishing process to expose the copper pillars;

[0014] Form a front side redistribution layer and implant solder balls on the one or more processor chips; and

[0015] Separate the carrier board by ultraviolet laser debonding technology.

[0016] Based on a further improvement of the above method, forming a memory through back-end processes includes:

[0017] Etch through-silicon vias on the memory chip and fill them with copper;

[0018] Form a front side redistribution layer on the etched memory chip;

[0019] Bond a carrier board on the front side redistribution layer;

[0020] Grind the back side of the memory chip flat by chemical mechanical polishing process to expose the through-silicon vias;

[0021] Form a back side redistribution layer and implant solder balls on the ground back side of the memory chip; and

[0022] Separate the carrier board by ultraviolet laser debonding technology.

[0023] Based on a further improvement of the above method, forming an image sensor through back-end processes includes:

[0024] Form a front side redistribution layer on the image sensor chip;

[0025] Bond a carrier board on the front side redistribution layer;

[0026] Thin the substrate of the image sensor chip by chemical mechanical polishing process; and

[0027] Form through-silicon vias on the carrier board by back via process.

[0028] Based on a further improvement of the above method, the image sensor chip is a CMOS image sensor chip, and the manufacturing method of the CMOS image sensor chip includes:

[0029] Fabricate photodiodes and pixel regions on a wafer;

[0030] Fabricate a metal interconnect layer on the wafer.

[0031] On the other hand, an embodiment of the present invention provides a three-dimensional sensing and computing integrated structure, including:

[0032] A processor, a memory, and an inverted image sensor in a fan-out package stacked in sequence on a substrate; wherein,

[0033] The fan-out packaged processor includes one or more processor chips, the plastic encapsulation of the one or more processor chips, the front-side redistribution layer of the one or more processor chips, and solder balls thereon.

[0034] The memory includes memory chips, through-silicon vias, the front-side redistribution layer of the memory chips, and solder balls thereon, and the back-side redistribution layer of the memory chips. The front-side redistribution layer and the back-side redistribution layer of the memory chips are electrically interconnected through the through-silicon vias.

[0035] The image sensor includes an image sensor chip, the front-side redistribution layer of the image sensor chip, and a carrier board thereon. The carrier board has through-silicon vias therein and the through-silicon vias are electrically interconnected with the front-side redistribution layer of the image sensor chip.

[0036] The front-side redistribution layer of the one or more processor chips and the back-side redistribution layer of the memory chips are electrically interconnected through solder balls. The front-side redistribution layer of the memory chips and the through-silicon vias in the carrier board are electrically interconnected through solder balls.

[0037] On the other hand, an embodiment of the present invention further provides a test structure for a three-dimensional sensing, memory, and computing integrated structure. The three-dimensional sensing, memory, and computing integrated structure includes a fan-out packaged processor, a memory, and an inverted image sensor stacked in sequence. It is characterized in that the test structure includes:

[0038] A test control interface, a chip select register, a bypass register located on the image sensor, and a scan boundary unit located around the image sensor chip;

[0039] A test control interface, a chip select register, a bypass register located on one processor chip, and a scan boundary unit located around the one or more processor chips;

[0040] A main control test interface and two slave test control interfaces located on the memory. The main control test interface controls the two slave test control interfaces in parallel, and the main control test interface is used to receive external test signals;

[0041] One of the slave test control interfaces is serially interconnected with the test control interface, the chip select register, the bypass register located on the image sensor, and the scan boundary unit located around the image sensor chip to form an image sensor test structure;

[0042] The other slave test control interface is serially interconnected with the test control interface, the chip select register, the bypass register located on one processor chip, and the scan boundary unit located around the one or more processor chips to form a processor test structure.

[0043] Based on the further improvement of the above test structure, the image sensor test structure is configured as follows:

[0044] The chip select register and the bypass register select whether to test the image sensor chip. If the chip select register and the bypass register select to test the image sensor chip, the on-off and logic tests of the image sensor chip are performed through the scan boundary unit located around the image sensor chip.

[0045] The processor test structure is configured as follows:

[0046] The chip select register and the bypass register select whether to test the processor chip. If the chip select register and the bypass register select to test the processor chip, the on-off and logic tests of the processor chip are performed through the scan boundary unit located around the processor chip.

[0047] Based on the further improvement of the above test structure, the main control test interface, the slave test control interface, and the test control interface are JTAG interfaces.

[0048] Based on the further improvement of the above test structure, the image sensor test structure and the processor test structure are serially interconnected through the through-silicon vias in the memory.

[0049] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0050] 1. In the solution of the present invention, the processor is fan-out packaged, and after the redistribution layer is fabricated, it is bonded to the active interposer, which alleviates the wiring pressure of the active interposer.

[0051] 2. In the solution of the present invention, the bottom processors can communicate and interconnect with each other, fully ensuring the high bandwidth and low latency of the ring data transfer of the processors, and improving the processor speed and computing power.

[0052] 3. The solution of the present invention provides a three-dimensional testability design structure. This architecture is based on the IEEE1838 standard and is configured with a classic JTAG configuration interface based on 1149.1 to realize the joint test between the image sensor, the memory, and the processor.

[0053] 4. In the solution of the present invention, the JTAG interface is used as the test access interface, and multiple chips share the control signals TRST, TCK, and TMS, which can realize the tests in multiple links before bonding, during bonding, and after bonding.

[0054] 5. In the solution of the present invention, for the bottom processor chip, input and output test signals can be serially connected and a daisy chain can be formed through the redistribution layer of the fan-out package, which increases the test coverage rate of the processor and reduces the test time at the same time.

[0055] In the present invention, the above technical solutions can also be combined with each other to achieve more preferred combined solutions. Other features and advantages of the present invention will be described in the following specification, and some advantages can be made obvious from the specification, or can be understood by implementing the present invention. The objectives and other advantages of the present invention can be achieved and obtained through the content specifically pointed out in the specification and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The drawings are only for the purpose of showing specific embodiments, and are not considered as a limitation to the present invention. Throughout the drawings, the same reference signs denote the same components;

[0057] Figure 1 It is a schematic diagram of a three-dimensional sense-computation integrated structure according to an embodiment of the present invention.

[0058] Figure 2 It is a schematic flow diagram of a manufacturing method of a three-dimensional sense-computation integrated structure according to an embodiment of the present invention.

[0059] Figures 3-1 to 3-5 It shows a schematic structural diagram of a process flow of a fan-out package processor according to an embodiment of the present invention.

[0060] Figures 4-1 to 4-7 It shows a schematic structural diagram of a process flow of a memory according to an embodiment of the present invention.

[0061] Figures 5-1 to 5-5 It shows a schematic structural diagram of a process flow of an image sensor according to an embodiment of the present invention.

[0062] Figure 6 It shows a conceptual structural diagram of attaching a fan-out package processor to a substrate according to an embodiment of the present invention.

[0063] Figure 7 It shows a conceptual structural diagram of bonding a memory above a fan-out package processor according to an embodiment of the present invention.

[0064] Figure 8 It shows a schematic diagram of a test structure of a three-dimensional sense-computation integrated structure according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0065] The preferred embodiments of the present invention will be specifically described below with reference to the accompanying drawings. The accompanying drawings form a part of this application and are used together with the embodiments of the present invention to explain the principles of the present invention, rather than to limit the scope of the present invention.

[0066] Figure 1 It is a schematic diagram of a three-dimensional sensing, memory, and computing integrated structure according to an embodiment of the present invention.

[0067] The following will be combined with Figure 1 to describe the three-dimensional sensing, memory, and computing integrated structure of the embodiments of the present invention.

[0068] As Figure 1 shown, the three-dimensional sensing, memory, and computing integrated structure includes a first structure 100, a second structure 200, and a third structure 300 stacked in sequence on a substrate. The first structure 100 is a fan-out packaged processor, the second structure 200 is a memory, and the third structure 300 is an inverted image sensor.

[0069] The first structure 100 includes one or more processor chips, the plastic package of the processor chips, the front-side redistribution layer of the processor chips, and solder balls thereon.

[0070] The second structure 200 includes a memory chip, through-silicon vias, the front-side redistribution layer of the memory chip, and solder balls thereon, and the back-side redistribution layer of the memory chip. The front-side redistribution layer and the back-side redistribution layer are electrically interconnected through the through-silicon vias. It should be noted that the active region of an image sensor fabricated using CMOS (Complementary Metal-Oxide-Semiconductor) technology is the memory chip.

[0071] The third structure 300 includes an image sensor chip, the front-side redistribution layer of the image sensor chip, and a carrier board thereon. The carrier board has through-silicon vias and the through-silicon vias are electrically interconnected with the front-side redistribution layer of the image sensor chip. In Figure 1 the image sensor chip includes an image sensor substrate, a pixel region, back-side deep trench isolation, and a metal interconnect layer.

[0072] It should be noted that the processor chips, memory chips, and image sensor chips in this embodiment are chips fabricated by chip manufacturers in the front-end process (Front End Of the Line, FEOL), while the three-dimensional sensing, memory, and computing integrated structure provided in this embodiment is fabricated using the back-end process (Back End Of the Line, BEOL), and the three-dimensional sensing, memory, and computing integrated structure provided in this embodiment is for testing the functions of these chips.

[0073] In this embodiment, the front-side redistribution layer of the processor chip and the back-side redistribution layer of the memory chip are electrically interconnected through solder balls, and the front-side redistribution layer of the memory chip and the through-silicon vias in the carrier board are electrically interconnected through solder balls.

[0074] The 3D sensing, memory, and computing integrated structure provided in this embodiment can package the image sensor chip, the memory chip, and the processor chip through Figure 1 a 3D heterogeneous integration method. Solder balls are used for interconnection between the image sensor 300 and the memory 200. At the same time, the memory 200 also functions as an active interposer. The through-silicon vias in the memory 200 can realize communication between the upper-layer image sensor chip and the lower-layer processor chip. In addition, multiple bottom processor chips are fan-out packaged to not only realize the interconnection between the processor chips but also be bonded to the back of the memory 200 through solder balls and lead out from the front of the memory 200 to the substrate for external interconnection.

[0075] The 3D sensing, memory, and computing integrated structure provided in this embodiment performs a fan-out package on the processor, bonds it to the active interposer after manufacturing the redistribution layer, and relieves the wiring pressure of the active interposer.

[0076] The bottom processors in the 3D sensing, memory, and computing integrated structure provided in this embodiment can communicate and interconnect with each other, fully ensuring the high bandwidth and low latency of the ring-shaped data transfer of the processors, and improving the processor speed and computing power.

[0077] Figure 2 It is a schematic flowchart of the manufacturing method of the 3D sensing, memory, and computing integrated structure according to an embodiment of the present invention.

[0078] Next, in conjunction with Figure 2 the manufacturing method of this 3D sensing, memory, and computing integrated structure will be described.

[0079] As Figure 2 shown, the manufacturing method of this 3D sensing, memory, and computing integrated structure includes:

[0080] Step S101: Form a fan-out packaged processor, memory, and image sensor through back-end processes.

[0081] Semiconductor processes are the processes of manufacturing semiconductor devices, including front-end processes and back-end processes. Front-end processes involve steps such as cleaning of silicon wafers, ion implantation, heat treatment, lithography, etching, thin-film deposition, planarization, and interconnection. Back-end processes include chip testing, packaging, and surface treatment. The fan-out packaged processor, memory, and image sensor in this embodiment are manufactured through back-end processes, while the processor chips, memory chips, and image sensor chips in the processor, memory, and image sensor of this embodiment are manufactured through front-end processes.

[0082] The manufacturing methods of the processor, memory, and image sensor in S101 will be described below in conjunction with specific process flows.

[0083] Figures 3-1 to 3-5 The structural schematic diagram of the process flow of the fan-out package processor according to an embodiment of the present invention is shown.

[0084] Below in conjunction with Figures 3-1 to 3-5 The process flow of the fan-out package processor according to an embodiment of the present invention will be described.

[0085] The process flow of the fan-out package processor includes:

[0086] Step S10: Place one or more processor chips on a carrier plate with bonding glue and fabricate copper pillars above the chips.

[0087] As Figure 3-1 shown, in this step, one or more processor chips can be arranged and placed on a temporary carrier plate with temporary bonding glue and copper pillars can be fabricated.

[0088] Step S20: Cover the one or more processor chips and the copper pillars with a molding material.

[0089] As Figure 3-2 shown, in this step, a molding material can be covered.

[0090] Step S30: Use a chemical mechanical polishing process to flatten the molding material and expose the copper pillars.

[0091] As Figure 3-3 shown, in this step, the molding material can be thinned by chemical mechanical polishing and the copper pillars can be exposed.

[0092] Step S40: Form a front-end redistribution layer and implant solder balls on the one or more processor chips.

[0093] As Figure 3-4 shown, in this step, a redistribution layer can be made on the surface of the processor chip and solder balls can be implanted.

[0094] Step S50: Separate the carrier plate through ultraviolet laser debonding technology.

[0095] As Figure 3-5 shown, in this step, the processor chip can be separated from the temporary carrier plate through ultraviolet laser debonding technology to obtain the fan-out package processor in this embodiment.

[0096] Figures 4-1 to 4-7 The structural schematic diagram of the process flow of the memory according to an embodiment of the present invention is shown.

[0097] The following will describe the process flow of the memory according to the embodiments of the present invention in conjunction with Figures 4-1 to 4-7 the process flow of the memory according to the embodiments of the present invention will be described.

[0098] First, as Figure 4-1 shown, the image sensor active region, i.e., the memory chip, can be fabricated using the previous process.

[0099] The process flow of this memory includes:

[0100] Step S60: Etch through-silicon vias in the memory chip and fill them with copper.

[0101] As Figure 4-2 shown, in this step, deep hole etching can be performed using through-silicon via technology and filled with copper. The through-silicon vias are located between adjacent active regions.

[0102] Step S70: Form a front-side redistribution layer on the etched memory chip.

[0103] As Figure 4-3 shown, in this step, the front-side redistribution layer can be fabricated.

[0104] Step S80: Bond a carrier board to the front-side redistribution layer.

[0105] As Figure 4-4 shown, in this step, a temporary carrier board can be bonded to the front side of the memory chip.

[0106] Step S90: Use chemical mechanical polishing process to planarize the back side of the memory chip and expose the through-silicon vias.

[0107] As Figure 4-5 shown, in this step, thinning etching of the through-silicon vias can be performed on the back side of the memory chip to expose the through-silicon vias.

[0108] Step S100: Form a back-side redistribution layer on the planarized back side of the memory chip and implant solder balls.

[0109] As Figure 4-6 shown, in this step, the back-side redistribution layer can be fabricated and solder balls can be implanted.

[0110] Step S110: Separate the carrier board through ultraviolet laser de-bonding technology.

[0111] As Figure 4-7 shown, in this step, the front-side temporary carrier board can be de-bonded through ultraviolet laser de-bonding technology to obtain the memory in this embodiment.

[0112] Figures 5-1 to 5-5 The structural schematic diagram of the process flow of the image sensor according to the embodiments of the present invention is shown.

[0113] The following will describe Figures 5-1 to 5-5 the process flow of the image sensor according to the embodiments of the present invention.

[0114] First, as Figure 5-1 shown, a photodiode and a pixel region can be fabricated on a silicon substrate, and a metal interconnect layer can be fabricated on the top silicon to obtain an image sensor chip. The fabrication process of the image sensor chip belongs to the front-end process and will not be elaborated here.

[0115] The process flow of the image sensor includes:

[0116] Step S120: Form a front-side redistribution layer on the image sensor chip.

[0117] As Figure 5-2 shown, in this step, a metal interconnect layer for the back-end process (i.e., the redistribution layer in this article) can be fabricated on the front side of the image sensor chip.

[0118] Step S130: Bond a carrier substrate to the front-side redistribution layer.

[0119] As Figure 5-3 shown, in this step, the front side of the front-side redistribution layer can be bonded to a silicon carrier substrate to reinforce the wafer.

[0120] Step S140: Thin the substrate of the image sensor chip using a chemical mechanical polishing process.

[0121] As Figure 5-4 shown, in this step, the back silicon substrate of the image sensor chip can be thinned to enhance light transmission.

[0122] Step S150: Form through-silicon vias on the carrier substrate using a via-last process.

[0123] As Figure 5-5 shown, in this step, through-silicon vias on the silicon carrier substrate can be fabricated using a via-last process to obtain the image sensor in this embodiment.

[0124] Next, return to Figure 2 Continue to describe the manufacturing method of the three-dimensional sensing and computing integrated structure.

[0125] Step S102: Mount the fan-out packaged processor on a substrate.

[0126] Figure 6 shows a conceptual structural schematic diagram of mounting a fan-out packaged processor on a substrate according to an embodiment of the present invention. As Figure 6 shown, in step S102, multiple processor chips can be mounted on corresponding positions on the package substrate through a thermal conductive adhesive.

[0127] Step S103: Bond the memory above the processor of the fan-out package.

[0128] Figure 7 The conceptual structural diagram of bonding the memory above the processor of the fan-out package according to an embodiment of the present invention is shown. As Figure 7 shown, in step S103, the memory as an active interposer can be bonded above the processor.

[0129] Step S104: Invert and bond the image sensor above the memory, and wire bond from the memory to the substrate.

[0130] Figure 1 The conceptual structural diagram of the 3D sensing, memory, and computing integrated structure formed according to step S104 is shown. As Figure 1 shown, in step S104, the image sensor can be inverted and bonded above the active interposer through micro solder balls, and wire bond from the active interposer to the substrate.

[0131] The solution of the present invention also provides a 3D testability structure (Design For Test, DFT) for testing the 3D sensing, memory, and computing integrated structure according to the embodiment of the present invention.

[0132] Figure 8 The schematic diagram of the test structure of the 3D sensing, memory, and computing integrated structure according to the embodiment of the present invention is shown.

[0133] As Figure 8 shown, the test structure of the 3D sensing, memory, and computing integrated structure includes:

[0134] 1. The test control interface, chip select register, bypass register located on the image sensor, and the scan boundary unit located around the image sensor chip (i.e., the image sensor logic unit in Figure 8 ).

[0135] 2. The main control test interface and two slave test control interfaces (i.e., the slave test control interface 1 and slave test control interface 2 in Figure 8 ) located on the memory. The main control test interface controls the two slave test control interfaces in parallel, and the main control test interface is used to receive external test signals.

[0136] 3. The test control interface, chip select register, bypass register located on one processor chip (i.e., the processor chip at the lower left in Figure 8 ), and the scan boundary unit located around all processor chips (i.e., the processor logic unit in Figure 8 ).

[0137] 4. Configuration circuit. The configuration circuit serially interconnects the test control interface 2 with the test control interface, chip select register, bypass register located on the image sensor, and the scan boundary unit located around the image sensor chip to form an image sensor test structure.

[0138] In this image sensor test structure, the chip select register and the bypass register are used to determine whether to test the image sensor chip, and the scan boundary unit is used to perform on-off and logic tests on the image sensor chip.

[0139] The configuration circuit also serially interconnects the test control interface 1 with the test control interface, chip select register, bypass register located on a processor chip, and the scan boundary units located around all processor chips to form a processor test structure. In this processor test structure, the chip select register and the bypass register are used to determine whether to test a certain processor chip, and the scan boundary unit is used to perform on-off and logic tests on the processor chip to be tested.

[0140] In some embodiments, Figure 8 the main control test interface, slave test control interface, and test control interface in can be JTAG interfaces. The external test signal is input through the JTAG interface to the main control test interface located on the active backplane. The main control test interface controls two slave test control interfaces simultaneously: slave test control interface 1 and slave test control interface 2. Slave test control interface 2 and slave test control interface 1 respectively control the image sensor and the processor.

[0141] Slave test control interface 2 realizes the information transfer to the test control interface on the image processor through the JTAG interface on the image processor; slave test control interface 2 determines whether to test this image sensor chip through the chip select register and the bypass register. Slave test control interface 1 realizes the information transfer to the test control interface on the processor through the JTAG interface on the processor; slave test control interface 1 determines whether to test a certain sensor chip through the chip select register and the bypass register.

[0142] This mechanism determines that the test structure in the embodiments of the present invention can test the three-dimensional stacked chips at different test levels, and different test levels of all component pairs in the three-dimensional stack can be tested simultaneously or independently by loading instruction signals.

[0143] If it is decided to test a certain image sensor chip or sensor chip, the logic unit can be accessed through the scan boundary unit around it, or the interconnection of the logic unit can be tested. The boundary scan units connected up and down by the through-silicon vias in the memory can realize the transmission of test signals, so as to perform a continuity test on the interconnection structure. So far, the test results meet the requirements of logic and continuity tests. This structure, combined with test vectors and an automatic test machine, can achieve efficient and low-cost testing in mass production.

[0144] Compared with the prior art, the embodiment of the present invention provides a three-dimensional testability design structure. Based on the IEEE1838 standard, it is configured with a classic JTAG configuration interface based on 1149.1 to realize the joint test between the image sensor, the memory and the processor.

[0145] Compared with the prior art, in the embodiment of the present invention, the JTAG interface is used as the test access interface, and multiple chips share the control signal, so that the tests in multiple links before bonding, during bonding and after bonding can be realized.

[0146] Compared with the prior art, in the embodiment of the present invention, for the bottom processor chip, the input and output test signals can be serially connected and a daisy chain can be formed through the redistribution layer of the fan-out package, which increases the test coverage rate of the processor and reduces the test time at the same time.

[0147] The above is only the preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention.

Claims

1. A manufacturing method of a three-dimensional sense-computation integrated structure, characterized in that, It includes the following steps: Forming a processor, a memory, and an image sensor of a fan-out package through a back-end process; Mounting the processor of the fan-out package onto a substrate; Bonding the memory above the processor of the fan-out package; And Inverting and bonding the image sensor above the memory, and wire bonding from the memory to the substrate.

2. The method according to claim 1, characterized in that, Forming a processor of a fan-out package through a back-end process includes: Placing one or more processor chips on a carrier plate with bonding glue and fabricating copper pillars; Covering the one or more processor chips and the copper pillars with a molding compound; Using a chemical mechanical polishing process to flatten the molding compound and expose the copper pillars; Forming a front-side redistribution layer and implanting solder balls on the one or more processor chips; and Separating the carrier plate through an ultraviolet laser debonding technique.

3. The method according to claim 1, characterized in that, Forming a memory through a back-end process includes: Performing through-silicon via etching on a memory chip and filling it with copper; Forming a front-side redistribution layer on the etched memory chip; Bonding a carrier plate on the front-side redistribution layer; Using a chemical mechanical polishing process to flatten the back surface of the memory chip and expose the through-silicon via; Forming a back-side redistribution layer and implanting solder balls on the flattened back surface of the memory chip; and Separating the carrier plate through an ultraviolet laser debonding technique.

4. The method according to claim 1, characterized in that Forming an image sensor through a back-end process includes: Forming a front-side redistribution layer on an image sensor chip; Bonding a carrier plate on the front-side redistribution layer; Using a chemical mechanical polishing process to thin the substrate of the image sensor chip; and Forming through-silicon vias on the carrier plate using a back via process.

5. The method according to claim 4, wherein The image sensor chip is a CMOS image sensor chip, and the manufacturing method of the CMOS image sensor chip includes: Fabricating a photodiode and a pixel region on a wafer; Fabricating a metal interconnect layer on the wafer.

6. A three-dimensional sense-compute integrated structure, characterized in that, It includes: A processor of a fan-out package, a memory, and an inverted image sensor stacked in sequence on a substrate; wherein, The processor of the fan-out package includes one or more processor chips, the molding of the one or more processor chips, the front-side redistribution layer of the one or more processor chips, and solder balls thereon; The memory includes a memory chip, through-silicon vias, the front-side redistribution layer of the memory chip and solder balls thereon, the back-side redistribution layer of the memory chip, and the front-side redistribution layer and the back-side redistribution layer of the memory chip are electrically interconnected through the through-silicon vias; The image sensor includes an image sensor chip, the front-side redistribution layer of the image sensor chip, and a carrier plate thereon, and the carrier plate has through-silicon vias and the through-silicon vias are electrically interconnected with the front-side redistribution layer of the image sensor chip; The front-side redistribution layer of the one or more processor chips and the back-side redistribution layer of the memory chip are electrically interconnected through solder balls, and the front-side redistribution layer of the memory chip and the through-silicon vias in the carrier plate are electrically interconnected through solder balls.

7. A test structure for a three-dimensional sensing and computing integrated structure, characterized in that, The three-dimensional sensing, computing, and integration structure includes a processor of a fan-out package, a memory, and an inverted image sensor stacked in sequence, and the test structure includes: A test control interface, a chip select register, a bypass register located on the image sensor, and a scan boundary unit located around the image sensor chip; A test control interface, a chip select register, a bypass register located on a processor chip, and a scan boundary unit located around one or more processor chips; A main control test interface and two slave test control interfaces located on the memory, the main control test interface controls the two slave test control interfaces in parallel, and the main control test interface is used to receive external test signals; One of the slave test control interfaces is serially interconnected with a test control interface, a chip select register, a bypass register located on the image sensor, and a scan boundary unit located around the image sensor chip to form an image sensor test structure; The other slave test control interface is serially interconnected with a test control interface, a chip select register, a bypass register located on a processor chip, and a scan boundary unit located around one or more processor chips to form a processor test structure.

8. The test structure according to claim 7, wherein The image sensor test structure is configured to: The chip select register and the bypass register select whether to test the image sensor chip. If the chip select register and the bypass register select to test the image sensor chip, the on / off and logic tests of the image sensor chip are performed through the scan boundary unit located around the image sensor chip; The processor test structure is configured to: The chip select register and the bypass register select whether to test the processor chip. If the chip select register and the bypass register select to test the processor chip, the on / off and logic tests of the processor chip are performed through the scan boundary unit located around the processor chip.

9. The test structure according to claim 8, characterized in that, The main control test interface, the slave test control interface, and the test control interface are JTAG interfaces.

10. The test structure according to claim 9, wherein The image sensor test structure and the processor test structure are serially interconnected through the through-silicon vias in the memory.

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