Substrate structure and manufacturing method thereof

Abstract

The invention provides a substrate structure and a manufacturing method thereof. The substrate structure comprises a first base material and a second base material. The first substrate includes a first core layer and a first conductor. The second substrate includes a second core layer and a second conductor. A metal diffusion bonding interface is arranged between the first conductor and the second conductor. A covalent bond bonding interface is arranged between the first core layer and the second core layer.

Description

Technical Field

[0001] The present invention relates to a substrate structure and a manufacturing method thereof, and particularly to a substrate structure with conductive vias and a manufacturing method thereof. Background Art

[0002] Currently, when fabricating high aspect ratio (AR) glass vias (Through Glass Via, TGV) in a glass substrate, it is usually achieved by butt-joining glass substrates with a resin material and electrically connecting the glass vias in the two glass substrates with a conductive paste in the resin material. That is to say, after the two glass substrates are butt-joined, there is a conductive paste between the glass vias. Alternatively, the thickness of the glass substrate used is greater than 200 microns, such as 500 microns, and high aspect ratio glass vias are formed through processes such as laser, etching, and hole filling. Thus, it can be seen that there are difficulties in fabricating high aspect ratio glass vias in a glass substrate. Summary of the Invention

[0003] The present invention provides a substrate structure and a manufacturing method thereof, and the substrate structure and manufacturing method thereof can have high aspect ratio glass vias.

[0004] A method for manufacturing a substrate structure according to the present invention includes the following steps: providing a first substrate including a first core layer and a first conductor exposed to the outside; providing a second substrate including a second core layer and a second conductor exposed to the outside; forming conductive nanowires on the first conductor or the second conductor; and aligning the first conductor of the first substrate with the second conductor of the second substrate, and positioning the conductive nanowires between the first conductor and the second conductor, so as to join the first substrate and the second substrate by at least a conductive diffusion bonding method formed by the conductive nanowires.

[0005] In one embodiment, the first conductor or the second conductor includes the same material as the conductive nanowires.

[0006] In one embodiment, the first conductor or the second conductor includes a copper layer, and the conductive nanowires are copper nanowires.

[0007] In one embodiment, the copper nanowires are directly formed on the copper layer.

[0008] In one embodiment, the first substrate or the second substrate further includes a polymer, and during the process of aligning the first conductor of the first substrate with the second conductor of the second substrate, the polymer is also positioned between the first core layer and the second core layer, so as to further join the first substrate and the second substrate by a chain-like or network structure formed by the polymer.

[0009] In one embodiment, during the process of joining the separated first substrate and the second substrate, the temperature is less than or equal to 200 °C.

[0010] In one embodiment, the polymer includes a silicone polymer, and the chain or network structure has at least bridging oxygen.

[0011] A substrate structure of the present invention includes a first substrate and a second substrate. The first substrate includes a first core layer and a first conductor. The second substrate includes a second core layer and a second conductor. There is a metal diffusion bonding interface between the first conductor and the second conductor. There is a covalent bond bonding interface between the first core layer and the second core layer.

[0012] In one embodiment, the metal diffusion bonding interface is a copper diffusion bonding interface.

[0013] In one embodiment, the covalent bond bonding interface is a chain or network structure having at least bridging oxygen.

[0014] Based on the above, since the conductive nanowires have the characteristics of low melting point and high surface area, the temperature in the process operation can be reduced, and problems such as warping and cracking of the chips in the components caused by too high temperature in the bonding process can be avoided. Therefore, the copper bonding between the conductive nanowires allows a lower heating temperature to improve the quality of the glass vias with a high aspect ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figures 1 to 12 FIG. is a partial cross-sectional schematic view of a partial manufacturing method of a substrate structure according to a first embodiment of the present invention;

[0016] Figures 13 to 19 FIG. is a partial cross-sectional schematic view of a partial manufacturing method of a substrate structure according to a second embodiment of the present invention.

[0017] DESCRIPTION OF THE REFERENCE NUMERALS

[0018] 100, 200: Substrate structure

[0019] 110: First substrate

[0020] 111: Core layer

[0021] 112: Via hole

[0022] 113: Insulating layer

[0023] 114: First conductive layer

[0024] 115: Second conductive layer

[0025] 116: Conductive via hole

[0026] 117: Third conductive layer

[0027] 118: Patterning mask layer

[0028] 201: Fourth conductive layer

[0029] 120: Conductive nanowire

[0030] 130: Hydrolysis reaction

[0031] 132: Condensation reaction

[0032] 140: Covalent bond bonding interface

[0033] 150: Metal diffusion bonding interface

[0034] 202: Organic resin layer

[0035] 210: Second substrate

[0036] D1: Pore size

[0037] D2: Wire diameter or line width

[0038] T1, T2, T3: Thickness Detailed implementation manners

[0039] Examples are listed below and described in detail in conjunction with the accompanying drawings. However, the provided examples are not intended to limit the scope covered by the present invention. In addition, the accompanying drawings are for illustrative purposes only and are not drawn to the original size.

[0040] In addition, terms such as "including" and "having" used in this text are all open-ended terms, that is, they mean "including but not limited to".

[0041] It should be understood that although the terms "first", "second", "third", etc. may be used in this text to describe various components, parts, regions, layers, and / or portions, these components, parts, regions, and / or portions should not be limited by these terms. These terms are only used to distinguish one component, part, region, layer, or portion from another component, part, region, layer, or portion. Therefore, the "first component", "part", "region", "layer", or "portion" discussed below may be referred to as the second component, part, region, layer, or portion without departing from the teachings of this text.

[0042] Directional terms mentioned in this text, such as "upper", "lower", "top", "bottom", etc., are only references to the directions in the accompanying drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0043] In the accompanying drawings, each drawing shows the general characteristics of the methods, structures, and / or materials used in specific embodiments. However, these drawings should not be construed as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative sizes, thicknesses, and positions of each film layer, region, and / or structure may be reduced or enlarged.

[0044] In the following embodiments, the same or similar components will be denoted by the same or similar reference numerals, and redundant descriptions thereof will be omitted. In addition, features in different embodiments can be combined with each other without conflict, and simple equivalent changes and modifications made according to the scope of this specification or claims still fall within the scope covered by this patent.

[0045] <First Embodiment>

[0046] Figures 1 to 12 FIG. is a partial cross-sectional schematic view of a method for manufacturing a part of a substrate structure according to a first embodiment of the present invention. Among them, Figures 1 to 5 FIG. is a partial cross-sectional schematic view of forming a first substrate 110 with conductive vias.

[0047] Please refer to Figure 1 , and provide a first substrate 110. The first substrate 110 includes a core board 111 and at least one through hole 112 (two through holes are schematically shown) penetrating the core board 111.

[0048] In one embodiment, the core board 111 can be a glass plate. In one embodiment, the core board 111 can also be a ceramic plate, a bismaleimide triazine (BT) plate, an epoxy glass fiber unclad laminate (such as FR4) plate, a polyimide (PI) coated plate, an Ajinomoto build-up film (ABF) plate, or a multilayer circuit board, but the present invention is not limited thereto. In one embodiment, the thickness T1 of the core board 111 can be in the range of about 100 microns to about 400 microns.

[0049] In one embodiment, the through hole 112 can be a through hole. In one embodiment, the through hole 112 can be formed by mechanical drilling, laser drilling, etching, or other suitable methods. In one embodiment, the through hole 112 can be a glass through hole, and the aperture D1 of the through hole 112 can be in the range of about 20 microns to about 150 microns.

[0050] Please refer to Figure 2, an insulating layer 113 may be selectively formed on the core board 111 and the sidewalls of the vias 112. In one embodiment, the insulating layer 113 may include an adhesion promotion layer (APL). The insulating layer may be formed, for example, by deposition or other suitable means. In one embodiment, the insulating layer 113 includes oxides, nitrides, combinations thereof, such as silicon dioxide (such as SiO2 or SiOx), aluminum oxide (such as Al2O3), titanium oxide (such as TiO2 or TiO or TiOx), or silicon nitride (Si3N4 or SiNx), but the present invention is not limited thereto. In one embodiment, the thickness T2 of the insulating layer 113 may be in the range of about 0.01 nanometers to about 100 nanometers.

[0051] Please refer to Figure 3 , a first conductive layer 114 may be selectively formed on the core board 111 and the sidewalls of the vias 112. The first conductive layer 114 may cover the insulating layer 113 (if any).

[0052] In one embodiment, the first conductive layer 114 may be referred to as a seed layer. In one embodiment, the first conductive layer 114 may include copper or / and titanium, but the present invention is not limited thereto. In one embodiment, the first conductive layer 114 may be formed using a sputtering process or an electroless plating process, or may first use a sputtering process and then an electroless plating process to completely cover the sidewalls of the vias 112.

[0053] Please refer to Figure 4 , a second conductive layer 115 is formed at least within the vias 112. The second conductive layer 115 may be formed on the first conductive layer 114 (if any). In one embodiment, the second conductive layer 115 may be a copper layer. In one embodiment, the second conductive layer 115 may be formed by electroplating.

[0054] Please refer to Figure 5 , portions of the first conductive layer 114 and the second conductive layer 115 outside the vias 112 are removed. The first conductive layer 114 and the second conductive layer 115 within the vias 112 may be retained to form a conductive via 116. That is, the conductive via 116 includes the first conductive layer 114 and the second conductive layer 115, and the conductive via 116 penetrates through the core board 111. That is, in Figure 5 , a plurality of conductive vias 116 may be electrically separated from each other.

[0055] It should be noted that Figure 5Or the remaining similar drawings may only show an embodiment of a part or a cross-section of a part in an embodiment. In an unillustrated embodiment or an unshown cross-section, on the upper surface (above in the drawing) or the lower surface (below in the drawing) of the core board 111, there may still be some portions of the first conductive layer 114 and some portions of the second conductive layer 115. These remaining portions of the first conductive layer 114 and the second conductive layer 115 may have corresponding patterns and can form appropriate circuits (such as: can be referred to as circuit layers) or marks (such as: can be referred to as positioning marks).

[0056] Figures 6 to 9 Partial cross-sectional schematic diagram of forming the conductive nanowire 120 on the conductive via 116.

[0057] Please refer to Figure 6 , and a third conductive layer 117 can be selectively formed on at least one side of the first substrate 110.

[0058] In one embodiment, the third conductive layer 117 can be referred to as a seed layer. In one embodiment, the third conductive layer 117 may include copper or / and titanium, but the present invention is not limited thereto. In one embodiment, the third conductive layer 117 can be formed using a sputtering process or an electroless plating process, or can first use a sputtering process and then an electroless plating process so that the sidewalls of the conductive vias 116 can be completely covered.

[0059] In one embodiment, the third conductive layer 117 can be referred to as a conductive connection layer. That is to say, among Figure 5 the plurality of conductive vias 116 that are electrically separated from each other, in Figure 6 they can be electrically connected through the third conductive layer 117.

[0060] Please refer to Figure 7 , and a patterned mask layer 118 is formed on at least one side of the core board 111. The openings of the patterned mask layer 118 can expose some portions of the third conductive layer 117. The openings of the patterned mask layer 118 can correspond to the positions where the conductive nanowires (such as Figure 8 the conductive nanowire 120 shown) are to be formed.

[0061] The material of the patterned mask layer 118 is different from that of the third conductive layer 117, and the purpose is to make the subsequent conductive nanowires (such as Figure 8The conductive nanowires 120 shown can be more easily located on the exposed portion of the third conductive layer 117 and less easily located on the patterned mask layer 118. For example, subsequent conductive nanowires can be more easily formed on the exposed portion of the third conductive layer 117 and less easily formed on the patterned mask layer 118. As another example, even if subsequent conductive nanowires may be formed on both the third conductive layer 117 and the patterned mask layer 118, the conductive nanowires on the patterned mask layer 118 can be more easily removed (e.g., by peeling). In one embodiment, the material of the patterned mask layer 118 can include photoresist. In one embodiment, the photoresist layer 118 can include a dry film.

[0062] Please refer to Figure 8 , to form conductive nanowires 120. The material of the conductive nanowires 120 is substantially the same as or similar to the material of the third conductive layer 117. For example, the third conductive layer 117 is a copper layer, and the conductive nanowires 120 are copper nanowires. As another example, the third conductive layer 117 is a copper layer, the conductive nanowires 120 are copper nanowires, and the concentration or lattice state of copper in the third conductive layer 117 is substantially the same as or similar to the concentration or lattice state of copper in the conductive nanowires 120.

[0063] In one embodiment, a porous membrane layer (not labeled) can be hot-pressed onto the exposed portion of the third conductive layer 117 of the patterned mask layer 118. The aforementioned porous membrane layer can constitute a growth template for the conductive nanowires 120. Then, on the aforementioned growth template, corresponding conductive nanowires 120 are formed by an appropriate method (e.g., copper electroplating).

[0064] In one embodiment, the thickness of the conductive nanowires 120 (i.e., the corresponding height of most of the respective conductive nanowires 120; or, its average) is greater than the thickness of the third conductive layer 117. In this way, it can be suitable for subsequent processes. In one embodiment, the thickness of the conductive nanowires 120 can be adjusted by an appropriate method (e.g., the concentration of metal ions in the plating solution, the current of electroplating, the formation time, or temperature, etc.).

[0065] In Figure 8 the embodiment shown, the height of the conductive nanowires 120 is higher than that of the patterned mask layer 118, but the present invention is not limited thereto. That is to say, the height of the conductive nanowires 120 may be lower than that of the patterned mask layer 118, and Figure 8 the embodiment shown is only for emphasizing the exaggerated illustration of the conductive nanowires 120.

[0066] Please refer to Figures 8 to 9, perform an appropriate removal process (which may include one or more removal steps and cleaning steps) to at least remove the photoresist layer 118 (shown in Figure 8 ) and a portion of the third conductive layer 117 to form a structure as shown in Figure 9 .

[0067] In one embodiment, a portion of the third conductive layer 117 (such as the portion of the third conductive layer 117 under the conductive nanowire 120) may be retained. In one embodiment, during the aforementioned removal process, a portion of the conductive nanowire 120 may be removed (such as a shorter or more peripheral conductive nanowire 120 may be removed); and / or, a portion of the conductive nanowire 120 may be removed (such as a portion of a conductive nanowire 120 may be removed to make the conductive nanowire 120 shorter or thinner). That is to say, compared with the conductive nanowires 120 in Figure 8 , the distribution of the conductive nanowires 120 in Figure 9 may be smaller, the thickness of the conductive nanowires 120 may be thinner, and / or the conductive nanowires 120 may be thinner. That is to say, if the conductive nanowires 120 in Figure 8 have a first distribution range, and the conductive nanowires 120 in Figure 9 have a second distribution range, then the second distribution range is smaller than the first distribution range. That is to say, if the conductive nanowires 120 in Figure 8 have a first thickness, and the conductive nanowires 120 in Figure 9 have a second thickness, then the second thickness is thinner than the first thickness. That is to say, if the conductive nanowires 120 in Figure 8 have a first diameter, and the conductive nanowires 120 in Figure 9 have a second diameter, then the second diameter is smaller than the first diameter. Additionally, the aforementioned thickness or diameter may be the average value measured for multiple conductive nanowires 120 by an appropriate method (such as using an electron microscope). Additionally, after the aforementioned removal process, since the electrical and / or physical properties of the conductive nanowires 120 basically do not change much (such as still being electrically connected to the corresponding conductive vias 116 basically; and / or, the lattice state is basically the same), the same symbol (i.e., 120) is still used for marking in FIGS. 9 and subsequent figures.

[0068] From the enlarged view, the thickness T3 of the conductive nanowires 120 can be in the range of about 1 micron to about 50 microns, and the wire diameter or wire width D2 of the conductive nanowires 120 can be in the range of about 4 nanometers to about 4 microns.

[0069] Additionally, since before the aforementioned removal process, the thickness of the conductive nanowires 120 (i.e., Figure 8The thickness of the middle conductive nanowire 120) is already greater than the thickness of the third conductive layer 117. Therefore, after appropriate processes (i.e., Figure 9 ), the conductive nanowire 120 can still be retained.

[0070] Figures 10 to 12 It is a partial cross-sectional schematic diagram of the joint of two substrates 110 and 210 to form the substrate structure 100 of the first embodiment of the present invention.

[0071] Please refer to Figure 10 and Figure 11 to provide a second substrate 210 that is the same as or similar to the first substrate 110, and chemically bond the first substrate 110 and the second substrate 210.

[0072] In one embodiment, the core plates 111 in the first substrate 110 and the second substrate 210 are joined by the sol–gel process. The sol–gel process mainly goes through two stages: hydrolysis reaction 130 and condensation co ndensation) reaction 132.

[0073] In the hydrolysis reaction 130 stage, the starting reactant can be silane oxide (Si(OR)4, where R is an alkyl functional group; for example, including: methyl, ethyl, propyl or isopropyl) (not shown, and not limited thereto), which becomes hydroxide after hydrolysis. The chemical reaction formula can be shown as the following <Reaction formula 1>. In addition, in Figure 10 only the molecular structural formula after the hydrolysis reaction 130 is schematically presented, and thus R is not shown.

[0074] <Reaction formula 1>

[0075] Si-OR + H2O → Si-OH + R-OH

[0076] In one embodiment, a temperature exceeding 100 degrees Celsius can promote the hydrolysis reaction. For example, the water molecules generated by the hydrolysis reaction can easily become gaseous and be removed under the condition of exceeding 100 degrees Celsius.

[0077] In the condensation reaction 132 stage, after heating, the silane oxide containing hydroxyl groups easily reacts with the hydroxyl groups in other alkoxides to form covalent bonds, and after continuous reactions, polymerizes into a chain-like or network structure with bridging oxygen. The chemical reaction formula can be shown as the following <Reaction formula 2>.

[0078] <Reaction formula 2>

[0079] Si-OH + HO-Si → Si-O-Si + H2O

[0080] In one embodiment, the core board 111 in the first substrate 110 is joined to the core board 111 of the second substrate 210 by the polymerization of macromolecules. In Figure 11 Only the molecular structural formula during the condensation reaction 132 is schematically presented.

[0081] Please refer to Figure 12 , when heating, the first substrate 110 and the second substrate 210 are joined, so that the core layer 111 of the first substrate 110 and the core layer 111 of the second substrate 210 are joined by chemical bonding force (as described above). Moreover, the conductive nanowires 120 on the conductive vias 116 of the first substrate 110 and the conductive vias 116 and the conductive nanowires 120 on the second substrate 210 also undergo metal-to-metal diffusion bonding by heating. Therefore, the core layer 111 and the conductive nanowires 120 of the first substrate 110 and the core layer 111 and the conductive nanowires 120 of the second substrate 210 are completely joined to form the substrate structure 100 of the first embodiment.

[0082] In one embodiment, the conductive nanowires 120 of the first substrate 110 and the conductive nanowires 120 of the second substrate 210 are both copper nanowires, and Cu-to-Cu diffusion bonding can be performed between them by heating.

[0083] The conductive nanowires 120 have the characteristics of low melting point and high surface area, so the temperature and pressure in the process operation can be reduced, so as to reduce or even avoid problems such as warping and cracking of the chips in the components caused by too high temperature and pressure in the joining process. Taking copper nanowires as an example, the copper joining between them allows a lower heating temperature (i.e., lower than the melting point of metallic copper), for example, not exceeding about 200 degrees Celsius. In one embodiment, the heating temperature can be in the range of about 100 degrees Celsius to about 200 degrees Celsius, for example, about 170 degrees Celsius (170 °C).

[0084] Please continue to refer to Figure 12 , the substrate structure 100 of the first embodiment of the present invention includes a first substrate 110 and a second substrate 210. In one embodiment, both the first substrate 110 and the second substrate 210 include a core layer 111 and conductive vias 116. In one embodiment, an insulating layer 113 may be selectively included on the core layer 111 and / or on the sidewalls of the conductive vias 116. The conductive vias 116 may include a first conductive layer 114 and a second conductive layer 115.

[0085] In one embodiment, there is a metal diffusion bonding interface 150 between the conductive vias 116 of the first substrate 110 and the conductive vias 116 of the second substrate 210. In one embodiment, the metal diffusion bonding interface 150 is a copper diffusion bonding interface. In one embodiment, the metal diffusion bonding interface 150 is formed by corresponding metal nanowires (a kind of conductive nanowires, such as copper nanowires). In one embodiment, although the metal diffusion bonding interface 150 is described in the way of "bonding interface", structurally it may be a thin layer structure or a structure formed by interweaving and bonding of nanowires. In one embodiment, the material of the conductive via 116 is the same as or similar to the material of the metal diffusion bonding interface 150. In one embodiment, when the material of the conductive via 116 is substantially the same as the material of the metal diffusion bonding interface 150, there may be no obvious interface or delamination between them (such as between the conductive via 116 of the first substrate 110 and the conductive via 116 of the second substrate 210; and / or between a certain conductive via 116 and the metal diffusion bonding interface 150).

[0086] In one embodiment, there is a covalent bond bonding interface 140 formed by chemical bonding force between the core layers 111 of the first substrate 110 and the core layers 111 of the second substrate 210. In one embodiment, although the covalent bond bonding interface 140 is described in the way of "bonding interface", structurally it may be a thin layer structure

[0087] <Second Embodiment>

[0088] Figures 13 to 19 It is a partial cross-sectional schematic diagram of a part of the manufacturing method of the substrate structure according to the second embodiment of the present invention.

[0089] The structure and process method of the substrate structure 200 of the second embodiment of the present invention are similar to those of the substrate structure 100 of the first embodiment. The main difference between the two is that: an organic resin layer 202 is included on the core layer 111 of at least one of the first substrate 110 and the second substrate 210.

[0090] Figure 13 It is a partial cross-sectional schematic diagram of forming the first substrate 110 with conductive vias 116. Figure 13 Same as that of the first embodiment Figure 5 , the process method of the first substrate 110 with conductive vias 116 is the same as or similar to that of the first embodiment Figures 1 to 5 Same or similar.

[0091] Figures 14 to 18 It is a partial cross-sectional schematic diagram of forming an organic resin layer 202 on the core layer 111 and forming conductive nanowires 120 on the conductive vias 116.

[0092] Please refer to Figure 14, in some embodiments, after forming the first substrate 110 with the conductive vias 116, a fourth conductive layer 201 may be formed on one side of the first substrate 110. In one embodiment, the fourth conductive layer 201 may function as a common electrode. In one embodiment, among Figure 13 the plurality of conductive vias 116 that are electrically separated from each other, in Figure 15 they can be electrically connected through the fourth conductive layer 201. In one embodiment, the fourth conductive layer 201 may include copper, but the present invention is not limited thereto. In one embodiment, the fourth conductive layer 201 may be formed using a sputtering process, but the present invention is not limited thereto.

[0093] In one embodiment, the first substrate 110 and the second substrate 210 of the foregoing first embodiment may also selectively include a conductive layer that is the same as or similar to the fourth conductive layer 201.

[0094] Please refer to Figure 15 , an organic resin layer 202 is formed on the other side of the first substrate 110 opposite to the side including the fourth conductive layer 201. In one embodiment, the material of the organic resin layer 202 may include liquid-crystal polymer (LCP), but the present invention is not limited thereto.

[0095] Please refer to Figures 16 to 18 , a second substrate 210 that is the same as or similar to the first substrate 110 is provided, and the core boards 111 in the first substrate 110 and the second substrate 210 are bonded by chemical bonding force.

[0096] In one embodiment, the core boards 111 in the first substrate 110 and the second substrate 210 are bonded by the sol–gel process. The sol–gel process mainly undergoes two stages: hydrolysis reaction 130 and condensation reaction 132.

[0097] In the hydrolysis reaction 130 stage, the starting reactant may be silane oxide (Si(OR)4), where R is an alkyl functional group in the organic resin layer 202, and after hydrolysis, it becomes a hydroxide. The chemical reaction formula may be as shown in the foregoing <Reaction formula 1>. In Figure 16 the left frame 130 only schematically presents the molecular structural formula of the hydrolysis reaction 130.

[0098] In the condensation reaction stage 132, after heating, the silane oxide containing hydroxyl groups easily reacts with the hydroxyl groups in other alkoxides to form covalent bonds, and after continuous reactions, it polymerizes into a chain-like or network structure with bridging oxygen. The chemical reaction formula can be as shown in the aforementioned <Reaction Formula 2>. The core board 111 in the first substrate 110 is joined to the core board 111 of the second substrate 210 through the polymerization of macromolecules. In Figure 16 Only the molecular structural formula during the condensation reaction 132 is schematically presented in the right frame 132 of

[0099] Please refer to Figure 17 , and part of the organic resin layer 202 can be removed by an appropriate method (such as etching or laser ablation), thereby exposing the corresponding conductive via 116.

[0100] Please continue to refer to Figure 17 , and conductive nanowires 120 can be formed in the same or similar manner as the aforementioned method. The conductive nanowires 120 can be directly formed on the conductive vias 116.

[0101] In addition, after forming the conductive nanowires 120, the fourth conductive layer 201 can be correspondingly removed in an appropriate step.

[0102] Figures 18 to 19 FIG. is a partial cross-sectional schematic view of the joint of the two substrates 110 and 210 to form the substrate structure 200 of the second embodiment of the present invention.

[0103] Please refer to Figure 18 , when heating, the first substrate 110 and the second substrate 210 are joined so that the organic resin layer 202 on the core layer 111 of the first substrate 110 and the organic resin layer 202 on the core layer of the second substrate 210 are joined by chemical bonding force (as described above). And, the conductive nanowires 120 on the conductive vias 116 of the first substrate 110 and the conductive nanowires 120 on the conductive vias 116 of the second substrate 210 also undergo metal-to-metal diffusion bonding through heating.

[0104] Please refer to Figure 19 , the organic resin layer 202 and the conductive nanowires 120 on the core layer 111 of the first substrate 110 and the organic resin layer 202 and the conductive nanowires 120 on the core layer 111 of the second substrate 210 are completely joined to form the substrate structure 200 of the second embodiment.

[0105] Please continue to refer to Figure 19, the substrate structure 200 of the second embodiment of the present invention includes a first substrate 110 and a second substrate 210. In one embodiment, both the first substrate 110 and the second substrate 210 include a core layer 111 and conductive vias 116. In one embodiment, an insulating layer 113 may be selectively included on the core layer 111 and on the sidewalls of the conductive vias 116. The conductive vias 116 may include a first conductive layer 114 and a second conductive layer 115. An organic resin layer 202 may be disposed on the core layer 111.

[0106] In the foregoing embodiment, to form corresponding conductive nanowires on a conductor (such as the conductive via 116). And, the corresponding conductors in different substrates (such as the first substrate 110 and the second substrate 210) can be joined through the conductive nanowires they include. And, the corresponding insulators in different substrates (such as the first substrate 110 and the second substrate 210) can be made to form a chain-like or network structure having bridging atoms (such as bridging oxygen) between them through covalent bonds, so as to join the corresponding insulators in different substrates. Due to the foregoing two types of joining (i.e., joining of conductors and joining of insulators), effective joining (such as forming atomic bridging; and metal-to-metal diffusion joining) can be formed at a low heating temperature (such as lower than the melting point of metallic copper) because of the corresponding materials and / or structures (such as materials having siloxane, siloxanyl groups; and copper nanowires). Therefore, the possibility of causing thermal damage to the components and / or thermal warping due to heating during the joining process can be reduced. In this way, the quality and effect of the joining can be improved.

[0107] In the foregoing embodiment, the conductive layer can be a single-layer or multi-layer structure. And if the conductive layer is a multi-layer structure, there may be no insulating material or dielectric material between the foregoing multi-layers. Additionally, in terms of structure, if the conductive layer is a multi-layer structure, even if the foregoing multi-layers are formed by different processes, they can still be (but not limited to) represented by the same terms and / or symbols.

[0108] In the foregoing embodiment, the insulating layer can be a single-layer or multi-layer structure. And if the insulating layer is a multi-layer structure, there may be no conductive material between the foregoing multi-layers. Additionally, in terms of structure, if the insulating layer is a multi-layer structure, even if the foregoing multi-layers are formed by different processes, they can still be (but not limited to) represented by the same terms and / or symbols.

[0109] In the foregoing embodiment, one conductor and another conductor can be electrically connected to each other through corresponding conductive members (such as conductive vias, circuits). That is to say, unless otherwise specifically stated or implied, even if one conductor and another conductor are not shown electrically connected in the drawings, the foregoing one conductor and the foregoing another conductor can still be electrically connected to each other through conductive members that are not shown in the drawings or on the cross-sections that are not shown.

Claims

1. A method for fabricating a substrate structure, characterized in that, Comprising: Providing a first substrate, including a first core layer and a first conductor exposed to the outside; Providing a second substrate, including a second core layer and a second conductor exposed to the outside; Forming a conductive nanowire on the first conductor or the second conductor; And Corresponding the first conductor of the first substrate with the second conductor of the second substrate, and positioning the conductive nanowire between the first conductor and the second conductor, so as to join the first substrate and the second substrate by at least a conductive diffusion bonding manner formed by the conductive nanowire.

2. The method for fabricating a substrate structure according to claim 1, wherein Wherein the first conductor or the second conductor comprises the same material as the conductive nanowire.

3. The method for fabricating a substrate structure according to claim 2, wherein Wherein the first conductor or the second conductor comprises a copper layer, and the conductive nanowire is a copper nanowire.

4. The method for fabricating a substrate structure according to claim 3, wherein Wherein the copper nanowire is directly formed on the copper layer.

5. The method for fabricating a substrate structure according to claim 1, wherein Wherein the first substrate or the second substrate further comprises a polymer, and during the process of corresponding the first conductor of the first substrate with the second conductor of the second substrate, the polymer is also positioned between the first core layer and the second core layer, so as to further join the first substrate and the second substrate by a chain-like or network structure formed by the polymer.

6. The method for fabricating a substrate structure according to claim 1 or 5, characterized in that, Wherein during the process of joining the separated first substrate and the second substrate, the temperature is less than or equal to 200 °C.

7. The method for fabricating a substrate structure according to claim 5, wherein Wherein the polymer comprises a silicone polymer, and the chain-like or network structure has at least bridging oxygen.

8. A substrate structure, characterized in that, Comprising: A first substrate, which includes a first core layer and a first conductor; And A second substrate, which includes a second core layer and a second conductor, wherein: There is a metal diffusion bonding interface between the first conductor and the second conductor; And There is a covalent bond bonding interface between the first core layer and the second core layer.

9. The substrate structure according to claim 8, characterized in that, Wherein the metal diffusion bonding interface is a copper diffusion bonding interface.

10. The substrate structure according to claim 8, wherein Wherein the covalent bond bonding interface is a chain-like or network structure having at least bridging oxygen.

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