Fully depleted silicon-on-insulator (FDSOI) wafer and manufacturing method thereof
By introducing high germanium content compressively strained silicon germanium materials and tensile strained silicon layers into the FDSOI wafer, the problem of insufficient PMOS hole mobility in traditional FDSOI technology is solved, and the synchronous improvement of PMOS and NMOS performance is achieved, and the overall performance and stability of CMOS devices are improved.
Patent Information
- Application Number
- CN202510529118.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-24
- Publication Date
- 2025-07-25
AI Technical Summary
The traditional FDSOI technology lacks hole mobility in PMOS transistors in nodes of 14nm and below, resulting in unbalanced performance of CMOS devices, making it difficult to take into account both low power consumption and high performance in high-performance logic applications.
By introducing compressively strained silicon germanium materials with high germanium content into the FDSOI wafer, combined with tensile strained silicon layer and wafer bonding technology, heterogeneous integration of PMOS and NMOS is achieved, improving the hole mobility of PMOS and maintaining the high electron mobility of NMOS.
It achieves balanced improvements in PMOS and NMOS performance, improves the overall performance of CMOS devices, reduces power consumption and enhances the stability and reliability of the device, and is suitable for low voltage and low power consumption designs.
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Figure CN120376505A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductors, and particularly to a fully depleted silicon-on-insulator (FDSOI) wafer and a manufacturing method thereof. Background Art
[0002] As an effective solution to a series of challenges faced by traditional complementary metal-oxide-semiconductor (CMOS) devices during the miniaturization process, such as short-channel effect, leakage power consumption, process complexity, high cost, and poor device performance consistency, the fully depleted silicon-on-insulator (FDSOI) technology has achieved remarkable application results at technology nodes such as 28 nm and 22 nm. However, with the continuous development of nodes towards 14 nm and below, the FDSOI technology faces many manufacturing challenges, especially the issues of uniformity control, defect management, and electric field control during the manufacturing process of an extremely thin silicon body (20 - 40 nm) have become increasingly prominent. Although the thin silicon body can effectively improve the electric field control ability, as the size is further reduced, its effect in suppressing the short-channel effect gradually weakens. Therefore, in high-performance logic applications at the 14 nm node and below, the traditional FDSOI technology gradually exposes performance bottlenecks in terms of the hole mobility of P-type metal-oxide-semiconductor (PMOS) transistors in CMOS devices, resulting in performance imbalance between N-type metal-oxide-semiconductor (NMOS) transistors and PMOS transistors in current CMOS devices.
[0003] That is to say, there is an urgent need to manufacture an FDSOI wafer that simultaneously has high hole mobility and high electron mobility to improve the performance of CMOS devices finally manufactured using the FDSOI wafer. Summary of the Invention
[0004] In view of this, the purpose of this application is to provide a fully depleted silicon-on-insulator (FDSOI) wafer and a manufacturing method thereof, which can manufacture an FDSOI wafer that simultaneously has high hole mobility and high electron mobility, and improve the performance of CMOS devices manufactured using the FDSOI wafer.
[0005] This application provides a manufacturing method of a fully depleted silicon-on-insulator (FDSOI) wafer, and the method includes:
[0006] Providing a first substrate, on which a first silicon-germanium layer, a second silicon-germanium layer, a first silicon layer, and a first buried oxide layer are sequentially stacked, wherein the germanium content of the first silicon-germanium layer is less than that of the second silicon-germanium layer; the first silicon layer is a tensile-strained silicon layer; the sequentially stacked first substrate, first silicon-germanium layer, second silicon-germanium layer, first silicon layer, and first buried oxide layer include an N-type conductive region and a P-type conductive region;
[0007] Etch away the first buried oxide layer and the first silicon layer located in the P-type conductive region;
[0008] Form a third silicon germanium layer on the surface of the second silicon germanium layer in the P-type conductive region, where the germanium content of the third silicon germanium layer is greater than that of the second silicon germanium layer; the germanium content of the third silicon germanium layer is greater than 50%;
[0009] Form a second buried oxide layer on the surface of the third silicon germanium layer. The first substrate, the first silicon germanium layer, the second silicon germanium layer, the first silicon layer, the first buried oxide layer, the third silicon germanium layer, and the second buried oxide layer constitute a donor substrate;
[0010] Provide an acceptor substrate, where the acceptor substrate includes a second substrate and a third buried oxide layer located on one side of the second substrate;
[0011] Bond the donor substrate and the acceptor substrate in the direction where the first buried oxide layer faces the third buried oxide layer;
[0012] Remove the first substrate, the first silicon germanium layer, and the second silicon germanium layer to obtain a fully depleted silicon-on-insulator FDSOI wafer. The FDSOI wafer includes a first silicon layer located in the N-type conductive region and a third silicon germanium layer located in the P-type conductive region.
[0013] Optionally, the germanium content of the third silicon germanium layer is 60%-70%.
[0014] Optionally, forming the third silicon germanium layer on the surface of the second silicon germanium layer in the P-type conductive region includes:
[0015] Form a third silicon germanium layer on the surface of the second silicon germanium layer in the P-type conductive region by using a low-temperature selective epitaxy process. The thickness of the third silicon germanium layer is the same as that of the first silicon layer.
[0016] Optionally, the third silicon germanium layer is a compressive strained silicon germanium layer.
[0017] Optionally, the germanium content of the second silicon germanium layer is 40%, and the germanium content of the first silicon germanium layer is 10%-30%.
[0018] Optionally, before etching away the first buried oxide layer and the first silicon layer located in the P-type conductive region, the method further includes:
[0019] Etch the first silicon germanium layer, the second silicon germanium layer, the first silicon layer, the first buried oxide layer, and a part of the thickness of the first substrate to form a groove;
[0020] An insulating material is filled in the groove to form a shallow trench isolation, and the shallow trench isolation divides a first substrate, a first silicon-germanium layer, a second silicon-germanium layer, a first silicon layer, and a first buried oxide layer which are sequentially stacked into an N-type conductive region and a P-type conductive region.
[0021] Optionally, the obtaining of the fully depleted silicon-on-insulator FDSOI wafer by removing the first substrate, the first silicon-germanium layer, and the second silicon-germanium layer includes:
[0022] Removing the first substrate by using one or more of a mechanical thinning process, a dry etching process, and a wet etching process;
[0023] Removing the first silicon-germanium layer and the second silicon-germanium layer by using a chemical mechanical polishing process to obtain a fully depleted silicon-on-insulator FDSOI wafer.
[0024] The present application provides a fully depleted silicon-on-insulator FDSOI wafer, including:
[0025] A second substrate, a third buried oxide layer, and an oxide layer which are sequentially stacked; the second substrate, the third buried oxide layer, and the oxide layer include an N-type conductive region and a P-type conductive region; the first silicon layer is a tensile strained silicon layer;
[0026] A third silicon-germanium layer is disposed on the oxide layer in the P-type conductive region, and a first silicon layer is disposed on the oxide layer in the N-type conductive region; the germanium content of the third silicon-germanium layer is greater than 50%.
[0027] Optionally, the germanium content of the third silicon-germanium layer is 60%-70%.
[0028] Optionally, the third silicon-germanium layer is a compressive strained silicon-germanium layer.
[0029] The present application provides a method for manufacturing a fully depleted silicon-on-insulator (FDSOI) wafer, the method comprising: providing a first substrate, sequentially stacking a first silicon-germanium layer, a second silicon-germanium layer, a first silicon layer, and a first buried oxide layer on the first substrate, the first silicon layer being a tensile-strained silicon layer, that is, the first silicon layer having a strong electron mobility, and the germanium content of the first silicon-germanium layer being less than that of the second silicon-germanium layer; the sequentially stacked first substrate, first silicon-germanium layer, second silicon-germanium layer, first silicon layer, and first buried oxide layer including an N-type conduction region and a P-type conduction region; etching away the first buried oxide layer and the first silicon layer located in the P-type conduction region; forming a third silicon-germanium layer on the surface of the second silicon-germanium layer in the P-type conduction region, the germanium content of the third silicon-germanium layer being greater than that of the second silicon-germanium layer; the germanium content of the third silicon-germanium layer being greater than 50%, that is, the third silicon-germanium layer having a high germanium content and being able to have a strong hole mobility; forming a second buried oxide layer on the surface of the third silicon-germanium layer, the first substrate, first silicon-germanium layer, second silicon-germanium layer, first silicon layer, first buried oxide layer, third silicon-germanium layer, and second buried oxide layer constituting a donor substrate; providing an acceptor substrate, the acceptor substrate including a second substrate and a third buried oxide layer located on one side of the second substrate; bonding the donor substrate and the acceptor substrate in the direction of the first buried oxide layer facing the third buried oxide layer; removing the first substrate, first silicon-germanium layer, and second silicon-germanium layer to obtain a fully depleted silicon-on-insulator (FDSOI) wafer, the FDSOI wafer including the first silicon layer in the N-type conduction region and the third silicon-germanium layer in the P-type conduction region. Thus, it can be seen that in the present application, by forming the first silicon-germanium layer and the second silicon-germanium layer with gradually increasing germanium content on the donor substrate, a third silicon-germanium layer with a high germanium content is manufactured, thereby realizing a high hole mobility in the P-type conduction region. Since the first silicon layer has tensile strain, a high electron mobility in the N-type conduction region can be realized. After bonding the donor substrate and the acceptor substrate, an FDSOI wafer including a P-type conduction region with a high hole mobility and an N-type conduction region with a high electron mobility is obtained, that is, an FDSOI wafer capable of simultaneously having a high hole mobility and a high electron mobility can be manufactured, realizing relatively balanced performance of the PMOS transistor manufactured in the P-type conduction region and the NMOS transistor manufactured in the N-type conduction region, and finally realizing the manufacture of high-performance CMOS devices using the FDSOI wafer. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0031] Figure 1The flowchart shows a method for manufacturing a fully depleted silicon-on-insulator (FDSOI) wafer provided by an embodiment of the present application;
[0032] Figures 2 - 8 The structural diagram shows a fully depleted silicon-on-insulator (FDSOI) wafer manufactured by the method for manufacturing a fully depleted silicon-on-insulator (FDSOI) wafer provided by an embodiment of the present application. Detailed implementation manners
[0033] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.
[0034] Many specific details are set forth in the following description in order to provide a thorough understanding of the present application, but the present application may be implemented in other ways different from those described herein. Those skilled in the art can make similar generalizations without departing from the spirit of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.
[0035] The present application is described in detail in conjunction with the schematic diagrams. When detailing the embodiments of the present application, for the sake of convenience of explanation, the cross-sectional views showing the device structures will be enlarged locally out of the general scale, and the schematic diagrams are only examples and should not limit the protection scope of the present application here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.
[0036] In high-performance logic applications at the 14nm node and below, traditional FDSOI technology has gradually exposed performance bottlenecks in terms of the hole mobility of P-type metal-oxide-semiconductor (PMOS) transistors in CMOS devices. In traditional FDSOI at the 14nm and below nodes, the performance bottleneck of FDSOI PMOS due to low hole mobility (significantly lagging behind NMOS) restricts the overall performance balance of CMOS circuits; it is difficult to maintain the tensile strain of the silicon channel in FDSOI NMOS.
[0037] To solve this problem, the hole mobility of PMOS transistors has been effectively improved by introducing high-mobility silicon-germanium materials, significantly making up for the performance gap between PMOS transistors and NMOS transistors. The higher the germanium content in the germanium-silicon material, the higher the hole mobility. However, it is difficult to manufacture an FDSOI wafer with both a silicon layer and a germanium-silicon layer with a high germanium content. Currently, the germanium content of the germanium-silicon layer in FDSOI wafers is relatively low, resulting in a poor improvement effect on hole mobility.
[0038] In addition, the effect of suppressing short-channel effects in traditional FDSOI weakens under an ultra-thin channel, resulting in an increase in leakage current and subthreshold current, which affects device reliability. When operating at low voltages, the drive current of FDSOI CMOS is insufficient, making it difficult to balance low power consumption and high-performance requirements.
[0039] Therefore, to break through the bottleneck of existing technologies, FDSOI technology urgently needs to achieve the co-integration of silicon-channel NMOS and silicon-germanium-channel PMOS to ensure a balanced improvement in the performance of NMOS and PMOS on the same silicon platform. By solving their respective performance bottlenecks, the application prospects of FDSOI technology at more advanced nodes can be further promoted.
[0040] That is to say, there is an urgent need to fabricate FDSOI wafers with both high hole mobility and high electron mobility to improve the performance of CMOS devices ultimately fabricated using the FDSOI wafers.
[0041] Based on this, the present application provides a method for manufacturing a fully depleted silicon-on-insulator (FDSOI) wafer, the method comprising: providing a first substrate, sequentially laminating a first silicon-germanium layer, a second silicon-germanium layer, a first silicon layer, and a first buried oxide layer on the first substrate, the first silicon layer being a tensile-strained silicon layer, that is, the first silicon layer has a strong electron mobility, and the germanium content of the first silicon-germanium layer is less than that of the second silicon-germanium layer; the sequentially laminated first substrate, first silicon-germanium layer, second silicon-germanium layer, first silicon layer, and first buried oxide layer include an N-type conductive region and a P-type conductive region; etching away the first buried oxide layer and the first silicon layer located in the P-type conductive region; forming a third silicon-germanium layer on the surface of the second silicon-germanium layer in the P-type conductive region, the germanium content of the third silicon-germanium layer being greater than that of the second silicon-germanium layer; the germanium content of the third silicon-germanium layer is greater than 50%, that is, the germanium content of the third silicon-germanium layer is relatively high and can have a strong hole mobility; forming a second buried oxide layer on the surface of the third silicon-germanium layer, and the first substrate, first silicon-germanium layer, second silicon-germanium layer, first silicon layer, first buried oxide layer, third silicon-germanium layer, and second buried oxide layer constitute a donor substrate; providing an acceptor substrate, the acceptor substrate including a second substrate and a third buried oxide layer located on one side of the second substrate; bonding the donor substrate and the acceptor substrate in the direction of the first buried oxide layer facing the third buried oxide layer; removing the first substrate, first silicon-germanium layer, and second silicon-germanium layer to obtain a fully depleted silicon-on-insulator (FDSOI) wafer, the FDSOI wafer including the first silicon layer in the N-type conductive region and the third silicon-germanium layer in the P-type conductive region. Thus, it can be seen that the present application manufactures a third silicon-germanium layer with a high germanium content by forming the first silicon-germanium layer and the second silicon-germanium layer with gradually increasing germanium content in the donor substrate, thereby achieving a high hole mobility in the P-type conductive region. Due to the tensile strain of the first silicon layer, a high electron mobility in the N-type conductive region can be achieved. After bonding the donor substrate and the acceptor substrate, an FDSOI wafer including a P-type conductive region with a high hole mobility and an N-type conductive region with a high electron mobility is obtained, that is, an FDSOI wafer with both a high hole mobility and a high electron mobility can be manufactured, realizing a more balanced performance of the PMOS transistor manufactured in the P-type conductive region and the NMOS transistor manufactured in the N-type conductive region, and ultimately realizing the manufacture of high-performance CMOS devices using the FDSOI wafer.
[0042] To better understand the technical solutions and technical effects of the present application, the following will describe specific embodiments in detail with reference to the accompanying drawings.
[0043] See Figure 1 , which is a schematic flowchart of a method for manufacturing a fully depleted silicon-on-insulator (FDSOI) wafer provided by an embodiment of the present application.
[0044] The method for manufacturing a fully depleted silicon-on-insulator (FDSOI) wafer provided by this embodiment includes the following steps:
[0045] S101, provide a first substrate, on which a first silicon-germanium layer, a second silicon-germanium layer, a first silicon layer, and a first buried oxide layer are sequentially stacked. The germanium content of the first silicon-germanium layer is less than that of the second silicon-germanium layer; the first silicon layer is a tensile-strained silicon layer; the sequentially stacked first substrate, first silicon-germanium layer, second silicon-germanium layer, first silicon layer, and first buried oxide layer include an N-type conductive region and a P-type conductive region.
[0046] In an embodiment of the present application, the first substrate 110 may be a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. On the first substrate 110, a first silicon-germanium layer 120, a second silicon-germanium layer 130, a first silicon layer 210, and a first buried oxide layer 220 are sequentially stacked, as shown in Figure 2 the figure. Among them, the elements included in the first silicon-germanium layer 120 and the second silicon-germanium layer 130 at least include silicon and germanium. The germanium content of the first silicon-germanium layer 120 is less than that of the second silicon-germanium layer 130. The germanium content refers to the molar content of germanium occupying all elements. The first silicon-germanium layer 120 serves as a buffer layer between the second silicon-germanium layer 130 and the first substrate 110.
[0047] As an example, the materials of the first silicon-germanium layer 120 and the second silicon-germanium layer 130 are silicon-germanium (SiGe), SiGeC, or SiGeCB.
[0048] As a possible implementation, the germanium content of the second silicon-germanium layer 130 is 40%, and the germanium content of the first silicon-germanium layer 120 is 10% - 30%.
[0049] As an example, the thickness of the first silicon-germanium layer 120 is 10 - 200 nm, the thickness of the second silicon-germanium layer 130 is 10 - 200 nm. The thickness of the first silicon layer 210 is 10 nm, and the thickness of the first buried oxide layer 220 is 5 - 10 nm.
[0050] The material of the first silicon layer 210 is silicon. The first silicon layer 210 may be a tensile-strained silicon layer. The tensile-strained silicon layer can improve the electron mobility, thereby realizing the channel layer of an NMOS transistor with high electron mobility. The drive current is comparable to that of a fin field-effect transistor (FinFET), and the dynamic power consumption is reduced.
[0051] As a possible implementation, the material of the first buried oxide layer 220 is an insulating material, such as silicon oxide.
[0052] In an embodiment of the present application, the first substrate 110, the first silicon-germanium layer 120, the second silicon-germanium layer 130, the first silicon layer 210, and the first buried oxide layer 220 that are sequentially stacked include an N-type conductive region 200 and a P-type conductive region 300. The N-type conductive region 200 can be used for manufacturing NMOS transistors subsequently, and the P-type conductive region 300 can be used for manufacturing PMOS transistors subsequently.
[0053] As a possible implementation, the N-type conductive region 200 and the P-type conductive region 300 can be divided by using shallow trench isolation 610, as shown in the reference. Figure 2 The steps for specifically forming the shallow trench isolation 610 are introduced as follows.
[0054] Etch the first silicon-germanium layer 120, the second silicon-germanium layer 130, the first silicon layer 210, the first buried oxide layer 220, and a part of the thickness of the first substrate 110 to form a groove, and this groove divides the first substrate 110, the first silicon-germanium layer 120, the second silicon-germanium layer 130, the first silicon layer 210, and the first buried oxide layer 220 that are sequentially stacked into an N-type conductive region 200 and a P-type conductive region 300. Fill the groove with an insulating material to form the shallow trench isolation 610. At this time, the shallow trench isolation 610 divides the first substrate 110, the first silicon-germanium layer 120, the second silicon-germanium layer 130, the first silicon layer 210, and the first buried oxide layer 220 that are sequentially stacked into an N-type conductive region 200 and a P-type conductive region 300.
[0055] S102, etch and remove the first buried oxide layer and the first silicon layer located in the P-type conductive region.
[0056] In an embodiment of the present application, the first silicon layer 210 can be used as the channel layer for subsequently forming NMOS transistors. To improve the performance of the PMOS transistors formed subsequently, silicon material may not be used as the channel layer. Therefore, the first buried oxide layer 220 and the first silicon layer 210 located in the P-type conductive region 300 can be etched and removed to expose the second silicon-germanium layer 130 located in the P-type conductive region 300, as shown in the reference. Figure 3 as shown.
[0057] When etching and removing the first buried oxide layer 220 and the first silicon layer 210 located in the P-type conductive region 300, the second silicon-germanium layer 130 can be used as an etch stop layer to ensure that the P-type conductive region 300 has a good surface quality after etching, thereby helping to form a thin film with a higher crystallization quality subsequently.
[0058] S103, form a third silicon-germanium layer on the surface of the second silicon-germanium layer in the P-type conductive region. The germanium content of the third silicon-germanium layer is greater than that of the second silicon-germanium layer; the germanium content of the third silicon-germanium layer is greater than 50%.
[0059] In an embodiment of the present application, since the first buried oxide layer 220 and the first silicon layer 210 in the P-type conductive region 300 are completely etched away, in order to achieve a higher hole mobility for the subsequently formed PMOS transistor, a third silicon-germanium layer 310 can be formed on the surface of the second silicon-germanium layer 130 in the P-type conductive region 300, as shown in reference Figure 4 as shown.
[0060] Among them, the germanium content of the third silicon-germanium layer 310 is greater than that of the second silicon-germanium layer 130; based on the germanium content of the second silicon-germanium layer 130, it is easier to form a third silicon-germanium layer 310 with a higher germanium content. The germanium content of the third silicon-germanium layer 310 is greater than 50%, so as to achieve a higher germanium content of the third silicon-germanium layer 310, and then achieve a higher hole mobility, and the performance of the PMOS transistor manufactured by using the third silicon-germanium layer 310 subsequently is better.
[0061] As a possible implementation, since the germanium content of the third silicon-germanium layer 310 is greater than that of the second silicon-germanium layer 130, the third silicon-germanium layer 310 has compressive strain, that is, the third silicon-germanium layer 310 is a compressive-strained silicon-germanium layer. The compressive-strained silicon-germanium layer can achieve a decrease in the threshold voltage of the PMOS transistor, optimize the subthreshold swing, support ultra-low voltage operation below 0.5V, and reduce the static power consumption.
[0062] As a possible implementation, the germanium content of the third silicon-germanium layer 310 is 60%-70%. That is to say, based on the second silicon-germanium layer 130 with a germanium content of 40%, a third silicon-germanium layer 310 with a higher germanium content can also be formed. The third silicon-germanium layer 310 with a higher germanium content can provide a higher hole mobility. The third silicon-germanium layer 310 with a higher germanium content reduces the bandgap through band engineering, alleviates the short-channel effect, and reduces the leakage current by more than 30%.
[0063] As a possible implementation, a third silicon-germanium layer 310 can be formed on the surface of the second silicon-germanium layer 130 in the P-type conductive region 300 by using a low-temperature selective epitaxy process. The third silicon-germanium layer 310 formed by the low-temperature selective epitaxy process has a higher crystal quality and can further improve the hole mobility.
[0064] The thickness of the third silicon-germanium layer 310 is the same as that of the first silicon layer 210, so as to achieve uniform film layers in the P-type conductive region 300 and the N-type conductive region 200, which is helpful for subsequently forming PMOS transistors and NMOS transistors with smaller performance differences.
[0065] S104, form a second buried oxide layer on the surface of the third silicon-germanium layer. The first substrate, the first silicon-germanium layer, the second silicon-germanium layer, the first silicon layer, the first buried oxide layer, the third silicon-germanium layer, and the second buried oxide layer constitute a donor substrate.
[0066] In an embodiment of the present application, after forming the third silicon germanium layer 310 on the surface of the second silicon germanium layer 130 located in the P-type conductive region 300, a second buried oxide layer 320 may also be formed on the surface of the third silicon germanium layer 310, as shown in reference to Figure 5 shown.
[0067] As a possible implementation, the material of the second buried oxide layer 320 is an insulating material, such as silicon oxide.
[0068] Specifically, an insulating material may be filled on the surface of the third silicon germanium layer 310, and then chemical mechanical polishing treatment is performed to obtain the second buried oxide layer 320.
[0069] In an embodiment of the present application, the first substrate 110, the first silicon germanium layer 120, the second silicon germanium layer 130, the first silicon layer 210, the first buried oxide layer 220, the third silicon germanium layer 310, and the second buried oxide layer 320 together constitute a donor substrate. Among them, the first silicon layer 210 and the first buried oxide layer 220 are located in the N-type conductive region 200, and the third silicon germanium layer 310 and the second buried oxide layer 320 are located in the P-type conductive region 300.
[0070] S105, provide an acceptor substrate, where the acceptor substrate includes a second substrate and a third buried oxide layer located on one side of the second substrate.
[0071] In an embodiment of the present application, the donor substrate includes the first silicon layer 210 located in the N-type conductive region 200 and the third silicon germanium layer 310 located in the P-type conductive region 300. To manufacture a complete fully depleted silicon-on-insulator (FDSOI) wafer, an acceptor substrate can be provided. The acceptor substrate includes a second substrate 410 and a third buried oxide layer 420 located on one side of the second substrate 410, as shown in reference to Figure 6 shown, that is, the acceptor substrate provides the insulating layer and the substrate of the FDSOI wafer.
[0072] The second substrate 410 may be a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon germanium substrate, etc. Since the FDSOI wafer is manufactured based on the present application, the second substrate 410 is a silicon substrate.
[0073] The material of the third buried oxide layer 420 is an insulating material, such as silicon oxide. The thickness of the third buried oxide layer 420 is 10 nm.
[0074] S106, bond the donor substrate and the acceptor substrate in the direction of the first buried oxide layer facing the third buried oxide layer.
[0075] In an embodiment of the present application, the donor substrate can provide a first silicon layer 210 and a third silicon germanium layer 310, and the acceptor substrate can provide a third buried oxide layer 420 and a second substrate 410. The donor substrate and the acceptor substrate can be bonded in a direction where the first buried oxide layer 220 or the second buried oxide layer 220 faces the third buried oxide layer 420, so as to form an integrated structure of the first silicon layer 210, the third silicon germanium layer 310, the third buried oxide layer 420 and the second substrate 410. Refer to Figure 7 as shown.
[0076] S107, Remove the first substrate, the first silicon germanium layer and the second silicon germanium layer to obtain a fully depleted silicon-on-insulator (FDSOI) wafer. The FDSOI wafer includes a first silicon layer located in the N-type conductivity region and a third silicon germanium layer located in the P-type conductivity region.
[0077] In an embodiment of the present application, after bonding the donor substrate and the acceptor substrate, the first substrate 110, the first silicon germanium layer 120 and the second silicon germanium layer 130 can be removed to obtain an FDSOI wafer. At this time, the FDSOI wafer includes a second substrate 410, a third buried oxide layer 420, a second buried oxide layer 320 and a third silicon germanium layer 310 located in the P-type conductivity region 300, and a first buried oxide layer 220 and a first silicon layer 210 located in the N-type conductivity region 200. Refer to Figure 8 as shown.
[0078] That is to say, the insulating layers of the FDSOI wafer are the third buried oxide layer 420, the second buried oxide layer 320 and the first buried oxide layer 220. The third buried oxide layer 420, the second buried oxide layer 320 and the first buried oxide layer 220 can be used to improve the electric field control ability.
[0079] Specifically, a mechanical thinning process, a dry etching process, and / or a wet etching process can be used to remove the first substrate 110. During the process of removing the first substrate 110, the first silicon germanium layer 120 can serve as an etching stop layer, so that after removing the first substrate 110, the surface quality of the first silicon germanium layer 120 is good.
[0080] A chemical mechanical polishing process is used to remove the first silicon germanium layer 120 and the second silicon germanium layer 130 to obtain an FDSOI wafer. During the process of removing the first silicon germanium layer 120 and the second silicon germanium layer 130, a part of the thickness of the shallow trench isolation 610 is also removed at the same time, so that the surface on the side of the shallow trench isolation 610 away from the second substrate 410 is flush with the first silicon layer 210 or the third silicon germanium layer 310.
[0081] It can be seen that the manufacturing method of the fully depleted silicon-on-insulator (FDSOI) wafer provided by the embodiments of the present application realizes the heterogeneous integration of tensile-strained silicon (NMOS) and compressive-strained silicon germanium (PMOS) on the same FDSOI wafer through a low-temperature lateral selective epitaxy process and a wafer bonding process, breaking through the limitations of silicon-based materials on electron mobility and hole mobility in traditional FDSOI CMOS processes, and achieving synchronous improvement in the performance of NMOS and PMOS. The manufacturing method of the present application is compatible with mainstream CMOS processes, and the process modification cost is controllable, with the potential to be extended to more advanced nodes. Through the collaborative design of the SiGe channel and the fully depleted structure, the physical limitations of traditional FinFETs are broken through, and high-performance devices are achieved at smaller nodes. The use of compressive-strained silicon germanium materials with a high germanium content (60-70%) significantly improves the hole mobility of PMOS. When the germanium content reaches 60-70%, the hole mobility of PMOS is greatly improved compared with traditional silicon materials, thereby achieving higher drive current, better switching performance, and higher operating frequency. The use of tensile-strained silicon as the NMOS channel material significantly improves electron mobility, and the tensile strain achieved through wafer bonding can be stably maintained after preparation, further enhancing the performance of NMOS. As the germanium content in the PMOS silicon germanium channel increases to 60-70%, the threshold voltage of the device shows a downward trend, and the subthreshold swing becomes steeper, significantly improving the switching characteristics of the device. This optimization not only helps to reduce power consumption, especially suitable for low-voltage operating environments, but also significantly enhances the overall performance of the device while maintaining low power consumption. The silicon germanium channel material with a high germanium content can effectively reduce the short-channel effect. Under the condition of a high germanium content, the negative impact of channel length shortening on device performance is alleviated. Especially at the nanoscale, the leakage current and subthreshold current are better controlled, thereby improving the stability and reliability of the device. Due to the low bandgap and excellent current transmission characteristics of the silicon germanium channel material with a high germanium content, the power consumption of the device at low voltage can be effectively controlled. By increasing the germanium content, excellent device performance can be maintained under low-power operation, and this characteristic makes this design particularly suitable for low-power designs.
[0082] Based on the manufacturing method of a fully depleted silicon-on-insulator (FDSOI) wafer provided in the above embodiments, the embodiments of the present application also provide a fully depleted silicon-on-insulator (FDSOI) wafer. The working principle will be described in detail below with reference to the drawings.
[0083] See Figure 8 , which is a schematic structural diagram of a fully depleted silicon-on-insulator (FDSOI) wafer provided by an embodiment of the present application.
[0084] The fully depleted silicon-on-insulator (FDSOI) wafer provided in this embodiment includes a second substrate 410, a third buried oxide layer 420, and an oxide layer that are sequentially stacked; the second substrate 410, the third buried oxide layer 420, and the oxide layer include an N-type conductivity region 200 and a P-type conductivity region 300; the first silicon layer 210 is a tensile strained silicon layer.
[0085] Specifically, the oxide layer located in the N-type conductivity region 200 is the first buried oxide layer 220, and the oxide layer located in the P-type conductivity region 300 is the second buried oxide layer 320.
[0086] A third silicon germanium layer 310 is disposed on the oxide layer located in the P-type conductivity region 300, and a first silicon layer 210 is disposed on the oxide layer located in the N-type conductivity region 200. The germanium content of the third silicon germanium layer 310 is greater than 50%.
[0087] As a possible implementation, the germanium content of the third silicon germanium layer 310 is 60%-70%. That is to say, based on the second silicon germanium layer 130 with a germanium content of 40%, a third silicon germanium layer 310 with a higher germanium content can also be formed. The third silicon germanium layer 310 with a higher germanium content can provide a higher hole mobility. The third silicon germanium layer 310 with a higher germanium content reduces the bandgap through bandgap engineering, alleviates the short-channel effect, and the leakage current is reduced by more than 30%.
[0088] As a possible implementation, the third silicon germanium layer 310 is a compressive strained silicon germanium layer.
[0089] It can be seen that the fully depleted silicon-on-insulator (FDSOI) wafer provided in the embodiment of the present application combines strain engineering with the fully depleted characteristics of the FDSOI ultra-thin body to achieve the collaborative optimization of power consumption, performance, and reliability. By reasonably selecting strain materials (such as tensile strained silicon for NMOS and compressive strained silicon germanium for PMOS), the mobility of the channel material is optimized, thereby improving the device performance. The oxide layer not only effectively suppresses the short-channel effect but also can be used as a strain buffer layer to reduce the interference of the second substrate on the channel strain, thereby further improving the stability and performance of the device.
[0090] Each embodiment in this specification is described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and the key points of each embodiment are the differences from other embodiments. In particular, for the structural embodiments, since they are basically similar to the method embodiments, they are described relatively simply, and the relevant parts can be referred to the partial descriptions of the method embodiments. Those of ordinary skill in the art can understand and implement without creative efforts.
[0091] The above is only the preferred embodiment of the present application. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present application, or modify it into equivalent embodiments with equivalent changes, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of protection of the technical solution of the present application.
Claims
1. A manufacturing method of a fully depleted silicon on insulator FDSOI wafer, characterized in that, The method includes: Providing a first substrate, on which a first silicon-germanium layer, a second silicon-germanium layer, a first silicon layer, and a first buried oxide layer are sequentially stacked, wherein the germanium content of the first silicon-germanium layer is less than that of the second silicon-germanium layer; the first silicon layer is a tensile-strained silicon layer; the sequentially stacked first substrate, first silicon-germanium layer, second silicon-germanium layer, first silicon layer, and first buried oxide layer include an N-type conductive region and a P-type conductive region; Etching and removing the first buried oxide layer and the first silicon layer located in the P-type conductive region; Forming a third silicon-germanium layer on the surface of the second silicon-germanium layer in the P-type conductive region, wherein the germanium content of the third silicon-germanium layer is greater than that of the second silicon-germanium layer; the germanium content of the third silicon-germanium layer is greater than 50%; Forming a second buried oxide layer on the surface of the third silicon-germanium layer, and the first substrate, first silicon-germanium layer, second silicon-germanium layer, first silicon layer, first buried oxide layer, third silicon-germanium layer, and second buried oxide layer constitute a donor substrate; Providing an acceptor substrate, which includes a second substrate and a third buried oxide layer located on one side of the second substrate; Bonding the donor substrate and the acceptor substrate in the direction of the first buried oxide layer facing the third buried oxide layer; Removing the first substrate, first silicon-germanium layer, and second silicon-germanium layer to obtain a fully depleted silicon-on-insulator FDSOI wafer, and the FDSOI wafer includes a first silicon layer located in the N-type conductive region and a third silicon-germanium layer located in the P-type conductive region.
2. The method according to claim 1, wherein The germanium content of the third silicon-germanium layer is 60%-70%.
3. The method according to claim 1, characterized in that The forming of the third silicon-germanium layer on the surface of the second silicon-germanium layer in the P-type conductive region includes: Forming a third silicon-germanium layer on the surface of the second silicon-germanium layer in the P-type conductive region by using a low-temperature selective epitaxy process, and the thickness of the third silicon-germanium layer is the same as that of the first silicon layer.
4. The method according to claim 1, wherein The third silicon-germanium layer is a compressive-strained silicon-germanium layer.
5. The method according to claim 1, wherein The germanium content of the second silicon-germanium layer is 40%, and the germanium content of the first silicon-germanium layer is 10%-30%.
6. The method according to any one of claims 1-5, characterized in that, Before etching and removing the first buried oxide layer and the first silicon layer located in the P-type conductive region, the method further includes: Etching the first silicon-germanium layer, the second silicon-germanium layer, the first silicon layer, the first buried oxide layer, and a part of the thickness of the first substrate to form a groove; Filling an insulating material in the groove to form a shallow trench isolation, and the shallow trench isolation divides the sequentially stacked first substrate, first silicon-germanium layer, second silicon-germanium layer, first silicon layer, and first buried oxide layer into an N-type conductive region and a P-type conductive region.
7. The method according to claim 1, wherein The removing of the first substrate, first silicon-germanium layer, and second silicon-germanium layer to obtain a fully depleted silicon-on-insulator FDSOI wafer includes: Removing the first substrate by using one or more of a mechanical thinning process, a dry etching process, and a wet etching process; Removing the first silicon-germanium layer and the second silicon-germanium layer by using a chemical mechanical polishing process to obtain a fully depleted silicon-on-insulator FDSOI wafer.
8. A fully depleted silicon-on-insulator (FDSOI) wafer, characterized in that, Includes: A second substrate, a third buried oxide layer, and an oxide layer sequentially stacked; the second substrate, third buried oxide layer, and oxide layer include an N-type conductive region and a P-type conductive region; A third silicon-germanium layer is provided on the oxide layer located in the P-type conductive type region, and a first silicon layer is provided on the oxide layer located in the N-type conductive type region; the first silicon layer is a tensile-strained silicon layer; the germanium content of the third silicon-germanium layer is greater than 50%.
9. The FDSOI wafer according to claim 8, wherein, The germanium content of the third silicon-germanium layer is 60%-70%.
10. The FDSOI wafer according to claim 8, wherein, The third silicon-germanium layer is a compressive-strained silicon-germanium layer.