Semiconductor packaging structure and forming method thereof

Abstract

A method of forming a semiconductor package structure includes forming an integrated circuit device including a transistor formed at a top surface of a semiconductor substrate of a wafer, a front-side interconnect structure formed over and connected to the integrated circuit device, and a back-side interconnect structure formed over and connected to the front-side interconnect structure. An electrical connector is formed over and connected to the front-side interconnect structure, a back-side grinding process is performed to thin the semiconductor substrate, and a back-side interconnect structure is formed on the back side of the integrated circuit device. The backside interconnect structure includes a power transfer network and is configured to receive the positive supply voltage from the electrical connector and redistribute the positive supply voltage to the integrated circuit device.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor package structure and a method of forming the same. Background Art

[0002] A power delivery network (PDN) is formed in a device die for delivering power to an integrated circuit. The PDN is used to provide a positive power supply voltage (VDD) and electrical ground to individual devices such as transistors. Summary of the Invention

[0003] According to one aspect of embodiments of the present application, a method of forming a semiconductor package structure is provided, including: forming an integrated circuit device including a first transistor, wherein the first transistor is formed at a top surface of a semiconductor substrate of a wafer; forming a front-side interconnect structure located above the integrated circuit device and connected to the integrated circuit device; forming a first electrical connector located above the front-side interconnect structure and connected to the front-side interconnect structure; performing a backside grinding process to thin the semiconductor substrate; and forming a backside interconnect structure on a backside of the integrated circuit device, wherein the backside interconnect structure includes a power delivery network, and the power delivery network is configured to receive a positive power supply voltage from the first electrical connector and redistribute the positive power supply voltage to the integrated circuit device.

[0004] According to another aspect of embodiments of the present application, a semiconductor package structure is provided, including: a device die including: a plurality of integrated circuit devices; a front-side interconnect structure located above the integrated circuit devices and connected to the integrated circuit devices; an electrical connector located above the front-side interconnect structure; and a backside interconnect structure located on a backside of the integrated circuit devices, wherein the backside interconnect structure includes a power delivery network that electrically connects the electrical connector to the backside of the integrated circuit devices.

[0005] According to still another aspect of embodiments of the present application, a semiconductor package structure is provided, including: a plurality of transistors including: a first transistor including: a first source / drain region; and a second source / drain region, wherein the first transistor serves as a power switch configured to turn on or off a connection between the first source / drain region and the second source / drain region. A second transistor including: a third source / drain region; and a fourth source / drain region, wherein the second transistor is a signal transistor configured to receive a signal; the semiconductor package structure further includes: a front-side interconnect structure located on a front side of the plurality of transistors; an electrical connector located above the front-side interconnect structure, wherein the electrical connector is electrically connected to the first source / drain region; and a backside interconnect structure located on a backside of the plurality of transistors, wherein the backside interconnect structure electrically connects the second source / drain region to the third source / drain region. Description of the Drawings

[0006] As will be best understood in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0007] Figures 1-8 A cross-sectional view of an intermediate stage in the formation of a device die including a power transmission network according to some embodiments is shown.

[0008] Figure 9 A perspective view of a device die including a backside power transmission network and a frontside power input according to some embodiments is shown.

[0009] Figure 10 A perspective view of a transistor for delivering power from the front side to the back side of a device die according to some embodiments is shown.

[0010] Figure 11 A package including a device die that includes a power transmission network according to some embodiments is shown.

[0011] Figure 12 A process flow for forming a device die according to some embodiments is shown. Detailed Description

[0012] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are formed in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations being discussed.

[0013] Furthermore, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to encompass different orientations of the device during use or operation. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0014] A device die including a dorsal power transmission network and a ventral power input, and a method of forming the same are provided. According to some embodiments of the present disclosure, a device die is formed that includes an electrical connector for receiving power located on the ventral side of the device die. Power supplies (VDD and VSS) are conducted to the dorsal side of the device die and distributed from the dorsal side of the device die to the devices. By forming the electrical connector on the ventral side and the power transmission network on the dorsal side, heat dissipation can be improved, and power can be delivered with a smaller voltage drop. It should be understood that although a gate-all-around (GAA) transistor is used as an example to explain the concepts of the present disclosure, other types of transistors, such as planar transistors, fin field-effect transistors (FinFETs), etc., may also be employed.

[0015] The embodiments discussed herein are intended to provide examples to enable the making or use of the subject matter of the present disclosure, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the scope contemplated by the various embodiments. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0016] Figures 1 to 8 A cross-sectional view of an intermediate stage in the formation of a device die according to some embodiments of the present disclosure is shown. The corresponding process is also schematically reflected in Figure 12 the process flow shown.

[0017] Figure 1 A cross-sectional view of the formation of a wafer 20 is shown. As Figure 12 shown, in process flow 200, the corresponding process is shown as process 202. According to some embodiments, wafer 20 is or includes a device wafer that includes active devices and possibly passive devices, which are represented as integrated circuit devices 24. A plurality of chips / dies 20' may be included in wafer 20, and one of the chips 20' is shown.

[0018] According to some embodiments, wafer 20 includes a semiconductor substrate 22. The semiconductor substrate 22 may be formed of or include crystalline silicon, crystalline germanium, silicon germanium, carbon-doped silicon, or a III-V compound semiconductor (such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc.). Shallow trench isolation (STI) regions (not shown) may be formed in the semiconductor substrate 22 to isolate the active regions within the semiconductor substrate 22.

[0019] According to some embodiments, integrated circuit devices are formed on the top surface of a semiconductor substrate 22 and are collectively referred to as front-end-of-line (FEOL) structures / devices. According to some embodiments, the integrated circuit devices may include complementary transistors, resistors, capacitors, diodes, etc. The integrated circuit devices include transistors 24A, 24B, and 24C, and are represented by them. Depending on the context, these transistors are collectively referred to as integrated circuit devices 24 or transistors 24.

[0020] According to some embodiments, the integrated circuit device 24 includes transistors 24A, 24B, and 24C. Transistor 24A is a pseudo-transistor for conducting power from the front side to the back side of the integrated circuit 24, and its source / drain regions 26A and 28A are interconnected. Transistor 24B has two functions. First, transistor 24B is a power switch, and the power supply at the source / drain region 26B can be conducted to the source / drain region 28B at a specific time and not conducted to the source / drain region 28B at other times. Second, transistor 24B serves as a power path for conducting power from the front side to the back side of the integrated circuit device 24. The operation of transistor 24B is controlled by a signal on the gate electrode 46B to control whether power is connected to the back side of the integrated circuit device 24 through transistor 24B.

[0021] According to some embodiments, transistors 24A, 24B, and 24C include gate-all-around (GAA) transistors. According to alternative embodiments, transistors 24A, 24B, and 24C can be formed by planar transistors, fin field-effect transistors (FinFETs), complementary field-effect transistors, etc. In the illustrated example, GAA transistors are employed. The structure of transistor 24A is discussed in detail below as an example, and other transistors may have a similar structure.

[0022] According to some embodiments, transistor 24A includes a channel region 30A that may include semiconductor nanostructures and a gate stack 47A surrounding the channel region 30A. Source / drain regions 26A and 28A are connected to opposite ends of the channel region 30A. The source / drain regions may refer to the source or the drain individually or collectively, depending on the context.

[0023] The gate stack 47A includes a gate dielectric 44A and a gate electrode 46A. The gate dielectric 44A may include an interface layer such as a silicon oxide layer and a high-k dielectric layer on the interface layer. The gate electrode 46A includes multiple layers, which may include a work function layer, a fill metal layer, and possibly other layers, such as a capping layer below the work function layer and a barrier layer above the work function layer. When transistor 24A is a p-type transistor, the work function layer may have a p-type work function material (e.g., a work function higher than about 4.6 eV), or when transistor 24A is an n-type transistor, it may have an n-type work function material (e.g., a work function lower than about 4.6 eV).

[0024] According to some embodiments, the source / drain regions 26A and 28A may include a semiconductor material. When the corresponding transistor 24A is a p-type transistor, the source / drain regions 26A and 28A may include a semiconductor such as silicon, silicon germanium, etc. A p-type dopant such as boron, indium, etc. may be doped. When the corresponding transistor 24A is an n-type transistor, the source / drain regions 26A and 28A may include a semiconductor such as silicon, carbon-doped silicon, etc. An n-type dopant such as phosphorus, arsenic, antimony, etc. may be doped.

[0025] A silicide layer 34 is formed at the top surface of the source / drain regions 26A and 28A. A contact etch stop layer (CESL) 40 and an ILD 42 are formed over the source / drain regions 26A and 28A. According to some embodiments, the CESL 40 is formed of SiN, SiOC, etc. The ILD 42 is formed of silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), etc. The ILD 42 may be formed using spin coating, flowable chemical vapor deposition (FCVD), etc. According to alternative embodiments, the ILD 42 may also be formed using a deposition method such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), etc.

[0026] Source / drain contact plugs 36A1 and 36A2 are formed above the silicide layer 34 and contact the silicide layer 34, and penetrate the CESL 40 and the ILD 42. According to some embodiments, the contact plugs 36A1 and 36A2 are formed of or include a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys, and / or multilayers thereof. The formation of the contact plugs 36A1 and 36A2 may include forming contact openings in the ILD 42, filling the contact openings with a conductive material, and performing a planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process to make the contact plugs 36A1 and 36A2 flush with the top surface of the ILD 42.

[0027] The transistors 24B and 24C may be formed in the same process (or a different process) as the formation of the transistor 24A. Each of the transistors 24B and 24C may also have the same conductive type as the transistor 24A or an opposite conductive type. The transistors 24B and 24C may have a structure similar to that of the transistor 24 and include components of the same type as the transistor 24A. For example, the transistors 24B and 24C also include a channel region, source / drain regions, a gate stack, a silicide layer, source / drain contact plugs, etc. Therefore, the features of the transistors 24B and 24C are not discussed in detail and can be found by referring to the discussion of the transistor 24A.

[0028] The features of transistors 24B and 24C are denoted using reference symbols similar to the corresponding features of transistor 24A, except that the component symbols of transistor 24A include the suffix "A", while the component symbols of transistors 24B and 24C include the suffixes "B" and "C", respectively. The similar features of transistors 24A, 24B, and 24C can be collectively referred to using the corresponding reference numerals without using the letters "A", "B", or "C". For example, the source / drain regions of transistor 24 (including transistors 24A, 24A, and 24C) can be collectively referred to as source / drain regions 26 and 28, and the channel regions can be collectively referred to as channel region 30. Thus, the gate dielectric, gate electrode, and gate stack of transistor 24 are collectively referred to as gate dielectric 44, gate electrode 46, gate stack 47, and source / drain contact plug 36.

[0029] According to some embodiments, conductive components 36-3 and 36-4 are also formed and can be formed in the same process as forming source / drain contact plugs 36A1, 36A2, 36B1, 36B2, 36C1, and 36C2. Conductive component 36-4 is different from conductive component 36-3 in that conductive component 36-3 has a metal wire portion and does not include any via portion under the wire portion. On the other hand, conductive component 36-4 includes a wire portion 36-4L and a via portion 36-4V. The wire portion 36-4L and the via portion 36-4V are continuously connected with no distinguishable interface therebetween and are formed by a dual-damascene process. The bottoms of source / drain contact plugs 36A1 and 36A2 can be at substantially the same level as the bottom surface of metal component 36-3 and the bottom surface of wire portion 36-4L.

[0030] Power via 48 can be formed before forming metal component 36-3, and the bottom of metal component 36-3 contacts the top surface of power via 49. Power via 48 can also be formed of a metal material, such as copper, tungsten, cobalt, titanium, titanium nitride, tantalum, tantalum nitride, nickel, etc., or a combination thereof. Via portion 36-4V can contact the top surface of the underlying dielectric material, which can be a shallow trench isolation (STI) region, ILD 42, etc.

[0031] Transistors 24A, 24B, and 24C and conductive components 36-3 and 36-4 are separated from each other by region 50. Although the details of region 50 are not shown, region 50 can include CESL, ILD, STI regions, conductive components for connecting adjacent components, etc.

[0032] Further referring Figure 1 , the front-side interconnect structure 58 is formed to include a metal layer and a dielectric layer. As Figure 12As shown, in process 200, the corresponding process is shown as process 204. The interconnect structure 58 also includes a dielectric layer 52 (also referred to as an inter-metal dielectric (IMD)), an etch stop layer (not shown), metal lines 54, and vias 56. Metal lines at the same level are hereinafter collectively referred to as metal layers. According to some embodiments, the interconnect structure 58 includes multiple metal layers (M0 to Mtop), including metal lines 54 interconnected by vias 56. The metal layers in the interconnect structure 58 can be represented as M0, M1…Mtop-1, Mtop, etc.

[0033] The metal lines 54 and vias 56 can be formed of copper or a copper alloy, or can be formed of or include other metals such as aluminum, tungsten, nickel, etc. According to some embodiments, the dielectric layer 52 includes a low-k dielectric material. For example, the dielectric constant (k value) of the low-k dielectric material can be lower than about 3.5 or lower than about 3.0. The dielectric layer 52 can include a carbon-containing low-k dielectric material (such as SiOCN), hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. The etch stop layer can be formed of or include alumina, aluminum nitride, SiOC, SiON, etc., or multiple layers thereof. Forming the metal lines 54 and vias 56 in the dielectric layer 52 can include a single damascene process and / or a dual damascene process.

[0034] According to some embodiments, the total number of metal layers M0 to Mtop can be greater than about 9 and can be in the range of about 9 to 16. According to some embodiments, the top metal layer Mtop is formed in the top dielectric layer of the dielectric layer 52. As described above, the top dielectric layer can be formed of or include a low-k dielectric material. Alternatively, the top dielectric layer can be formed of or include a non-low-k dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon oxynitride, silicon nitride, etc., or multiple layers thereof.

[0035] Then, a dielectric layer 60 is formed on the interconnect structure 58. As Figure 12 shown, in process 200, the corresponding process is shown as process 206. The dielectric layer 60 can include dielectric layers 60A, 60B, and 60C. According to some embodiments, the dielectric layer 60A includes USG, the dielectric layer 60B includes silicon nitride, and the dielectric layer 60C includes silicon oxide (e.g., formed by high-density plasma (HDP) chemical vapor deposition (CVD)), and other dielectric materials can also be used.

[0036] Referring to Figure 2 , a carrier 62 is attached to the front side of the wafer 20. As Figure 12As shown, in process 200, the corresponding process is shown as process 208. According to some embodiments, the carrier 62 can be a blank wafer. The blank wafer can be a blank silicon wafer. The bonding layer 64 according to these embodiments can be used to bond the silicon wafer to the wafer 20. According to some embodiments, the bonding layer 64 can be formed of a silicon-containing dielectric material, such as SiO, SiC, SiOC, SiON, SiOCN, etc.

[0037] According to an alternative embodiment, the carrier 62 includes a glass carrier, which can be attached to the wafer 20 through an adhesive 64. The adhesive 64 can be a light-to-thermal conversion (LTHC) material, which is configured to decompose under the heat of light (such as a laser beam).

[0038] Figure 3 The backside thinning of the semiconductor substrate 22 according to some embodiments is shown. As Figure 12 shown, in process 200, the corresponding process is shown as process 210. The backside thinning process can be performed by a CMP process, a mechanical grinding process, etc. According to some embodiments, as Figure 3 shown, the semiconductor substrate 22 ( Figure 2 ) is completely removed, and the bottom surfaces of the source / drain regions 26 and 28 of the transistor 24 are exposed. The gate dielectric 44 can be used as a stop layer to perform the backside thinning process. Alternatively, other components such as the source / drain regions 26 and 28 or the power vias 48 can be used as the stop layer. The bottom surface of the power via 48 may also be exposed.

[0039] According to an alternative embodiment, the backside thinning process can be performed while leaving a thin layer of the semiconductor substrate 22. For example, as Figure 2 shown, the portion 22' can be retained without being removed. According to these embodiments, subsequently formed conductive components (such as vias) penetrate the remaining semiconductor substrate 22. A dielectric isolation layer is also formed to surround the conductive components, thereby electrically insulating the conductive components from the remaining semiconductor substrate portion 22' (if any).

[0040] In addition, a feedthrough via (FTV) 49 is formed from the backside of the wafer 20 to be electrically connected to the conductive component 36-4. As Figure 12 shown, in process 200, the corresponding process is shown as process 212. The forming process can include etching the dielectric layer in the region 50 to form an opening, filling the opening with a conductive material, and performing a planarization process, such as a CMP process or a mechanical grinding process. The etched portion of the region 50 can be a part of the STI region or a part of the CESL 40 and the ILD 42. The FTV 49 lands on the bottom surface of the via portion 36-4V, which serves as an etch stop layer in the etching process.

[0041] Figure 4shows the formation of a backside silicide layer 66 on the bottom surfaces of the source / drain regions 26 and 28. As Figure 12 shown, in process flow 200, the corresponding process is shown as process 214. According to some embodiments, a metal such as titanium, cobalt, etc. is deposited on the backside of the wafer 20. Then an annealing process is performed to react the metal layer with the bottom surface portions of the source / drain regions 26 and 28 to form the metal silicide layer 66. Then the unreacted portions of the metal layer are removed in an etching process. The formation order of the FTV 49 and the backside silicide layer 66 can be reversed.

[0042] Referring Figure 5 to Figure 12 shows the formation of a backside redistribution structure 70. As Figure 12 shown, in process flow 200, the corresponding process is shown as process 216. The backside redistribution structure 70 includes a dielectric layer 72 and redistribution lines (RDLs) 74 formed in the dielectric layer 72. The dielectric layer 72 can be formed of an organic dielectric material such as polyimide, PBO, BCB, etc. or an inorganic dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, USG, etc.

[0043] The RDLs 74 can be formed of or include materials such as aluminum, copper, nickel, tungsten, titanium, etc. According to some embodiments, forming a layer of RDLs 74 can include forming the dielectric layer 72, etching the corresponding dielectric layer 72 to form openings, plating a metal seed layer extending into the openings, forming a patterned plating mask where some portions of the metal seed are exposed, and plating to form the RDLs 74. According to alternative embodiments, the RDLs 74 can be formed by a damascene process.

[0044] The RDLs 74 are formed to electrically connect the power supply voltages (including VDD and VSS (electrical ground)) to the backside power delivery network (PDN) (hereinafter also referred to as the backside PDN 74) of the integrated circuit device 24. For example, the RDLs 74 electrically connect the power from the source / drain regions 26A, 28A, and 28B to the signal transistors in the integrated circuit device 24, which are represented by the transistor 24C.

[0045] According to some embodiments, the RDLs 74 conduct the power supply voltages to the silicide layer 66 of the signal transistors 24C such that the source / drain regions of the transistors 24 to be connected to the power supply (VDD or VSS) can receive power from the bottom sides of the corresponding source / drain regions 26 and 28. The illustrated RDLs 74 represent the routing of the VDD wiring and the VSS wiring. It should also be understood that the RDLs 74 are schematically shown and more details of the power delivery scheme are discussed in the subsequent paragraphs.

[0046] After forming the dorsal interconnect structure 70, a bonding layer 76 is formed. The bonding layer 76 can be used to prevent moisture from reaching the dorsal RDL 74 and can also be used for bonding to a carrier. According to some embodiments, the bonding layer 76 can be formed of a silicon-containing dielectric material such as SiO, SiC, SiOC, SiON, SiOCN, etc.

[0047] Reference Figure 6 , the carrier 78 is bonded to the wafer 20 through the bonding layers 76 and 80. As Figure 12 shown, in process 200, the corresponding process is shown as process 218. According to some embodiments, the carrier 78 can be a support substrate, and according to some embodiments, the support substrate can be a blank silicon substrate. The support substrate can be formed of a uniform material such as silicon, and there are no other materials in the support substrate except the uniform material. A bonding layer 80 is formed on the carrier 78 to bond the carrier 78 to the bonding layer 76. The bonding layer 80 can include a silicon-containing dielectric material such as SiO, SiC, SiOC, SiON, SiOCN, etc. The bonding can include fusion bonding.

[0048] In a subsequent process, the carrier 62 is detached. As Figure 12 shown, in process 200, the corresponding process is shown as process 220. When the carrier 62 is a glass carrier adhered to the underlying structure by LTHC, a laser beam can be used to decompose the LTHC, thereby detaching the carrier 62. When the carrier 62 is a silicon wafer bonded to the wafer 20 by fusion bonding, the carrier 62 can be removed, for example, in a CMP process, a mechanical grinding process, an etching process, and / or a process including implantation and annealing. The resulting structure is as Figure 7 shown, where the dielectric layer 60 is exposed.

[0049] Next, as Figure 8 shown, metal pads 82 and vias 84 are formed. As Figure 12 shown, in process 200, the corresponding process is shown as process 222. According to some embodiments, the vias 84 are formed in the dielectric layers 60B and 60A, and the metal pads 82 are formed in the dielectric layer 60C. The formation process can include a dual-damascene process, where via openings are formed in the dielectric layers 60B and 60A, and trenches are formed in the dielectric layer 60C. Conductive material can be filled into the via openings and trenches, and then a planarization process is performed to remove the excess conductive material.

[0050] Further reference Figure 8 , an electrical connector 86 (including a power electrical connector 86A and a signal electrical connector 86B) is formed. As Figure 12As shown, in process 200, the corresponding process is shown as process 224. According to some embodiments, the electrical connector 86 includes a solder region, which can be formed by plating solder balls on the metal pads 82 and reflowing the solder balls. According to alternative embodiments, the electrical connector 86 includes a non-reflowable (non-solder) metallic material. For example, the electrical connector 86 can be formed as a copper pillar and may or may not include a nickel capping layer. Some of the electrical connectors 86 are shown as dashed lines to indicate that these electrical connectors 86 may or may not be formed.

[0051] Then, the structure in Figure 8 is divided into a plurality of identical packages 110 by a sawing process. As Figure 12 shown, in process 200, the corresponding process is shown as process 226. According to some embodiments, when the carrier 78 is a silicon support substrate and is bonded to the wafer 20 by fusion bonding, the carrier 78 can remain on the wafer 20 during dicing. Thus, the separated device die 20' is attached to the sawed piece 78' of the carrier 78 (referred to as the support substrate 78'). When the device die 20' is powered on, the support substrate 78' can assist in heat dissipation in the final package.

[0052] Figure 9 A perspective view of a wafer 20 (and device die 20') according to some embodiments is shown. The electrical connector 86A receives a power supply voltage and conducts the power supply voltages VDD and VSS to the lower metal lines in the metal layers M0 to Mtop. The power supply voltage can be conducted to the backside RDL 74, which redistributes the power to integrated circuit devices such as transistors.

[0053] The transistor 24B serves as a power switch for gating the power supply. Figure 9 Also shown is a signal electrical connector 86B for receiving signals and conducting the signals to the transistor 24C for further processing.

[0054] Figure 10 A perspective view of a portion of a device die 20' according to some embodiments is shown. The shown portion includes a transistor 24A or 24B, which includes a channel (semiconductor nanostructure) 30A or 30B, and a gate electrode 46 surrounding the channel 30. The via 74 is part of the RDL 74 and is connected to the backside of the source / drain region 26 for conducting power from the front side of the transistor 24A / 24B to the backside.

[0055] Figure 11 A package 102 including a device die 20' according to some embodiments is shown. The device die 20' is bonded to a package assembly 90. The package assembly 90 can be a silicon interposer, an organic interposer, a package substrate, a printed circuit board, a package, etc. The power supplies VDD and VSS can be provided to the electrical connector 91 of the package assembly 90 and conducted to the electrical connector 86A of the device die.

[0056] According to some embodiments, Figure 11 A power chip 95 engaged with a package component 90 is schematically shown. The power chip 95 can be used to convert power from a high power supply voltage such as 12V, 3.3V to a low power supply voltage such as 1.2V and / or 0.9V, and conduct the lower power supply voltage to an electrical connector 86A through a conductive path 93. The power can be gated by a transistor 24B, and a gated power supply VDD and a non-gated power supply are provided to some integrated circuits. The non-gated power supply can be conducted to the backside PDN through a pseudo-transistor 24A( Figure 8 ) and conductive components 36-3 and 36-4.

[0057] According to some embodiments, a heat sink 94 is attached to the package component 90 by an adhesive 92. The heat sink 94 can also be attached to the device die 20' through a thermal interface material 96, which further adheres to a support substrate 78'.

[0058] Return reference Figure 8 , the power supply voltages received from the electrical connectors 86A, 86C, and 86D are conducted to metal wires 54 and vias 56, and then conducted to the backside of a transistor 24C (one transistor 24C is shown) through transistors 24A and 24B. The power supply voltages can also be conducted to the backside of the transistor 24C through a first conductive path including conductive components 36-3 and a power via 48 and a second conductive path including conductive components 36-4 and an FTV 49.

[0059] According to some embodiments, the transistor 24A is a pseudo-transistor, whose source / drain regions 26A and 28A are connected to each other and connected in parallel to conduct power. The gate stack 47A of the pseudo-transistor 24A can be electrically floating. For example, the entire top surface of the pseudo-transistor 24A can be in physical contact with a dielectric material such as a dielectric layer 52.

[0060] On the other hand, transistor 24B can be an active transistor used as a power switch. For example, the source / drain regions 26B of transistor 24B are connected to a power supply node (VDD or VSS). Transistor 24B is also referred to as a gated transistor (power switch), which is configured to receive power (e.g., true VDD (TVDD)) at the source / drain regions 26B. According to the signal received at the gate electrode 46B of transistor 24B, transistor 24B can conduct the TVDD voltage to the source / drain region 28B, which is referred to as pseudo VDD (VVDD), or can cut off the conduction so that power is not conducted to some (but not all) parts of the backside PDN 74. According to some embodiments, on the front side of the source / drain region 28B, a silicide layer may not be formed, and a source / drain contact plug may not be formed. According to these embodiments, the entire top surface of the source / drain region 28B can be in contact with a dielectric component such as CESL 40.

[0061] Transistor 24C can be an active transistor and is not used to conduct power from the front side to the backside PDN 74. Power can be connected to the backside of the source / drain region 26C from the backside PDN 74. According to some embodiments, on the front side of the source / drain region 26C, a silicide layer may not be formed, and a source / drain contact plug may not be formed. The entire top surface of the source / drain region 26C can be in contact with a dielectric component such as CESL 40. According to an alternative embodiment, the power supply voltage provided to the source / drain region 26C from the backside can be further conducted to the front side of transistor 24, for example, to a nearby transistor or other device. Therefore, the corresponding silicide layer 34 and source / drain contact plug 36C1 are shown as dashed lines to indicate that these features may or may not be formed.

[0062] According to some embodiments, transistor 24C inputs or outputs signals, for example, through the source / drain region 28C and the source / drain contact plug 36C2. According to some embodiments, the source / drain region 28C can be connected to the electrical connector 86B.

[0063] Since the gate of the active transistor is on the front side, power or signals are connected to the gate of the active transistor (such as 24C) from the front side. Power is also received from the electrical connectors 86A, 86C, and 86D. Since most of the power is routed to the backside of the transistor, the front-side power routing can be reduced. For example, only the metal layers M0 and M1 are used for routing the lateral power to the transistor, while the upper metal layers are not used for lateral power routing. This releases some front-side chip area for signal routing.

[0064] According to some embodiments, throughout the device die 20’, no signal is conducted to the back side of the transistor, and the back side is only used for power conduction. Moving the power wiring to the back side can avoid competition between power wiring and signal wiring. The signal wiring on the front side is easier. The power supply line on the back side can be formed wider. This results in a reduced voltage drop.

[0065] The conduction paths including the conductive component 36-3 and the power via 48, and the conduction path including the conductive component 36-4 and the FTV 49 can also be used for power conduction. According to some embodiments, the conductive components 36-3 and 36-4 receive power from the electrical connectors 86C and 86D respectively. According to alternative embodiments, the connectors 86C and 86D are not formed, but the conductive components 36-3 and 36-4 receive power from the electrical connector 86A (as well as the transistors 24A and 24B).

[0066] The electrical connector 86B can be used to receive / output signals. The electrical connector 86B can be directly connected to the transistor 24C, or provide signals to other circuits that ultimately provide signals to the transistor 24C.

[0067] Embodiments of the present disclosure have some advantageous features. By receiving power and signals from the front side of the device die, the back side of the device die can be connected to the carrier, which helps with heat dissipation. In addition, by moving the power wiring to the back side of the device die, since there is no signal wiring on the back side, there is more space for power wiring, the power supply line can be made wider, and the voltage drop is smaller.

[0068] According to some embodiments of the present disclosure, a method of forming a semiconductor package structure includes: forming an integrated circuit device including a first transistor, wherein the first transistor is formed at the top surface of a semiconductor substrate of a wafer; forming a front-side interconnect structure located above the integrated circuit device and connected to the front side of the integrated circuit device; forming a first electrical connector located above the front-side interconnect structure and connected to the front-side interconnect structure; performing a backside grinding process to thin the semiconductor substrate; and forming a backside interconnect structure on the back side of the integrated circuit device, wherein the backside interconnect structure includes a power transmission network, and the power transmission network is configured to receive a positive power supply voltage from the first electrical connector and redistribute the positive power supply voltage to the integrated circuit device.

[0069] In one embodiment, the method further includes: bonding a blanket carrier to a wafer, wherein the blanket carrier is located on the back side of the integrated circuit device; and sawing the wafer and the blanket carrier into a plurality of packages. In one embodiment, the method further includes: bonding the front side of one of the plurality of packages to a package assembly; and attaching a heat sink to a piece of the blanket carrier in one of the plurality of packages. In one embodiment, the method further includes: epitaxially growing an epitaxial semiconductor region, wherein a power transmission network is electrically connected to a first electrical connector through the epitaxial semiconductor region.

[0070] In one embodiment, the epitaxial semiconductor region is a source / drain region of a transistor in the integrated circuit device. In one embodiment, the transistor is a power switch including a gate and an additional source / drain region, and wherein the power switch is configured to turn on or off the connection between the source / drain region and the additional source / drain region. In one embodiment, the transistor is a dummy transistor, the dummy transistor further includes a gate and an additional source / drain region, and wherein the power transmission network is electrically connected to the first electrical connector through the source / drain region and the additional source / drain region.

[0071] In one embodiment, the method further includes: forming a metal component that connects the first electrical connector to the power transmission network. In one embodiment, the method further includes: forming a second electrical connector located above and connected to the front-side interconnect structure, wherein the second electrical connector is a signal node. In one embodiment, the method further includes: forming an additional source / drain region; and forming a source / drain silicide layer on the back side of the additional source / drain region, wherein the power transmission network is connected to the additional source / drain region through the source / drain silicide layer.

[0072] According to some embodiments of the present disclosure, a semiconductor package structure includes a device die, the device die including: a plurality of integrated circuit devices; a front-side interconnect structure located above and connected to the integrated circuit devices; an electrical connector located above the front-side interconnect structure; and a back-side interconnect structure located on the back side of the integrated circuit devices, wherein the back-side interconnect structure includes a power transmission network that electrically connects the electrical connector to the back side of the integrated circuit devices.

[0073] In one embodiment, the semiconductor package structure further includes a transistor, the transistor including a first source / drain region, wherein the first source / drain region electrically connects an electrical connector to a power transmission network. In one embodiment, the transistor further includes a second source / drain region, wherein the transistor is configured to turn on or off the connection from the first source / drain region to the second source / drain region in response to a signal on the gate of the transistor. In some embodiments, the transistor further includes a second source / drain region that is electrically shorted to the first source / drain region, wherein the second source / drain region also electrically connects the electrical connector to the power transmission network.

[0074] In one embodiment, the semiconductor package structure further includes a signal transistor, the signal transistor including: a source / drain region; and a source / drain silicide layer located on the back side of the source / drain region, wherein the power transmission network is electrically connected to the source / drain region through the source / drain silicide layer. In one embodiment, the semiconductor package structure further includes a carrier bonded to the back side of the device die. In one embodiment, the semiconductor package structure further includes a heat sink attached to the carrier.

[0075] According to some embodiments of the present disclosure, a semiconductor package structure includes a plurality of transistors, wherein a first transistor includes a first source / drain region; and a second source / drain region, wherein the first transistor serves as a power switch configured to turn on or off the connection between the first source / drain region and the second source / drain region; a second transistor including a third source / drain region; and a fourth source / drain region, wherein the second transistor is a signal transistor configured to receive a signal; a front-side interconnect structure located on the front side of the plurality of transistors; an electrical connector located above the front-side interconnect structure, wherein the electrical connector is electrically connected to the first source / drain region; and a back-side interconnect structure located on the back side of the plurality of transistors, wherein the back-side interconnect structure electrically connects the second source / drain region to the third source / drain region.

[0076] In one embodiment, the semiconductor package structure further includes: a first silicide layer located on the back side of the second source / drain region; and a second silicide layer located on the back side of the third source / drain region, wherein the back-side interconnect structure electrically connects the second source / drain region to the third source / drain region through the first silicide layer and the second silicide layer. In one embodiment, the first transistor is configured to transfer the power received from the electrical connector into the first source / drain region and transfer the power from the second source / drain region to the back-side interconnect structure.

[0077] The foregoing has outlined the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages as those introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations therein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a semiconductor package structure, comprising: Forming an integrated circuit device including a first transistor, wherein the first transistor is formed at a top surface of a semiconductor substrate of a wafer; Forming a front-side interconnect structure located above the integrated circuit device and connected to the integrated circuit device; Forming a first electrical connector located above the front-side interconnect structure and connected to the front-side interconnect structure; Performing a backside grinding process to thin the semiconductor substrate; and Forming a backside interconnect structure on a backside of the integrated circuit device, wherein the backside interconnect structure includes a power transmission network, and the power transmission network is configured to receive a positive power supply voltage from the first electrical connector and redistribute the positive power supply voltage to the integrated circuit device.

2. The method according to claim 1, further comprising: Bonding a blanket carrier to the wafer, wherein the blanket carrier is located on the backside of the integrated circuit device; and Sawing the wafer and the blanket carrier into a plurality of packages.

3. The method according to claim 2, further comprising: Bonding a front side of one of the plurality of packages to a package assembly; And Attaching a heat sink to a piece of the blanket carrier in one of the plurality of packages.

4. The method according to claim 1 further includes epitaxially growing an epitaxial semiconductor region, wherein, The power transmission network is electrically connected to the first electrical connector through the epitaxial semiconductor region.

5. The method according to claim 4, wherein, The epitaxial semiconductor region is a source / drain region of a transistor in the integrated circuit device.

6. The method according to claim 5, wherein, The transistor is a power switch including a gate and additional source / drain regions, and wherein the power switch is configured to turn on or off a connection between the source / drain region and the additional source / drain region.

7. The method according to claim 5, wherein The transistor is a pseudo-transistor, the pseudo-transistor further includes a gate and additional source / drain regions, and wherein the power transmission network is electrically connected to the first electrical connector through the source / drain region and the additional source / drain region.

8. A semiconductor package structure, comprising: A device die, the device die including: A plurality of integrated circuit devices; A front-side interconnect structure located above the integrated circuit devices and connected to the integrated circuit devices; An electrical connector located above the front-side interconnect structure; and A backside interconnect structure located on a backside of the integrated circuit devices, wherein the backside interconnect structure includes a power transmission network that electrically connects the electrical connector to a backside of the integrated circuit devices.

9. A semiconductor package structure, comprising: A plurality of transistors, including: A first transistor, including: A first source / drain region; and A second source / drain region, wherein the first transistor is used as a power switch, and the power switch is configured to turn on or off a connection between the first source / drain region and the second source / drain region; A second transistor, including: A third source / drain region; and A fourth source / drain region, wherein the second transistor is a signal transistor configured to receive a signal; A front-side interconnect structure located on a front side of the plurality of transistors; An electrical connector is located above the front-side interconnect structure, wherein the electrical connector is electrically connected to the first source / drain region; and A back-side interconnect structure is located on the back side of the plurality of transistors, wherein the back-side interconnect structure electrically connects the second source / drain region to the third source / drain region.

10. The semiconductor package structure according to claim 9, further comprising: A first silicide layer is located on the back side of the second source / drain region; And A second silicide layer is located on the back side of the third source / drain region, wherein the back-side interconnect structure electrically connects the second source / drain region to the third source / drain region through the first silicide layer and the second silicide layer.

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