Manufacturing method of semiconductor structure
By forming an isolation layer in the cut path area of the semiconductor structure to cover the surface of the dielectric structure, the problem of conductive layer pollution caused by diffusion of dielectric structure components is solved, and effective pollution protection is achieved.
Patent Information
- Application Number
- CN202410162009.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-01-24
- Filing Date
- 2024-02-05
- Publication Date
- 2025-07-25
AI Technical Summary
In the cut path region of the semiconductor structure, components of the dielectric structure tend to diffuse into the air during storage, resulting in contamination of the topmost conductive layer.
A protective layer is formed on the dielectric structure, and an isolation layer is formed in the scribed grooves in the cutting path area. A U-shaped isolation layer is formed through a dry etching process to cover the exposed dielectric structure surface to prevent components from diffusion.
It effectively prevents the diffusing of components in the dielectric structure into the air and protects the top conductive layer from contamination.
Smart Images
Figure CN120376513A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a semiconductor structure, and more particularly to a method for manufacturing a semiconductor structure including dicing trenches. Background Art
[0002] After some semiconductor structures are fabricated, the dielectric structure exposed by the dicing trenches in the scribe line region is exposed to air. During the period when the semiconductor structure is stored in a warehouse waiting for further processing by a packaging and testing factory, the components in the dielectric structure (e.g., fluorine (F)) may diffuse into the air and contaminate the topmost conductive layer (e.g., pad) exposed to the air. However, how to prevent the topmost conductive layer from being contaminated is an ongoing goal. Summary of the Invention
[0003] The present invention provides a method for manufacturing a semiconductor structure, which can effectively prevent the topmost conductive layer from being contaminated.
[0004] The present invention proposes a method for manufacturing a semiconductor structure, including the following steps. Provide a substrate. The substrate includes a scribe line region and a device region. Form a dielectric structure on the substrate. Form an interconnect structure in the dielectric structure of the device region. The interconnect structure includes a plurality of conductive layers. Form a protective layer on the dielectric structure. Pattern the protective layer and the dielectric structure to form dicing trenches in the dielectric structure of the scribe line region and openings in the dielectric structure of the device region. The openings expose the topmost conductive layer. Form an isolation material layer in the dicing trenches, the openings, and on the protective layer. Form a photoresist layer on the isolation material layer in the dicing trenches. After forming the photoresist layer, perform a first etching process on the isolation material layer to form a first isolation layer in the dicing trenches and a second isolation layer in the openings. The first isolation layer covers the surface of the dielectric structure exposed by the dicing trenches. Remove the photoresist layer.
[0005] According to an embodiment of the present invention, in the above method for manufacturing a semiconductor structure, the conductive layer may include a metal layer.
[0006] According to an embodiment of the present invention, in the above method for manufacturing a semiconductor structure, the interconnect structure may further include a plurality of plugs. The plurality of plugs may be connected to the plurality of conductive layers.
[0007] According to an embodiment of the present invention, in the above method for manufacturing a semiconductor structure, the top surface of the photoresist layer may be lower than the bottom surface of the protective layer.
[0008] According to an embodiment of the present invention, in the above method for manufacturing a semiconductor structure, the first etching process is, for example, a dry etching process.
[0009] According to an embodiment of the present invention, in the method for manufacturing the above semiconductor structure, the method for forming the photoresist layer may include the following steps. A photoresist material layer is formed on the isolation material layer. The photoresist material layer may fill the dicing grooves and openings. A second etching process is performed on the photoresist material layer to completely remove the photoresist material layer located in the openings and partially remove the photoresist material layer located in the dicing grooves to form the photoresist layer.
[0010] According to an embodiment of the present invention, in the method for manufacturing the above semiconductor structure, the method for forming the photoresist material layer is, for example, spin coating.
[0011] According to an embodiment of the present invention, in the method for manufacturing the above semiconductor structure, the second etching process is, for example, a dry etching process.
[0012] According to an embodiment of the present invention, in the method for manufacturing the above semiconductor structure, the cross-sectional shape of the first isolation layer may include a U shape.
[0013] According to an embodiment of the present invention, in the method for manufacturing the above semiconductor structure, the second isolation layer may expose the topmost conductive layer.
[0014] Based on the above, in the method for manufacturing the semiconductor structure proposed by the present invention, since the first isolation layer covers the surface of the dielectric structure exposed by the dicing grooves, the components in the dielectric structure exposed by the dicing grooves can be effectively prevented from diffusing into the air, thereby effectively preventing the topmost conductive layer from being contaminated.
[0015] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are given below and are described in detail in conjunction with the accompanying drawings as follows. Brief Description of the Drawings
[0016] Figures 1A to 1G It is a manufacturing process sectional view of the semiconductor structure of some embodiments of the present invention.
[0017] Symbol Description
[0018] 10: Semiconductor structure
[0019] 100: Substrate
[0020] 102: Dielectric structure
[0021] 104: Interconnection structure
[0022] 106: Conductive layer
[0023] 108: Plug
[0024] 110: Protective layer
[0025] 112: Isolation material layer
[0026] 112a, 112b: Isolation layer
[0027] 114: Isolation material layer
[0028] 114a: Photoresist layer
[0029] OP1: Opening
[0030] R1: Saw street area
[0031] R2: Device area
[0032] S1: Top surface
[0033] S2: Bottom surface
[0034] T1: Dicing groove Detailed implementation manners
[0035] Examples are listed below and described in detail in conjunction with the accompanying drawings. However, the provided examples are not intended to limit the scope covered by the present invention. For ease of understanding, the same components will be denoted by the same reference numerals in the following description. In addition, the accompanying drawings are for illustrative purposes only and are not drawn to the original scale. In fact, for the sake of clarity of discussion, the dimensions of various features can be arbitrarily increased or decreased.
[0036] Figures 1A to 1G It is a manufacturing process sectional view of a semiconductor structure according to some embodiments of the present invention.
[0037] Please refer to Figure 1A , and a substrate 100 is provided. The substrate 100 includes a saw street area R1 and a device area R2. In some embodiments, the device area R2 may be an area for forming active (active) devices and / or passive (passive) devices. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. In addition, although not shown in the figure, the required semiconductor devices (such as active devices and / or passive devices) may be formed on and / or in the substrate 100, and the description thereof is omitted here.
[0038] Next, a dielectric structure 102 is formed on the substrate 100. In some embodiments, the dielectric structure 102 may be a multi-layer structure. In some embodiments, the material of the dielectric structure 102 may include fluorosilicate glass (FSG), silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the method of forming the dielectric structure 102 is, for example, chemical vapor deposition.
[0039] In addition, an interconnect structure 104 is formed in the dielectric structure 102 of the device region R2. In some embodiments, the interconnect structure 104 may be electrically connected to semiconductor devices (not shown) in the device region R2. The interconnect structure 104 includes a plurality of conductive layers 106. In some embodiments, the topmost conductive layer 106 may serve as a pad. In some embodiments, the conductive layer 106 may include a metal layer. Additionally, the interconnect structure 104 may further include a plurality of plugs 108. The plurality of plugs 108 may be connected to the plurality of conductive layers 106. In some embodiments, the material of the plugs 108 is, for example, a conductive material such as metal. Furthermore, the number of the conductive layers 106 and the number of the plugs 108 are not limited to the numbers shown in the figure. As long as the number of the conductive layers 106 and the number of the plugs 108 are plural, they fall within the scope covered by the present invention. In some embodiments, the interconnect structure 104 may be formed by an interconnect process.
[0040] Next, a protective layer 110 is formed on the dielectric structure 102. The protective layer 110 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the protective layer 110 is, for example, silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the forming method of the protective layer 110 is, for example, chemical vapor deposition.
[0041] Please refer to Figure 1B , the protective layer 110 and the dielectric structure 102 are patterned to form a dicing trench T1 in the dielectric structure 102 of the dicing street region R1, and an opening OP1 in the dielectric structure 102 of the device region R2. The dicing trench T1 may expose the surface of the dielectric structure 102 in the dicing street region R1. The opening OP1 may expose the topmost conductive layer 106. In some embodiments, the dicing trench T1 and the opening OP1 may penetrate through the protective layer 110. In some embodiments, the protective layer 110 and the dielectric structure 102 may be patterned by a photolithography process and an etching process (e.g., a dry etching process). In some embodiments, the trench T1 and the opening OP1 may be formed by the same photomask. Therefore, without adding an extra photomask, the dicing trench T1 and the opening OP1 can be formed simultaneously, thereby effectively reducing the manufacturing cost.
[0042] Please refer to Figure 1C , an isolation material layer 112 is formed in the dicing trench T1 and the opening OP1 and on the protective layer 110. The isolation material layer 112 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the isolation material layer 112 is, for example, silicon nitride, silicon oxynitride (SiON), or a combination thereof. In some embodiments, the forming method of the isolation material layer 112 is, for example, chemical vapor deposition.
[0043] Please refer to Figure 1D, a photoresist material layer 114 can be formed on the isolation material layer 112. The photoresist material layer 114 fills the scribing trench T1 and the opening OP1. In some embodiments, the method of forming the photoresist material layer 114 is, for example, spin coating.
[0044] Please refer to Figure 1E , a re-etching process can be performed on the photoresist material layer 114 to completely remove the photoresist material layer 114 in the opening OP1 and partially remove the photoresist material layer 114 in the scribing trench T1 to form a photoresist layer 114a. Thus, the photoresist layer 114a can be formed on the isolation material layer 112 in the scribing trench T1. In some embodiments, the top surface S1 of the photoresist layer 114a can be lower than the bottom surface S2 of the protective layer 110. In some embodiments, the re-etching process performed on the photoresist material layer 114 is, for example, a dry etching process.
[0045] Please refer to Figure 1F , after the photoresist layer 114a is formed, a re-etching process is performed on the isolation material layer 112 to form an isolation layer 112a in the scribing trench T1 and an isolation layer 112b in the opening OP1. The isolation layer 112a covers the surface of the dielectric structure 102 exposed by the scribing trench T1. In some embodiments, the cross-sectional shape of the isolation layer 112a can include a U shape. In some embodiments, the isolation layer 112b can expose the topmost conductive layer 106. In addition, since the isolation layer 112a covers the surface of the dielectric structure 102 exposed by the scribing trench T1, components (such as fluorine) in the dielectric structure 102 exposed by the scribing trench T1 can be effectively prevented from diffusing into the air, and thus the topmost conductive layer 106 can be effectively prevented from being contaminated. In some embodiments, the re-etching process performed on the isolation material layer 112 is, for example, a dry etching process.
[0046] Please refer to Figure 1G , the photoresist layer 114a is removed. In some embodiments, the method of removing the photoresist layer 114a is, for example, plasma ashing.
[0047] Based on the above embodiments, in the manufacturing method of the semiconductor structure 10, since the isolation layer 112a covers the surface of the dielectric structure 102 exposed by the scribing trench T1, components in the dielectric structure 102 exposed by the scribing trench T1 can be effectively prevented from diffusing into the air, and thus the topmost conductive layer 106 can be effectively prevented from being contaminated.
[0048] In summary, in the method for manufacturing the semiconductor structure of the above embodiments, since the isolation layer covers the surface of the dielectric structure exposed by the dicing trench, the components in the dielectric structure exposed by the dicing trench can be effectively prevented from diffusing into the air, thereby effectively preventing the topmost conductive layer from being contaminated.
[0049] Although the present invention is disclosed in combination with the above embodiments, it is not intended to limit the present invention. Any person of ordinary skill in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.
Claims
1. A method of manufacturing a semiconductor structure, comprising: Providing a substrate, wherein the substrate includes a dicing street region and a device region; Forming a dielectric structure on the substrate; Forming an interconnect structure in the dielectric structure of the device region, wherein the interconnect structure includes a plurality of conductive layers; Forming a protective layer on the dielectric structure; Patterning the protective layer and the dielectric structure to form a dicing trench in the dielectric structure of the dicing street region and an opening in the dielectric structure of the device region, wherein the opening exposes the topmost conductive layer; Forming an isolation material layer in the dicing trench, the opening, and on the protective layer; Forming a photoresist layer on the isolation material layer in the dicing trench; After forming the photoresist layer, performing a first etching process on the isolation material layer to form a first isolation layer in the dicing trench and a second isolation layer in the opening, wherein the first isolation layer covers the surface of the dielectric structure exposed by the dicing trench; And Removing the photoresist layer.
2. The method of manufacturing a semiconductor structure according to claim 1, wherein the conductive layer includes a metal layer.
3. The method of manufacturing a semiconductor structure according to claim 1, wherein the interconnect structure further includes: A plurality of plugs connected to the plurality of conductive layers.
4. The method of manufacturing a semiconductor structure according to claim 1, wherein the top surface of the photoresist layer is lower than the bottom surface of the protective layer.
5. The method of manufacturing a semiconductor structure according to claim 1, wherein the first etching process includes a dry etching process.
6. The method of manufacturing a semiconductor structure according to claim 1, wherein the method of forming the photoresist layer includes: Forming a photoresist material layer on the isolation material layer, wherein the photoresist material layer fills the dicing trench and the opening; And Performing a second etching process on the photoresist material layer to completely remove the photoresist material layer in the opening and partially remove the photoresist material layer in the dicing trench to form the photoresist layer.
7. The method of manufacturing a semiconductor structure according to claim 6, wherein the method of forming the photoresist material layer includes spin coating.
8. The method of manufacturing a semiconductor structure according to claim 6, wherein the second etching process includes a dry etching process.
9. The method of manufacturing a semiconductor structure according to claim 1, wherein the cross-sectional shape of the first isolation layer includes a U shape.
10. The method of manufacturing a semiconductor structure according to claim 1, wherein the second isolation layer exposes the topmost conductive layer.