Molding compound and semiconductor package having the same

Abstract

Disclosed are a molding compound and a semiconductor device having the same. The molding compound includes: a matrix; and a filler comprising filler particles. The filler particles each comprise an inner core comprising an electrically conductive or semi-conductive material and an electrically insulating cap.

Description

[0001] This application is a divisional application of the invention patent application with the application date of April 17, 2019, the title of "Molding Compound and Semiconductor Package with Molding Compound", and the application number of 201910307781.1. Technical Field

[0002] The present disclosure generally relates to molding compounds and semiconductor devices including packages having molding compounds. Background Art

[0003] A molding compound is a plastic used to encapsulate semiconductor dies, where, for example, discrete semiconductor devices or integrated circuits having multiple integrated devices are integrated. Generally, a molding compound is a synthetic material that includes a matrix material such as an epoxy resin or a silicone resin and a filler such as silica as a main component.

[0004] The molding compound can be molded and cured into a solid-shaped package. In this solid state, the encapsulated semiconductor can be protected from various potential damages and electrical insulation is provided.

[0005] A package composed of a cured molding compound can include mobile or fixed charge carriers such as ions or charged molecules as impurities. Such impurities may be initially included in the molding compound, may originate from the manufacturing process, or may diffuse into the package over time. Examples of such impurities include hydroxide ions (OH - ) or sodium ions (Na + ). During operation, some types of semiconductor dies may generate an electric field in the package. In particular, a semiconductor die in which power semiconductor devices such as diodes or transistors are integrated may generate an electric field with a high field strength in the package. Such an electric field may cause charged impurities to enter the package and accumulate at certain positions inside the package. Such accumulation of charged impurities can have a negative impact on the operation of the devices integrated in the die. Specifically, such charged impurities may reduce the voltage blocking ability of the devices and enhance the leakage current.

[0006] There is a need for a molding compound that reduces or avoids the accumulation of charged impurities in the package. Summary of the Invention

[0007] One example relates to a molding compound. The molding compound includes a matrix and a filler including filler particles, where each filler particle includes a core having a conductive or semiconductive material and an electrically insulating capping.

[0008] Another example relates to a semiconductor device having at least one semiconductor die and a molding compound of the type previously explained. Brief Description of the Drawings

[0009] Examples will be explained below with reference to the accompanying drawings. The accompanying drawings are used to illustrate certain principles, so only aspects necessary for understanding these principles are shown. The accompanying drawings are not necessarily to scale. In the accompanying drawings, the same reference numerals denote similar features.

[0010] Figure 1A and Figure 1B shows an example of a molded compound including a matrix and a filler having filler particles;

[0011] Figure 2A and Figure 2B shows a vertical cross - sectional view of a semiconductor device including a package having a molded compound and an enlarged view of details of the package;

[0012] Figure 3 schematically shows an example of filler particles having a rough surface;

[0013] Figure 4 shows a vertical cross - sectional view of a semiconductor device having a package made of a molded compound;

[0014] Figure 5 shows a vertical cross - sectional view of a semiconductor device according to another example; and

[0015] Figure 6A and Figure 6B shows an example of a semiconductor device including a plurality of semiconductor dies and a housing at least partially filled with a molded compound. Detailed Description

[0016] In the following detailed description, reference will be made to the accompanying drawings. The accompanying drawings form a part of the description and illustrate, by way of example, how the invention may be used and implemented. It should be understood that the features of the various embodiments described herein may be combined with each other unless otherwise expressly stated.

[0017] Figure 1A and Figure 1B shows an example of a molded compound. Figure 1A shows a vertical cross - sectional view of a part of the molded compound, and Figure 1B shows Figure 1A enlarged detail A of the molded compound shown in Figure 1A and Figure 1B , the molded compound includes a matrix 1 and a filler having a plurality of filler particles 2 embedded in and surrounded by the matrix 1. Referring to Figure 1B, each of the filler particles 2 (hereinafter simply referred to as particle 2) includes a core 21 and a cap 22 surrounding the core 21. The core 21 includes a conductive or semiconductive material, and the cap 22 includes an electrically insulating material.

[0018] According to one example, the molding compound includes at least 10 weight percent (wt.%) of filler, at least 30 wt.%, or at least 50 wt.% of filler. That is, at least 10%, at least 30%, or at least 50% of the weight of the molding compound is derived from the weight of the filler particles 2. In particular, the molding compound may include between at least 60 wt.% and 90 wt.% of filler.

[0019] According to one example, the matrix 1 includes an epoxy resin. Based on the molding compound including the epoxy resin, a semiconductor package can be formed by heating the molding compound to make the epoxy resin flow, introducing the molding compound into a mold, curing the molding compound, and removing the package made of the molding compound from the mold. Additionally, for the matrix 1 and the filler particles 2, the molding compound may include at least one of a catalyst that accelerates the curing of the molding compound and a release agent that facilitates the release of the cured molding compound from the mold. According to one example, each of these additional components in the molding compound is less than 3 wt.%.

[0020] Additionally, the molding compound may include electrically insulating and thermally conductive particles, for example, particles made of diamond, tungsten carbide, other carbides, aluminum nitride, silicon nitride, or electrically insulating silicon carbide (SiC). Such particles can help reduce the thermal resistance of the molding compound.

[0021] According to another example, the matrix 1 includes a silicone resin. The silicone resin-based molding compound can be cured by exposing the molding compound to air or by using a furnace process.

[0022] According to one example, the core 21 includes a semiconductor material, and the cap 22 includes a semiconductor oxide. Examples of the semiconductor material include, but are not limited to, silicon (Si) and silicon carbide (SiC). The particle 2 having a core 21 composed of silicon or silicon carbide may include a cap 22 composed of silicon oxide (SiO2). According to one example, the core 21 includes a doped semiconductor material to enhance the conductivity of the core. The doping type can be n-type or p-type. According to one example, the doping concentration is higher than 1E18 cm -3 , higher than 1E19 cm -3 , or higher than 1E21 cm -3 .

[0023] According to one example, the "electrically insulating silicon carbide" particles that can be used as the electrically insulating and thermally conductive particles mentioned above are undoped or have a doping concentration lower than 1E14 cm-3 SiC particles with a doping concentration of

[0024] According to another example, the core 21 includes a metal, and the cap 22 includes a corresponding metal oxide. Examples of the metal include, but are not limited to, aluminum (Al), magnesium (Mg), nickel (Ni), zinc (Zn), or titanium (Ti).

[0025] Filler particles can be formed by providing semiconductor particles or metal particles and by oxidizing the surfaces of these particles in an oxidizing atmosphere during a temperature process. For example, by (a) grinding single-crystalline or polycrystalline silicon into particles of a desired size and (b) oxidizing the surfaces of the semiconductor particles obtained from the grinding process in an oxidizing atmosphere during a temperature process, particles having a silicon core 21 and a silicon oxide cap 22 can be formed.

[0026] According to one example, the filler particles are selected such that their size is between 10 micrometers (μm) and 100 micrometers. The "size" of a particle is the average diameter d of a particle, given by the following formula:

[0027]

[0028] where d is the average diameter of particle 2, and V is the volume of particle 2. For illustrative purposes only, in Figure 1A and Figure 1B particle 2 is depicted as having a spherical shape. However, this is for illustrative purposes only. Particle 2 can also be formed to have any other shape.

[0029] According to one example, the particles 2 have substantially the same size. According to another example, the particles 2 include two or more groups of particles, where the particles in one group substantially have the same size. "The same size" means that the size of the particles is in the range of 0.9·d i and 1.1·d i where d i is the desired size of the particles in the corresponding group.

[0030] According to one example, the thickness of the cap 22 is between 2 nanometers (nm) and 400 nanometers. The "thickness" of the cap is the size of the cap in a direction perpendicular to the surface of the cap 22 or perpendicular to the interface between the cap 22 and the core 21.

[0031] According to one example, the thickness of the capping 22 is adapted to the average diameter of the particles such that the dielectric strength of the filler particles is greater than the dielectric strength of the matrix. This is explained by way of example below. Assume that the matrix 1 is an epoxy resin having a dielectric strength of approximately 100 kV / cm and the capping 22 is silica having a dielectric strength of approximately 2 MV / cm (about 20 times the dielectric strength of the filler material). In order to achieve that the filler particles 2 do not reduce the dielectric strength of the molded compound, approximately 1 / 20 of the diameter of the filler particles should be formed by the capping 22. This percentage increases as the dielectric strength of the capping material decreases relative to the dielectric strength of the matrix, and vice versa.

[0032] An encapsulation made of a cured molded compound may include charge carriers such as ions or charged molecules as impurities. Such charge carriers may be initially included in the molded compound or may diffuse into the encapsulation 3 over time. Examples of such impurities include hydroxide ions (OH - ) or sodium ions (Na + ). Such charge carriers are able to move in the molded compound under the influence of an electric field. In a conventional molded compound including electrically insulating filler particles such as molten silica particles, positively charged carriers may accumulate at a location close to the source of the negative potential generating the electric field, and negatively charged carriers may accumulate at a location close to the source of the positive potential generating the electric field. Such accumulation of charge carriers may have a negative impact on semiconductor devices or integrated circuits integrated in a semiconductor die encapsulated by the encapsulation.

[0033] When using a molded compound of the type explained with reference to Figure 1A and Figure 1B (i.e., a molded compound including filler particles 2 having a conductive or semiconductive core 21 and a capping 22), such accumulation of charge carriers at certain locations is avoided or at least reduced. This is explained below with reference to Figure 2A and Figure 2B

[0034] Figure 2A Schematically shows a cross-sectional view of a part of a semiconductor device including a semiconductor die 100 and an encapsulation 3 including a molded compound of the type explained with reference to Figure 1A and Figure 1B . In Figure 2A , only a part of the semiconductor die 100 and a part of the encapsulation 3 with the molded compound are shown. More specifically, Figure 2Ashows a part of the semiconductor die 100 in a region close to the surface 101 of the semiconductor die and a part of the package 3 adjacent to this surface. The package 3 can be directly adjacent to the surface 101 of the semiconductor die 100. Optionally, an insulating or passivation layer 200 is arranged between the surface 101 of the semiconductor die 100 and the package 3. The insulating or passivation layer 200 can include at least one of an oxide layer, a nitride layer, an imide layer, etc. According to one example, the insulating or passivation layer 200 includes a layer stack having a plurality of different electrically insulating layers. According to one example, a wiring device is embedded in the insulating or passivation layer 200. This wiring device can interconnect semiconductor devices (not shown) integrated in the semiconductor die 100. Additionally, the wiring device can also include contact pads (not shown) at the surface 201 of the insulating or passivation layer 200, where these contact pads can be used to contact one or more semiconductor devices integrated in the semiconductor die 100 from the outside. Such a wiring device is known and thus no further explanation is needed in this regard.

[0035] In Figure 2A , the reference numerals 111 and 112 denote regions of the semiconductor die 100 having different potentials during operation of the semiconductor die 100. These regions 111, 112 can be doped semiconductor regions or metallizations. These regions 111, 112 can be two regions among various regions in the semiconductor die 100 that can have different potentials. Examples of these regions 111, 112 include but are not limited to: field plates at the edge terminations of power semiconductor devices; source and drain regions of lateral power transistor devices; source regions and field plates of vertical power transistor devices, etc.

[0036] Due to the different potentials of the regions 111, 112, there is an electric field between these regions 111, 112, where this electric field can extend into the package 3. For illustrative purposes only, the field lines of the electric field in the package 3 are shown as dashed lines in FIG. 2. Figure 2B is Figure 2A an enlarged view of part B of the package 3 shown in Figure 2B . Referring to Figure 2B , for illustrative purposes, it only shows one field line of the electric field, and the electric field does not pass through the core 21 of the filler particle 2. This is due to the fact that the core 21 is made of a conductive or semiconductive material. Due to the electric field, the core 21 has a certain potential. This potential is the same at every position of the core 21 and thus the same at every position of the interface between the core 21 and the insulating cap 22. Referring to Figure 2B , due to the electric field, charged ions can reach the particle 2. For illustrative purposes only, Figure 2BSome positively charged carriers P and some negatively charged carriers N are shown. In the case where the surface of the particle 2 has been reached, there is no force that will further move the charge carriers P, N. This is due to the fact that the core 21 is free from the electric field. Thus, in the molding compound with particles 2 having a conductive or semiconductive core 21 and an insulating cap 22, the charge carriers P, N are trapped at the individual particles 2 in some way. Due to the large number of particles 2 distributed over the molding compound, the trapped charge carriers are also distributed over the molding compound and do not accumulate in the molding compound at positions close to the first and second regions 111, 112, so that a locally enhanced electric field can occur.

[0037] By implementing filler particles 2 having a rough surface including holes, the trapping effect explained above can be improved. Figure 3 An example of a filler particle 2 having a rough surface is schematically shown. Such a rough or irregularly formed surface can be obtained when the filler particles 2 are produced from larger pieces of conductive or semiconductive material during a grinding process and the particles obtained by the grinding process are oxidized.

[0038] According to an example, the filler particles 2 comprise the same type of semiconductor material as the semiconductor die 100. However, the doping levels of these materials may be different. In this case, the molding compound mainly composed of the filler material and the semiconductor die 100 basically have the same coefficient of thermal expansion. This helps to reduce the thermal stress at the interface between the semiconductor die 100 and the molding compound. In this regard, it should be noted that the "semiconductor die" used herein refers to a device including a single-crystal semiconductor body and may additionally include a passivation layer, wiring devices inside the passivation layer, and contact pads directly on the surface of the single-crystal semiconductor body or on the surface of the passivation layer. The "semiconductor material of the semiconductor die" is the semiconductor material of the single-crystal semiconductor body included in the semiconductor die. According to an example, the above-mentioned "same type of semiconductor material" includes: the semiconductor die includes at least one of single-crystal silicon (Si) or silicon carbide (SiC), and the core 21 of the filler particle 2 includes one of Si or SiC, wherein the core 21 may include single-crystal or polycrystalline semiconductor material.

[0039] According to another example, the coefficient of thermal expansion of the filler particles 2 can be less than the coefficient of thermal expansion of the semiconductor die 100, and the coefficient of thermal expansion of the other materials of the molding compound (e.g., the matrix 1) can be greater than the coefficient of thermal expansion of the semiconductor die 100. In this case, the combination of the filler particles 2 and the matrix 1 in the molding compound can produce an average coefficient of thermal expansion that is substantially equal to the coefficient of thermal expansion of the semiconductor die 100. According to one example, the filler particles 2 include a silicon carbide (SiC) core 22, and the semiconductor die 100 includes single-crystalline silicon (Si), where SiC has a lower thermal conductivity than Si.

[0040] The molding compound explained above can be used to form various types of packages for encapsulating at least one semiconductor die. That is, Figure 2A the package 3, only a part of which is shown in, can have different forms. Referring below to Figure 4 , 5 and Figures 6A to 6B explain some examples.

[0041] Figure 4 shows a vertical cross-sectional view of a semiconductor device including a package 3 made of a molding compound of the type explained previously in this document. The package 3 encapsulates the semiconductor die 100. Additionally, the semiconductor device includes legs 51, 52 that protrude from the package 3 and are electrically connected to the semiconductor die 100 inside the package 3. The legs 51, 52 can be connected to the semiconductor die 100 in various ways. Figure 4 shows two different examples of how the legs 51, 52 can be connected to the semiconductor die 100. In the example shown in Figure 4 , one of the legs 51, 52, 51, is connected to the semiconductor die 100, where the contact surface of the semiconductor die 100 is mounted to a part of the leg 51 arranged inside the package 3. The other of the legs 52 is connected to the semiconductor die 100 using a bonding wire 51. The bonding wire is connected between the contact pad of the leg 52 inside the package 3 and the contact pad of the semiconductor die 100. Figure 4 The contact pads of the semiconductor die 100 are not explicitly shown in. Although Figure 4 only two legs 51, 52 of the semiconductor device are shown, it should be noted that multiple legs protruding from the package 3 and connected to different contact pads of the semiconductor die 100 can be included in the semiconductor device.

[0042] Figure 5 shows another type of semiconductor device having a semiconductor die 100 and a package 3. In this example, contact electrodes 53, 54 connected to the contact pads of the semiconductor die 100 are accessible at the surface of the package 3. This type of device can be referred to as an SMD (surface mount device).

[0043] According to one example, Figure 4 and Figure 5 a semiconductor device of the type shown in Figure 4 and Figure 5 includes only one semiconductor die 100. However, this is only one example. According to another example (not shown), the encapsulation 3 of the type shown in Figure 4 and Figure 5 encapsulates two or more semiconductor dies. These semiconductor dies can be arranged closely adjacent to each other in a so-called chip-by-chip configuration. According to another example, one of two or more semiconductor dies is arranged on another of the two or more semiconductor dies in a so-called chip-by-chip configuration. For example, according to Figure 4 and Figure 5 , the matrix material of the encapsulation 3 is epoxy resin.

[0044] Figure 6A and Figure 6B show a semiconductor device according to another example. In this example, the semiconductor device includes housings 6, 7 in which a plurality of semiconductor dies 1001 - 1003 are arranged. The molding compounds 1, 2 of the type previously explained herein at least partially fill the space between the semiconductor dies 1001 - 1003 and the housing 7. According to one example, in this example the matrix material is silicone resin. In Figure 6A and Figure 6B , the example shown, the housing includes a substrate 6 and a lid 7. Figure 6A and Figure 6B do not show contact pins that protrude from the housings 6, 7 and are connected to the dies 1001 - 1003 inside the housings. In this example, the encapsulation of the semiconductor device is formed by the housings 6, 7 and the molding compound inside the housings 6, 7.

[0045] Referring to Figure 6A and Figure 6B , the semiconductor dies 1001 - 1003 are mounted to the first contact pads 63 of the substrate 6. According to one example, the substrate 6 is a DCB (direct copper bonding) substrate and includes an electrically insulating carrier 61 and a number of contact pads 62, 63, 64 on the carrier 61 (three in the example shown in Figure 6A and Figure 6B ). According to one example, the carrier 61 is made of ceramic and the contact pads include copper. According to one example, the semiconductor dies 1001 - 1003 are not only mounted to the first contact pads 63 but are also electrically connected to the contact pads 63.

[0046] Referring to Figure 6A and Figure 6B, at the corresponding surfaces of die 1001 - 1003 facing away from the first contact pad 61, the semiconductor dies 1001 - 1003 may further include contact pads 1211 - 1213, 1221 - 1223. These other contact pads 1211 - 1213, 1221 - 1223 of die 1001 - 1003 may be connected to the second and third contact pads 62, 64 of the substrate 6 by bonding wires 431 - 433, 421 - 423 (as shown), planar conductors, etc.

[0047] According to one example, vertical power transistors are integrated in semiconductor dies 1001 - 1003, wherein the drain nodes of the corresponding power transistors are formed at those surfaces of die 1001 - 1003 connected to the first contact pad 63, the source nodes are formed by contact pads 1211 - 1223, and the gate nodes are formed by the other contact pads 1211 - 1213.

[0048] In Figure 6A and Figure 6B the example shown, the substrate 6 forms part of the housing. However, this is only an example. According to another example (not shown), a substrate with dies is embedded in the housing.

[0049] Although the present disclosure is not so limited, the following numbered examples illustrate one or more aspects of the present disclosure.

[0050] Example 1. A molding compound, comprising: a matrix; and a filler including filler particles (2), wherein each filler particle includes a core and an electrically insulating capping, and the core includes a conductive or semiconductive material.

[0051] Example 2. The molding compound of Example 1, wherein the core includes one of silicon and silicon carbide, and wherein the capping includes silicon oxide.

[0052] Example 3. The molding compound of any combination of Examples 1 - 2, wherein the semiconductive material is a doped semiconductive material.

[0053] Example 4. The molding compound of any combination of Examples 1 - 3, wherein the doping concentration of the doped semiconductive material is greater than 1E18 cm -3 .

[0054] Example 5. The molding compound of any combination of Examples 1 - 4, wherein the core includes a metal, and wherein the capping includes a metal oxide.

[0055] Example 6. The molding compound of any combination of Examples 1 - 5, wherein the molding compound includes at least 10 wt.% filler.

[0056] Example 7. A molded compound of any combination of Examples 1 to 6, wherein the molded compound comprises a filler between 60 wt.% and 90 wt.%.

[0057] Example 8. A molded compound of any combination of Examples 1 to 7, wherein the particle size of the filler particles is between 10 microns and 100 microns.

[0058] Example 9. A molded compound of any combination of Examples 1 to 8, wherein the thickness of the capping is between 2 nanometers and 400 nanometers.

[0059] Example 10. A molded compound of any combination of Examples 1 to 9, wherein the capping has a rough surface.

[0060] Example 11. A molded compound of any combination of Examples 1 to 10, wherein the matrix comprises one of epoxy resin and silicone resin.

[0061] Example 12. A molded compound of any combination of Examples 1 to 11, further comprising at least one of a catalyst, a release agent material, and a colorant.

[0062] Example 13. A semiconductor device, comprising: at least one semiconductor die; and a molded compound according to any combination of Examples 1 to 12.

[0063] Example 14. The semiconductor device of Example 13, wherein the semiconductor die comprises at least one of single crystal silicon (Si) and single crystal silicon carbide (SiC).

[0064] Example 15. The semiconductor device of any combination of Examples 12 to 14, further comprising: a carrier, wherein at least one semiconductor die is mounted to the carrier.

[0065] Example 16. The semiconductor device of any combination of Examples 12 to 15, wherein the semiconductor device comprises a plurality of semiconductor dies mounted to the carrier.

[0066] Example 17. The semiconductor device of any combination of Examples 12 to 16, wherein the molded compound forms an encapsulation of the semiconductor device.

[0067] Example 18. The semiconductor device of any combination of Examples 12 to 17, further comprising: a housing, wherein the molded compound at least partially fills the housing.

[0068] Although the present invention has been described with reference to exemplary examples, the description is not intended to be construed in a limiting sense. When referring to the description, those skilled in the art will clearly realize that modifications and combinations can be made to these exemplary examples as well as other examples of the present invention. Therefore, it is intended that the appended claims cover any such modifications or examples.

Claims

1. A molding compound for reducing or avoiding the accumulation of charged impurities in a package, comprising: a matrix (1); and a filler including filler particles (2), wherein each of the filler particles includes: a core (21) including a semiconductive material; and an electrically insulating cap (22) and a rough surface; wherein the rough surface includes holes such that the rough surface is configured to trap charge carriers as impurities in the molding compound.

2. The molded compound according to claim 1, wherein, The core (21) includes one of silicon carbide or silicon as the semiconductive material, and wherein the electrically insulating cap (22) includes silicon oxide.

3. The molding compound according to claim 1 or 2, Among them, wherein the semiconductive material is a doped semiconductive material.

4. The molding compound according to claim 3, Among them, The doping concentration of the doped semiconductive material is greater than 1E18 cm -3 .

5. The molding compound according to claim 1 or 2, Among them, wherein the molding compound includes at least 10 wt.% of the filler.

6. The molding compound according to claim 5, Among them, wherein the molding compound includes the filler between 60 wt.% and 90 wt.%.

7. The molding compound according to claim 1 or 2, Among them, wherein the particle size of the filler particles is between 10 microns and 100 microns.

8. The molding compound according to claim 6, Among them, wherein the thickness of the electrically insulating cap is between 2 nanometers and 400 nanometers.

9. The molded compound according to claim 1 or 2, wherein, The electrically insulating cap has a rough surface.

10. The molded compound according to claim 1 or 2, wherein, The matrix includes one of epoxy resin and silicone resin.

11. The molding compound according to claim 1 or 2, further comprising at least one of a catalyst, a release agent material, and a colorant.

12. A semiconductor device, comprising: at least one semiconductor die (100; 1001 - 1003), which includes a semiconductor material; and the molding compound according to any one of claims 1 to 11.

13. The semiconductor device according to claim 12, Among them, wherein the filler particles (2) include the same type of semiconductor material as the semiconductor die (100).

14. The semiconductor device according to claim 13, Among them, wherein the at least one semiconductor die (100; 1001 - 1003) includes at least one of single crystal silicon (Si) and single crystal silicon carbide (SiC).

15. The semiconductor device according to claim 13 or 14, further comprising: a carrier (61), wherein the at least one semiconductor die (100; 1001 - 1003) is mounted to the carrier (61).

16. The semiconductor device according to claim 15, Among them, wherein the semiconductor device includes a plurality of semiconductor dies (1001 - 1003) mounted to the carrier (61).

17. The semiconductor device according to any one of claims 12 to 14, Among them, wherein the molding compound (1) forms the package of the semiconductor device.

18. The semiconductor device according to any one of claims 12 to 14, further comprising: a housing, wherein the molding compound (1) at least partially fills the housing.

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