Semiconductor packaging structure, semiconductor module and electronic equipment

Abstract

The invention provides a semiconductor packaging structure, a semiconductor module and electronic equipment, the semiconductor packaging structure comprises a first packaging body and a second packaging body, the first packaging body comprises a first substrate and a first chip, the second packaging body comprises a second substrate, the first chip is located on the first substrate, and the second substrate is located on the first chip. The ratio range of the thickness of the first chip to the distance between the first substrate and the second substrate is controlled to be not greater than 0.5, so that the size of the semiconductor packaging structure and the thickness of the first chip are synchronously reduced, and the stability of the structure and the performance of the first chip can be maintained; the semiconductor packaging structure has the characteristics of small size and high reliability.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor packaging, and particularly to a semiconductor packaging structure, a semiconductor module, and an electronic device. Background Art

[0002] The package-on-package (PoP) technology is a typical three-dimensional packaging technology solution. Due to its structural feature of being able to integrate a logic chip and a memory chip simultaneously, it has become one of the main packaging solutions that continuously pursue smaller volume and thinner size characteristics.

[0003] The package-on-package technology is a packaging structure formed by vertically stacking two or more chips together. It can reduce the area occupied by the chips on the main board, and thus has been widely applied in electronic devices such as mobile phones and tablets. In order to pursue the structural characteristics of smaller volume and thinner size, the prior art reduces the thickness of the logic chip to continuously compress the total thickness of the packaging structure. However, the reduction of the logic chip thickness not only reduces the structural strength of the logic chip in the packaging structure, affecting the reliability of the packaging structure, but also there is an uneven chip heating phenomenon, affecting the working performance of the packaging structure.

[0004] Therefore, how to provide a semiconductor packaging structure, a semiconductor module, and an electronic device that can take into account the reliability of the packaging structure and the characteristics of small volume has become a technical problem that needs to be urgently solved by those skilled in the art. Summary of the Invention

[0005] The present application aims to at least solve one of the technical problems in the related art to some extent.

[0006] To this end, the first object of the present application is to propose a semiconductor packaging structure, a semiconductor module, and an electronic device that can take into account the performance requirements of the chip while satisfying the characteristics of small volume of the packaging structure.

[0007] To achieve the above object, the first aspect embodiment of the present application proposes a semiconductor packaging structure, including:

[0008] A first package, the first package includes a first substrate and a first chip, and the first chip is located on the first substrate;

[0009] A second package, coupled to the first package; the second package includes a second substrate, and the first chip is located between the first substrate and the second substrate;

[0010] Wherein, the ratio range of the thickness T1 of the first chip to the distance D1 between the first substrate and the second substrate is less than 0.5.

[0011] Optionally, the thickness T1 of the first chip ranges from 50 μm to 90 μm.

[0012] Optionally, the semiconductor package structure further includes a heat dissipation structure disposed on the first chip.

[0013] Optionally, the heat dissipation structure is disposed between the first chip and the second substrate, directly contacting and covering the first upper surface of the first chip, and the first upper surface is the surface of the first chip away from the first substrate.

[0014] Optionally, the ratio of the thickness T2 of the heat dissipation structure to the spacing D1 between the first substrate and the second substrate ranges from 0.3 to 0.5.

[0015] Optionally, the thickness T2 of the heat dissipation structure ranges from 5 μm to 50 μm.

[0016] Optionally, the spacing D2 between the heat dissipation structure and the second substrate is not greater than 40 μm.

[0017] Optionally, the heat dissipation structure includes one of diamond material, silicon material or copper material.

[0018] Optionally, the first package further includes an encapsulation layer and a conductive structure located in the encapsulation layer. The encapsulation layer fills between the first substrate and the second substrate to surround and encapsulate the first chip, and the conductive structure is disposed on the periphery of the first chip to electrically connect the first substrate and the second substrate.

[0019] Optionally, a first wiring layer is provided in the first substrate, and the first lower surface of the first chip is electrically connected to the first wiring layer. The first lower surface is the surface of the first chip close to the first substrate; a second wiring layer is provided in the second substrate, and the first wiring layer is electrically connected to the second wiring layer through the conductive structure.

[0020] Optionally, the heat dissipation structure is located on the side of the second substrate away from the first substrate. In the direction perpendicular to the surface of the first substrate, the vertical projection of the first chip on the first substrate and the vertical projection of the heat dissipation structure on the first substrate at least partially overlap.

[0021] Optionally, the heat dissipation structure penetrates through the second substrate, contacts the first upper surface of the first chip, and extends to cover the first upper surface; in the direction perpendicular to the surface of the first substrate, the vertical projection of the first chip on the first substrate and the vertical projection of the heat dissipation structure on the first substrate at least partially overlap.

[0022] Optionally, the heat dissipation structure passes through the second substrate and maintains a preset distance from the first upper surface of the first substrate; in a direction perpendicular to the surface of the first substrate, the vertical projection of the first chip on the first substrate at least partially overlaps with the vertical projection of the heat dissipation structure on the first substrate.

[0023] Optionally, the second substrate includes a groove, and the heat dissipation structure fills the groove, wherein the groove does not penetrate the second substrate; in a direction perpendicular to the surface of the first substrate, a vertical projection of the first chip on the first substrate and a vertical projection of the heat dissipation structure on the first substrate at least partially overlap

[0024] A second aspect of the present application provides a semiconductor module, which includes any one of the above-mentioned semiconductor packaging structures.

[0025] A third aspect of the present application provides an electronic device, which includes any one of the above-mentioned semiconductor packaging structures.

[0026] The semiconductor packaging structure, semiconductor module and electronic device provided by the present application have at least the following beneficial effects:

[0027] The present application provides a semiconductor package structure semiconductor module and electronic device, semiconductor module and electronic device. The semiconductor package structure includes a first package body and a second package body, the first package body includes a first substrate and a first chip, the second package body includes a second substrate, the first chip is located on the first substrate, and the second substrate is located on the first chip. By controlling the ratio range of the thickness of the first chip to the spacing between the first substrate and the second substrate to be no more than 0.5, the volume of the semiconductor package structure and the thickness of the first chip are reduced synchronously, and the first chip can maintain the stability of structure and performance, so as to meet the characteristics of small volume and high reliability of the semiconductor package structure.

[0028] Furthermore, the present application provides a semiconductor packaging structure, a semiconductor module and an electronic device, which also include a heat dissipation structure arranged on the first chip. By arranging a heat dissipation structure with a high thermal conductivity on the first chip, the heat radiated by the first chip as a heat source can be quickly discharged under the guidance of the heat dissipation structure, thereby improving the heat dissipation efficiency of the first chip, preventing the temperature of the first chip from exceeding the temperature threshold range, and making the heat dissipation efficiency of the first chip no longer limited by the thickness of the first chip, thereby further reducing the thickness of the first chip and the volume of the semiconductor packaging structure.

[0029] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. Description of the Drawings

[0030] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description of embodiments in conjunction with the drawings, wherein:

[0031] Figures 1 to 10 It is a schematic cross-sectional structure diagram of a semiconductor package structure shown according to an embodiment of the present application.

[0032] 100 First package body; 110 First substrate; 111 First wiring layer; 120 First chip; 130 Encapsulation layer; 140 Conductive structure; 150 Conductive terminal; 200 Second package body; 210 Second substrate; 211 Second wiring layer; 220 Second chip; Heat dissipation structure 300. Detailed Description of the Embodiments

[0033] Embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are intended to explain the present application and should not be construed as limiting the present application.

[0034] Currently, in order to further pursue the structural characteristics of smaller volume and thinner size for electronic devices, the overall volume of the internal package structure is usually continuously compressed, especially the thickness of the package structure. Moreover, the thickness of the package structure is closely related to the thickness dimension of the internal chip. Therefore, reducing the chip thickness has become the main way to achieve the goal of smaller volume and thinner size for electronic devices. However, reducing the chip thickness will reduce the overall structural strength of the chip and affect the structural stability of the chip within the package structure. At the same time, further thinning of the chip thickness will also affect the heat dissipation efficiency of the chip, resulting in a large temperature gradient within the package structure due to uneven heat dissipation. When the temperature gradient is severe, it will also reduce the working performance of the chip and affect the performance stability of the chip within the package structure.

[0035] Therefore, how to reasonably adjust the size of the package structure and the size of the chip within the package structure under the existing process capabilities to meet the structural characteristics of smaller volume and thinner size of the package structure, while not affecting the reliability and performance stability of the package structure.

[0036] Based on the above problems, a first aspect of the embodiments of the present application provides a semiconductor package structure, as Figure 1As shown, the semiconductor package structure includes a first package body 100 and a second package body 200, and the second package body 200 is coupled to the first package body 100. The first package body 100 includes a first substrate 110 and a first chip 120. The first chip 120 is located on the first substrate 110. The second package body 200 includes a second substrate 210, and the first chip 120 is located between the first substrate 110 and the second substrate 210. Among them, the ratio range of the thickness T1 of the first chip 120 to the spacing D1 between the first substrate 110 and the second substrate 210 is less than 0.5.

[0037] The chip is obtained by cutting a wafer. To maintain a certain operability, the thickness of the wafer produced by the foundry is generally about 700 μm. Then, the testing and packaging factory must grind and thin the wafer to be suitable for cutting and assembly, generally grinding it to about the preset thickness. Especially for the chip structure used in the stack / layer structure, the wafer used generally needs to be ground to a thickness below the preset thickness. For example, the chip thickness in the stack / layer structure / package is usually about 100 μm, so as to reduce the size of the semiconductor package structure as much as possible under the conventional packaging process. However, the larger the thickness of the chip, the more conducive it is to improving the heat dissipation efficiency of the chip, and then obtaining a stronger power budget. That is to say, there needs to be a certain proportional relationship between the thickness of the chip and the size of the semiconductor package structure in order to make the semiconductor package structure take into account the structural characteristics of a small size and a strong power budget.

[0038] Since the first chip 120 is located between the first substrate 110 and the second substrate 210, and the ratio range of the thickness T1 of the first chip 120 to the spacing D1 between the first substrate 110 and the second substrate 210 is not greater than 0.5, the thickness T1 of the first chip 120 and the spacing D1 between the first substrate 110 and the second substrate 210 are basically positively correlated. That is to say, by controlling the thickness T1 of the first chip 120, the value range of the spacing D1 between the first substrate 110 and the second substrate 210 can be initially calculated, so that the volume of the first package body 100 is controlled within an ideal size range, and then the overall volume of the semiconductor package structure is controlled.

[0039] Therefore, when the ratio of the thickness T1 of the first chip 120 to the spacing D1 between the first substrate 110 and the second substrate 210 is not greater than 0.5, during or after the first chip 120 forms the first package body 100 by packaging, the packaging stress it receives will be within a preset stress threshold range, avoiding structural problems such as breakage or warping of the first chip 120 in the first package body 100, and thus ensuring the structural stability of the first chip 120 in the first package body 100.

[0040] Meanwhile, the ratio of the thickness T1 of the first chip 120 to the spacing D1 between the first substrate 110 and the second substrate 210 is less than 0.5. This not only enables the volume of the semiconductor packaging structure to decrease synchronously with the thickness of the first chip 120, but also enables the heat dissipation efficiency of the first chip 120 during operation to be balanced with that of the first package 100, thereby keeping the temperature of the first chip 120 within a preset temperature threshold range, ensuring the performance stability of the first chip 120 within the first package 100, and also enabling the semiconductor packaging structure to maintain a strong power budget.

[0041] As an example, the ratio range of the thickness T1 of the first chip 120 to the spacing D1 between the first substrate 110 and the second substrate 210 is between 0.2 and 0.49, so as to compress the thickness of the first chip 120 and the first package 100, achieving the purpose of reducing the volume of the semiconductor packaging structure.

[0042] As an example, the range of the thickness T1 of the first chip 120 is between 50 μm and 90 μm, which can be between 50 μm and 70 μm, or between 70 μm and 90 μm, so as to control the thickness T1 of the first chip 120 below 100 μm.

[0043] In addition, the first chip 120 can be a flip chip, including an opposite first upper surface and a first lower surface. The first upper surface is the surface closer to the second substrate 210, and the first lower surface is the surface closer to the first substrate 110. Thus, the first chip 120 can be coupled to the first substrate 110 through a plurality of solders. Among them, the solder can be solder balls, solder columns, copper columns, etc.

[0044] The first chip 120 includes a System-on-Chip (SoC), a Logic Device, a Memory Device, a Radio Frequency (RF) device, etc., or any combination thereof. Exemplarily, the first chip 120 may include a Micro Control Unit (MCU) die, a MicroProcessor Unit (MPU) chip, a Power Management Integrated Circuit (PMIC) chip, a Radio Frequency Front End (RFFE) chip, an Accelerated Processing Unit (APU) chip, a Central Processing Unit (CPU) chip, a Graphics Processing Unit (GPU) chip, an Input Output (IO) chip, a Dynamic Random Access Memory (DRAM) controller, a Static Random Access Memory (SRAM), a High Bandwidth Memory (HBM), an Application Processor (AP) chip, etc., or any combination thereof.

[0045] It should be noted that the above semiconductor package structure is applicable to a stacked package structure, including but not limited to being applied in any suitable electronic device. Exemplarily, the electronic device includes a smart phone, a tablet computer, a notebook computer, a wearable electronic device (e.g., a smart watch), a set-top box (e.g., a media device or a mobile hotspot), and an automotive computing system (e.g., a navigation and entertainment system).

[0046] As Figure 1 shown, in some embodiments, the first package 100 further includes an encapsulation layer 130 and a conductive structure 140 located in the encapsulation layer 130. The encapsulation layer 130 fills the space between the first substrate 110 and the second substrate 210 and surrounds and encapsulates the first chip 120, while the conductive structure 140 is disposed on the peripheral side of the first chip 120 to electrically connect the first substrate 110 and the second substrate 210.

[0047] It can be understood that since the encapsulation layer 130 surrounds and encapsulates the first chip 120 and is spaced apart from the second package 200, the first chip 120 can be stably disposed on the first substrate 110, thereby protecting the first chip 120 from the surrounding environment and preventing the first chip 120 from being damaged by uncertain factors such as internal and external stresses, chemicals, and / or moisture, ensuring the stability of the structure and / or performance of the first chip 120 within the first package 100.

[0048] At the same time, since air has a low thermal conductivity (0.024 watts per meter kelvin, W / mK) that inhibits the diffusion of heat radiation, it is difficult for the heat generated by the first chip 120 as a heat source to be directly exported quickly through the air. That is, when the first chip 120 is operating, a medium with a high thermal conductivity is required on its periphery to quickly export the heat on its surface to prevent the temperature of the first chip 120 from exceeding the temperature threshold range and affecting the performance stability of the first chip 120. By disposing the encapsulation layer 130 between the first substrate 110 and the second substrate 210, not only can it provide bottom support for the second substrate 210 located above the first chip 120, but also it can transfer the heat generated by the first chip 120 during operation to the second substrate 210 to a certain extent and be exported by the second substrate 210 outside the semiconductor package structure, so that the surface temperature of the first chip 120 can be maintained within the temperature threshold, effectively improving the thermal conductivity efficiency of the first chip 120 and ensuring the stability of the performance of the first chip 120.

[0049] Furthermore, since the conductive structure 140 electrically connects the first substrate 110 and the second substrate 210, the first chip 120 located on the first substrate 110 can be electrically connected to the second chip 220 located on the second substrate 210 through the conductive structure 140. That is to say, by coupling and connecting with the conductive internal structure, the second package 200 enables the first package 100 to be electrically connected to the second package 200.

[0050] Since the conductive structure 140 is disposed around the periphery of the first chip 120 and the first chip 120 is encapsulated by the encapsulation layer 130 and spaced apart from the side of the first chip 120, the conductive structure 140 can also be protected from the environment under the protection of the encapsulation layer 130, thereby preventing the conductive structure 140 from being damaged under the influence of uncertain factors such as internal and external stresses, chemicals, and / or moisture, ensuring the stability of the internal structure and / or performance of the semiconductor package structure.

[0051] It should be noted that the encapsulation layer 130 is made of non-conductive materials, including but not limited to moldable polymers, epoxy resins, resins, etc. or combinations thereof.

[0052] The conductive structure 140 is made of a conductive material, including a conductive column, a solder ball, a copper core solder ball, etc. or a combination thereof, including but not limited to copper, aluminum, tungsten, etc., alloys thereof, or a combination thereof.

[0053] like Figure 1 As shown, in some embodiments, a first wiring layer 111 is provided in the first substrate 110, and the first lower surface of the first chip 120 is electrically connected to the first wiring layer 111; a second wiring layer 211 is provided in the second substrate 210, and the first wiring layer 111 is electrically connected to the second wiring layer 211 through a conductive structure 140.

[0054] It can be understood that the main material of the first substrate 110 and the second substrate 210 can be a passivation layer formed by a dielectric material and / or a polymer material, and the first wiring layer 111 and the second wiring layer 211 are respectively arranged in the passivation layer, with only a partial surface exposed at a preset position, so that the conductive structure 140 can electrically connect the first wiring layer 111 and the second wiring layer 211 with the partial surface.

[0055] Similarly, the first chip 120 is located on the first substrate 110 and is coupled to the exposed surface of the first wiring layer 111 through a plurality of solders, so that the first chip 120 can maintain electrical connection with the second wiring layer 211 .

[0056] As an example, the polymer material includes polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, etc. or a combination thereof, and the dielectric material includes silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, etc. or a combination thereof.

[0057] The first wiring layer 111 and the second wiring layer 211 may include a conductive layer, a conductive column, a conductive via, etc. or a combination thereof, and may be composed of a conductive metal material, including a metal single substance such as copper, gold, tungsten, a metal alloy or a combination thereof.

[0058] like Figures 2 to 9 As shown, in some embodiments, the semiconductor package structure further includes a heat dissipation structure 300 , and the heat dissipation structure 300 is disposed on the first chip 120 .

[0059] It can be understood that the heat dissipation structure 300 can be composed of metal and / or non-metallic materials with high thermal conductivity. By setting the high thermal conductivity heat dissipation structure 300 on the first chip 120, the heat radiated by the first chip 120 as a heat source can be quickly discharged under the guidance of the heat dissipation structure 300, thereby improving the heat dissipation efficiency of the first chip 120, preventing the temperature of the first chip 120 from exceeding the temperature threshold range, and making the heat dissipation efficiency of the first chip 120 no longer limited by the thickness of the first chip 120, thereby achieving the purpose of further reducing the thickness of the first chip 120 and the volume of the semiconductor packaging structure.

[0060] As an example, the heat dissipation structure 300 includes materials such as diamond, silicon, copper, or combinations thereof.

[0061] As Figures 2 to 4 shown, in some embodiments, the heat dissipation structure 300 is disposed between the first chip 120 and the second substrate 210, directly contacting and covering the first upper surface of the first chip 120.

[0062] It can be understood that since the heat dissipation structure 300 directly contacts and covers the first upper surface of the first chip 120, the heat dissipation structure 300 can be an attachment film attached to the first upper surface of the first chip 120 to directly contact the first chip 120 and quickly conduct the heat radiated by the first chip 120. At the same time, forming the heat dissipation structure 300 attached to the first chip 120 can further reduce the thickness of the first chip 120, and further reduce the size of the first package 100.

[0063] As an example, when the heat dissipation structure 300 is composed of diamond material, its thermal conductivity can reach 900 W / mK to 2320 W / mK, which is much greater than the thermal conductivity of the silicon material constituting the first chip 120 and the material of the encapsulation layer 130 covering the first chip 120. That is to say, by attaching the heat dissipation structure 300 to the first upper surface of the first chip 120, the internal heat of the first chip 120 can be quickly exported from the first upper surface, and at the same time, the temperature of the first upper surface is made more uniform, preventing a large temperature gradient from appearing on the first upper surface.

[0064] Furthermore, when the ratio range of the thickness T2 of the heat dissipation structure 300 to the distance D1 between the first substrate 110 and the second substrate 210 is between 0.3 and 0.5, the heat dissipation structure 300 can not only further reduce the thickness T1 of the first chip 120, but also effectively control the temperature of the first chip 120 to keep it within the temperature threshold range, ensuring that the performance of the first chip 120 in the first package 100 maintains a strong power budget. At the same time, the size of the first package 100 can also be further improved. In addition, as the thickness T1 of the first chip is further reduced, the stress on the first chip can be further reduced, improving the yield of the packaging structure.

[0065] When the ratio range of the thickness T2 of the heat dissipation structure 300 to the distance D1 between the first substrate 110 and the second substrate 210 is between 0.3 and 0.44, and the ratio range of the thickness T1 of the first chip 120 to the distance D1 between the first substrate 110 and the second substrate 210 is between 0.35 - 0.49, the heat dissipation of the first chip 210 and the packaging stress it receives can also reach a relatively low balance state.

[0066] Among them, the thickness T2 of the heat dissipation structure 300 ranges from 5 μm to 40 μm, and the distance D2 between the heat dissipation structure 300 and the second substrate 210 is less than 40 μm. The larger the thickness T2 of the heat dissipation structure 300, the smaller the range of the distance D2 between it and the second substrate 210, and the higher the heat dissipation efficiency of the heat dissipation structure 300 for the first chip 120.

[0067] As Figure 3 and Figure 4 shown, when the distance D2 between the heat dissipation structure 300 and the second substrate 210 approaches 0 μm, the upper surface of the heat dissipation structure 300 is substantially coplanar with the upper surface of the encapsulation layer 130, jointly forming the upper surface of the first package 100, and the second substrate 210 is coupled to the first package 100, enabling the heat dissipation structure 300 to directly contact the lower surface of the second substrate 210. Furthermore, the heat dissipation structure 300 can directly transfer the heat generated by the first chip 120 to the second substrate 210, and the heat is transferred to the outside of the semiconductor package structure by the second wiring layer 211 provided in the second substrate 210, keeping the first chip 120 continuously within the temperature threshold range and ensuring the performance stability of the first chip 120 in the first package 100.

[0068] It should be noted that the coverage area of the heat dissipation structure 300 on the first upper surface of the first chip 120 is not specifically limited in this application. The coverage area can be larger than the area of the first upper surface, equal to the area of the first upper surface, or smaller than the area of the first upper surface. Among them, as Figure 4 shown, the larger the coverage area of the heat dissipation structure 300 on the first upper surface of the first chip 120, the higher its heat dissipation efficiency for the first chip 120, and it is more conducive to controlling the uniformity of the internal temperature of the first chip 120 and reducing the internal temperature gradient during the operation of the first chip 120.

[0069] As Figures 5 to 9 shown, in some other embodiments, the heat dissipation structure 300 is disposed on the first chip 120, but is not limited to being between the first chip 120 and the second substrate 210, and in the direction perpendicular to the surface of the first substrate 110, the vertical projection of the first chip 120 on the first substrate 110 and the vertical projection of the heat dissipation structure 300 on the first substrate 110 at least partially overlap.

[0070] As Figure 5As shown, when the heat dissipation structure 300 is directly arranged on the side of the second substrate 210 close to the first substrate 110, the heat radiated by the first chip 120 serving as a heat source can be quickly discharged under the guidance of the heat dissipation structure 300, thereby improving the heat dissipation efficiency of the first chip 120, preventing the temperature of the first chip 120 from exceeding the temperature threshold range, and improving the performance or reliability of the first chip 120.

[0071] Furthermore, if Figure 6 and Figure 7 As shown, the heat dissipation structure 300 is disposed in the second substrate 210, and the groove disposed on the side of the second substrate 210 near the first substrate 110 is filled, or the groove disposed on the side of the second substrate close to the first substrate 110 is filled, so as to reduce the distance between the heat dissipation structure 300 and the first chip 120, thereby shortening the heat dissipation path of the first chip 120, which is beneficial to improving the heat dissipation efficiency of the first chip 120. Among them, the groove does not penetrate the second substrate 210.

[0072] Furthermore, if Figure 8 As shown, the heat dissipation structure 300 is arranged in the second substrate 210 and extends vertically from a side of the second substrate 210 away from the first substrate 110, penetrating the second substrate 210, and maintaining a preset distance between the second upper surface of the first substrate 110, so as to further reduce the distance between the heat dissipation structure 300 and the first chip 120, thereby shortening the heat dissipation path of the first chip 120.

[0073] Furthermore, if Figure 9 As shown, the heat dissipation structure 300 is arranged in the second substrate 210 and extends vertically from a side of the second substrate 210 away from the first substrate 110, penetrates the second substrate 210, contacts the first upper surface of the first chip 120, and extends to cover the first upper surface of the first chip 120, so as to further reduce the distance between the heat dissipation structure 300 and the first chip 120, shortening the heat dissipation path of the first chip 120.

[0074] At the same time, since the vertical projection of the first chip 120 on the first substrate 110 at least partially overlaps with the vertical projection of the heat dissipation structure 300 on the first substrate 110, and the larger the area of vertical overlap, the more conducive it is to reducing the straight-line distance between the heat dissipation structure 300 and the first chip 120, the higher the heat dissipation efficiency of the heat dissipation structure 300 on the first chip 120.

[0075] It should be noted that the specific structural form of the heat dissipation structure 300 on the second substrate 210 is not specifically limited in this application. Among them, the smaller the distance between the heat dissipation structure 300 and the first chip 120, and the larger the overlapping area between the vertical projection of the first chip 120 on the first substrate 110 and the vertical projection of the heat dissipation structure 300 on the first substrate 110, the shorter the heat dissipation path of the first chip 120, which is more conducive to improving the heat dissipation efficiency of the first chip 120, and thus conducive to improving the performance or reliability of the first chip 120.

[0076] As Figure 10 shown, in some embodiments, the second package 200 further includes a second chip 220, and the second chip 220 is located on the second substrate 210.

[0077] It can be understood that the second chip 220 may be a flip chip, including an opposite second upper surface and a second lower surface, the second lower surface is the surface close to the second substrate 210, and the second upper surface is the surface far from the second substrate 210.

[0078] Among them, the second chip 220 is coupled to the second substrate 210 through a plurality of solders and is electrically connected to a second wiring layer 211 disposed in the second substrate 210 and exposing a partial surface, so that the second chip 220 can be electrically connected to the first chip 120 through the second wiring layer 211, the connection structure, and the first wiring layer 111 in sequence. The solders connecting the second chip 220 and the second wiring layer 211 may be solder balls, solder posts, copper pillars, etc.

[0079] The second chip 220 includes a system on a chip, a logic device, a memory device, a radio frequency device, etc. or any combination thereof. Exemplarily, the second chip 220 may include a microcontroller bare chip, a microprocessor unit chip, a power management integrated circuit chip, a radio frequency front-end chip, an acceleration processing unit chip, a central processing unit chip, a graphics processing unit chip, an input / output chip, a dynamic random access memory controller, a static random access memory, a high-bandwidth memory, an application processor chip, etc. or any combination thereof

[0080] As Figure 8 shown, in some embodiments, the first package 100 further includes a plurality of conductive terminals 150, and the plurality of conductive terminals 150 are disposed below the first substrate 110.

[0081] It can be understood that by disposing a plurality of conductive terminals 150 below the first substrate 110, the semiconductor package structure can be coupled and connected to a printed circuit board (Printed Circuit Board, PCB) through the conductive terminals 150 in subsequent processes, so that the semiconductor package structure can be electrically connected to the outside through the printed circuit board.

[0082] Since the first wiring layer 111 is disposed in the first substrate 110 and partially exposes a surface at a preset position, the conductive terminal 150 is coupled to the partially exposed surface, thereby being electrically connected to the first wiring layer 111 .

[0083] It should be noted that the types of conductive terminals 150 include micro bumps, solder balls, ball grids, etc. or a combination thereof, and the specific materials can be formed of conductive materials, including but not limited to metals such as copper, aluminum, tungsten, or their alloys or a combination of metals and alloys.

[0084] A second aspect of the embodiments of the present application further provides a semiconductor module, which includes the semiconductor packaging structure described in any one of the above embodiments.

[0085] A third aspect of the embodiments of the present application further provides an electronic device, which includes the semiconductor packaging structure described in any one of the above embodiments.

[0086] In summary, the present application provides a semiconductor packaging structure, a semiconductor module and an electronic device, wherein the semiconductor module and the electronic device include the semiconductor packaging structure. The semiconductor packaging structure includes a first package body 100 and a second package body 200, wherein the first package body 100 includes a first substrate 110 and a first chip 120, and the second package body 200 includes a second substrate 210, wherein the first chip 120 is located on the first substrate 110, and the second substrate 210 is located on the first chip 120. By controlling the ratio of the thickness of the first chip 120 to the spacing between the first substrate 110 and the second substrate 210 to be no greater than 0.5, the volume of the semiconductor packaging structure and the thickness of the first chip 120 are reduced simultaneously, and the first chip 120 can maintain the stability of the structure and performance, so as to meet the characteristics of the semiconductor packaging structure with small volume and high reliability.

[0087] Furthermore, the present application provides a semiconductor packaging structure, a semiconductor module and an electronic device, which also include a heat dissipation structure 300 disposed on the first chip 120. By disposing the heat dissipation structure 300 with a high thermal conductivity on the first chip 120, the heat radiated by the first chip 120 as a heat source can be quickly discharged under the guidance of the heat dissipation structure 300, thereby improving the heat dissipation efficiency of the first chip 120, preventing the temperature of the first chip 120 from exceeding the temperature threshold range, and making the heat dissipation efficiency of the first chip 120 no longer limited by the thickness of the first chip 120, thereby achieving the purpose of further reducing the thickness of the first chip 120 and the volume of the semiconductor packaging structure.

[0088] In the description of the foregoing embodiments, the descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0089] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present application, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

Claims

1. A semiconductor package structure, characterized in that, Comprising: A first encapsulation body, the first encapsulation body including a first substrate and a first chip, the first chip being located on the first substrate; A second encapsulation body, coupled to the first encapsulation body; the second encapsulation body including a second substrate, the first chip being located between the first substrate and the second substrate; Wherein, the ratio of the thickness T1 of the first chip to the spacing D1 between the first substrate and the second substrate is less than 0.

5.

2. The semiconductor package structure according to claim 1, wherein The thickness T1 of the first chip ranges from 50μm to 90μm.

3. The semiconductor package structure according to claim 1, wherein, The semiconductor encapsulation structure further includes a heat dissipation structure, the heat dissipation structure being disposed on the first chip.

4. The semiconductor package structure according to claim 3, wherein, The heat dissipation structure is disposed between the first chip and the second substrate, directly contacting and covering the first upper surface of the first chip, the first upper surface being the surface of the first chip away from the first substrate.

5. The semiconductor package structure according to claim 4, wherein, The ratio of the thickness T2 of the heat dissipation structure to the spacing D1 between the first substrate and the second substrate ranges from 0.3 to 0.

5.

6. The semiconductor package structure according to claim 4, wherein The thickness T2 of the heat dissipation structure ranges from 5μm to 40μm.

7. The semiconductor package structure according to claim 4, wherein, The spacing D2 between the heat dissipation structure and the second substrate is not greater than 40μm.

8. The semiconductor package structure according to claim 3, wherein, The heat dissipation structure includes one of diamond material, silicon material or copper material.

9. The semiconductor package structure according to claim 1, wherein The first encapsulation body further includes an encapsulation layer, and a conductive structure located in the encapsulation layer, the encapsulation layer filling between the first substrate and the second substrate, surrounding and encapsulating the first chip, the conductive structure being disposed on the peripheral side of the first chip, electrically connecting the first substrate and the second substrate.

10. The semiconductor package structure according to claim 9, wherein, A first wiring layer is provided in the first substrate, the first lower surface of the first chip being electrically connected to the first wiring layer, the first lower surface being the surface of the first chip close to the first substrate; a second wiring layer is provided in the second substrate, the first wiring layer being electrically connected to the second wiring layer through the conductive structure.

11. The semiconductor package structure according to claim 3, wherein The semiconductor encapsulation structure further includes a heat dissipation structure, the heat dissipation structure being located on the side of the second substrate away from the first substrate, in the direction perpendicular to the surface of the first substrate, the vertical projection of the first chip on the first substrate and the vertical projection of the heat dissipation structure on the first substrate at least partially overlap.

12. The semiconductor package structure according to claim 3, wherein, The semiconductor encapsulation structure further includes a heat dissipation structure, the heat dissipation structure penetrating through the second substrate, contacting the first upper surface of the first chip, and extending to cover the first upper surface, in the direction perpendicular to the surface of the first substrate, the vertical projection of the first chip on the first substrate and the vertical projection of the heat dissipation structure on the first substrate at least partially overlap.

13. The semiconductor package structure according to claim 3, wherein, The semiconductor encapsulation structure further includes a heat dissipation structure, the heat dissipation structure penetrating through the second substrate, and maintaining a preset spacing from the first upper surface of the first substrate, in the direction perpendicular to the surface of the first substrate, the vertical projection of the first chip on the first substrate and the vertical projection of the heat dissipation structure on the first substrate at least partially overlap.

14. The semiconductor package structure according to claim 3, wherein, The semiconductor package structure further includes a heat dissipation structure. The second substrate includes a groove, and the heat dissipation structure fills the groove. Wherein, the groove does not penetrate through the second substrate, and in a direction perpendicular to the surface of the first substrate, the vertical projection of the first chip on the first substrate and the vertical projection of the heat dissipation structure on the first substrate at least partially overlap.

15. A semiconductor module, characterized in that, The semiconductor module includes the semiconductor package structure according to any one of claims 1-14.

16. An electronic device, characterized in that, The electronic device includes the semiconductor package structure according to any one of claims 1-14.

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