High power conversion circuit with integrated bootstrap diode

Abstract

A circuit for providing alternating signals to a switching node. The circuit comprises three power transistors, two capacitors and two gate drivers. The first transistor and the second transistor are connected in series, and the switching node is connected between the transistors. When the first transistor is turned on and the second transistor is turned off, a high voltage is provided to the switching node via the first transistor. When the first transistor is turned off and the second transistor is turned on, a low voltage is provided to the switching node via the second transistor. The transistor is controlled via a gate driver. The charge is supplied to the gate driver via the capacitor. The capacitors are charged via the intermediate power source, and the third power transistor is connected in a diode configuration between the two capacitors. The circuit is capable of withstanding a high voltage difference across the transistor and can be implemented monolithically on the same epitaxial stack.

Description

Background Art

[0001] Electronic circuits typically include transistors that act as electronic switches for regulating or controlling current in part of a circuit. One type of transistor is a field-effect transistor, in which a voltage is applied to a gate terminal to turn the transistor on and off. A semiconductor channel region is disposed between a drain terminal and a source terminal. When the transistor is on, current flows through the semiconductor channel region between the source terminal and the drain terminal. When the transistor is off, little or no current flows through the semiconductor channel region between the source terminal and the drain terminal. The gate terminal is disposed over the semiconductor channel region between the source terminal and the drain terminal. The voltage on the gate terminal generates an electric field that affects whether the semiconductor channel region conducts current, hence the term "field-effect transistor".

[0002] Silicon has traditionally been used to make transistors. However, semiconductor materials with a wider bandgap can be used to make transistors that conduct higher power and operate at a higher efficiency than silicon transistors. Silicon carbide (SiC), aluminum nitride (AlN), zinc oxide (ZnO), and gallium nitride (GaN) are all examples of wide-bandgap semiconductor materials that can be used in power electronic devices. One way to use such wide-bandgap semiconductor materials is to form two different semiconductor materials to form a heterojunction therebetween.

[0003] The two semiconductor materials can have sufficiently different bandgaps such that when brought together, the bandgap of the junction just drops below the Fermi level within the channel layer. This means that electrons can flow freely within this region. This region is thin in depth and forms a plane parallel to the upper surface of the channel region. Therefore, this region is referred to as the "2DEG" region to emphasize its planar form. Additionally, due to the high mobility of electrons in this region, this region is also referred to as the 2DEG "electron sea". Thus, the 2DEG region is highly conductive. The 2DEG region can form the channel region of a power semiconductor to allow high current with a relatively low resistance to pass through. A field-effect transistor using such a 2DEG is called a "high electron mobility transistor" (or HEMT).

[0004] The subject matter claimed herein is not limited to embodiments that solve any disadvantages or operate only in environments such as those described above. Instead, this background is provided only to illustrate an example technical field in which some embodiments described herein may be practiced. Summary of the Invention

[0005] The embodiments described herein relate to a conversion circuit for providing an alternating signal. The conversion circuit can be used to control high voltage and high current and can also be monolithically implemented on the same chip, thereby allowing the circuit to be compact. By way of example only, the alternating signal can alternate between a high voltage (e.g., several hundred volts) and a low voltage (e.g., ground). The circuit includes two power transistors connected in series between a high voltage power supply (e.g., providing several hundred volts) and a low voltage power supply (e.g., providing ground). The power transistor connected to the high voltage power supply can be referred to as the "high" power transistor, while the power transistor connected to the low power supply can be referred to as the "low" power transistor.

[0006] Accordingly, by alternately turning on and off which power transistor, an alternating signal is applied to the output node of the conversion circuit, which is located between the two power transistors. The high power transistor has a gate driver (referred to as the "high" gate driver) that controls whether the high power transistor is turned on or off. On the other hand, the low power transistor has a low gate driver (referred to as the "low" gate driver) that controls whether the low power transistor is turned on or off. A capacitor ("high" capacitor) is connected between the upper voltage supply node and the lower voltage supply node of the high gate driver. Another capacitor ("low" capacitor) is connected between the upper voltage supply node and the lower voltage supply node of the low gate driver. The capacitors for the respective gate drivers operate to maintain a consistent voltage difference between the upper voltage supply node and the lower voltage supply node of the respective gate drivers.

[0007] To charge the low capacitor, an intermediate power supply (e.g., providing +6 volts, or sometimes referred to as Vdd) is connected to the upper voltage supply node of the low gate driver and to the upper terminal of the low capacitor. In addition, a low voltage power supply (e.g., ground, or sometimes referred to as Vss) is connected to the lower voltage supply node of the low gate driver. Accordingly, the low gate driver is powered.

[0008] On the other hand, the high capacitor is used to provide a stable voltage difference between the upper voltage supply node and the lower supply node of the high gate driver. The lower voltage supply node of the high gate driver is connected to the lower terminal of the high capacitor and to the output node of the conversion circuit. Accordingly, an alternating signal is provided to the lower voltage supply node of the high gate driver. As long as the voltage at the upper voltage supply node also alternates in a similar manner to maintain an appropriate voltage difference. This is achieved by connecting the upper terminal of the high capacitor to the upper voltage supply node of the high gate driver and also by connecting a third power transistor in a diode configuration, where the forward bias direction is from the intermediate power supply to the upper terminal of the high capacitor.

[0009] Accordingly, during the transition dead time when both the high-power transistor and the low-power transistor are turned off, the upper terminal of the high capacitor receives charge from the intermediate power supply via the forward-biased third power transistor. On the other hand, when the alternating signal provided at the output node of the conversion circuit is high, the third power transistor is reverse-biased with a relatively high high voltage difference, the magnitude of which is the difference between the high voltage power supply (e.g., providing several hundred volts) and the low voltage power supply (e.g., providing ground). However, the third power transistor can withstand such a high reverse-biased voltage difference.

[0010] This ability to withstand such high reverse-biased voltages can be achieved by making each of the three power transistors from a semiconductor material (e.g., gallium nitride) that allows a high voltage difference between its respective drain and source nodes. Additionally, each power transistor can be made from the same semiconductor material and can thus also be monolithically constructed in the same epitaxial stack. In some embodiments, the gate driver and capacitor can also be constructed on the same epitaxial stack. Accordingly, the circuit (or at least most of the circuit) can be monolithically constructed and can thus be compact while allowing the circuit to manage high voltages and currents.

[0011] Additional features and advantages will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the teachings herein. The features and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims. The features of the invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] To describe the manner in which the advantages and features of the circuits, systems, and methods described herein can be obtained, a more specific description of the embodiments outlined herein will be presented by reference to the specific embodiments illustrated in the drawings. It should be understood that these drawings only depict typical embodiments of the circuits, systems, and methods described herein and should not be considered as limiting their scope. Certain circuits, systems, and methods will be described and explained with additional specificity and detail by using the drawings, wherein:

[0013] Figure 1 A conversion circuit is illustrated in which the principles described herein can be practiced, and is only one example of a circuit consistent with the principles described herein; and

[0014] Figure 2 A signal diagram is illustrated that shows an example of a signal representing the voltage at various locations in the conversion circuit representing Figure 1 of. DETAILED DESCRIPTION

[0015] The embodiments described herein relate to a conversion circuit for providing an alternating signal. The conversion circuit can be used to control high voltage and high current and can also be monolithically implemented on the same chip, thereby allowing the circuit to be compact. By way of example only, the alternating signal can alternate between a high voltage (e.g., several hundred volts) and a low voltage (e.g., ground). The circuit includes two power transistors connected in series between a high voltage power supply (e.g., providing several hundred volts) and a low voltage power supply (e.g., providing ground). The power transistor connected to the high voltage power supply can be referred to as the "high" power transistor, while the power transistor connected to the low power supply can be referred to as the "low" power transistor.

[0016] Accordingly, by alternately turning on and off which power transistor, an alternating signal is applied to the output node of the conversion circuit, which is located between the two power transistors. The high power transistor has a gate driver (referred to as the "high" gate driver) that controls whether the high power transistor is on or off. On the other hand, the low power transistor has a low gate driver (referred to as the "low" gate driver) that controls whether the low power transistor is on or off. A capacitor ("high" capacitor) is connected between the upper voltage supply node and the lower voltage supply node of the high gate driver. Another capacitor ("low" capacitor) is connected between the upper voltage supply node and the lower voltage supply node of the low gate driver. The capacitors for the respective gate drivers operate to maintain a consistent voltage difference between the upper voltage supply node and the lower voltage supply node of the respective gate drivers.

[0017] To charge the low capacitor, an intermediate power supply (e.g., providing +6 volts, or sometimes referred to as Vdd) is connected to the upper voltage supply node of the low gate driver and to the upper terminal of the low capacitor. In addition, a low voltage power supply (e.g., ground, or sometimes referred to as Vss) is connected to the lower voltage supply node of the low gate driver. Accordingly, the low gate driver is powered.

[0018] On the other hand, the high capacitor is used to provide a stable voltage difference between the upper voltage supply node and the lower supply node of the high gate driver. The lower voltage supply node of the high gate driver is connected to the lower terminal of the high capacitor and to the output node of the conversion circuit. Accordingly, an alternating signal is provided to the lower voltage supply node of the high gate driver. As long as the voltage at the upper voltage supply node also alternates in a similar manner to maintain an appropriate voltage difference f. This is achieved by connecting the upper terminal of the high capacitor to the upper voltage supply node of the high gate driver and also by connecting a third power transistor in a diode configuration, where the forward bias direction is from the intermediate power supply to the upper terminal of the high capacitor.

[0019] Accordingly, during the transition dead time when both the high-power transistor and the low-power transistor are turned off, the upper terminal of the high capacitor receives charge from the intermediate power supply via the forward-biased third power transistor. On the other hand, when the alternating signal provided at the output node of the conversion circuit is high, the third power transistor is reverse-biased with a relatively high high voltage difference, the magnitude of which is the difference between the high voltage power supply (e.g., providing several hundred volts) and the low voltage power supply (e.g., providing ground). However, the third power transistor can withstand such a high reverse-biased voltage difference.

[0020] This ability to withstand such high reverse-biased voltages can be achieved by making each of the three power transistors from a semiconductor material (e.g., gallium nitride) that allows a high voltage difference between its respective drain and source nodes. Additionally, each power transistor can be made from the same semiconductor material and can thus also be monolithically constructed in the same epitaxial stack. In some embodiments, the gate driver and the capacitor can also be constructed on the same epitaxial stack. Accordingly, the circuit (or at least most of the circuit) can be monolithically constructed and can thus be compact while allowing the circuit to manage high voltages and currents.

[0021] Figure 1 The conversion circuit 100 is illustrated in which the principles described herein can be practiced and is merely one example of a circuit consistent with the principles described herein. The conversion circuit 100 provides an alternating signal at the output node 101. By way of example only, the alternating signal can alternate between a high voltage (e.g., several hundred volts) and a low voltage (e.g., ground). The conversion circuit 100 includes two power transistors 110 and 120 connected in series, and the output node 101 is connected between the two power transistors.

[0022] The power transistor 110 has a gate node 111 that controls whether current flows between the drain node 112 and the source node 113 of the power transistor 110. Similarly, the power transistor 120 has a gate node 121 that controls whether current flows between the drain node 122 and the source node 123 of the power transistor 120. In this specification and the claims, a "power transistor" is a transistor that is capable of transmitting more than 1 watt of power when turned on. In one example, each of the power transistors 110 and 120 can be a field effect transistor capable of having a drain-to-source voltage of at least 50 volts (when turned off). However, the principles described herein are not limited to the power transistors 110 and 120 being any particular type of transistor. The source node 113 of the power transistor 110 and the drain node 122 of the power transistor 120 are connected together, and the output node 101 is connected between these two nodes. By way of example, an external device (not shown) can be connected to the output node 101 and can thus draw charge from the output node 101.

[0023] As described above, the conversion circuit 100 is configured to provide an alternating signal at the output node 101. The alternating signal provided to the output node 101 can alternate between a high voltage (e.g., several hundred volts) and a low voltage (e.g., ground). To achieve this, a power supply can be connected to the power terminals 102 and 103 of the conversion circuit 100. More specifically, a high-voltage power supply (e.g., providing several hundred volts) can be connected to the drain node 112 of the power transistor 110 via the power terminal 102. Thus, the power transistor 110 can be referred to herein as the "high" power transistor 110. In addition, a low-voltage power supply (e.g., providing ground) can be connected to the source node 123 of the power transistor 120 via the power terminal 103. Thus, the power transistor 120 can be referred to herein as the "low" power transistor 120. In addition, to prevent confusion, hereinafter the "high" power transistor 110 will be simply referred to as the "high transistor", and hereinafter the "low" power transistor 120 will be simply referred to as the "low transistor".

[0024] In any case, when the high transistor 110 is turned on and the low transistor 120 is turned off, the high-voltage power supply provides a high voltage to the output node 101 via the high transistor 110. On the other hand, when the high transistor 110 is turned off and the low transistor 120 is turned on, the low-voltage power supply provides a low voltage to the output node 101 via the low transistor 120.

[0025] The conversion circuit 100 further includes two gate drivers 130 and 140. The gate driver 130 controls the on / off state of the high transistor 110 and is thus referred to herein as the "high" gate driver 130. Similarly, the gate driver 140 controls the on / off state of the low transistor 120 and is thus referred to herein as the "low" gate driver 140. More specifically, the high gate driver 130 has an output node 131 connected to the gate node 111 of the high transistor 110. Similarly, the low gate driver 140 has an output node 141 connected to the gate node 121 of the low transistor 120.

[0026] As shown in the figure, the controller 150 provides an input signal to the high gate driver 130 via the data input node 132, and then this input signal turns the high transistor 110 on or off. Similarly, the controller 160 provides an input signal to the low gate driver 140 via the data input node 142, and then this input signal turns the low transistor 120 on or off. The controllers 150 and 160 jointly coordinate the switching of each of the high transistor 110 and the low transistor 120 and can be considered as a single controller. An example of such coordination is shown in Figure 2 and will be further discussed later.

[0027] The conversion circuit 100 further includes two capacitors 170 and 180. The capacitor 170 is connected between the voltage supply nodes of the high gate driver 130 and is thus referred to herein as the "high" capacitor 170. The capacitor 180 is connected between the voltage supply nodes of the low gate driver 140 and is thus referred to herein as the "low" capacitor 180. Specifically, the high capacitor 170 is connected between the low voltage supply node 133 and the high voltage supply node 134 of the high gate driver 130. The high capacitor 170 is charged to maintain a relatively constant voltage difference between the upper voltage supply node 134 and the lower voltage supply node 133 of the high gate driver 130, thereby powering the high gate driver 130. The low capacitor 180 is connected between the low voltage supply node 143 and the high voltage supply node 144 of the low gate driver 140. Similarly, the low capacitor 180 is charged to maintain a relatively constant voltage difference between the upper voltage supply node 144 and the lower voltage supply node 143 of the low gate driver 140, thereby powering the low gate driver 140.

[0028] The lower voltage supply node 133 of the high gate driver 130 and the lower terminal 171 of the high capacitor 170 are connected to the source node 113 of the high transistor 110 (and thus to the output node 101). On the other hand, the lower voltage supply node 143 of the low gate driver 140 and the lower terminal 181 of the low capacitor 180 are connected to the source node 123 of the low transistor 120 (and thus to the low voltage power supply).

[0029] An intermediate power supply (e.g., providing +6 volts) is connected to the upper voltage supply node 144 of the low gate driver 140 and to the upper terminal 182 of the low capacitor 180 via the power terminal 104. Accordingly, this intermediate power supply supplies charge to the low capacitor 180 and the low gate driver 140 such that the low gate driver 140 can consistently control the low transistor 120. For example, in the case of a low voltage power supply providing ground and an intermediate power supply providing +6 volts, the low capacitor 180 will be charged to have a voltage difference of 6 volts between its upper terminal 182 and its lower terminal 181. Thus, in this case, depending on the control signal from the controller 160, the low gate driver 140 can provide (+6 volts, e.g., the on voltage) from its upper voltage supply node 144 to the gate node 121 of the low transistor 120, or provide ground (e.g., the off voltage) from its lower voltage supply node 143.

[0030] On the other hand, the high capacitor 170 is used to provide a stable voltage difference between the upper voltage supply node 134 and the lower voltage supply node 133 of the high gate driver 130, thereby powering the high gate driver 130. When an alternating signal is provided to the output node 101, the alternating signal is also provided to the lower voltage supply node 133 of the high gate driver 130. As long as the voltage at the upper voltage supply node 134 also alternates in a similar manner so as to maintain an appropriate voltage difference between the upper voltage supply node 134 and the lower voltage supply node 133 of the high gate driver 130. This is achieved via the high capacitor 170 and by supplying charge to the upper terminal 172 of the high capacitor 170 through the third power transistor 190 connected in a diode configuration, where the forward bias direction is from the intermediate power supply to the upper terminal 172 of the high capacitor 170.

[0031] Specifically, the drain node 192 of the third power transistor 190 is connected to the upper terminal 172 of the high capacitor 170, and the source node 193 of the third power transistor 190 is connected to the upper terminal 182 of the low capacitor 180. In addition, the third power transistor 190 is connected such that the source node 193 serves as the anode of the diode and the drain node 192 serves as the cathode of the diode. That is, the third power transistor 190 serves as a diode. In addition, since the third power transistor 190 is a power transistor, it has a high reverse breakdown voltage of, for example, several hundred volts or higher.

[0032] There are various ways to connect the third power transistor 190 in a "diode configuration". For example, in Figure 1 , the gate node 191 of the third power transistor 190 is connected to the source node 193 of the third power transistor 190, thereby showing one way in which the third power transistor 190 can be connected in a diode configuration. The functionality of the conversion circuit 100 will be described as if the third power transistor 190 is connected as illustrated in Figure 1 .

[0033] In operation, when the voltage at the drain node 192 of the third power transistor 190 is at least lower than the voltage at the source node 192 of the third power transistor 190 by the threshold voltage of the third power transistor 190, the third power transistor 190 conducts and allows charge to flow from the intermediate power supply to the upper terminal 172 of the high capacitor 170. By way of example only, this can occur during the "conversion dead time" when each of the high transistor 110 and the low transistor 120 is turned off, as will be explained later with respect to Figure 2 .

[0034] On the other hand, when the voltage at the drain node 192 is at least not lower than the threshold voltage of the voltage at the source node 193 of the third power transistor 190, the third power transistor 190 blocks the current from flowing from the intermediate power supply to the upper terminal 172 of the high capacitor 170. In fact, when the voltage at the drain node 192 is several hundred volts higher than the voltage at the source node 193, the third power transistor 190 can even block the current flow.

[0035] As described above, each of the high transistor 110, the low transistor 120, and the third power transistor 190 is a power transistor capable of withstanding a voltage difference of several hundred volts or higher (when off) between its corresponding drain node and source node. This can be achieved by making each of the high transistor 110, the low transistor 120, and the third power transistor 190 from a semiconductor material that allows a high voltage difference (such as gallium nitride, silicon carbide, or gallium arsenide). In addition, each of the high transistor 110, the low transistor 120, and the third power transistor 190 can be made from the same semiconductor material, and thus can also be monolithically constructed on several parts of the same epitaxial stack. In fact, the third power transistor 190 can be a finger transistor of one of the high transistor 110 or the low transistor 120. In some embodiments, other components of the circuit 100 (e.g., the high gate driver 130, the low gate driver 140, the high capacitor 170, and the low capacitor 180) can also be constructed on the same epitaxial stack. Accordingly, the conversion circuit 100 (or at least part of the conversion circuit 100) can be monolithically constructed on the same epitaxial stack, and thus can be compact while allowing the conversion circuit 100 to be used for high-power applications.

[0036] To more specifically explain how and when charge is provided to the upper terminal 172 of the high capacitor 170 via the third power transistor 190, reference will now be made to Figure 2 explain the operation of the conversion circuit 100. Figure 2 A signal chart 200 is illustrated, which shows an example of a signal representing the voltage at various positions in the conversion circuit 100.

[0037] Four signals 201, 202, 203, and 204 are illustrated, provided only by way of example. The horizontal axis represents time passing from left to right, where the same horizontal position in each of the four signals 201, 202, 203, and 204 represents the same time. The vertical axis of each corresponding signal 201, 202, 203, and 204 represents the amplitude of the corresponding signal. The time is divided into time periods T1 to T10.

[0038] The signal 201 represents the gate control voltage output by the high gate driver 130 to the gate node 111 of the high transistor 110. When the signal 201 is high (e.g., approximately positive 6 volts, see time periods T3 and T7), the high transistor 110 is turned on, and when the signal 201 is low (e.g., approximately zero volts, see time periods T1, T2, T4, T5, T6, T8, T9, and T10), the high transistor 110 is turned off. Similarly, the signal 202 represents the gate control voltage output by the low gate driver 140 to the gate node 121 of the low transistor 120. When the signal 202 is high (see time periods T1, T5, and T9), the low transistor 120 is turned on, and when the signal 202 is low (see time periods T2, T3, T4, T6, T7, T8, and T10), the low transistor 120 is turned off. Note that each of the high transistor 110 and the low transistor 120 is turned off during the time periods T2, T4, T6, T8, and T10. These time periods during which both the high transistor 110 and the low transistor 120 are turned off are referred to herein as "transition dead times". Recall that charging of the high capacitor 170 may occur during this transition dead time.

[0039] The signal 203 represents the voltage at the output node 101. The signal 204 represents the voltage at the upper terminal 172 of the high capacitor 170. For purposes of explanation, it is assumed that each of the high capacitor 170 and the low capacitor 180 has been charged prior to time T1 to have a voltage difference of approximately 6 volts between its respective upper and lower terminals. Additionally, it is assumed that the third power transistor 190 has a gate-to-drain threshold voltage of approximately 2 volts. Additionally, it is assumed that the high voltage power supply provides +400 volts, the low voltage power supply provides ground, and the intermediate power supply provides +6 volts. However, the principles described herein are not limited to the voltages provided by the power supplies connected to the circuit 100, and are not limited to the threshold voltages of the transistors 110, 120, and 190.

[0040] During the time period T1, the high transistor 110 is turned off (due to the low signal 201), while the low transistor 120 is turned on (due to the high signal 202). Thus, approximately zero volts is provided to the output node 101 from the low voltage power supply via the low transistor 120 (see signal 203). Since the high capacitor 170 has been charged to have a voltage difference of approximately 6 volts, and the lower terminal 171 of the high capacitor 170 is at approximately zero volts, the upper terminal 172 of the high capacitor 170 is at approximately +6 volts (see signal 204). Thus, during the time period T1, the voltage at the drain node 192 is approximately the same as the voltages at the connected gate node 191 and source node 193, and the third power transistor 190 is turned off. This is repeated during the time periods T5 and T9.

[0041] During time period T2, the high transistor 110 remains off (due to the low signal 201), and the low transistor 120 is cut off (due to the low signal 202). In this case, even though the output node 101 is not supplied with a high voltage or a low voltage, the components or circuits (not shown) connected to the output node 101 continue to draw current from the output node 101. This causes the voltage at the output node 101 to drop to approximately minus 2 volts (see signal 203). The voltage drop at the output node 101 is limited by the gate-to-drain threshold voltage of the low transistor 120 (e.g., 2 volts). That is, if the voltage at the output node 101 drops below the gate-to-drain threshold voltage of the low transistor 120, then the low transistor 120 conducts, and just enough charge is supplied to the output node 101 via the low transistor 120 to stabilize the output node 101 at approximately minus 2 volts.

[0042] In any case, since the voltage at the lower terminal 171 of the high capacitor 170 drops by approximately 2 volts, this also causes a corresponding voltage drop at the upper terminal 172, thus causing the voltage at the upper terminal 172 to drop from 6 volts to approximately 4 volts (see signal 204 in time T2). Accordingly, the voltage at the upper terminal 172 of the high capacitor 170, and thus the voltage at the drain node 192, drops to approximately the gate-to-drain threshold voltage below the voltage at the source node 193, and the third power transistor 190 conducts just enough to allow some current to flow to maintain the voltage at the upper terminal 172 at 4 volts in this example. Therefore, during the time period T2, which is a conversion pause time period, charge is supplied from the intermediate power supply to the upper terminal 172 of the high capacitor 170 via the third power transistor 190. This is repeated during time periods T6 and T10.

[0043] During time period T3, the low transistor 120 remains off (due to the low signal 202), and the high transistor 110 conducts (due to the high signal 201). Therefore, +400 volts from the high voltage power supply is supplied to the output node 101 via the high transistor 110 (see signal 203). Since the high capacitor 170 has been charged to have a voltage difference of approximately 6 volts, this causes the upper terminal 172 of the high capacitor 170 to rise to approximately +406 volts (see signal 204). Therefore, the voltage at the drain node 193 of the third power transistor 190 is approximately 400 volts higher than the voltage at the source node 192 of the third power transistor 190, and thus the third power transistor 190 turns off and is severely reverse-biased. Accordingly, during time period T3, the third power transistor 190 blocks the current and protects the conversion circuit 100. This is repeated during time period T7.

[0044] During time period T4, the low transistor 120 remains off (due to the low signal 202), and the high transistor is cut off (due to the low signal 201). In this case, even though the output node 101 is not supplied with a high voltage or a low voltage, the components or circuits (not shown) connected to the output node 101 continue to draw current from the output node 101. If this current consumption is large enough, the behavior of the conversion circuit 100 during time period T4 will be similar to its behavior during time period T2, and the voltage at the output node 101 will again drop to several volts below ground (see signal 203). In this case, the voltage at the upper terminal 172 of the high capacitor 170, and thus the voltage at the drain node 192 of the third power transistor 190, can again drop to at least below the threshold voltage of the voltage at the source node 193 of the power transistor 190. Therefore, the third power transistor 190 can conduct again and allow charge to be supplied from the intermediate power supply to the upper terminal 172 of the capacitor 170. This is repeated during time period T8.

[0045] As a side note, the voltage at the output node 101 will just be at about 400 volts provided by the high voltage power supply during time period T3. Therefore, it may take more time for the voltage at the output node 101 to drop all the way to -2 volts. Accordingly, the current drawn from the output node 101 during time period T4 will make it less likely for the voltage at the output node 101 to drop all the way to -2 volts within a given time period. Therefore, the third power transistor 190 is less likely to conduct during time period T4 compared to during time period T2. Of course, the likelihood of the output node 101 dropping all the way to -2 volts will increase as the dwell time allowed for time period T4 becomes longer.

[0046] In any case, as Figure 1 and Figure 2 shown, the conversion circuit 100 ensures that the high capacitor 170 is fully charged during the dwell time periods T2, T4, T6, T8, and T10. Therefore, the conversion circuit 100 allows a consistent charge supply to the high gate driver 130, and thus to the gate node 111 of the high transistor 110. Additionally, using the third power transistor 190 in a diode configuration to achieve such recharge of the high capacitor 170 prevents damage to the conversion circuit 100, thus allowing the conversion circuit 100 to operate at high voltages and high currents. Furthermore, most of the conversion circuit 100 can be implemented monolithically, thus allowing the conversion circuit 100 to be compact.

[0047] Text support section

[0048] Clause 1. A conversion circuit for providing an alternating signal at a conversion node, the conversion circuit comprising: a first power transistor having a gate node that controls whether current flows between a drain node and a source node of the first power transistor, the first power transistor at least partially forming a first part of an epitaxial stack; a first gate driver having an output node connected to the gate node of the first power transistor, a first voltage supply node connected to the source node of the first power transistor, and a second voltage supply node; a first capacitor connected between the first voltage supply node and the second voltage supply node of the first gate driver; a second power transistor having a gate node that controls whether current flows between a drain node and a source node of the second power transistor, the drain node of the second power transistor being connected to the source node of the first power transistor, the conversion node being connected between the source node of the first power transistor and the drain node of the second power transistor, the second power transistor at least partially forming a second part of the epitaxial stack; a second gate driver having an output node connected to the gate node of the second power transistor, a first voltage supply node connected to the source node of the second power transistor, and a second voltage supply node; a second capacitor connected between the first voltage supply node and the second voltage supply node of the second gate driver; and a third power transistor having a gate node that controls whether current flows between a drain node and a source node of the third power transistor, the drain node of the third power transistor being connected to the second voltage supply node of the first gate driver, the source node of the third power transistor being connected to the second voltage supply node of the second gate driver, the third power transistor being in a diode configuration such that there is a forward bias direction from the source node to the drain node of the third power transistor, the third power transistor at least partially forming a third part of the epitaxial stack.

[0049] Clause 2. The conversion circuit according to Clause 1, wherein the third power transistor is in the diode configuration by connecting the gate node of the third power transistor to the source node of the third power transistor.

[0050] Clause 3. The conversion circuit according to Clause 1, wherein the epitaxial stack is epitaxially grown on a substrate along an epitaxial growth direction, the epitaxial stack includes a channel layer and a barrier layer epitaxially grown on the channel layer, an interface between the barrier layer and the channel layer defines a heterojunction of an induced two-dimensional electron gas (2DEG) within the channel layer, and the 2DEG extends perpendicular to the epitaxial growth direction.

[0051] Clause 4. The conversion circuit according to Clause 3, wherein the channel layer includes gallium nitride (GaN), and the barrier layer includes aluminum gallium nitride (AlGaN).

[0052] Clause 5. The conversion circuit according to Clause 1, the circuit further includes: a first power terminal connected to the drain node of the first power transistor, the first power terminal being configured to receive power from a first external power supply; a second power terminal connected to the source node of the second power transistor, the second power terminal being configured to receive power from a second external power supply; and a third power terminal connected to the source node of the third power transistor, the third power terminal being configured to receive power from a third external power supply.

[0053] Clause 6. The conversion circuit according to Clause 5, wherein the first external power supply provides at least +50 volts.

[0054] Clause 7. The conversion circuit according to Clause 5, wherein the second external power supply provides ground.

[0055] Clause 8. The conversion circuit according to Clause 5, wherein the third external power supply is configured to provide a gate voltage to a second voltage supply node of the first gate driver, and is configured to provide a portion of the gate voltage to the second voltage supply node of the second gate driver via the third power transistor.

[0056] Clause 9. The conversion circuit according to Clause 8, wherein the gate voltage is between +4.5 volts and +7 volts.

[0057] Clause 10. The conversion circuit according to Clause 5, the circuit further includes a controller configured to control each of the first gate driver and the second gate driver such that: during a first time period, the first power transistor is turned off and the second power transistor is turned on, so that the conversion node receives power from the second external power supply via the second power transistor; during a second time period, the first power transistor is turned off and the second power transistor is turned off, so that current is drawn from the conversion node via a component connected to the conversion node, thereby causing the voltage at the conversion to decrease, and thereby causing the voltage at the drain node of the third power transistor to decrease to at least the threshold voltage of the third power transistor lower than the voltage present at the connected gate node and source node of the third power transistor, so that the third power transistor allows current to flow from the source node of the third power transistor to the drain node, thereby replenishing charge to the first capacitor; during a third time period, the second power transistor is turned off and the first power transistor is turned on, so that the conversion node receives power from the first external power supply via the first power transistor, and so that the third power transistor prevents current from flowing from the drain node of the third power transistor to the source node; and during a fourth time period, the second power transistor is turned off and the first power transistor is turned off, so that current is drawn from the conversion node via the component connected to the conversion node, thereby causing the voltage at the conversion node to decrease, and thereby causing the voltage at the drain node of the third power transistor to decrease to at least the threshold voltage of the third power transistor lower than the voltage present at the connected gate node and the source node of the third power transistor, so that the third power transistor allows current to flow from the source node of the third power transistor to the drain node, thereby replenishing charge to the first capacitor.

[0058] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the features or acts described above, or the order of the above acts. On the contrary, the described features and acts are disclosed as example forms for implementing the claims.

[0059] The present disclosure may be implemented in other specific forms without departing from its basic features. The described embodiments are to be considered in all respects as illustrative and not restrictive. All changes within the meaning and range of equivalence of the claims are included within their scope.

[0060] When introducing an element in the appended claims, the articles "a", "an", "the", and "said" are intended to mean that there is one or more than one element. The terms "comprising", "including", and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements.

Claims

1. A conversion circuit for providing an alternating signal at a conversion node, the conversion circuit comprising: A first power transistor having a gate node that controls whether current flows between a drain node and a source node of the first power transistor, the first power transistor at least partially forming a first part of an epitaxial stack; A first gate driver having an output node connected to the gate node of the first power transistor, a first voltage supply node connected to the source node of the first power transistor, and a second voltage supply node; A first capacitor connected between the first voltage supply node of the first gate driver and the second voltage supply node of the first gate driver; A second power transistor having a gate node that controls whether current flows between a drain node and a source node of the second power transistor, the drain node of the second power transistor being connected to the source node of the first power transistor, the conversion node being connected between the source node of the first power transistor and the drain node of the second power transistor, the second power transistor at least partially forming a second part of the epitaxial stack; A second gate driver having an output node connected to the gate node of the second power transistor, a first voltage supply node connected to the source node of the second power transistor, and a second voltage supply node; A second capacitor connected between the first voltage supply node of the second gate driver and the second voltage supply node of the second gate driver; And A third power transistor having a gate node that controls whether current flows between a drain node and a source node of the third power transistor, the drain node of the third power transistor being connected to the second voltage supply node of the first gate driver, the source node of the third power transistor being connected to the second voltage supply node of the second gate driver, the third power transistor being in a diode configuration so as to have a forward bias direction from the source node of the third power transistor to the drain node of the third power transistor, the third power transistor at least partially forming a third part of the epitaxial stack.

2. The conversion circuit according to claim 1, wherein the third power transistor is in the diode configuration by connecting the gate node of the third power transistor to the source node of the third power transistor.

3. The conversion circuit according to claim 1, wherein the epitaxial stack is epitaxially grown on a substrate along an epitaxial growth direction, the epitaxial stack includes a channel layer and a barrier layer epitaxially grown on the channel layer, an interface between the barrier layer and the channel layer defines a heterojunction of an induced two-dimensional electron gas (2DEG) within the channel layer, and the 2DEG extends perpendicular to the epitaxial growth direction.

4. The conversion circuit according to claim 3, wherein the channel layer includes gallium nitride (GaN), and the barrier layer includes aluminum gallium nitride (AlGaN).

5. The conversion circuit according to claim 1, the circuit further includes: A first power terminal connected to the drain node of the first power transistor, the first power terminal being configured to receive power from a first external power source; A second power terminal connected to the source node of the second power transistor, the second power terminal being configured to receive power from a second external power source; And A third power terminal connected to the source node of the third power transistor, the third power terminal being configured to receive power from a third external power source.

6. The conversion circuit according to claim 5, wherein the first external power source provides at least +50 volts.

7. The conversion circuit according to claim 5, wherein the second external power source provides ground.

8. The conversion circuit according to claim 5, wherein the third external power source is configured to provide a gate voltage to the second voltage supply node of the first gate driver and is configured to provide a portion of the gate voltage to the second voltage supply node of the second gate driver via the third power transistor.

9. The conversion circuit according to claim 8, wherein the gate voltage is between +4.5 volts and +7 volts.

10. The conversion circuit according to claim 5, the circuit further includes a controller configured to control each of the first gate driver and the second gate driver such that: During a first time period, the first power transistor is turned off and the second power transistor is turned on, such that the conversion node receives power from the second external power source via the second power transistor; During a second time period, the first power transistor is turned off and the second power transistor is turned off, such that current is drawn from the conversion node via components connected to the conversion node, thereby causing the voltage at the conversion to decrease, and thereby causing the voltage at the drain node of the third power transistor to decrease to be at least the threshold voltage of the third power transistor lower than the voltages present at the gate node and the source node to which the third power transistor is connected, such that the third power transistor allows current to flow from the source node of the third power transistor to the drain node, thereby replenishing charge to the first capacitor; During a third time period, the second power transistor is turned off and the first power transistor is turned on, such that the conversion node receives power from the first external power source via the first power transistor and such that the third power transistor blocks current from flowing from the drain node of the third power transistor to the source node thereof; and During a fourth time period, the second power transistor is turned off and the first power transistor is turned off, such that current is drawn from the conversion node via the components connected to the conversion node, thereby causing the voltage at the conversion node to decrease and thereby causing the voltage at the drain node of the third power transistor to decrease to at least the threshold voltage of the third power transistor lower than the voltages present at the connected gate node and the source node of the third power transistor, such that the third power transistor allows current to flow from the source node of the third power transistor to the drain node thereof, thereby replenishing charge to the first capacitor.

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