A frequency jitter circuit

Abstract

The present invention discloses a frequency-jittering circuit, whose oscillation stage includes a comparator COMP1 and an inverter INV1. The circuit implements the function of a hysteresis comparator in response to changes in a reference voltage VREF formed by a voltage source. The reference voltage control stage includes: a fourth NMOS transistor NM4 that receives current from a fifth PMOS transistor PM5 to generate a new bias voltage; a folding input stage of a transconductance amplifier composed of PMOS transistors, connected to a further circuit voltage VM and a comparison voltage VCAP; a fourteenth PMOS transistor PM14, a third resistor R3, and a second capacitor C2 forming a reference voltage circuit for generating an oscillator reference voltage VOSCREF. The oscillator reference voltage VOSCREF is input to a cascode stage to convert the current difference of the folding input stage, achieving nearly linear transconductance amplification. The frequency-jittering function implemented by the present invention reduces noise in a switching power supply, facilitates electromagnetic compatibility, and reduces the workload of power supply designers.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and more specifically to the field of switching power supplies, in particular to a frequency jittering circuit. Background Art

[0002] Usually, when a switching power supply is working, it is easy to generate a lot of electromagnetic interference noise. If it is not suppressed, it will easily interfere with the normal operation of some equipment and circuits.

[0003] When a switching power supply operates at a fixed frequency, its noise amplitude is high, making noise suppression more difficult. In some cases, it may even be impossible to suppress it within the required range, significantly increasing design costs. Frequency jittering technology can disperse the previously concentrated noise energy over a wider spectrum, thereby reducing the noise amplitude and making electromagnetic compatibility design easier to achieve. Summary of the Invention

[0004] The purpose of the present invention is to provide a frequency jittering circuit that solves the defects of the prior art, is simple and reliable, and is suitable for CMOS technology. At the same time, the capacitance in the circuit is small, which is convenient for integration and reduces the layout area.

[0005] To achieve the above technical objectives, the present invention provides a frequency-jittering circuit, which includes an oscillator stage as a first-stage circuit STAGE1 and a reference voltage control stage as a second-stage circuit STAGE2, wherein: the oscillator stage includes: a comparator COMP1 and an inverter INV1, which cooperates with the change of the reference voltage VREF formed by the high voltage VH and the low voltage VL of the voltage source to realize the function of the hysteresis comparator, the first and second PMOS transistors PM1 and PM2 form a current mirror for proportionally replicating the current of the current source I1, the second PMOS transistor PM2 and the third PMOS transistor PM3 form a current mirror, the first and second NMOS transistors NM1 and NM2 form a current mirror, and the fourth PMOS transistor PM4 is used to control whether the current of the third PMOS transistor PM3 can flow into the comparator COMP1. a comparison voltage VCAP node; a third NMOS transistor NM3 for controlling whether the current at the comparison voltage VCAP node can flow into the second NMOS transistor NM2; the reference voltage control stage comprising: a fifth PMOS transistor PM5 as a reference current source; a fourth NMOS transistor NM4 receiving the current of the fifth PMOS transistor PM5 to generate a new bias voltage; a folding input stage of a transconductance amplifier composed of PMOS transistors and connected to other circuit voltages VM and the comparison voltage VCAP, respectively; a fourteenth PMOS transistor PM14, a third resistor R3, and a second capacitor C2 forming a reference voltage circuit for generating an oscillator reference voltage VOSCREF; the oscillator reference voltage VOSCREF is input to a common-source and common-gate stage to convert the current difference of the folding input stage to achieve almost linear transconductance amplification.

[0006] The present invention provides a frequency-jittering circuit, which provides an oscillation stage of a first-stage circuit STAGE1 and a reference voltage control stage of a second-stage circuit STAGE2. The frequency-jittering function can be realized through a simple circuit, thereby reducing the noise of a switching power supply, making it easier to achieve electromagnetic compatibility, and reducing the labor of power supply designers.

[0007] As a further improvement, the high voltage VH and the low voltage VL pass through a first transmission gate TG1 and a second transmission gate TG2 respectively, and the reference voltage VREF is controlled by the input voltage VA and the output voltage VB of the inverter INV1 .

[0008] As a further improvement, the voltage of the high voltage VH is higher than the voltage of the low voltage VL. When the comparison voltage VCAP rises from low, the input voltage VA is high, the output voltage VB is low, the first transmission gate TG1 is turned on, and the reference voltage VREF is equal to the high voltage VH; when the comparison voltage VCAP drops from high, the input voltage VA is low, the output voltage VB is high, the second transmission gate TG2 is turned on, and the reference voltage VREF is equal to the low voltage VL.

[0009] As a further improvement, the ratio of the effective width-to-length ratios of the second and third PMOS transistors PM2 and PM3 is equal to the ratio of the effective width-to-length ratios of the first and second NMOS transistors NM1 and NM2, the first, second and third PMOS transistors PM1, PM2 and PM3 have a common source to the power supply VDD and a common gate connected to the current source I1, the first and second NMOS transistors NM1 and NM2 have a common source and are grounded and a common gate and are connected to the drain of the second PMOS transistor PM2 and the drain of the first NMOS transistor NM1, and the drain of the first PMOS transistor PM1 is connected to the current source I1.

[0010] As a further improvement, the drain of the second NMOS transistor NM2 is connected to the source of the third NMOS transistor NM3, the third NMOS transistor NM3 and the fourth PMOS transistor PM4 have a common drain connected to the comparison voltage VCAP and a common gate connected to the output voltage VB, the source of the fourth PMOS transistor PM4 is connected to the drain of the third PMOS transistor PM3, and the comparison voltage VCAP is grounded via the first capacitor C1.

[0011] As a further improvement, the fifth and fourteenth PMOS transistors PM5 and PM14 have a common source connected to the power supply VDD and a gate biased, the drain of the fourteenth PMOS transistor PM14 is connected to the oscillator reference voltage VOSCREF and grounded via the third resistor R3, the second capacitor C2 is connected to the oscillator reference voltage VOSCREF and grounded, the fourth NMOS transistor NM4 and the fifth PMOS transistor PM5 have a common drain, the gate of the fourth NMOS transistor NM4 is connected to the drain and the source is grounded.

[0012] As a further improvement, the sixth, seventh, eighth, and ninth PMOS transistors PM6, PM7, PM8, and PM9 and a resistor R constitute the folding input stage of the transconductance amplifier. The sixth and seventh PMOS transistors PM6, PM7 share a common source and gate with the fifth PMOS transistor PM5. The drains of the sixth and seventh PMOS transistors PM6 and PM7 are respectively connected to the sources of the eighth and ninth PMOS transistors PM8 and PM9. The gates of the eighth and ninth PMOS transistors PM8 and PM9 are respectively connected to the other circuit voltage VM and the comparison voltage VCAP. The sixth and seventh PMOS transistors PM6 and PM7 are current sources with an effective width-to-length ratio of 1:1, which control the bias current of the folding input stage. The eighth and ninth PMOS transistors PM8 and PM9 form a differential pair with an effective width-to-length ratio of 1:1. Both ends of the resistor R are respectively connected to the drains of the sixth and seventh PMOS transistors PM6 and PM7.

[0013] As a further improvement, the fifth and sixth NMOS transistors NM5 and NM6 have a common gate and are connected to the bias node voltage VBN, the seventh and eighth NMOS transistors NM7 and NM8 have a common gate and are connected to the drain of the fifth PMOS transistor PM5 and the source is grounded, the fifth and seventh NMOS transistors NM5 and NM7 have their source and drain connected and connected to the drain of the eighth PMOS transistor PM8, the sixth and eighth NMOS transistors NM6 and NM8 have their source and drain connected and connected to the drain of the ninth PMOS transistor PM9; the tenth, eleventh, twelfth, and thirteenth PMOS transistors PM10 and PM11 have their source and drain connected. M11, PM12, and PM13 share a source with the fifth PMOS transistor PM5; the tenth and thirteenth PMOS transistors PM10 and PM13 share a gate and are connected to the drains of the tenth PMOS transistor PM10 and the fifth NMOS transistor NM5; the eleventh and twelfth PMOS transistors PM11 and PM12 share a gate and are connected to the drains of the eleventh PMOS transistor PM11 and the sixth NMOS transistor NM6, so as to convert the current difference of the folded input stage into the current difference between the tenth and eleventh PMOS transistors PM10 and PM11.

[0014] As a further improvement, the ninth and tenth NMOS transistors NM9 and NM10 are used to process the current difference of the tenth and eleventh PMOS transistors PM10 and PM11. The ninth and tenth NMOS transistors NM9 and NM10 share a gate and are connected to the drain of the twelfth PMOS transistor PM12 and the drain of the ninth NMOS transistor NM9. The thirteenth PMOS transistor PM13 and the tenth NMOS transistor NM10 share a drain and are connected to the oscillator reference voltage VOSCREF. The oscillator reference voltage VOSCREF is formed between the drains of the thirteenth and fourteenth PMOS transistors PM13 and PM14. The fifth and fourteenth PMOS transistors PM5 and PM14 share a gate and are connected to the current source I1.

[0015] As a further improvement, the gate of the fifth PMOS transistor PM5 is connected to the drain of the first PMOS transistor PM1 so as to be directly biased by the first-stage circuit STAGE1. The ratio of the effective width-to-length ratios of the tenth and thirteenth PMOS transistors PM10 and PM13 is equal to the ratio of the effective width-to-length ratios of the eleventh and twelfth PMOS transistors PM11 and PM12. The ninth and tenth NMOS transistors NM9 and NM10 form a 1:1 current mirror. The resistor R is composed of first and second resistors R1 and R2 connected in series. The resistance of the resistor R is equal to the sum of the resistances of the first and second resistors R1 and R2. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the circuit principle of the present invention;

[0017] Figure 2 Schematic diagram of the simulation of the present invention. DETAILED DESCRIPTION

[0018] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0019] like Figures 1 to 2 As shown, the present invention provides a frequency jittering circuit, which provides an embodiment with relatively set NMOS tubes and PMOS tubes, and can be correspondingly transformed according to the common sense in the field under the technical solutions and effects disclosed in the present invention.

[0020] The present invention provides a frequency-jittering circuit, which includes an oscillator stage as a first-stage circuit STAGE1 and a reference voltage control stage as a second-stage circuit STAGE2, wherein: the oscillator stage includes: a comparator COMP1 and an inverter INV1, which realizes the function of a hysteresis comparator by coordinating the change of a reference voltage VREF formed by a high voltage VH and a low voltage VL of a voltage source; a first and a second PMOS transistor PM1 and PM2 form a current mirror for proportionally replicating the current of a current source I1; the second PMOS transistor PM2 and the third PMOS transistor PM3 form a current mirror; the first and the second NMOS transistors NM1 and NM2 form a current mirror; and the fourth PMOS transistor PM4 is used to control whether the current of the third PMOS transistor PM3 can flow into the comparison voltage VC of the comparator COMP1. AP node; a third NMOS transistor NM3 is used to control whether the current at the comparison voltage VCAP node can flow into the second NMOS transistor NM2; the reference voltage control stage includes: a fifth PMOS transistor PM5 as a reference current source, a fourth NMOS transistor NM4 receiving the current of the fifth PMOS transistor PM5 to generate a new bias voltage, a folding input stage of a transconductance amplifier composed of PMOS transistors and connected to other circuit voltages VM and the comparison voltage VCAP respectively, a fourteenth PMOS transistor PM14, a third resistor R3, and a second capacitor C2 forming a reference voltage circuit for generating an oscillator reference voltage VOSCREF, the oscillator reference voltage VOSCREF input to a common-source common-gate stage to convert the current difference of the folding input stage to achieve almost linear transconductance amplification.

[0021] The present invention provides a frequency jittering circuit, which provides an oscillation stage of a first-stage circuit STAGE1 and a reference voltage control stage of a second-stage circuit STAGE2. The frequency jittering function can be realized with a simple circuit, thereby reducing the noise of a switching power supply, making it easier to achieve electromagnetic compatibility, and reducing the labor of power supply designers.

[0022] As a further improvement, the high voltage VH and the low voltage VL pass through a first transmission gate TG1 and a second transmission gate TG2 respectively, and the reference voltage VREF is controlled by the input voltage VA and the output voltage VB of the inverter INV1 .

[0023] As a further improvement, the voltage of the high voltage VH is higher than the voltage of the low voltage VL. When the comparison voltage VCAP rises from low, the input voltage VA is high, the output voltage VB is low, the first transmission gate TG1 is turned on, and the reference voltage VREF is equal to the high voltage VH; when the comparison voltage VCAP drops from high, the input voltage VA is low, the output voltage VB is high, the second transmission gate TG2 is turned on, and the reference voltage VREF is equal to the low voltage VL.

[0024] As a further improvement, the ratio of the effective width-to-length ratios of the second and third PMOS transistors PM2 and PM3 is equal to the ratio of the effective width-to-length ratios of the first and second NMOS transistors NM1 and NM2, the first, second and third PMOS transistors PM1, PM2 and PM3 have a common source to the power supply VDD and a common gate connected to the current source I1, the first and second NMOS transistors NM1 and NM2 have a common source and are grounded and a common gate and are connected to the drain of the second PMOS transistor PM2 and the drain of the first NMOS transistor NM1, and the drain of the first PMOS transistor PM1 is connected to the current source I1.

[0025] As a further improvement, the drain of the second NMOS transistor NM2 is connected to the source of the third NMOS transistor NM3, the third NMOS transistor NM3 and the fourth PMOS transistor PM4 have a common drain connected to the comparison voltage VCAP and a common gate connected to the output voltage VB, the source of the fourth PMOS transistor PM4 is connected to the drain of the third PMOS transistor PM3, and the comparison voltage VCAP is grounded via the first capacitor C1.

[0026] As a further improvement, the fifth and fourteenth PMOS transistors PM5 and PM14 have a common source connected to the power supply VDD and a gate biased, the drain of the fourteenth PMOS transistor PM14 is connected to the oscillator reference voltage VOSCREF and grounded via the third resistor R3, the second capacitor C2 is connected to the oscillator reference voltage VOSCREF and grounded, the fourth NMOS transistor NM4 and the fifth PMOS transistor PM5 have a common drain, the gate of the fourth NMOS transistor NM4 is connected to the drain and the source is grounded.

[0027] As a further improvement, the sixth, seventh, eighth, and ninth PMOS transistors PM6, PM7, PM8, and PM9 and the first and second resistors R1 and R2 form the folding input stage of the transconductance amplifier. The sixth and seventh PMOS transistors PM6 and PM7 share a common source and gate with the fifth PMOS transistor PM5. The drains of the sixth and seventh PMOS transistors PM6 and PM7 are respectively connected to the sources of the eighth and ninth PMOS transistors PM8 and PM9. The gates of the eighth and ninth PMOS transistors PM8 and PM9 are respectively connected to the other circuit voltage VM and the comparison voltage VCAP. The sixth and seventh PMOS transistors PM6 and PM7 are current sources with an effective width-to-length ratio of 1:1, which control the bias current of the folding input stage. The eighth and ninth PMOS transistors PM8 and PM9 form a differential pair with an effective width-to-length ratio of 1:1. The two ends of the resistor R are respectively connected to the drains of the sixth and seventh PMOS transistors PM6 and PM7.

[0028] As a further improvement, the fifth and sixth NMOS transistors NM5 and NM6 have a common gate and are connected to the bias node voltage VBN, the seventh and eighth NMOS transistors NM7 and NM8 have a common gate and are connected to the drain of the fifth PMOS transistor PM5 and the source is grounded, the fifth and seventh NMOS transistors NM5 and NM7 have their source and drain connected and connected to the drain of the eighth PMOS transistor PM8, the sixth and eighth NMOS transistors NM6 and NM8 have their source and drain connected and connected to the drain of the ninth PMOS transistor PM9; the tenth, eleventh, twelfth, and thirteenth PMOS transistors PM10 and PM11 have their source and drain connected. M11, PM12, and PM13 share a source with the fifth PMOS transistor PM5; the tenth and thirteenth PMOS transistors PM10 and PM13 share a gate and are connected to the drains of the tenth PMOS transistor PM10 and the fifth NMOS transistor NM5; the eleventh and twelfth PMOS transistors PM11 and PM12 share a gate and are connected to the drains of the eleventh PMOS transistor PM11 and the sixth NMOS transistor NM6, so as to convert the current difference of the folded input stage into the current difference between the tenth and eleventh PMOS transistors PM10 and PM11.

[0029] As a further improvement, the ninth and tenth NMOS transistors NM9 and NM10 are used to process the current difference between the tenth and eleventh PMOS transistors PM10 and PM11. The ninth and tenth NMOS transistors NM9 and NM10 share a common gate and are connected to the drain of the twelfth PMOS transistor PM12 and the drain of the ninth NMOS transistor NM9. The thirteenth PMOS transistor PM13 and the tenth NMOS transistor NM10 share a common drain and are connected to the oscillator reference voltage VOSCREF. The oscillator reference voltage VOSCREF is formed between the drains of the thirteenth and fourteenth PMOS transistors PM13 and PM14. The fifth and fourteenth PMOS transistors PM5 and PM14 share a common gate and are connected to the current source I1. It should be noted that the gates (GATE terminals) of PM5 and PM14 can be biased from other locations as needed. In other words, PM5 and PM14 can have a variety of specific embodiments and can be biased from other locations as needed, all while achieving the same technical effects and objectives using the same or similar technical means.

[0030] As a further improvement, the gate of the fifth PMOS transistor PM5 is connected to the drain of the first PMOS transistor PM1 so as to be directly biased by the first-stage circuit STAGE1. The effective width-to-length ratio of the tenth and thirteenth PMOS transistors PM10 and PM13 is equal to the effective width-to-length ratio of the eleventh and twelfth PMOS transistors PM11 and PM12. The ninth and tenth NMOS transistors NM9 and NM10 form a 1:1 current mirror. The resistor R is composed of first and second resistors R1 and R2 connected in series. The resistance of the resistor R is equal to the sum of the resistances of the first and second resistors R1 and R2. Preferably, the resistances of the first and second resistors are equal.

[0031] The following is combined with Figure 1 and Figure 2 The preferred example of the present invention is shown to specifically illustrate the circuit principle of the present invention.

[0032] STAGE1: This stage is the oscillation stage.

[0033] VH and VL are voltage sources provided by other components. Transmission gates TG1 and TG2, controlled by VA and VB, control the VREF voltage. VH is higher than VL. When VCAP rises from a low voltage, VA is high, VB is low, TG1 turns on, and VREF = VH. When VCAP falls from a high voltage, VA is low, VB is high, TG2 turns on, and VREF = VL. COMP1 is a comparator, and INV1 is an inverter. By adjusting VREF, this component implements a hysteresis comparator with a hysteresis range between VL and VH.

[0034] I1 is a current source, and PM1 and PM2 form a current mirror, which is used to proportionally replicate the current of I1. For the sake of convenience, the ratio of PM1 to PM2 (or the effective width-to-length ratio) is 1:1, but it can be adjusted according to actual use.

[0035] Similarly, PM3 and PM2 form a current mirror, and NM1 and NM2 form a current mirror. The main feature of the current mirror here is that if the ratio of the effective width-to-length ratio of PM2 to the effective width-to-length ratio of PM3 is K1, then the ratio of the effective width-to-length ratio of NM1 to the effective width-to-length ratio of NM2 is also K1. At the same time, the value of K1 is generally much greater than 1, achieving small currents for PM3 and NM2. Through such a design, the current of the PM3 tube when operating in the saturation region can be made the same as the current of the NM2 tube when operating in the saturation region, that is:

[0036] IPM3=INM2

[0037] PM4 controls whether the current from PM3 can flow into the VCAP node; NM3 controls whether the current from the VCAP node can flow into NM2. When VB is high, NM3 conducts, PM4 does not conduct, and capacitor C1 discharges through the NM2 current INM2. When VB is low, NM3 does not conduct, PM4 conducts, and capacitor C1 charges through PM3's current IPM3. The charge and discharge cycles of C1 control the frequency jittering cycle. If the highest level of the VCAP capacitor is VH and the lowest level is VL, the frequency jittering cycle is:

[0038]

[0039] The oscillator's operating principle can be described as follows: when VCAP is lower than VL, VB is low, PM3 charges C1 through PM4, and the VCAP voltage rises at a fixed rate, at which point VREF = VH. When it rises above VH, the comparator flips, VB goes high, NM2 discharges C1 through NM3, and the VCAP voltage decreases at a fixed rate, at which point VREF = VL. Once VCAP drops to VL, the next cycle begins.

[0040] STAGE2: This is the reference voltage control stage.

[0041] PM5 is a reference current source. For convenience, the GATE terminal of PM5 is directly biased by STAGE1 here (in actual applications, this current source can be taken from a reference current source elsewhere).

[0042] NM4 receives the current from PM5 and generates a new bias voltage, which is used to bias the voltage of the rest of the stage. PM6, PM7, PM8, PM9, and R1 and R2 form the folded input stage of the transconductance amplifier (the part between PM6 and PM13 in the figure, including PM6 and PM13 forming the transconductance amplifier). PM6 and PM7 are current sources with an effective width-to-length ratio of 1:1, which control the bias current of the folded input stage. PM8 and PM9 form a differential pair with an effective width-to-length ratio of 1:1, making their transconductance:

[0043] gm=gm8=gm9

[0044] R1 and R2 are used to limit the effective transconductance Gm of this stage. At the same time, they can make this stage have a wide linear range, so that the output VOSCREF voltage of this stage changes almost linearly within a certain range. Here, R1=R2=R is set. The effective transconductance of the folded input stage can be calculated as:

[0045]

[0046] As can be seen from the above formula, if R is large enough, the nonlinear problem of gm can be ignored, so that the effective Gm of this stage is almost only affected by R. Furthermore, the difference between the current IPM8 of PM8 and the current IPM9 of PM9 can be written as:

[0047]

[0048] VM is generated by other circuits and its value is greater than VL and less than VH. Usually VM can be configured as:

[0049] VM=(VL+VH) / 2

[0050] PM10, PM11, NM5, NM6, NM7, and NM8 form the cascode stage, converting the current difference of the folded input stage into the current difference between PM10 and PM11. NM7 and NM8 form a 1:1 common-source current mirror, used to set the bias current. NM5 and NM6 form a common gate, primarily isolating the drain voltage of PM8 and PM9 without affecting their current flow, while also reducing the offset of the differential pair PM8 and PM9. VBN is used to bias NM5 and NM6. For simplicity, the specific VBN bias circuit is not shown here.

[0051] Since the currents of NM7 and NM8 are equal, the current difference between PM9 and PM8 will be directly reflected in PM10 and PM11. PM10 and PM11 use diode connection (gate connected to drain). It can be seen that:

[0052]

[0053] PM12, PM13, NM9, and NM10 are used to process the above current difference. PM10 and PM13 form a current mirror with an effective width-to-length ratio of K2; PM11 and PM12 also form a current mirror with an effective width-to-length ratio of K2. NM9 and NM10 form a 1:1 current mirror. NM9 receives the current from PM12, making the current of NM10 equal to that of PM12. Therefore, the voltage difference between PM9 and PM8 is ultimately converted to the current difference between PM13 and NM10, achieving almost linear transconductance amplification. The current difference between PM13 and NM10 can be written as:

[0054]

[0055] PM14, R3, and C2 form a reference voltage circuit for generating VOSCREF, which is used to power a linear voltage-controlled oscillator to achieve the frequency-jittering function. The linear voltage-controlled oscillator is not discussed here. The gate (GATE terminal) of PM14 can be biased from elsewhere. Preferably, PM14 is a reference current source, which is generated here using BANDGAP technology and has a low temperature coefficient. R3 and BANDGAP use the same type of resistor, which can offset the temperature coefficient, thereby making VOSCREF also have a low temperature coefficient. C2 is used to filter out system noise, making VOSCREF more stable. From the figure, it is easy to derive the expression of VOSCREF:

[0056]

[0057] In typical applications, the maximum value of the second term in the brackets above is less than 10% of the first term, with a typical value around 3%. It's easy to see from the above formula that VOSCREF is generated by two currents flowing through the resistor: a DC term and an AC term. The first term (IPM14) is the DC term, while the second term is the AC term.

[0058] To better understand the principle of this circuit, you can refer to Figure 2 .

[0059] The first row shows the VL / VM / VH levels, where VL is approximately 0.4V, VM is approximately 1.2V, and VH is approximately 2.0V. In the figure, a narrow pulse appears at 2.1ms for VL. This pulse is caused by the transmission gate during state switching and does not affect actual operation.

[0060] The second line shows the voltage at node B, and the third line shows the VCAP voltage, which is also the voltage at capacitor C1. When the voltage at capacitor C1 rises from low to high, node B is at a low level. At this time, PM3 charges capacitor C1 through PM4. The PM3 charging current is constant, so the VCAP voltage rises at a fixed slope. When the VCAP voltage rises above VH, the voltage at node B flips, PM4 turns off, NM3 turns on, and NM2 discharges capacitor C1 through NM3. Since the discharge current is constant and equal to the charging current, the VCAP voltage decreases at a fixed slope during this process, and the absolute value of the decreasing slope is equal to the increasing slope.

[0061] The fourth row shows the VOSCREF voltage. Its center value is approximately 1.2V, with a maximum voltage of approximately 1.235V and a minimum voltage of approximately 1.165V. The 1.2V center value is determined by the DC term in the VOSCREF expression. It can be seen that when VCAP changes linearly, the VOSCREF voltage also changes approximately linearly, and VOSCREF and VCAP are in phase. The VOSCREF voltage fluctuation is approximately 1.2V ±3%.

[0062] The fifth row shows the OSC voltage, but due to its high frequency, the specific frequency cannot be clearly seen in the graph. To address this issue, the sixth row visualizes the OSC frequency values ​​from the fifth row. As can be seen, the OSC center level is around 375 kHz, with a maximum frequency of approximately 385 kHz and a minimum frequency of approximately 365 kHz. The OSC frequency fluctuates by approximately 375 kHz + / - 2.7%, roughly the same ratio as VOSCREF.

[0063] It should be understood that the scope of the present invention is not limited to the non-limiting embodiments, and it should be understood that the non-limiting embodiments are only provided as examples. The substantial scope of protection required by this application is further reflected in the scope provided by the independent claims and their dependent claims.

Claims

1. A frequency-jittering circuit comprising an oscillator stage as a first-stage circuit STAGE1 and a reference voltage control stage as a second-stage circuit STAGE2, characterized in that: The oscillation stage includes: a comparator COMP1 and an inverter INV1, which realize the function of a hysteresis comparator in conjunction with the change of a reference voltage VREF formed by a high voltage VH and a low voltage VL of a voltage source; a first and a second PMOS transistor PM1 and PM2 form a current mirror for proportionally replicating the current of a current source I1; a second PMOS transistor PM2 and a third PMOS transistor PM3 form a current mirror; a first and a second NMOS transistor NM1 and NM2 form a current mirror; a fourth PMOS transistor PM4 is used to control whether the current of the third PMOS transistor PM3 can flow into a comparison voltage VCAP node of the comparator COMP1; and a third NMOS transistor NM3 is used to control whether the current of the comparison voltage VCAP node can flow into the second NMOS transistor NM2; The ratio of the effective width-to-length ratios of the second and third PMOS transistors PM2 and PM3 is equal to the ratio of the effective width-to-length ratios of the first and second NMOS transistors NM1 and NM2; the first, second, and third PMOS transistors PM1, PM2, and PM3 have a common source connected to the power supply VDD and a common gate connected to the current source I1; the first and second NMOS transistors NM1 and NM2 have a common source and are grounded, and a common gate connected to the drain of the second PMOS transistor PM2 and the drain of the first NMOS transistor NM1; and the drain of the first PMOS transistor PM1 is connected to the current source I1; The reference voltage control stage includes: a fifth PMOS transistor PM5 serving as a reference current source; a fourth NMOS transistor NM4 receiving the current of the fifth PMOS transistor PM5 to generate a new bias voltage; a folding input stage of a transconductance amplifier composed of PMOS transistors connected to a further circuit voltage VM and the comparison voltage VCAP; a fourteenth PMOS transistor PM14, a third resistor R3, and a second capacitor C2 forming a reference voltage circuit for generating an oscillator reference voltage VOSCREF; the oscillator reference voltage VOSCREF is input to a cascode stage to convert the current difference of the folding input stage, thereby achieving nearly linear transconductance amplification.

2. The frequency jittering circuit according to claim 1, wherein: The high voltage VH and the low voltage VL pass through a first transmission gate TG1 and a second transmission gate TG2 respectively, and the reference voltage VREF is controlled by the input voltage VA and the output voltage VB of the inverter INV1 .

3. The frequency jittering circuit according to claim 2, wherein: The voltage of the high voltage VH is higher than that of the low voltage VL. When the comparison voltage VCAP rises from low, the input voltage VA is high, the output voltage VB is low, the first transmission gate TG1 is turned on, and the reference voltage VREF is equal to the high voltage VH; when the comparison voltage VCAP falls from high, the input voltage VA is low, the output voltage VB is high, the second transmission gate TG2 is turned on, and the reference voltage VREF is equal to the low voltage VL.

4. The frequency jittering circuit according to claim 3, wherein: The drain of the second NMOS transistor NM2 is connected to the source of the third NMOS transistor NM3. The third NMOS transistor NM3 and the fourth PMOS transistor PM4 have a common drain connected to the comparison voltage VCAP and a common gate connected to the output voltage VB. The source of the fourth PMOS transistor PM4 is connected to the drain of the third PMOS transistor PM3. The comparison voltage VCAP is grounded via the first capacitor C1.

5. The frequency jittering circuit according to claim 1, wherein: The fifth and fourteenth PMOS transistors PM5 and PM14 have a common source connected to the power supply VDD and a gate connected for biasing. The drain of the fourteenth PMOS transistor PM14 is connected to the oscillator reference voltage VOSCREF and grounded via the third resistor R3. The second capacitor C2 is connected to the oscillator reference voltage VOSCREF and grounded. The fourth NMOS transistor NM4 and the fifth PMOS transistor PM5 have a common drain. The gate and drain of the fourth NMOS transistor NM4 are connected and the source is grounded.

6. The frequency jittering circuit according to claim 5, wherein: The sixth, seventh, eighth, and ninth PMOS transistors PM6, PM7, PM8, and PM9 and a resistor R constitute the folding input stage of the transconductance amplifier. The sixth and seventh PMOS transistors PM6, PM7 share a common source and gate with the fifth PMOS transistor PM5. The drains of the sixth and seventh PMOS transistors PM6 and PM7 are respectively connected to the sources of the eighth and ninth PMOS transistors PM8 and PM9. The gates of the eighth and ninth PMOS transistors PM8 and PM9 are respectively connected to the other circuit voltage VM and the comparison voltage VCAP. The sixth and seventh PMOS transistors PM6 and PM7 are current sources with an effective width-to-length ratio of 1:1, controlling the bias current of the folding input stage. The eighth and ninth PMOS transistors PM8 and PM9 form a differential pair with an effective width-to-length ratio of 1:

1. Both ends of the resistor R are respectively connected to the drains of the sixth and seventh PMOS transistors PM6 and PM7.

7. The frequency jittering circuit according to claim 6, wherein: The fifth and sixth NMOS transistors NM5 and NM6 share a common gate and are connected to the bias node voltage VBN. The seventh and eighth NMOS transistors NM7 and NM8 share a common gate and are connected to the drain of the fifth PMOS transistor PM5 and have their sources grounded. The sources and drains of the fifth and seventh NMOS transistors NM5 and NM7 are connected and connected to the drain of the eighth PMOS transistor PM8. The sources and drains of the sixth and eighth NMOS transistors NM6 and NM8 are connected and connected to the drain of the ninth PMOS transistor PM9. The tenth, eleventh, twelfth, and thirteenth PMOS transistors PM10, PM11, PM12, and PM13 share a source with the fifth PMOS transistor PM5. The tenth and thirteenth PMOS transistors PM10 and PM13 share a gate and are connected to the drain of the tenth PMOS transistor PM10 and the fifth NMOS transistor NM5. The eleventh and twelfth PMOS transistors PM11 and PM12 share a gate and are connected to the drain of the eleventh PMOS transistor PM11 and the sixth NMOS transistor NM6, so as to convert the current difference of the folded input stage into the current difference between the tenth and eleventh PMOS transistors PM10 and PM11.

8. The frequency jittering circuit according to claim 7, wherein: The ninth and tenth NMOS transistors NM9 and NM10 are used to process the current difference between the tenth and eleventh PMOS transistors PM10 and PM11. The ninth and tenth NMOS transistors NM9 and NM10 share a gate and are connected to the drain of the twelfth PMOS transistor PM12 and the drain of the ninth NMOS transistor NM9. The thirteenth PMOS transistor PM13 and the tenth NMOS transistor NM10 share a drain and are connected to the oscillator reference voltage VOSCREF. The oscillator reference voltage VOSCREF is formed between the drains of the thirteenth and fourteenth PMOS transistors PM13 and PM14. The fifth and fourteenth PMOS transistors PM5 and PM14 share a gate and are connected to the current source I1.

9. The frequency jittering circuit according to claim 8, wherein: The gate of the fifth PMOS transistor PM5 is connected to the drain of the first PMOS transistor PM1 so as to be directly biased by the first-stage circuit STAGE1. The effective width-to-length ratio of the tenth and thirteenth PMOS transistors PM10 and PM13 is equal to the effective width-to-length ratio of the eleventh and twelfth PMOS transistors PM11 and PM12. The ninth and tenth NMOS transistors NM9 and NM10 form a 1:1 current mirror. The resistor R is composed of first and second resistors R1 and R2 connected in series. The resistance of the resistor R is equal to the sum of the resistances of the first and second resistors R1 and R2.

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