A double-channel parallel processing architecture of ultra-high frequency partial discharge signals

Abstract

To solve the problem that the prior art is difficult to realize fast response and non-distortion recording of ultra-high frequency partial discharge signals when occasional pulses are generated, the application relates to a double-channel parallel processing architecture of ultra-high frequency partial discharge signals, comprising: a signal cloning circuit for receiving and synchronously outputting the ultra-high frequency partial discharge signals as a first target signal and a second target signal after lossless copying; a low-gain channel circuit for buffering and transmitting the first target signal to maintain the original bandwidth and dynamic range, and generating a first gain signal; a high-gain channel circuit for gain amplifying the second target signal to generate a second gain signal; a digital signal processing unit for synchronously clock control of the low-gain channel circuit and the high-gain channel circuit; and an FPGA chip integrated in the digital signal processing unit, for performing fusion splicing processing on the first gain signal and the second gain signal based on a waveform fusion splicing algorithm, and generating a fusion signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of measuring electrical variables, and particularly relates to a double-channel parallel processing architecture of ultra-high frequency partial discharge signals. BACKGROUND

[0002] The ultra-high frequency partial discharge signal generally refers to a nanosecond electromagnetic pulse with a frequency range of 300 MHz-3 GHz and a dynamic range of 60-100 dB, which is often generated in the transient discharge process of insulation defects of power equipment. Such signals have characteristics such as large amplitude span, short time domain characteristics, and strong occasionality, and are easily affected by the mutual restriction of the dynamic range and sensitivity of the detection system during dynamic capture: strong signals are prone to saturation distortion in high-gain mode, and weak signals are prone to being submerged by background noise in low-gain mode. Therefore, it is crucial for high-precision detection to realize undistorted recording of the nanosecond waveform of the ultra-high frequency partial discharge signal in a single discharge event.

[0003] The prior art generally detects and records the ultra-high frequency partial discharge signal based on an architecture combining an automatic gain mechanism and a single amplification path, however, the dynamic range of signal detection is limited to 30-40 dB, and the gain adjustment of the signal depends on an analog feedback mechanism. When such an architecture faces occasional pulses of the ultra-high frequency partial discharge signal, there is a significant time delay in gain switching, so it is often impossible to achieve dynamic response and complete gain matching of the occasional pulses within nanosecond time, which may result in loss of the leading pulse or clipping of the subsequent pulse. This dynamic response bottleneck seriously limits the complete capture ability of such an architecture for occasional pulses, and it is difficult to meet the requirement for undistorted recording of the full waveform of the ultra-high frequency partial discharge signal.

[0004] In view of this, it is urgent to provide a double-channel parallel processing architecture of ultra-high frequency partial discharge signals to achieve fast response and complete capture of the ultra-high frequency partial discharge signals. SUMMARY

[0005] Based on the foregoing analysis, the main purpose of the present application is to provide a double-channel parallel processing architecture of ultra-high frequency partial discharge signals to solve the problem that the traditional automatic gain detection architecture is difficult to achieve fast response and undistorted recording of the ultra-high frequency partial discharge signals when occasional pulses are generated.

[0006] To this end, the application provides a double-channel parallel processing architecture of ultra-high frequency partial discharge signals, which comprises: a signal cloning circuit, configured to receive the ultra-high frequency partial discharge signals, and synchronously output the ultra-high frequency partial discharge signals after lossless copying as a first target signal and a second target signal; a low-gain channel circuit, configured to perform buffer transmission of the first target signal while maintaining the original bandwidth and dynamic range, and output a first gain signal; a high-gain channel circuit, configured to perform gain amplification on the second target signal, and output a second gain signal; a digital signal processing unit, configured to synchronously control the low-gain channel circuit and the high-gain channel circuit; and an FPGA chip, integrated in the digital signal processing unit, configured to perform fusion splicing processing on the first gain signal and the second gain signal based on a waveform fusion splicing algorithm, and generate a fusion signal.

[0007] Preferably, the signal cloning circuit comprises a power divider, a first matching resistor, a second matching resistor, a first delay element group, a second delay element group, and a phase compensation network; an input end of the power divider is configured to receive the ultra-high frequency partial discharge signals, the power divider is configured to copy the ultra-high frequency partial discharge signals, and the copied ultra-high frequency partial discharge signals are synchronously output through a first output end and a second output end; a first end of the first matching resistor is electrically connected to the first output end of the power divider, a second end of the first matching resistor is electrically connected to a first end of the first delay element group, and a second end of the first delay element group is electrically connected to a first end of the phase compensation network; a first end of the second matching resistor is electrically connected to the second output end of the power divider, a second end of the second matching resistor is electrically connected to a first end of the second delay element group, and a second end of the second delay element group is electrically connected to a second end of the phase compensation network; and the phase compensation network is configured to perform synchronous phase compensation on the ultra-high frequency partial discharge signals output by the first output end and the second output end of the power divider.

[0008] Further preferably, the phase compensation network comprises a phase-shifting inductor, a first matching capacitor, and a second matching capacitor; a first end of the phase-shifting inductor is electrically connected to a first end of the first matching capacitor, a second end of the phase-shifting inductor is electrically connected to a second end of the second matching capacitor, a second end of the first matching capacitor is electrically connected to a first end of the second matching capacitor; the first end of the phase-shifting inductor is used as a first end of the phase compensation network to extract the first target signal; and the second end of the phase-shifting inductor is used as a second end of the phase compensation network to extract the second target signal.

[0009] As preferred, the low-gain channel circuit comprises a diplexer, a selection switch, and a first programmable gain amplifier; the diplexer is used for frequency isolation of the first target signal to maintain the original bandwidth and dynamic range of the first target signal, an input end thereof is used for receiving the first target signal, a first output end thereof is used for outputting the first isolated signal, and a second output end thereof is used for outputting the second isolated signal; a first input end of the selection switch is used for receiving the second isolated signal, a second input end thereof is used for receiving a reference ground signal, and an output end thereof is used for outputting the second isolated signal or the reference ground signal; a first input end of the first programmable gain amplifier is used for receiving the first isolated signal or a reference ground signal, a second input end thereof is used for receiving the second isolated signal, and an output end thereof is used for outputting the first gain signal.

[0010] As preferred, the high-gain channel circuit comprises a filter network, a differential amplifier, a band-pass filter, a radio frequency switch, and a second programmable gain amplifier; a first end of the filter network is used for receiving the second target signal, and a second end thereof is used for outputting an initial filtered signal; an input end of the differential amplifier is used for receiving the initial filtered signal, a first output end thereof is used for outputting a positive-phase amplified signal, and a second output end thereof is used for outputting a negative-phase amplified signal; a first input end of the radio frequency switch is used for receiving the positive-phase amplified signal, a second input end thereof is used for receiving the negative-phase amplified signal, and an output end thereof is used for selecting output of the positive-phase amplified signal or the negative-phase amplified signal; an input end of the band-pass filter is used for communication with the output end of the radio frequency switch, and an output end of the band-pass filter is used for outputting a band-pass filtered signal corresponding to the positive-phase amplified signal or the negative-phase amplified signal; a first input end of the second programmable gain amplifier is used for receiving the band-pass filtered signal, and an output end thereof is used for outputting the second gain signal.

[0011] As further preferred, the filter network comprises a first filter capacitor, a filter inductor, and a second filter capacitor; a first end of the first filter capacitor is electrically connected with a first end of the second filter capacitor, and a second end of the first filter capacitor is electrically connected with a first end of the filter inductor; a second end of the filter inductor is electrically connected with a second end of the second filter capacitor; and the first end of the second filter capacitor serves as the first end of the filter network, and the second end of the second filter capacitor serves as the second end of the filter network.

[0012] As preferred, the digital signal processing unit further comprises a clock processing unit circuit and at least two independent ADC acquisition unit circuits; the clock processing unit is used for synchronous clock control of the low-gain channel circuit and the high-gain channel circuit, and is used for driving the at least two independent ADC acquisition unit circuits to synchronously acquire and process the first gain signal and the second gain signal, and then transmit to the FPGA chip.

[0013] As preferred, the waveform fusion splicing algorithm performs fusion splicing processing on the first gain signal and the second gain signal, and generates a fusion signal, comprising: determining the effective overlap period of the first gain signal and the second gain signal , wherein represents the signal sampling point in the effective overlap period;

[0014] normalizing the first gain signal and the second gain signal respectively:

[0015] ;

[0016] wherein, is the gain coefficient of the low gain channel circuit, is the gain coefficient of the high gain channel circuit;

[0017] generating the fusion signal using weighted superposition method:

[0018] ;

[0019] wherein, is the weighting coefficient of the second gain signal.

[0020] As further preferred, it further comprises: obtaining the spectrum information of the first gain signal and the spectrum information of the second gain signal , determining the weighting coefficient of the second gain signal based on the spectrum information:

[0021] ;

[0022] wherein, is the spectrum correlation adjustment factor, is the spectrum correlation index, is the index frequency of the spectrum, and outputs the weight adjustment factor in the range of [0, 1]; is the basic weight of the second gain signal; is the real-time signal-to-noise ratio of the second gain signal; is the real-time signal-to-noise ratio of the first gain signal.

[0023] As preferred, it further comprises determining the basic weight of the second gain signal:

[0024] ;

[0025] wherein: a signal strength of the second gain signal representing the current signal sampling point; a weak signal threshold, a strong signal threshold, an empirical coefficient, a signal decay rate.

[0026] The double-channel parallel processing architecture of the ultra-high frequency partial discharge signal has the following beneficial effects:

[0027] Firstly, unlike the traditional automatic gain architecture which is limited by the fixed gain adjustment mechanism, the architecture realizes lossless replication of the ultra-high frequency partial discharge signal based on a signal cloning circuit, combines a low-gain channel circuit and a high-gain channel circuit to perform double-channel parallel processing on the ultra-high frequency partial discharge signal, utilizes the differential gain design of the low-gain channel circuit and the high-gain channel circuit to simultaneously achieve wide dynamic range maintenance for strong amplitude pulses and high sensitivity amplification for weak signals, and can also achieve rapid response to the ultra-high frequency partial discharge signal when an occasional pulse occurs.

[0028] Secondly, unlike the traditional architecture which relies on automatic gain control mode of feedback adjustment after signal stabilization, the architecture controls double-channel clock synchronization in real time through a digital signal processing unit, and dynamically fuses two signals based on a waveform splicing algorithm integrated in the FPGA chip, can directly extract complete strong signals of the low-gain channel and enhanced weak signals of the high-gain channel in a single sampling, and effectively fuse the two signals to achieve complete capture of the ultra-high frequency partial discharge signal.

[0029] Thirdly, considering that the strong signal has the risk of over-saturation when gain amplification is performed on the ultra-high frequency partial discharge signal, the architecture uses a waveform fusion splicing algorithm integrated in the FPGA chip to effectively fuse the first gain signal and the second gain signal, avoids signal clipping caused by excessively high gain of a single channel circuit, and effectively restores weak detail information missed by the low-gain channel circuit, thereby avoiding the signal distortion risk brought by relying only on hardware gain adjustment. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a double-channel parallel processing architecture of the ultra-high frequency partial discharge signal of an embodiment of the present application;

[0031] Figure 2 is a signal cloning circuit diagram of an embodiment of the present application;

[0032] Figure 3 is a low-gain channel circuit diagram of an embodiment of the present application;

[0033] Figure 4 is a high-gain channel circuit diagram of an embodiment of the present application;

[0034] Figure 5 is a front-end input circuit diagram of an embodiment of the present application;

[0035] Figure 6 is a fusion splicing flow chart of the first gain signal and the second gain signal of an embodiment of the present application. DETAILED DESCRIPTION

[0036] The application will be described in more detail with reference to the drawings. It should be noted that the following description of the application with reference to the drawings is merely illustrative and not restrictive.

[0037] In the case possible, each different embodiment described below can be recombined with each other to constitute other embodiments not shown in the following description; each different technical feature described below can also be recombined with each other to constitute other embodiments not shown in the following description.

[0038] Please refer to the accompanying Figures 1-6 .

[0039] Ultra-high frequency partial discharge signal, i.e. the nanosecond electromagnetic pulse with a frequency range of 300MHz-3GHz and a dynamic range of 60-100dB, usually refers to the partial discharge signal generated in the degradation process of power equipment. Such signals have obvious transient characteristics, and the duration of a single pulse is usually in the order of nanoseconds, and the occurrence time has high randomness and burstiness. Therefore, the dynamic range and response speed of the signal acquisition system are extremely high in actual detection. Since the signal may contain weak early fault information and may be accompanied by occasional strong pulse interference, the automatic gain control (AGC) technology is widely used to adapt to the change of signal intensity.

[0040] However, the existing automatic gain control technology is usually limited to single-channel dynamic response and equipped with fixed gain adjustment mechanism, and is limited to the adaptability of burst strong and large amplitude change partial discharge signal, and depends on the feedback adjustment process after the signal is stable. Therefore, it cannot timely and accurately capture the complete waveform characteristics of the occasional pulse signal, and there is a significant gap between the actual demand of online monitoring and fault warning of partial discharge in power equipment.

[0041] Therefore, in order to solve the problem that the traditional automatic gain detection architecture is difficult to realize fast response and non-distortion recording of the ultra-high frequency partial discharge signal when the occasional pulse is generated, the embodiment provides a dual-channel parallel processing architecture of the ultra-high frequency partial discharge signal, which is based on the principle of the cloning circuit to losslessly copy the ultra-high frequency partial discharge signal and generate two parallel signals in time domain synchronization and spectrum consistency, uses a low-gain channel circuit and a high-gain channel circuit with different gain amplification to respectively maintain a wide dynamic range and detect high sensitivity of the ultra-high frequency partial discharge signal, controls the two channel circuits based on a digital signal processing unit with a synchronous clock, and uses a waveform fusion splicing algorithm integrated in an FPGA chip (field programmable gate array) to fuse and splice the output signals of the low-gain channel and the high-gain channel, and finally generates a fusion signal as a complete ultra-high frequency partial discharge signal waveform.

[0042] Please refer to Figure 1 The dual-channel parallel processing architecture of the ultra-high frequency partial discharge signal mainly includes a signal cloning circuit, a low-gain channel circuit, a high-gain channel circuit and a digital signal processing unit. The signal cloning circuit is used to losslessly copy the ultra-high frequency partial discharge signal after receiving the signal, so that the two signals are in time domain synchronization and spectrum consistency, and are output as a first target signal and a second target signal. The first target signal is received by the low-gain channel circuit, which buffers and transmits the first target signal to maintain the original bandwidth and dynamic range, and then outputs the first target signal as a first gain signal. The second target signal is received by the high-gain channel circuit, which amplifies the second target signal, and then outputs the second target signal as a second gain signal. In the above architecture, the digital signal processing unit controls the low-gain channel and the high-gain channel with a synchronous clock signal to ensure that the output signals are in time domain consistency. At the same time, the FPGA chip integrated in the digital signal processing unit can perform waveform splicing on the first gain signal with wide dynamic range and the second gain signal with high sensitivity amplification through the integrated waveform fusion splicing algorithm, and finally obtain a fusion signal, i.e. a complete ultra-high frequency partial discharge signal waveform. The signal cloning circuit in the embodiment realizes lossless copying and dual-channel synchronous output of the ultra-high frequency partial discharge signal, the low-gain channel maintains the original dynamic range and waveform integrity of the strong signal, the high-gain channel improves the signal-to-noise ratio of the weak signal, and the FPGA chip integrated waveform fusion algorithm intelligently splices the dual-channel signals. In a single sampling, the strong signal is recorded without distortion and the weak signal is detected with high sensitivity, effectively solving the problems of incomplete capture of occasional pulses, waveform distortion and the like caused by dynamic response lag and gain switching limitation in the prior art.

[0043] In the embodiment, the dual-channel parallel processing architecture differentiates the gain of the first target signal and the second target signal transmitted after the signal cloning circuit is copied by respectively setting a low-gain channel circuit and a high-gain channel circuit. The gain range of the low-gain channel circuit can be 0-6 dB, which is mainly used to capture strong amplitude pulse signals and ensure that they are transmitted completely without distortion, while taking into account signal integrity and transmission loss compensation. The gain range of the high-gain channel circuit can be 20-40 dB, which is used to amplify weak signals step by step, significantly improve the signal-to-noise ratio, and effectively detect low-amplitude discharge signals caused by early faults. The design fully considers the characteristics of the ultra-high frequency partial discharge signal, such as wide dynamic range (usually more than 60 dB) and large amplitude span, as well as the implementation requirements of system noise floor, input limit and circuit stability.

[0044] Please refer to Figure 2 In order to further realize the lossless replication of the ultra-high frequency partial discharge signal, in the preferred embodiment, the signal cloning circuit is designed in detail: the signal cloning circuit includes a power divider W1, a first matching resistor R3, a second matching resistor R4, a first delay element group, a second delay element group and a phase compensation network. The input end IN of the power divider W1 receives the ultra-high frequency partial discharge signal, and the power divider W1 outputs the signal after equal replication through the first output end and the second output end respectively. The first output end O1 of the power divider W1 is electrically connected to the first end of the first matching resistor R3, the second end of the first matching resistor R3 is electrically connected to the first end of the first delay element group, and the second end of the first delay element group is electrically connected to the first end of the phase compensation network. At the same time, the second output end O2 of the power divider W1 is electrically connected to the first end of the second matching resistor R4, the second end of the second matching resistor R4 is electrically connected to the first end of the second delay element group, and the second end of the second delay element group is electrically connected to the second end of the phase compensation network. The first matching resistor R3 and the second matching resistor R4 are used to avoid reflection or loss of the ultra-high frequency partial discharge signal in the corresponding path during transmission due to impedance mismatch, so as to maintain the lossless transmission of the ultra-high frequency partial discharge signal. The first delay element group and the second delay element group are used to adjust the transmission time of the ultra-high frequency partial discharge signal in the corresponding path to compensate for any physical path difference or other factors that may cause signal delay. The phase compensation network is used to adjust and calibrate the phase of the ultra-high frequency partial discharge signal output by the first output end O1 and the second output end O2 of the power divider W1, thereby assisting the signal cloning circuit to complete the lossless replication and transmission of the ultra-high frequency partial discharge signal. Such circuit design can ensure that the first target signal and the second target signal extracted finally remain consistent in time domain.

[0045] Please refer to Figure 2, in order to further realize the time domain consistency of the ultra-high frequency corona signals output by the first output end O1 and the second output end O2 of the power divider W1, in a further preferred embodiment, the first delay element group and the second delay element group both adopt delay lines, delay inductors and delay capacitors; wherein the delay lines can provide time delay on the physical path, the delay inductors can adjust the phase delay of the ultra-high frequency corona signals, and the delay capacitors can cooperate with the delay inductors to fine-tune the phase and amplitude of the ultra-high frequency corona signals, thereby maximizing the time domain consistency of the two signals. In more detail, the first delay element group includes a first delay inductor L4, a first delay line and a first delay capacitor C4, wherein the first end of the first delay inductor L4 is electrically connected to the second end of the first matching resistor R3 through the first delay line, the second end of the first delay inductor L4 is electrically connected to the first end of the first delay capacitor C4, and the second end of the first delay capacitor C4 is electrically connected to the first end of the phase compensation network. The second delay element group includes a second delay inductor L5, a second delay line and a second delay capacitor C5, wherein the first end of the second delay inductor L5 is electrically connected to the second end of the second matching resistor R4 through the second delay line, the second end of the second delay inductor L5 is electrically connected to the first end of the second delay capacitor C5, and the second end of the second delay capacitor C5 is electrically connected to the second end of the phase compensation network. This electrical connection ensures that the signal can pass through multiple delay links in turn during transmission and finally converge to the phase compensation network for unified correction. Through the combination of the above elements, the signal cloning circuit can finely adjust the delay amount of each signal while losslessly copying the ultra-high frequency corona signals, thereby maximizing the elimination of delay deviations caused by physical factors, element parameters, etc. during transmission after copying. It should be noted that in actual application scenarios, the number, combination and model of the corresponding delay elements can also be designed according to the characteristics of the elements themselves, thereby increasing their flexibility of use.

[0046] Please refer to Figure 2, in order to further realize the phase compensation of the ultra-high frequency signal and assist the power divider to make the lossless copy of the ultra-high frequency local oscillation signal, in the further preferred embodiment, the phase compensation network is specifically designed: the phase compensation network comprises a phase-shifting inductor L6, a first matching capacitor C6 and a second matching capacitor C7. Wherein the first end of the phase-shifting inductor L6 is electrically connected with the first end of the first matching capacitor C6, the second end of the phase-shifting inductor L6 is electrically connected with the second end of the second matching capacitor C7, and the second end of the first matching capacitor C6 is electrically connected with the first end of the second matching capacitor C7, so that the above-mentioned elements constitute a complete phase compensation network. Wherein the first end of the phase-shifting inductor L6 is taken as the first end of the phase compensation network, and the second end thereof is taken as the second end of the phase compensation network. The above-mentioned design makes the first end and the second end of the phase compensation network able to cooperate with the first output end O1 and the second output end O2 of the power divider W1 respectively, and the phase compensation network is able to make the accurate phase correction of the two-way signals simultaneously by reasonably configuring the parameters of the phase-shifting inductor and the matching capacitor, and at the same time prevent the two-way signals from interfering with each other, so as to keep the integrity and consistency of the respective frequency spectrum.

[0047] Please refer to Figure 3To maintain the original bandwidth and dynamic range of the first target signal during buffered transmission, in another preferred embodiment, the low-gain channel circuit is designed as follows: The low-gain channel circuit mainly includes a duplexer D1, a selection switch S1, and a first programmable gain amplifier U4. After receiving the first target signal at its input, the duplexer D1 performs frequency isolation on the first target signal and generates a first isolation signal and a second isolation signal. The first output of the duplexer outputs the first isolation signal, and its second output outputs the second isolation signal. By introducing the duplexer to perform frequency isolation processing on the first target signal, preliminary division of the signal frequency band is achieved, thereby effectively suppressing mutual interference between different frequency bands. The first input of the selection switch S1 communicates with the second output of the duplexer D1 and receives the second isolation signal. Its second input is electrically connected to the ground wire through an isolation device to receive a reference ground signal. The output of the selection switch S1 outputs either the second isolation signal or the reference ground signal. The design of the selection switch allows the signal input to the digital-to-analog converter to be flexibly switched between the first isolation signal and the reference ground signal, thereby enhancing the system's adaptability and anti-interference capability. The first input terminal AIN# of the first programmable gain amplifier U4 communicates with the first output terminal of the duplexer D1 and receives the first isolation signal. Its second input terminal AIN communicates with the output terminal of the selection switch S1 and receives the second isolation signal or the reference ground signal. After receiving the first isolation signal, the reference ground signal, or the second isolation signal, the first programmable gain amplifier U4 processes and outputs the first gain signal. In this embodiment, the duplexer separates the input signal into a main frequency band containing effective partial discharge information and a secondary frequency band that may contain interference information, namely the first isolation signal and the second isolation signal. Then, the selection switch intelligently switches the input of the second isolation signal or the reference ground signal to the first programmable gain amplifier, thereby suppressing noise while retaining the complete dynamic range of the main signal (0-60dB). The first programmable gain amplifier optimizes the first isolation signal by 0-6dB to ensure that strong pulses are distortion-free, and selectively processes the second isolation signal to assist in analysis or completely suppress it. Finally, it outputs a first gain signal with both a wide dynamic range (total harmonic distortion <1%) and a high signal-to-noise ratio (SNR > 40dB), realizing high-fidelity acquisition and flexible analysis of UHF partial discharge signals in complex environments.

[0048] Please refer to Figure 4, in order to carry out stable gain amplification to the second target signal, in another preferred embodiment, the high gain channel circuit is designed as follows: the high gain channel circuit is configured with a filter network, a differential amplifier U5, a band-pass filter U7, a radio frequency switch U6 and a second programmable gain amplifier U8. Among them, the first end of the filter network receives the second target signal, and outputs the initial filtered signal from the second end after filtering the second target signal. The filter network can effectively suppress out-of-band noise and interference, improve the signal-to-noise ratio and maintain the purity of the output signal. Then, the input end +IN of the differential amplifier U5 receives the initial filtered signal, and after differential amplification at the reference input end -IN, the first output end +OUT and the second output end -OUT output the positive phase amplified signal and the negative phase amplified signal respectively. The differential amplifier U5 can amplify the filtered second gain signal with high fidelity, and in a high noise environment, using differential signals (positive and negative phases) can effectively suppress common mode interference. The differential amplifier U5 amplifies the difference between the two signals while ignoring the common noise component. The first input end RF1 of the radio frequency switch U6 is used to receive the positive phase amplified signal, the second input end RF2 is used to receive the negative phase amplified signal, and the output end RFC is used to output the positive phase amplified signal or the negative phase amplified signal. The radio frequency switch U6 can provide signal path selection function while reducing signal reflection, thereby maintaining the integrity of the signal. The input end of the band-pass filter U7 is used to receive the positive phase amplified signal or the negative phase amplified signal, and the output end is used to output the band-pass filtered signal corresponding to the positive phase amplified signal or the negative phase amplified signal. The band-pass filtered signal can only retain the signal component within the target frequency range, so it has strong anti-interference ability. The first input end of the second programmable gain amplifier U8 is used to receive the band-pass filtered signal, and the output end is used to output the second gain signal.

[0049] Please refer to Figure 4 , in order to preliminarily filter out the noise in the second target signal before inputting the differential amplifier, in a further preferred embodiment, the filter network is specifically designed: the filter network includes a first filter capacitor C11, a filter inductor L7 and a second filter capacitor C12, which can effectively suppress high-frequency noise of the second target signal before the signal enters the differential amplifier U5, thereby improving the signal-to-noise ratio and stability of the subsequent amplification link. Among them, the first end of the first filter capacitor C11 is used as the first end of the filter network, the second end of the first filter capacitor C11 is electrically connected with the first end of the filter inductor L7, the second end of the filter inductor L7 is electrically connected with the first end of the second filter capacitor C12, and the second end of the second filter capacitor C12 is electrically connected with the input end +IN of the differential amplifier U5. The above filter network realizes effective suppression of direct current component, low frequency interference and high frequency noise in the second target signal through the synergistic effect of the first filter capacitor C11, the filter inductor L7 and the second filter capacitor C12, improves the signal-to-noise ratio and frequency selectivity of the signal, and optimizes the impedance matching and system stability.

[0050] Please refer to Figure 5 In order to perform basic processing of the UHF partial discharge signal before the input signal cloning circuit, in another preferred embodiment, the dual-channel parallel architecture also includes an input front-end circuit, which includes a wireless chip U1, a transient voltage suppressor U2, a filter U3, a transformer T1, and... A matching network is used; the wireless chip U1 receives and transmits the initial UHF partial discharge signal. The transient voltage suppressor U2 is electrically connected between the RF terminal of the wireless chip and the input terminal IN of the filter U3, used for transient voltage regulation of the initial UHF partial discharge signal. The input terminal of the filter U3 receives the transiently regulated initial UHF partial discharge signal, and its output terminal outputs the filtered initial UHF partial discharge signal. The input terminal of the transformer T1 receives the filtered initial UHF partial discharge signal, and its output terminal outputs the UHF partial discharge signal after isolation and impedance transformation. The first end of the matching network is electrically connected to the output terminal of transformer T1, and its second end is electrically connected to the GND terminal of the wireless chip, used for radio frequency reflection processing of the UHF partial discharge signal. Furthermore... The first end of the matching network extracts the UHF partial discharge signal. In this embodiment, after the wireless chip U1 receives the initial UHF partial discharge signal, the transient voltage suppressor U2 clamps the overvoltage pulse to protect the back-end circuit; the bandpass filter U3 suppresses out-of-band interference and improves the signal-to-noise ratio; the transformer T1 achieves impedance matching and electrical isolation, reducing common-mode interference; the π-type matching network further optimizes the radio frequency characteristics, minimizing reflection loss while extracting the signal. This preprocessing chain enables the input signal cloning circuit to have better purity and stability, providing a high-quality signal source for subsequent dual-channel processing.

[0051] Please refer to Figure 5 In order to perform radio frequency reflection processing on ultra-high frequency partial discharge signals, in a further preferred embodiment, the following steps are taken: The matching network is designed in detail, including an input filter capacitor C1, a signal tuning inductor L2, a resonant capacitor C3, an output filter capacitor C2, an output matching inductor L3, and a load resistor R2. The first terminals of both the input and output filter capacitors are electrically connected to the GND terminal of the wireless chip, and serve as... The first terminal of the matching network. The second terminal of the input filter capacitor C1 is electrically connected to the first terminal of the signal tuning inductor L2, and the second terminal of the signal tuning inductor L2 is electrically connected to the first terminal of the resonant capacitor C3. The second terminal of the output filter capacitor C2 is electrically connected to the first terminal of the output matching inductor, and the second terminal of the output matching inductor is electrically connected to the first terminal of the load resistor. Furthermore, the second terminals of the resonant capacitor C3 and the load resistor R2 are both electrically connected to the output terminal of the transformer, serving as... The second end of the matching network. In the above circuit design, the input filter capacitor C1 provides a ground path for high-frequency interference, protecting the front-end chip; the signal tuning inductor L2 and the resonance capacitor C3 form a series resonance circuit, allowing the target frequency signal to pass through optimally; the output filter capacitor C2 and the output matching inductor L3 work together to further filter out stray signals and achieve impedance matching with the subsequent device; the load resistor R2 simulates the actual load, absorbs the effective signal energy, and prevents signal reflection. The overall structure not only improves signal integrity and system stability, but also enhances the detection sensitivity of weak partial discharge signals.

[0052] To further illustrate the control of the digital signal processing unit on the dual-channel parallel processing architecture of the ultra-high frequency partial discharge signal, in a further preferred embodiment, the digital signal processing unit is described in detail, including a clock processing unit circuit and at least two independent ADC acquisition unit circuits (digital-to-analog conversion acquisition unit circuits). The clock processing unit is used to synchronize the clock control of the low-gain channel circuit and the high-gain channel circuit, and to drive the at least two independent ADC acquisition unit circuits to synchronously acquire and process the first gain signal and the second gain signal, and then transmit them to the FPGA chip. This design eliminates the clock offset problem in traditional multi-channel acquisition, ensuring the waveform reconstruction accuracy of the subsequent ultra-high frequency partial discharge signal on the nanosecond time scale, to prevent distortion of the final fused waveform.

[0053] Please refer to Figure 6 Because the dynamic range of ultra-high frequency partial discharge signals is extremely large, weak discharge pulses and background noise coexist in the signal, so a single gain amplifier or single-path dynamic adjustment cannot effectively capture them, and there may be response blockage and signal distortion. To implement the waveform splicing algorithm integrated on the FPGA chip to perform waveform splicing operations on the first gain signal and the second gain signal, in another preferred embodiment, the execution of the waveform splicing algorithm is described in detail:

[0054] Based on the signal trigger time and the gain switching delay, the effective overlap time period between the two signals is determined, so that the waveforms of the first gain signal and the second gain signal are aligned. Let represent the signal sampling point in the effective overlap time period, the first gain signal output by the high-gain channel is denoted as , and the second gain signal output by the low-gain channel is denoted as ;

[0055] Different channels have different amplification factors, and direct superposition will cause amplitude imbalance, so to ensure that the true amplitude characteristics of the signal are preserved during the overlap time period, the first gain signal and the second gain signal are normalized respectively:

[0056] ;

[0057] wherein, is a gain coefficient of the low-gain channel circuit, is a gain coefficient of the high-gain channel circuit;

[0058] In the effective overlap period, the fusion signal is generated by using a weighted superposition method , the expression of which is as follows:

[0059] ;

[0060] wherein, is a weighting coefficient of the second gain signal.

[0061] In the above algorithm, the contribution proportion of the high / low gain channel is automatically adjusted according to the signal strength, the saturation is suppressed in the strong signal area, the sensitivity is enhanced in the weak signal area, and the two gain signals are dynamically fused in a weighted manner, so that the ultra-high frequency local signal from weak to strong pulse is seamlessly spliced, and the waveform mutation or information loss caused by gain switching is avoided.

[0062] Obtain the spectrum information of the first gain signal and the spectrum information of the second gain signal , determine the weighting coefficient of the second gain signal based on the spectrum information:

[0063]

[0064] wherein, is a spectrum correlation adjustment factor, is a spectrum correlation index, is an index frequency of the spectrum, is an S-shaped function, which is used to measure the spectrum matching degree of the first gain signal and the second gain signal, and outputs a weight adjustment factor in the range of [0, 1].

[0065] wherein is a basic weight, which is determined as follows:

[0066] ;

[0067] wherein: represents the signal strength of the current sampling point; represents a weak signal threshold, represents a strong signal threshold, ​​0 represents that the second gain signal is not used when the signal strength in the effective overlapping period is higher than the strong signal threshold; represents that smooth switching is realized in the signal transition zone to prevent splicing mutation, and is an empirical coefficient, which can be 0.2; controls the attenuation rate of the signal.

[0068] The waveform splicing method fundamentally solves the technical contradiction that a single gain channel cannot consider strong and weak signals, and not only retains the original waveform characteristics of the strong signal, but also effectively amplifies the detail information of the weak signal. By accurately positioning the effective overlapping time period between the high and low gain signals, and using dynamic weights based on signal strength to fuse the two signals sample by sample in this period, the adaptability and continuity of signal processing are realized. The weight distribution follows the adaptive principle of signal strength: when the signal strength is lower than the preset weak signal threshold, the high gain signal is given a higher weight to highlight the weak component; when the signal strength exceeds the strong signal threshold, the low gain signal is completely used to avoid distortion; in the transition zone between the two, smooth interpolation is used to realize natural transition and eliminate splicing mutation.

[0069] It should be noted that although the high gain channel has a high amplification factor, it is only used to enhance the information expression ability of the weak part of the signal, and does not dominate the final output. In the subsequent waveform splicing process, the algorithm will automatically select the complete signal from the low gain channel as the dominant component according to the signal strength, and switch to the high gain channel for supplementation in the area with low signal amplitude. Therefore, even if the initial signal contains strong occasional pulses and low amplitude discharge signals, the high gain channel only amplifies the relatively weak part, and does not affect the upper limit of the dynamic range of the overall output, thereby effectively avoiding the overflow or saturation problem caused by the large amplification of strong signals. This design enables the system to simultaneously consider the distortionless recording of strong signals and the high sensitivity capture of weak signals in a single sampling, significantly outperforming the dynamic response performance of traditional single-channel automatic gain control mechanism in the occasional strong pulse scenario.

[0070] To further determine the weak signal threshold and the strong signal threshold in actual application scenarios, in a further preferred embodiment, the weak signal threshold and the strong signal threshold are determined as follows:

[0071] ;

[0072] wherein, represents the minimum signal amplitude in the current window, represents the average signal strength in the current window, represent low frequency band energy (e.g. 300MHz~800MHz), represent total frequency band energy; is a weighting coefficient, controlling the influence of history information and spectral features, is a small constant to prevent log zero.

[0073]

[0074] wherein, represents the maximum amplitude of the signal within the current window, represents the average signal strength of the current window, represents the SNR estimation of the current frame, represents the SNR influence factor, is a small constant to prevent log zero, is a weighting coefficient, used to balance the relationship between peak and average.

[0075] wherein, the weak signal threshold comprehensively considers the minimum value, average value and low frequency energy proportion of the signal, and uses the energy concentration characteristics of the partial discharge signal in a specific frequency band to distinguish effective signals and noise. The strong signal threshold introduces the log calculation of the signal-to-noise ratio, so that the threshold can be automatically adjusted according to the noise level: when the signal-to-noise ratio is high, the threshold is lowered to retain more signal details; when the signal-to-noise ratio is low, the threshold is raised to avoid noise interference. This threshold calculation based on multi-dimensional signal features makes the dual-channel processing architecture in this embodiment have strong environmental adaptability.

[0076] It should be understood that the embodiments are only used to illustrate but not to limit the scope of the present application. Furthermore, it should be understood that after reading the content taught by the present application, those skilled in the art can make various modifications or changes to the present application, and these equivalent forms also fall within the scope defined by the appended claims of the present application.​

Claims

1. A dual-channel parallel processing architecture for ultra-high frequency partial discharge signals, characterized in that, The signal cloning circuit is used for receiving the ultra-high frequency partial discharge signal and synchronously outputting the ultra-high frequency partial discharge signal as a first target signal and a second target signal after lossless copying of the ultra-high frequency partial discharge signal; the signal cloning circuit comprises a power divider, a first matching resistor, a second matching resistor, a first delay element group, a second delay element group and a phase compensation network; wherein the phase compensation network is used for performing synchronous phase compensation on the ultra-high frequency partial discharge signal output by the first output end and the second output end of the power divider; The low-gain channel circuit is used for performing buffer transmission of the first target signal to maintain the original bandwidth and dynamic range, and outputting a first gain signal; The high-gain channel circuit is used for performing gain amplification on the second target signal, and outputting a second gain signal; The digital signal processing unit is used for synchronously clock controlling the low-gain channel circuit and the high-gain channel circuit; The FPGA chip integrated in the digital signal processing unit is used for performing dynamic weighted fusion splicing processing on the first gain signal and the second gain signal based on a waveform fusion splicing algorithm, and generating a fusion signal; wherein the waveform fusion splicing algorithm can automatically adjust the weight of the low-gain channel and the high-gain channel according to the signal strength of the first gain signal and the second gain signal. In the signal cloning circuit:

2. The dual lane parallel processing architecture of claim 1, wherein, The input end of the power divider is used for receiving the ultra-high frequency partial discharge signal, and the power divider is used for copying the ultra-high frequency partial discharge signal and synchronously outputting the copied ultra-high frequency partial discharge signal through the first output end and the second output end; and The first end of the first matching resistor is electrically connected with the first output end of the power divider, the second end of the first matching resistor is electrically connected with the first end of the first delay element group, and the second end of the first delay element group is electrically connected with the first end of the phase compensation network; The first end of the second matching resistor is electrically connected with the second output end of the power divider, the second end of the second matching resistor is electrically connected with the first end of the second delay element group, and the second end of the second delay element group is electrically connected with the second end of the phase compensation network. The phase compensation network comprises a phase-shifting inductor, a first matching capacitor and a second matching capacitor; 3. The dual lane parallel processing architecture of claim 2, wherein, The first end of the phase-shifting inductor is electrically connected with the first end of the first matching capacitor, the second end of the phase-shifting inductor is electrically connected with the second end of the second matching capacitor, and the second end of the first matching capacitor is electrically connected with the first end of the second matching capacitor; The first end of the phase-shifting inductor is used for extracting the first target signal as the first end of the phase compensation network; The second end of the phase-shifting inductor is used for extracting the second target signal as the second end of the phase compensation network. The low-gain channel circuit comprises a diplexer, a selection switch and a first programmable gain amplifier; 4. The dual lane parallel processing architecture of claim 1, wherein, ​ The duplexer is used for frequency isolation of the first target signal to maintain the original bandwidth and dynamic range of the first target signal, an input end of the duplexer is used for receiving the first target signal, a first output end of the duplexer is used for outputting a first isolated signal, and a second output end of the duplexer is used for outputting a second isolated signal; A first input end of the selection switch is used for receiving the second isolated signal, a second input end of the selection switch is used for receiving a reference ground signal, and an output end of the selection switch is used for outputting the second isolated signal or the reference ground signal; A first input end of the first programmable gain amplifier is used for receiving the first isolated signal or a reference ground signal, a second input end of the first programmable gain amplifier is used for receiving the second isolated signal, and an output end of the first programmable gain amplifier is used for outputting the first gain signal.

5. The dual lane parallel processing architecture of claim 1, wherein, The high-gain channel circuit includes a filter network, a differential amplifier, a band-pass filter, a radio frequency switch, and a second programmable gain amplifier; A first end of the filter network is used for receiving the second target signal, and a second end of the filter network is used for outputting an initial filtered signal; An input end of the differential amplifier is used for receiving the initial filtered signal, a first output end of the differential amplifier is used for outputting a positive-phase amplified signal, and a second output end of the differential amplifier is used for outputting a negative-phase amplified signal; A first input end of the radio frequency switch is used for receiving the positive-phase amplified signal, a second input end of the radio frequency switch is used for receiving the negative-phase amplified signal, and an output end of the radio frequency switch is used for selecting the positive-phase amplified signal or the negative-phase amplified signal to be outputted; An input end of the band-pass filter is used for communicating with the output end of the radio frequency switch, and an output end of the band-pass filter is used for outputting a band-pass filtered signal corresponding to the positive-phase amplified signal or the negative-phase amplified signal; A first input end of the second programmable gain amplifier is used for receiving the band-pass filtered signal, and an output end of the second programmable gain amplifier is used for outputting the second gain signal.

6. The dual lane parallel processing architecture of claim 5, wherein, The filter network includes a first filter capacitor, a filter inductor, and a second filter capacitor; A first end of the first filter capacitor is electrically connected to a first end of the second filter capacitor, and a second end of the first filter capacitor is electrically connected to a first end of the filter inductor; A second end of the filter inductor is electrically connected to a second end of the second filter capacitor; The first end of the second filter capacitor serves as the first end of the filter network, and the second end of the second filter capacitor serves as the second end of the filter network.

7. The dual lane parallel processing architecture of claim 1, wherein, The digital signal processing unit further includes a clock processing unit circuit and at least two independent ADC acquisition unit circuits; The clock processing unit is used for synchronous clock control of the low-gain channel circuit and the high-gain channel circuit, and is used for driving the at least two independent ADC acquisition unit circuits to synchronously acquire and process the first gain signal and the second gain signal, and then transmit the first gain signal and the second gain signal to the FPGA chip.

8. The dual lane parallel processing architecture of any of claims 1-7, wherein, The waveform fusion splicing algorithm is used for fusion splicing processing of the first gain signal and the second gain signal, and a fusion signal is generated, including: determining an effective overlap time period of the first gain signal and the second gain signal wherein denotes a signal sample point at the effective overlap time period; The first gain signal and the second gain signal are normalized respectively: ； wherein, G is a gain coefficient of the low gain channel circuit, G is a gain coefficient of the high gain channel circuit; Generating fusion signals using weighted superposition : ; wherein is a weighting factor for the second gain signal.

9. The dual lane parallel processing architecture of claim 8, wherein, Further including: Obtain the first gain signal Spectrum information and the second gain signal Spectrum information The weighting coefficients of the second gain signal are determined based on the spectral information. : ； wherein, is a spectral correlation term adjustment factor, is a spectral correlation index, is an index frequency of the spectrum, and outputs a weight adjustment factor in the range [0, 1]; is a base weight for the second gain signal; is a real-time signal-to-noise ratio for the second gain signal; is a real-time signal-to-noise ratio for the first gain signal.

10. The dual lane parallel processing architecture of claim 9, wherein, Also included is determining a base weight of the second gain signal : ； wherein: a signal strength of the second gain signal representing the current signal sample point; a weak signal threshold, a strong signal threshold, is an empirical coefficient, is a signal decay rate.

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