A touch detection circuit, a touch detection chip, and a touch key circuit

Abstract

The present invention relates to the field of touch detection technology and discloses a touch detection circuit, a touch detection chip, and a touch key circuit. The touch detection circuit includes a comparator CMP1, a reference voltage generating unit, a first delay unit, an SR trigger SR1, a first control switch, a second control switch, a third control switch, a fourth control switch, a fifth control switch, a capacitor C3, a drive unit, and a counting unit. The touch detection circuit and the touch key circuit of the present invention are provided with a capacitor C3. By controlling the on and off of the fourth control switch and the fifth control switch, when a finger touches the capacitor C6, part of the charge is released by the capacitor C3, thereby increasing the charging time of the capacitor C8. In this way, the difference in the charging time of the capacitor C8 when the capacitor C6 is touched and when the capacitor C6 is not touched is increased, that is, the sensitivity is improved, thereby achieving more accurate touch detection.

Description

Technical Field

[0001] The present invention relates to the field of touch detection technology, and in particular to a touch detection circuit, a touch detection chip, and a touch key circuit. Background Art

[0002] With the rapid development of electronic technology, many electronic products use touch buttons as a human-computer interaction medium in order to make the use of electronic products more convenient. Currently, the commonly used touch buttons can be divided into two types: resistive touch buttons and capacitive touch buttons. The working principles of these two types of touch buttons are as follows:

[0003] For resistive touch buttons, the principle is that when the human body presses on the resistor, the resistance value changes, and the change in resistance value causes the signal of the entire circuit to change, ultimately achieving the detection effect. However, the disadvantage of this detection method is that after long-term use, a large pressure is required for correct recognition, which is not a good user experience.

[0004] For capacitive touch buttons, the principle is that when the human body approaches the capacitive button, the current generated by the human body is coupled to the static capacitor, thereby increasing the capacitance value of the capacitive button. The change in capacitance value is judged by the working circuit inside the chip, and this change is converted into a digital signal to achieve the purpose of controlling the electronic device.

[0005] Due to the defects of resistive touch buttons, capacitive touch buttons are increasingly used. Figure 1 As shown, the capacitor CP is the capacitive button, the capacitor CF is the equivalent capacitance to ground when the human body touches the capacitive button, and the capacitor CX is the detection capacitor;

[0006] In actual use, the charge on capacitor CP is continuously transferred to capacitor CX by controlling the on and off of switches S2 and S3. When the human body touches the capacitive button, the charging time of capacitor CX is shorter than when it is not touched. Therefore, touch detection can be achieved based on the change in the charging time of capacitor CX.

[0007] As touch solutions become more and more complex, more and more touch buttons are required. A single IC can integrate dozens of buttons. At the same time, the capacitance of the capacitor CX is also required, which is generally less than 10nF. This puts higher demands on the sensitivity of touch detection. Figure 1 The circuit is connected in parallel by switches because all the capacitor buttons are connected in parallel ( Figure 1The diagram in the figure shows a single capacitive button (capacitor CP). The capacitive button pins and touch channel routing result in a very large parasitic capacitance CL. When external noise interference is significant, the capacitance changes very little after a finger touches the capacitive button, resulting in a small change in the charge and discharge times of capacitor CX. This poses a risk of masking the noise, making it impossible to effectively detect touch actions and resulting in low detection accuracy. Summary of the Invention

[0008] In view of the shortcomings of the background technology, the present invention provides a touch detection circuit, a touch detection chip and a touch button circuit. The technical problem to be solved is that when the number of buttons is large, the existing capacitive touch detection circuit may not be able to effectively detect the occurrence of touch actions due to the large capacitance of the parasitic current CL, and the detection accuracy is low.

[0009] To solve the above technical problems, in a first aspect, the present invention provides the following technical solutions: a touch detection circuit, comprising a comparator CMP1, a reference voltage generating unit, a first delay unit, an SR trigger SR1, a first control switch, a second control switch, a third control switch, a fourth control switch, a fifth control switch, a capacitor C3, a driving unit, and a counting unit;

[0010] The first control switch, the second control switch and the third control switch are connected in series in sequence, the input end of the first control switch is used to input the working voltage, and the output end of the third control switch is grounded;

[0011] The input end of the fourth control switch is electrically connected to the input end of the third control switch, the output end of the fourth control switch is electrically connected to the input end of the fifth control switch and is grounded via the capacitor C3, and the output end of the fifth control switch is grounded;

[0012] The positive input terminal of the comparator CMP1 is used to input the voltage to be measured, the reference voltage generating unit is used to provide a reference voltage for the negative input terminal of the comparator CMP1, the output terminal of the comparator CMP1 is electrically connected to the R input terminal of the SR trigger SR1 through the first delay unit, and the S input terminal of the SR trigger SR1 is used to input the trigger signal PPL;

[0013] The driving unit is electrically connected to the Q output terminal and the Q non-output terminal of the SR trigger SR1, and controls the on and off of the first control switch, the second control switch, the third control switch, the fourth control switch, and the fifth control switch based on the signal level state of the Q output terminal and the Q non-output terminal of the SR trigger SR1;

[0014] The counting unit is electrically connected to the Q output terminal of the SR flip-flop SR1 and starts counting when the output signal of the Q output terminal of the SR flip-flop SR1 is at a high level.

[0015] In certain embodiments of the first aspect, the driving unit simultaneously drives the first control switch and the fifth control switch to be turned on or off, and simultaneously drives the second control switch and the fourth control switch to be turned on or off, and drives the second control switch to be turned off when driving the first control switch to be turned on, and drives the second control switch to be turned on when driving the first control switch to be turned off;

[0016] The driving unit drives the third control switch to be turned on when the signal outputted from the Q output terminal of the SR flip-flop SR1 is at a low level, and otherwise drives the third control switch to be turned off.

[0017] In a certain implementation manner of the first aspect, the first control switch is a PMOS transistor, the second control switch is a transmission gate TG1 , and the third to fifth control switches are all NMOS transistors.

[0018] In certain embodiments of the first aspect, the driving unit includes AND gates AND1 to AND5, inverters INV1 to INV4, and a NOR gate NOR1;

[0019] The two input terminals of the AND gate AND5 are respectively used to input the start signal STH and the enable signal ENH, and the enable signal ENH is also respectively input to one input terminal of the AND gate AND2, one input terminal of the AND gate AND3, one input terminal of the AND gate AND4, and the input terminal of the inverter INV1; the frequency of the start signal STH is the same as the frequency of the enable signal ENH, the rising edge of the start signal STH is later than that of the enable signal ENH, and the high level duration of the start signal STH is shorter than the high level duration of the enable signal ENH;

[0020] The output end of the AND gate AND5 is electrically connected to the input end of the second delay unit and one input end of the AND gate AND1 respectively, the output end of the second delay unit is electrically connected to the other input end of the AND gate AND1, and the output end of the AND gate AND1 is electrically connected to the S input end of the SR trigger SR1;

[0021] The other input terminal of the AND gate AND2 is electrically connected to the Q non-output terminal of the SR flip-flop SR1, and the output terminal of the AND gate AND2 is electrically connected to the control terminal of the third control switch;

[0022] The Q output terminal of the SR flip-flop SR1 is electrically connected to the second input terminal of the AND gate AND3, the third input terminal of the AND gate AND3 is used to input the clock signal CTCK, the output terminal of the AND gate AND3 is electrically connected to the input terminal of the inverter INV2, the output terminal of the inverter INV2 is electrically connected to the second input terminal of the AND gate AND4 and the second input terminal of the NOR gate NOR1, and the third input terminal of the AND gate AND4 is electrically connected to the output terminal of the NOR gate NOR1, the input terminal of the inverter INV3, and the control terminal of the fourth control switch;

[0023] The output end of the inverter INV1 is electrically connected to the first input end of the NOR gate NOR1, and the third input end of the NOR gate NOR1 is electrically connected to the output end of the AND gate AND4, the input end of the inverter INV4, the control end of the fifth control switch and the first control end of the transmission gate TG1 respectively;

[0024] The output end of the inverter INV3 is electrically connected to the control end of the first control switch, and the output end of the inverter INV4 is electrically connected to the second control end of the transmission gate TG1.

[0025] In a certain embodiment of the first aspect, the reference voltage provided by the reference voltage generating unit to the negative input terminal of the comparator CMP1 is adjustable in size; the reference voltage generating unit includes a resistance branch formed by multiple resistors connected in series, at least one intermediate node on the resistance branch is connected to a sixth control switch, and the output terminal of each sixth control switch is electrically connected to the negative input terminal of the comparator CMP1.

[0026] In a certain embodiment of the first aspect, the present invention also includes a selector SEL1, the output end of the first delay unit is electrically connected to the first input end of the selector SEL1, and is also electrically connected to the second input end of the selector SEL1 through the digital filtering unit, and the output end of the selector SEL1 is electrically connected to the R input end of the SR trigger SR1.

[0027] In certain implementations of the first aspect, the positive input terminal of the comparator CMP1 is electrically connected to an RC filtering unit.

[0028] In certain embodiments of the first aspect, the RC filter unit includes a resistor R1 and a capacitor C1, the positive input terminal of the comparator CMP1 is electrically connected to one end of the resistor R1 and one end of the capacitor C1, respectively, the other end of the capacitor C1 is grounded, and the other end of the resistor R1 is used to input the voltage to be measured;

[0029] The negative input terminal of the comparator CMP1 is also grounded via a capacitor C2;

[0030] The output end of the first control switch is electrically connected to a resistor R2 , and the output end of the second control switch is electrically connected to a resistor R3 .

[0031] In a second aspect, the present invention further provides a touch detection chip, on which the above-mentioned touch detection circuit is provided.

[0032] In a third aspect, the present invention further provides a touch key circuit, comprising the above-mentioned touch detection circuit, further comprising a charging branch and a plurality of key branches, each key branch comprising a seventh control switch and a capacitor C6, one end of the capacitor C6 being grounded, and the other end being electrically connected to the resistor R2 via the seventh control switch;

[0033] The charging branch includes a capacitor C8 and an eighth control switch. The other end of the capacitor C8 is grounded, and the other end of the capacitor C8 is electrically connected to the resistor R3 through the eighth control switch.

[0034] The beneficial effects of the present invention compared with the prior art are as follows: for the touch detection circuit and touch button circuit of the present invention, by setting the capacitor C3, by controlling the on and off of the fourth control switch and the fifth control switch, when a finger touches the capacitor C6, part of the charge will be released by the capacitor C3, thereby increasing the filling time of the capacitor C8. In this way, the difference in the filling time of the capacitor C8 when the capacitor C6 is touched and when the capacitor C6 is not touched becomes larger, that is, the sensitivity is improved, thereby achieving more accurate touch detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A circuit diagram of an existing capacitive touch detection circuit;

[0036] Figure 2 is a circuit diagram of the touch detection circuit in Example 1;

[0037] Figure 3 This is a circuit diagram of the touch button circuit in Example 3;

[0038] Figure 4 for Figure 3 The relevant signal waveforms when the circuit shown is used. DETAILED DESCRIPTION

[0039] The present invention will now be described in further detail with reference to the accompanying drawings, which are simplified schematic diagrams that illustrate the basic structure of the present invention in a schematic manner.

[0040] Example 1

[0041] like Figure 2As shown, a touch detection circuit provided by this embodiment includes a comparator CMP1, a reference voltage generating unit 2, a first delay unit 1, an SR trigger SR1, a first control switch, a second control switch, a third control switch, a fourth control switch, a fifth control switch, a capacitor C3, a driving unit 3 and a counting unit 9;

[0042] exist Figure 2 In the embodiment, the first control switch is a PMOS transistor P1, the second control switch is a transmission gate TG1, the third control switch is an NMOS transistor N1, the fourth control switch is an NMOS transistor N2, and the fifth control switch is an NMOS transistor N3;

[0043] The first control switch, the second control switch and the third control switch are connected in series in sequence, the input end of the first control switch is used to input the working voltage, and the output end of the third control switch is grounded;

[0044] The input end of the fourth control switch is electrically connected to the input end of the third control switch, the output end of the fourth control switch is electrically connected to the input end of the fifth control switch and is grounded via the capacitor C3, and the output end of the fifth control switch is grounded;

[0045] The positive input terminal of the comparator CMP1 is used to input the voltage to be measured, where the voltage to be measured is Figure 3 The voltage on the capacitor C8 in the reference voltage generating unit 2 is used to provide a reference voltage for the negative input terminal of the comparator CMP1, the output terminal of the comparator CMP1 is electrically connected to the R input terminal of the SR trigger SR1 through the first delay unit 1, and the S input terminal of the SR trigger SR1 is used to input the trigger signal PPL;

[0046] The driving unit 3 is electrically connected to the Q output terminal and the Q non-output terminal of the SR flip-flop SR1, and controls the on and off of the first control switch, the second control switch, the third control switch, the fourth control switch, and the fifth control switch based on the signal level state of the Q output terminal and the Q non-output terminal of the SR flip-flop SR1;

[0047] The counting unit 9 is electrically connected to the Q output terminal of the SR flip-flop SR1 and starts counting when the output signal of the Q output terminal of the SR flip-flop SR1 is at a high level.

[0048] In actual use, for the touch detection circuit of the present invention, by setting the capacitor C3, by controlling the on and off of the fourth control switch and the fifth control switch, when a finger touches the capacitor C6, part of the charge will be released by the capacitor C3, thereby increasing the filling time of the capacitor C8. In this way, the difference in the filling time of the capacitor C8 when the capacitor C6 is touched and when the capacitor C6 is not touched becomes larger, that is, the sensitivity is improved, so that touch detection can be achieved more accurately.

[0049] Specifically, in this embodiment, the on-off control method of the first control switch to the fifth control switch is as follows:

[0050] The driving unit 3 drives the first control switch and the fifth control switch to be turned on or off simultaneously, and drives the second control switch and the fourth control switch to be turned on or off simultaneously, and drives the second control switch to be turned off when the first control switch is driven to be turned on, and drives the second control switch to be turned on when the first control switch is driven to be turned off;

[0051] The driving unit 3 drives the third control switch to turn on when the signal outputted from the Q output terminal of the SR flip-flop SR1 is at a low level, and otherwise drives the third control switch to turn off.

[0052] In this embodiment, Figure 2 As shown, the driving unit 3 includes AND gates AND1 to AND5, inverters INV1 to INV4 and a NOR gate NOR1;

[0053] The two input terminals of the AND gate AND5 are respectively used to input the start signal STH and the enable signal ENH. The enable signal ENH is also respectively input to one input terminal of the AND gate AND2, one input terminal of the AND gate AND3, one input terminal of the AND gate AND4, and the input terminal of the inverter INV1. The frequency of the start signal STH is the same as the frequency of the enable signal ENH. The rising edge of the start signal STH is later than that of the enable signal ENH, and the high-level duration of the start signal STH is shorter than the high-level duration of the enable signal ENH.

[0054] The output end of the AND gate AND5 is electrically connected to the input end of the second delay unit 4 and one input end of the AND gate AND1 respectively, the output end of the second delay unit 4 is electrically connected to the other input end of the AND gate AND1, and the output end of the AND gate AND1 is electrically connected to the S input end of the SR flip-flop SR1;

[0055] The other input terminal of the AND gate AND2 is electrically connected to the Q non-output terminal of the SR flip-flop SR1, and the output terminal of the AND gate AND2 is electrically connected to the control terminal of the third control switch;

[0056] The Q output terminal of the SR flip-flop SR1 is electrically connected to the second input terminal of the AND gate AND3, the third input terminal of the AND gate AND3 is used to input the clock signal CTCK, the output terminal of the AND gate AND3 is electrically connected to the input terminal of the inverter INV2, the output terminal of the inverter INV2 is electrically connected to the second input terminal of the AND gate AND4 and the second input terminal of the NOR gate NOR1, respectively, and the third input terminal of the AND gate AND4 is electrically connected to the output terminal of the NOR gate NOR1, the input terminal of the inverter INV3, and the control terminal of the fourth control switch, respectively;

[0057] The output terminal of the inverter INV1 is electrically connected to the first input terminal of the NOR gate NOR1, and the third input terminal of the NOR gate NOR1 is electrically connected to the output terminal of the AND gate AND4, the input terminal of the inverter INV4, the control terminal of the fifth control switch, and the first control terminal of the transmission gate TG1 respectively;

[0058] The output end of the inverter INV3 is electrically connected to the control end of the first control switch, and the output end of the inverter INV4 is electrically connected to the second control end of the transmission gate TG1.

[0059] In this embodiment, the clock signal CTCK can be generated by dividing the input clock by a frequency divider, so that the clock signal frequency required by the circuit can be set according to actual needs;

[0060] In addition, the counting unit 9 counts the clock during counting. The clock used for counting can also be generated by dividing the set input clock by a frequency divider.

[0061] Specifically, in this embodiment, the reference voltage provided by the reference voltage generating unit 2 to the negative input terminal of the comparator CMP1 is adjustable; Figure 2 In the embodiment, the reference voltage generating unit 2 includes a resistance branch formed by resistors R2 to R6 connected in series, four intermediate nodes on the resistance branch are connected to sixth control switches, and the output end of each sixth control switch is electrically connected to the negative input end of the comparator CMP1.

[0062] exist Figure 2 In the embodiment, the four sixth control switches are switch S1, switch S2, switch S3 and switch S4.

[0063] In actual use, the number and resistance values ​​of resistors in the resistance branch can be set according to actual needs to provide reference voltages of different sizes. In addition, the node position of the sixth control switch in parallel in the resistance branch can be selected according to actual needs.

[0064] Specifically, in this embodiment, Figure 2 In the present invention, the output end of the first delay unit 1 is electrically connected to the first input end of the selector SEL1, and is also electrically connected to the second input end of the selector SEL1 through the digital filtering unit 8, and the output end of the selector SEL1 is electrically connected to the R input end of the SR trigger SR1.

[0065] In actual use, the selector SEL1 can be set to determine whether to perform digital filtering on the output signal of the first delay unit 1 , thereby reducing interference in the signal input to the R input terminal of the SR latch SR1 .

[0066] Specifically, in this embodiment, Figure 2In the embodiment, the positive input terminal of the comparator CMP1 is electrically connected to the RC filter unit 5; in actual use, the voltage to be measured can be filtered by the RC filter unit 5, thereby ensuring that the signal input to the positive input terminal of the comparator CMP1 is clean.

[0067] More specifically, the RC filter unit 5 includes a resistor R1 and a capacitor C1, the positive input terminal of the comparator CMP1 is electrically connected to one end of the resistor R1 and one end of the capacitor C1 respectively, the other end of the capacitor C1 is grounded, and the other end of the resistor R1 is used to input the voltage to be measured;

[0068] In addition, Figure 2 In the figure, the negative input terminal of the comparator CMP1 is also grounded through the capacitor C2;

[0069] The output end of the first control switch is electrically connected to the resistor R2 , and the output end of the second control switch is electrically connected to the resistor R3 .

[0070] In addition, Figure 2 In the figure, the counting unit 9 is also electrically connected to a digital storage unit 10, through which the counting value of the counting unit 9 can be stored. In addition, an initialization unit can be set to set an initial value for the counting unit 9, so that the counting unit 9 can start counting from the initial value.

[0071] It should be noted that the working process of the touch detection circuit in this embodiment is described in the third embodiment and will not be described again here.

[0072] Example 2

[0073] This embodiment provides a touch detection chip, wherein the touch detection circuit in the first embodiment is provided on the touch detection chip.

[0074] Example 3

[0075] like Figure 3 As shown, this embodiment further provides a touch key circuit, including the touch detection circuit in the first embodiment, further including a charging branch 7 and a plurality of key branches 6, each key branch 6 includes a seventh control switch S5 and a capacitor C6, one end of the capacitor C6 is grounded, and the other end is electrically connected to the resistor R2 through the seventh control switch S5;

[0076] The charging branch 7 includes a capacitor C8 and an eighth control switch S6 . The other end of the capacitor C8 is grounded, and the other end of the capacitor C8 is electrically connected to the resistor R3 via the eighth control switch S6 .

[0077] for Figure 3 The circuit shown has the following working process:

[0078] S1: The driving unit 3 first drives the first control switch and the fourth control switch to turn on. At this time, the second control switch and the third control switch are turned off, and the eighth control switch S6 is turned on. The working voltage connected to the input end of the first control switch charges the capacitor C6, and at the same time, part of the charge on the capacitor C8 is transferred to the capacitor C3.

[0079] S2: Driving unit 3 drives the second control switch to turn on and the first control switch to turn off. At this time, the fourth control switch is turned off, the fifth control switch is turned on, and the seventh control switch S5 is turned on. Then, the charge on capacitor C3 is discharged through the fifth control switch.

[0080] S3: S1 and S2 are executed cyclically. When the voltage on the capacitor C8 reaches the reference voltage, the charge on the capacitor C8 is released through the third control switch, and the touch detection is completed.

[0081] for Figure 3 The circuit shown in the figure has the following relevant signal changes during actual use: Figure 4 As shown, Vcx is the voltage variation wavelength on the capacitor C8, CON1 is the signal waveform input to the control end of the first control switch, CON2 is the signal waveform input to the control end of the second control switch, specifically the signal waveform input to the gate of the left MOS transistor of the transmission gate TG1, DISCH is the signal waveform input to the control end of the third control switch, TMTR is the count value of the counting unit 9, and VREF is the reference voltage provided by the reference unit generating unit 2;

[0082] from Figure 4 It can be seen that the count value of the counting unit 9 changes when there is a finger touch or not.

[0083] The present invention is compared with the traditional touch detection circuit, and the relevant data are shown in Table 1:

[0084] Table 1

[0085]

[0086] As can be seen from Table 1, in the present invention, the difference in the number of full charges of capacitor C8 becomes larger when there is a finger touch and when there is no finger touch, so the detection accuracy is improved; in addition, by adjusting the capacitance value of capacitor C3, the improvement of different sensitivity performances can be achieved.

[0087] The above description is for inspiration. Based on the above description, relevant personnel can make various changes and modifications without departing from the technical concept of this invention. The technical scope of this invention is not limited to the content of the specification, but must be determined according to the scope of the claims.

Claims

1. A touch detection circuit, characterized in that: It includes a comparator CMP1, a reference voltage generating unit, a first delay unit, an SR trigger SR1, a first control switch, a second control switch, a third control switch, a fourth control switch, a fifth control switch, a capacitor C3, a driving unit and a counting unit; The first control switch, the second control switch and the third control switch are connected in series in sequence, the input end of the first control switch is used to input the working voltage, and the output end of the third control switch is grounded; The input end of the fourth control switch is electrically connected to the input end of the third control switch, the output end of the fourth control switch is electrically connected to the input end of the fifth control switch and is grounded via the capacitor C3, and the output end of the fifth control switch is grounded; The positive input terminal of the comparator CMP1 is used to input the voltage to be measured, the reference voltage generating unit is used to provide a reference voltage for the negative input terminal of the comparator CMP1, the output terminal of the comparator CMP1 is electrically connected to the R input terminal of the SR trigger SR1 through the first delay unit, the first delay unit is used to delay the output of the comparator CMP1 and then input it to the R input terminal of the SR trigger SR1, and the S input terminal of the SR trigger SR1 is used to input the trigger signal PPL; The driving unit is electrically connected to the Q output terminal and the Q non-output terminal of the SR trigger SR1, and controls the on and off of the first control switch, the second control switch, the third control switch, the fourth control switch, and the fifth control switch based on the signal level state of the Q output terminal and the Q non-output terminal of the SR trigger SR1; The counting unit is electrically connected to the Q output terminal of the SR flip-flop SR1 and starts counting when the output signal of the Q output terminal of the SR flip-flop SR1 is at a high level.

2. The touch detection circuit according to claim 1, wherein: The driving unit drives the first control switch and the fifth control switch to be turned on or off simultaneously, and drives the second control switch and the fourth control switch to be turned on or off simultaneously, and drives the second control switch to be turned off when driving the first control switch to be turned on, and drives the second control switch to be turned on when driving the first control switch to be turned off; The driving unit drives the third control switch to be turned on when the signal outputted from the Q output terminal of the SR flip-flop SR1 is at a low level, and otherwise drives the third control switch to be turned off.

3. The touch detection circuit according to claim 2, wherein: The first control switch is a PMOS transistor, the second control switch is a transmission gate TG1, and the third to fifth control switches are all NMOS transistors.

4. The touch detection circuit according to claim 3, wherein: The driving unit includes AND gates AND1 to AND5, inverters INV1 to INV4 and a NOR gate NOR1; The two input terminals of the AND gate AND5 are respectively used to input the start signal STH and the enable signal ENH, and the enable signal ENH is also respectively input to one input terminal of the AND gate AND2, one input terminal of the AND gate AND3, one input terminal of the AND gate AND4, and the input terminal of the inverter INV1; the frequency of the start signal STH is the same as the frequency of the enable signal ENH, the rising edge of the start signal STH is later than that of the enable signal ENH, and the high level duration of the start signal STH is shorter than the high level duration of the enable signal ENH; The output end of the AND gate AND5 is electrically connected to the input end of the second delay unit and one input end of the AND gate AND1 respectively, the output end of the second delay unit is electrically connected to the other input end of the AND gate AND1, and the output end of the AND gate AND1 is electrically connected to the S input end of the SR trigger SR1; The other input terminal of the AND gate AND2 is electrically connected to the Q non-output terminal of the SR flip-flop SR1, and the output terminal of the AND gate AND2 is electrically connected to the control terminal of the third control switch; The Q output terminal of the SR flip-flop SR1 is electrically connected to the second input terminal of the AND gate AND3, the third input terminal of the AND gate AND3 is used to input the clock signal CTCK, the output terminal of the AND gate AND3 is electrically connected to the input terminal of the inverter INV2, the output terminal of the inverter INV2 is electrically connected to the second input terminal of the AND gate AND4 and the second input terminal of the NOR gate NOR1, and the third input terminal of the AND gate AND4 is electrically connected to the output terminal of the NOR gate NOR1, the input terminal of the inverter INV3, and the control terminal of the fourth control switch; The output end of the inverter INV1 is electrically connected to the first input end of the NOR gate NOR1, and the third input end of the NOR gate NOR1 is electrically connected to the output end of the AND gate AND4, the input end of the inverter INV4, the control end of the fifth control switch and the first control end of the transmission gate TG1 respectively; The output end of the inverter INV3 is electrically connected to the control end of the first control switch, and the output end of the inverter INV4 is electrically connected to the second control end of the transmission gate TG1.

5. The touch detection circuit according to claim 1, wherein: The reference voltage provided by the reference voltage generating unit to the negative input terminal of the comparator CMP1 is adjustable in size; the reference voltage generating unit includes a resistance branch formed by multiple resistors connected in series, at least one intermediate node on the resistance branch is connected to a sixth control switch, and the output terminal of each sixth control switch is electrically connected to the negative input terminal of the comparator CMP1.

6. The touch detection circuit according to claim 1, wherein: It also includes a selector SEL1, the output end of the first delay unit is electrically connected to the first input end of the selector SEL1, and is also electrically connected to the second input end of the selector SEL1 through the digital filtering unit, and the output end of the selector SEL1 is electrically connected to the R input end of the SR trigger SR1.

7. A touch detection circuit according to any one of claims 1 to 6, characterized in that: The positive input terminal of the comparator CMP1 is electrically connected to an RC filter unit.

8. The touch detection circuit according to claim 7, wherein: The RC filter unit includes a resistor R1 and a capacitor C1, the positive input end of the comparator CMP1 is electrically connected to one end of the resistor R1 and one end of the capacitor C1 respectively, the other end of the capacitor C1 is grounded, and the other end of the resistor R1 is used to input the voltage to be measured; The negative input terminal of the comparator CMP1 is also grounded via a capacitor C2; The output end of the first control switch is electrically connected to a resistor R2 , and the output end of the second control switch is electrically connected to a resistor R3 .

9. A touch detection chip, characterized in that: The touch detection circuit according to claim 8 is provided on the touch detection chip.

10. A touch button circuit, characterized in that: The touch detection circuit according to claim 8 further includes a charging branch and a plurality of key branches, each key branch including a seventh control switch and a capacitor C6, one end of the capacitor C6 is grounded, and the other end is electrically connected to the resistor R2 through the seventh control switch; The charging branch includes a capacitor C8 and an eighth control switch. The other end of the capacitor C8 is grounded, and the other end of the capacitor C8 is electrically connected to the resistor R3 through the eighth control switch.

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