Driving circuit for composite dielectric gate photosensitive detector and driving method thereof

Abstract

The invention discloses a driving circuit for a composite dielectric gate photosensitive detector and a driving method thereof. The circuit comprises a logic circuit, a level conversion circuit and a core driving circuit, and the logic circuit is used for carrying out basic logic operation on a digital input signal to generate an enable signal for controlling the level conversion circuit to work; the level conversion circuit is used for outputting a high / low level according to the enable signal to control on and off of a transistor in the core driving circuit; and the core driving circuit finally outputs positive / negative high voltage or low voltage according to a signal sent by the pre-stage circuit. According to the circuit structure, accurate and rapid driving voltage transmission can be achieved, the driving voltage can be used for switching the working state of the composite dielectric gate photosensitive detector, and the circuit structure is simple, small in area and compatible with the standard integrated circuit technology.

Description

Technical Field

[0001] The present invention relates to a driving circuit and a driving method for a composite dielectric gate photosensitive detector, belonging to the field of integrated circuits. Background Art

[0002] A composite dielectric gate photosensitive detector is a photosensitive transistor with a structure similar to that of a floating gate device. Its working principle is based on the photoelectric effect. The semiconductor substrate absorbs photons in the light, enabling electrons in the valence band to gain sufficient energy to jump to the conduction band, thereby exciting the generation of electron-hole pairs. Under the action of an electric field, these electron-hole pairs are separated to form a photocurrent. Its working states mainly include three: reset, at this time, the gate terminal of the transistor is connected to a negative high voltage to release the residual electrons inside; exposure, the gate terminal of the transistor is connected to a low voltage and senses the ambient light environment of the field of view to complete the collection of photoelectrons; readout, a positive high voltage is applied to the gate terminal of the transistor to amplify and read the photoelectrons generated during the exposure stage. Compared with the basic imaging working process of reset-exposure-readout that requires multiple transistors to be integrated in a single pixel of a CIS (CMOS Image Sensor), a composite dielectric gate photosensitive detector can be realized with only a single transistor, greatly reducing the pixel area, which is beneficial to the improvement of imaging resolution and integration.

[0003] In order to give full play to the above advantages of the composite dielectric gate photosensitive detector, the high-voltage drive circuit for providing its operating voltage should be as simple as possible on the basis of being able to accurately transmit the required voltage to save area. In the prior art, MOSFET drive and IGBT drive are analyzed separately in the "Basic Principles of MOSFET and IGBT Gate Driver Circuits"; among them, the principle and structure of MOSFET drive are relatively simple. When a voltage is applied between the gate and source of the MOSFET, a conductive channel will be induced in the semiconductor material under the gate, allowing current to flow from the drain to the source; the switching state of the MOSFET is controlled by controlling the voltage of the gate; therefore, MOSFET drive is relatively simple. In low-frequency applications, a triode can be directly used for driving, and in high-frequency applications, a transformer or a dedicated chip is mostly used for driving; and because the gate input impedance of the MOSFET is very high, the loss of driving power is very small; however, MOSFET drive has relatively high requirements for the accuracy of the driving voltage. If the driving voltage is inaccurate, it may cause an increase in the on-resistance or a mis-conduction phenomenon; in addition, power devices such as resistors and inductors also need to be designed in the MOSFET drive circuit. The damping of the circuit is increased through the resistor to achieve current limiting and prevent parasitic oscillation, and the impedance of the matching signal source from the gate is matched to ensure the stable operation of the drive circuit; energy is released or absorbed through the inductor for filtering to provide a stable power supply environment for the MOSFET drive circuit, and high-frequency interference signals can also be effectively prevented from affecting normal switching operations; because it involves power devices such as resistors or inductors, the area is large, and the advantage of the small pixel of the composite dielectric gate photosensitive detector cannot be brought into play; the principle of IGBT drive is to control the conduction and turn-off of the IGBT by controlling the voltage between the gate and the emitter, which can carry high voltage and large current and is suitable for high-power scenarios; however, this drive circuit is relatively complex, and a single circuit cannot meet the conditions that the composite dielectric gate photosensitive detector needs to transmit negative high voltage and positive high voltage respectively in the reset and readout states, and two drive circuits, namely positive voltage drive and negative voltage drive, need to be designed separately according to the gate potential at turn-off; therefore, it will also cause excessive area power consumption.

[0004] Therefore, although the existing drive circuit structure can meet the requirements of different voltages required for the output of the composite dielectric gate photosensitive detector, due to the limitations of the circuit structure, it consumes a large amount of area power consumption and cannot bring into play the advantage of the small pixel area of the composite dielectric gate photosensitive detector. Summary of the Invention

[0005] Aiming at the defects existing in the above prior art, the present invention provides a drive circuit and a drive method for a composite dielectric gate photosensitive detector. This circuit structure is simple, does not contain large-area components, and can transmit all the voltages required for the operation of the composite dielectric gate photosensitive detector.

[0006] The first object of the present invention is to provide a driving circuit for a composite dielectric gate photosensitive detector, which driving circuit includes a logic circuit, a level conversion circuit, and a core driving circuit; Among them, the logic circuit includes a number of AND gates, OR gates, and inverters, and generates an enable signal for controlling the operation of the level conversion circuit by performing basic logic operations on digital input signals; The level conversion circuit includes a positive / negative high-voltage level conversion circuit and a low-voltage level conversion circuit, and controls the turning on and off of transistors in the core driving circuit according to the output result of the logic circuit; The core driving circuit includes 3 PMOS transistors and 2 NMOS transistors, and finally outputs positive / negative high voltage or low voltage by receiving the signal output by the level conversion circuit.

[0007] Further, the digital signals input to the logic circuit include SWITCH<1>, PULSE_TO_MUX, SWITCH<0>, and SWITCH<2>; Further, the positive high-voltage level conversion circuit in the level conversion circuit includes 4 PMOS transistors and 4 NMOS transistors; Further, the negative high-voltage level conversion circuit in the level conversion circuit includes 4 PMOS transistors and 4 NMOS transistors; Further, the low-voltage level conversion circuit in the level conversion circuit includes 2 PMOS transistors and 2 NMOS transistors; Further, the core driving circuit includes a first P-type MOS transistor PM1, a second P-type MOS transistor PM2, a first N-type MOS transistor NM1, a second N-type MOS transistor NM2, and a third N-type MOS transistor NM3; The first N-type MOS transistor NM1 is located in the low-voltage LV transmission path; the first P-type MOS transistor PM1 and the second P-type MOS transistor PM2 are located in the positive high-voltage HVP transmission path; the second N-type MOS transistor NM2 and the third N-type MOS transistor NM3 are located in the negative high-voltage HVN transmission path; The source inputs of the first N-type MOS transistor NM1, the first P-type MOS transistor PM1, and the second N-type MOS transistor NM2 are LV, HVP, and HVN respectively. The gate of the first N-type MOS transistor NM1 is connected to the output of the low-voltage level conversion circuit; the gate of the first P-type MOS transistor PM1 is connected to VHH, and the drain is connected to the source of the second P-type MOS transistor PM2; the gate of the second P-type MOS transistor PM2 is grounded; the source input of the second N-type MOS transistor NM2 is HVN, the gate is connected to the output VLL of the negative high-voltage level conversion circuit, the drain is connected to the source of the third N-type MOS transistor NM3, and the gate of the third N-type MOS transistor NM3 is grounded; the drains of the first N-type MOS transistor NM1, the second P-type MOS transistor PM2, and the third N-type MOS transistor NM3 are connected to each other and output the final output VO of the core driving circuit.

[0008] The second object of the present invention is to provide a driving method for a composite dielectric gate photosensitive detector, and the method includes: First, the logic circuit performs basic logic operations on the digital input signal to generate an enable signal for controlling the operation of the level conversion circuit; then the level conversion circuit outputs a high / low level according to the enable signal to control the turn-on and turn-off of the transistors in the core driving circuit; then the core driving circuit finally outputs a positive / negative high voltage or a low voltage according to the signal given by the level conversion circuit and transmits it to the control gate terminal of the composite dielectric gate photosensitive detector, thereby controlling its working state.

[0009] Further, the logic circuit is divided into three parts: The digital signals SWITCH<1> and PULSE_TO_MUX perform an AND operation once to generate an enable signal for the positive high voltage level conversion circuit (denoted as the positive high voltage enable signal); the enable signal of the positive high voltage level conversion circuit performs a reverse operation once to generate an input signal of the positive high voltage level conversion circuit (denoted as the positive high voltage input signal); The digital signal PULSE_TO_MUX performs a reverse operation once and then performs an AND operation with SWITCH<1>, and the generated signal performs an OR operation with SWITCH<0> once to generate an enable signal for the low voltage level conversion circuit (denoted as the low voltage enable signal); the enable signal of the low voltage level conversion circuit performs a reverse operation once to generate an input signal of the low voltage level conversion circuit (denoted as the low voltage input signal); The digital signal SWITCH<2> is the enable signal of the negative high voltage level conversion circuit (denoted as the negative high voltage enable signal); the enable signal of the negative high voltage level conversion circuit performs a reverse operation once to obtain an input signal of the negative high voltage level conversion circuit (denoted as the negative high voltage input signal).

[0010] Further, the positive high voltage input signal and the positive high voltage enable signal in the level conversion circuit act together to switch the amplitude of the output voltage: when the positive high voltage enable signal is at a high level and the positive high voltage input signal is at a low level, the output voltage Vout is equal to the input voltage Vin (Vin is a positive high voltage signal); when the positive high voltage enable signal is at a low level and the positive high voltage input signal is at a high level, the output voltage Vout is equal to the ground signal GND; the output signal of the positive high voltage level conversion circuit is VHH.

[0011] Further, in the negative high-voltage level conversion circuit of the level conversion circuit, the negative high-voltage input signal and the negative high-voltage enable signal act together to switch the amplitude of the output voltage: when the negative high-voltage enable signal is at a high level and the negative high-voltage input signal is at a low level, the output voltage Vout of the negative high-voltage level conversion circuit is equal to the input voltage Vin (Vin is a negative high-voltage signal); when the negative high-voltage enable signal is at a low level and the negative high-voltage input signal is at a high level, the output voltage Vout of the negative high-voltage level conversion circuit is equal to the ground signal GND.

[0012] Further, the low-voltage input signal in the level conversion circuit is the reverse signal of the low-voltage enable signal, and the two act together to switch the amplitude of the output voltage: when the low-voltage enable signal is at a high level and the low-voltage input signal is at a low level, the output voltage Vout is equal to the power supply signal VDD (VDD is a low-voltage signal); when the low-voltage enable signal is at a low level and the low-voltage input signal is at a high level, the output voltage Vout is equal to the ground signal GND; the output signal of the low-voltage level conversion circuit is EN_LV.

[0013] Further, in the core drive circuit, the first N-type MOS transistor NM1 is located in the low-voltage LV transmission path; the first P-type MOS transistor PM1 and the second P-type MOS transistor PM2 are located in the positive high-voltage HVP transmission path; the second N-type MOS transistor NM2 and the third N-type MOS transistor NM3 are located in the negative high-voltage HVN transmission path.

[0014] When the first P-type MOS transistor PM1 and the second N-type MOS transistor NM2 are in the off state and the first N-type MOS transistor NM1 is in the on state, the low-voltage LV transmission path is turned on, and the output voltage VO = LV; When the first N-type MOS transistor NM1 and the second N-type MOS transistor NM2 are in the off state and the first P-type MOS transistor PM1 and the second P-type MOS transistor PM2 are in the on state, the positive high-voltage HVP transmission path is turned on, and the output voltage VO = HVP; When the first N-type MOS transistor NM1 and the first P-type MOS transistor PM1 are in the off state and the second N-type MOS transistor NM2 and the third N-type MOS transistor NM3 are in the on state, the negative high-voltage HVN transmission path is turned on, and the output voltage VO = HVN.

[0015] The beneficial effects of the present invention are: The present invention provides a driving circuit for a composite dielectric grating photosensitive detector and a driving method thereof. The driving circuit includes a logic circuit, a level conversion circuit and a core driving circuit. All modules are composed of only basic transistor devices, without large-area components such as resistors and inductors, and the overall area consumption is small. Compared with the existing driving circuits, a single circuit can transmit positive / negative high voltages to meet the working voltage supply requirements of the composite dielectric grating photosensitive detector. In addition, the circuit provided by the present invention adopts a design compatible with standard integrated circuit processes, making it possible to apply the circuit structure in large-scale composite dielectric grating photosensitive detector arrays. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 It is a schematic diagram of the overall structure of a driving circuit structure for a composite dielectric grating photosensitive detector provided by the present invention; Figure 2 It is a schematic diagram of the structure of a positive high voltage level conversion circuit and a schematic diagram of a signal waveform in a driving circuit for a composite dielectric grating photosensitive detector provided by the present invention; Figure 3 It is a schematic diagram of the structure of a negative high voltage level conversion circuit and a schematic diagram of a signal waveform in a driving circuit for a composite dielectric grating photosensitive detector provided by the present invention; Figure 4 It is a schematic diagram of the structure of a low-voltage level conversion circuit and a schematic diagram of a signal waveform in a driving circuit for a composite dielectric grating photosensitive detector provided by the present invention; Figure 5 It is a truth value comparison table of input signal and output signal of a driving circuit for a composite dielectric grating photosensitive detector provided by the present invention; Figure 6 The present invention provides a signal waveform diagram for a driving circuit of a composite dielectric grating photosensitive detector. DETAILED DESCRIPTION

[0018] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0019] Embodiment 1 This embodiment provides a driving circuit for a composite dielectric grating photosensitive detector, such as Figure 1As shown in the figure, the drive circuit includes a logic circuit, a level conversion circuit, and a core drive circuit, and a total of 13 N-type transistors, 12 P-type transistors, 4 inverters, 2 AND gates, and 1 OR gate are used; Among them, the logic circuit includes 4 inverters, 2 AND gates, and 1 OR gate, and generates an enable signal for controlling the operation of the level conversion circuit by performing basic logic operations on the digital input signals; the inputs of the logic circuit include SWITCH<1>, PULSE_TO_MUX, SWITCH<0>, and SWITCH<2>; The digital signals SWITCH<1> and PULSE_TO_MUX perform an AND operation once to generate an enable signal for the positive high-voltage level conversion circuit (denoted as the positive high-voltage enable signal); the enable signal of the positive high-voltage level conversion circuit performs a reverse operation once to generate an input signal for the positive high-voltage level conversion circuit (denoted as the positive high-voltage input signal); The digital signal PULSE_TO_MUX performs a reverse operation once and then performs an AND operation with SWITCH<1>, and the generated signal performs an OR operation with SWITCH<0> once to generate an enable signal for the low-voltage level conversion circuit (denoted as the low-voltage enable signal); the enable signal of the low-voltage level conversion circuit performs a reverse operation once to generate an input signal for the low-voltage level conversion circuit (denoted as the low-voltage input signal); The digital signal SWITCH<2> is the enable signal for the negative high-voltage level conversion circuit (denoted as the negative high-voltage enable signal); the enable signal of the negative high-voltage level conversion circuit performs a reverse operation once to obtain an input signal for the negative high-voltage level conversion circuit (denoted as the negative high-voltage input signal).

[0020] The level conversion circuit includes a positive high-voltage level conversion circuit, a negative high-voltage level conversion circuit, and a low-voltage level conversion circuit, and realizes the control of the turning on and off of the transistors in the core drive circuit according to the output result of the logic circuit; The structure of the positive high-voltage level conversion circuit is as Figure 2 shown, and includes the third P-type MOS transistor PM3, the fourth P-type MOS transistor PM4, the fifth P-type MOS transistor PM5, the sixth P-type MOS transistor PM6, the fourth N-type MOS transistor NM4, the fifth N-type MOS transistor NM5, the sixth N-type MOS transistor NM6, and the seventh N-type MOS transistor NM7; The gate terminals of the sixth N-type MOS transistor NM6 and the seventh N-type MOS transistor NM7 are respectively connected to a positive high-voltage enable signal and a positive high-voltage input signal, the source terminals are grounded to the signal GND, and the drain terminals are respectively connected to the source terminals of the fourth N-type MOS transistor NM4 and the fifth N-type MOS transistor NM5; the drain terminals of the fourth N-type MOS transistor NM4 and the fifth N-type MOS transistor NM5 are respectively connected to the drain terminals of the fifth P-type MOS transistor PM5 and the sixth P-type MOS transistor PM6; the source terminals of the fifth P-type MOS transistor PM5 and the sixth P-type MOS transistor PM6 are respectively connected to the drain terminals of the third P-type MOS transistor PM3 and the fourth P-type MOS transistor PM4; the gate terminals of the fourth N-type MOS transistor NM4, the fifth N-type MOS transistor NM5, the fifth P-type MOS transistor PM5 and the sixth P-type MOS transistor PM6 are simultaneously connected to the power supply signal VDD; the source terminals of the third P-type MOS transistor PM3 and the fourth P-type MOS transistor PM4 are connected to the input voltage Vin; the gate terminal of the third P-type MOS transistor PM3 is connected to the source terminal of the sixth P-type MOS transistor PM6; the drain terminal of the third P-type MOS transistor PM3 is connected to the gate terminal of the fourth P-type MOS transistor PM4 and the source terminal of the fifth P-type MOS transistor PM5 to form the output Vout of the positive high-voltage level conversion circuit; The conduction states of the sixth N-type MOS transistor NM6 and the seventh N-type MOS transistor NM7 are controlled by the positive high-voltage enable signal and the positive high-voltage input signal, thereby controlling the states of two branches, and thus adjusting the output Vout of the positive high-voltage level conversion circuit to the input voltage Vin or the ground signal GND.

[0021] The structure of the negative high-voltage level conversion circuit is as Figure 3 shown, the seventh P-type MOS transistor PM7, the eighth P-type MOS transistor PM8, the ninth P-type MOS transistor PM9, the tenth P-type MOS transistor PM10, the eighth N-type MOS transistor NM8, the ninth N-type MOS transistor NM9, the tenth N-type MOS transistor NM10 and the eleventh N-type MOS transistor NM11; The source terminals of the seventh P-type MOS transistor PM7 and the eighth P-type MOS transistor PM8 are connected to the power supply VDD. The gate terminals are respectively connected to the negative high-voltage input signal and the negative high-voltage enable signal. The drain terminals are respectively connected to the source terminals of the ninth P-type MOS transistor PM9 and the tenth P-type MOS transistor PM10. The gate terminals of the ninth P-type MOS transistor PM9 and the tenth P-type MOS transistor PM10 are simultaneously connected to the ground signal GND. The drain terminals are respectively connected to the drain terminals of the eighth N-type MOS transistor NM8 and the ninth N-type MOS transistor NM9. The source terminals of the eighth N-type MOS transistor NM8 and the ninth N-type MOS transistor NM9 are respectively connected to the drain terminals of the tenth N-type MOS transistor NM10 and the eleventh N-type MOS transistor NM11. The source terminals of the tenth N-type MOS transistor NM10 and the eleventh N-type MOS transistor NM11 are simultaneously connected to the input voltage Vin. The gate terminals of the eighth N-type MOS transistor NM8 and the eleventh N-type MOS transistor NM11 are simultaneously connected to the drain terminal of the tenth P-type MOS transistor PM10. The gate terminals of the ninth N-type MOS transistor NM9 and the tenth N-type MOS transistor NM10 and the drain terminal of the ninth P-type MOS transistor PM9 are simultaneously connected to the output Vout of the negative high-voltage level conversion circuit. The conduction states of the seventh P-type MOS transistor PM7 and the eighth P-type MOS transistor PM8 are controlled by the negative high-voltage input signal and the negative high-voltage enable signal, thereby controlling the states of the two branches, and thus adjusting the output Vout of the negative high-voltage level conversion circuit to the input voltage Vin or the ground signal GND.

[0022] The structure of the low-voltage level conversion circuit is as Figure 4 shown, including the eleventh P-type MOS transistor PM11, the twelfth P-type MOS transistor PM12, the twelfth N-type MOS transistor NM12, and the thirteenth N-type MOS transistor NM13. The gate terminals of the twelfth N-type MOS transistor NM12 and the thirteenth N-type MOS transistor NM13 are respectively connected to the low-voltage input signal and the low-voltage enable signal. The source terminals are simultaneously connected to the ground signal GND. The drain terminals are respectively connected to the drain terminals of the eleventh P-type MOS transistor PM11 and the twelfth P-type MOS transistor PM12. The source terminals of the eleventh P-type MOS transistor PM11 and the twelfth P-type MOS transistor PM12 are connected to the power supply VDD. The gate terminal of the twelfth P-type MOS transistor PM12 is connected to the drain terminal of the twelfth N-type MOS transistor NM12. The gate terminal of the eleventh P-type MOS transistor PM11 is connected to the drain terminal of the thirteenth N-type MOS transistor NM13 as the output Vout of the low-voltage level conversion circuit. The conduction states of the twelfth N-type MOS transistor NM12 and the thirteenth N-type MOS transistor NM13 are controlled by the low-voltage input signal and the low-voltage enable signal, thereby controlling the states of the two branches, and thus adjusting the output Vout of the low-voltage level conversion circuit to the power supply VDD or the ground signal GND.

[0023] The core drive circuit includes a first P-type MOS transistor PM1, a second P-type MOS transistor PM2, a first N-type MOS transistor NM1, a second N-type MOS transistor NM2, and a third N-type MOS transistor NM3; and finally outputs positive / negative high voltage or low voltage by receiving the signal output by the level conversion circuit.

[0024] The source electrodes of the first N-type MOS transistor NM1, the first P-type MOS transistor PM1, and the second N-type MOS transistor NM2 receive LV, HVP, and HVN respectively. The gate of the first N-type MOS transistor NM1 is connected to the output EN_LV of the low-voltage level conversion circuit; the source electrode input of the first P-type MOS transistor PM1 is HVP, the gate is connected to the output VHH of the positive high-voltage level conversion circuit, and the drain is connected to the source electrode of the second P-type MOS transistor PM2; the gate of the second P-type MOS transistor PM2 is grounded; the source electrode input of the second N-type MOS transistor NM2 is HVN, the gate is connected to the output VLL of the negative high-voltage level conversion circuit, and the drain is connected to the source electrode of the third N-type MOS transistor NM3. The gate of the third N-type MOS transistor NM3 is grounded; the drains of the first N-type MOS transistor NM1, the second P-type MOS transistor PM2, and the third N-type MOS transistor NM3 are connected to each other and output the final output VO of the core drive circuit.

[0025] Embodiment 2 This embodiment provides a driving method for a composite dielectric gate photosensitive detector. This method is implemented based on the driving circuit provided in Embodiment 1. Specifically, this method includes: In the logic circuit, the digital signals SWITCH<1> and PULSE_TO_MUX undergo an AND operation once to generate the enable signal of the positive high-voltage level conversion circuit; the input signal of the positive high-voltage level conversion circuit is the inverted signal of the enable signal of the positive high-voltage level conversion circuit; The digital signal PULSE_TO_MUX undergoes an inversion operation once and then undergoes an AND operation with SWITCH<1>. The generated signal then undergoes an OR operation with SWITCH<0> to generate the enable signal of the low-voltage level conversion circuit; the input signal of the low-voltage level conversion circuit is the inverted signal of the enable signal of the low-voltage level conversion circuit; The digital signal SWITCH<2> is the enable signal of the negative high-voltage level conversion circuit, and the input signal of the negative high-voltage level conversion circuit is the inverted signal of the enable signal of the negative high-voltage level conversion circuit.

[0026] The waveforms of the enable signal and the input signal of the positive high-voltage level conversion circuit in the level conversion circuit are as Figure 2As shown, when the positive high-voltage enable signal is at a high level and the positive high-voltage input signal is at a low level, the output voltage Vout of the positive high-voltage level conversion circuit is equal to the input voltage Vin (Vin is the positive high-voltage signal); when the high-voltage enable signal is at a low level and the positive high-voltage input signal is at a high level, the output voltage Vout is equal to the ground signal GND.

[0027] The waveforms of the enable signal and the input signal of the negative high-voltage level conversion circuit in the level conversion circuit are as Figure 3 shown. When the enable signal of the negative high-voltage level conversion circuit is at a high level and the input signal of the negative high-voltage level conversion circuit is at a low level, the output voltage Vout of the negative high-voltage level conversion circuit is equal to the input voltage Vin (Vin is the negative high-voltage signal); when the enable signal of the negative high-voltage level conversion circuit is at a low level and the input signal of the negative high-voltage level conversion circuit is at a high level, the output voltage Vout of the negative high-voltage level conversion circuit is equal to the ground signal GND; The waveforms of the enable signal and the input signal of the low-voltage level conversion circuit in the level conversion circuit are as Figure 4 shown. When the enable signal of the low-voltage level conversion circuit is at a high level and the input signal of the low-voltage level conversion circuit is at a low level, the output voltage Vout of the low-voltage level conversion circuit is equal to the power supply signal VDD (VDD is the low-voltage signal); when the enable signal of the low-voltage level conversion circuit is at a low level and the input signal of the low-voltage level conversion circuit is at a high level, the output voltage Vout of the low-voltage level conversion circuit is equal to the ground signal GND.

[0028] In the core drive circuit: The first N-type MOS transistor NM1 in the core drive circuit is located in the low-voltage LV transmission path; the first P-type MOS transistor PM1 and the second P-type MOS transistor PM2 are located in the positive high-voltage HVP transmission path; the second N-type MOS transistor NM2 and the third N-type MOS transistor NM3 are located in the negative high-voltage HVN transmission path.

[0029] When the first P-type MOS transistor PM1 and the second N-type MOS transistor NM2 are in the off state and the first N-type MOS transistor NM1 is in the on state, the low-voltage LV transmission path is turned on, and the output voltage VO = LV; When the first N-type MOS transistor NM1 and the second N-type MOS transistor NM2 are in the off state and the first P-type MOS transistor PM1 and the second P-type MOS transistor PM2 are in the on state, the positive high-voltage HVP transmission path is turned on, and the output voltage VO = HVP; When the first N-type MOS transistor NM1 and the first P-type MOS transistor PM1 are in the off state and the second N-type MOS transistor NM2 and the third N-type MOS transistor NM3 are in the on state, the negative high-voltage HVN transmission path is turned on, and the output voltage VO = HVN.

[0030] The truth table of the four input signals SWITCH<0>, SWITCH<1>, SWITCH<2> and PULSE_TO_MUX of the overall circuit and the output signal VO is as Figure 5 shown; When SWITCH<0> is 1, SWITCH<1> and SWITCH<2> are 0, or when SWITCH<1> is 1, SWITCH<2> and PULSE_TO_MUX are 0, VO is the input low voltage LV; When SWITCH<1> and PULSE_TO_MUX are 1, SWITCH<0> and SWITCH<2> are 0, VO is the input positive high voltage HVP; When SWITCH<2> is 1, SWITCH<0> and SWITCH<1> are 0, VO is the input negative high voltage HVN.

[0031] When applying the circuit to drive a composite dielectric gate photosensitive detector, it is first necessary to transmit a negative high voltage to reset it, then transmit a low voltage during the exposure of the detector, and finally transmit a positive high voltage to read the signal of the detector. Combining the working principle of the circuit, the corresponding working timing is as Figure 6 shown; First, set SWITCH<2> to 1 and the other signals to 0, transmit the negative high voltage signal HVN to VO and then to the gate terminal of the composite dielectric gate photosensitive detector, drive the composite dielectric gate photosensitive detector into the reset state, and release the residual electrons inside; Then, set SWITCH<0> to 1 and the other signals to 0, transmit the low voltage signal LV to VO and then to the gate terminal of the composite dielectric gate photosensitive detector, provide a bias voltage for its exposure stage, and enable it to complete the collection of photoelectrons; Finally, set SWITCH<1> and PULSE_TO_MUX to 1 and the other signals to 0, transmit the positive high voltage signal HVP to VO and then to the gate terminal of the composite dielectric gate photosensitive detector, and perform the amplification and reading of photoelectrons.

[0032] So far, a complete imaging process has been carried out.

[0033] Some steps in the embodiments of the present invention can be implemented by software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk, etc.

[0034] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A driving circuit for a composite dielectric gate photosensitive detector, characterized in that, The circuit includes: a logic circuit, a level conversion circuit, and a core drive circuit; The logic circuit is used to perform logic processing on the input digital signal; the level conversion circuit includes a positive high-voltage level conversion circuit, a negative high-voltage level conversion circuit, and a low-voltage level conversion circuit, and is used to output different level conversion signals; the core drive circuit controls the conduction states of different transmission paths according to the enable signal output by the level conversion circuit, and then outputs positive / negative high voltage or low voltage.

2. The circuit according to claim 1, wherein The transmission paths of the core drive circuit include a low-voltage LV transmission path, a positive high-voltage HVP transmission path, and a negative high-voltage HVN transmission path; The low-voltage LV transmission path includes 1 N-type MOS transistor, and the gate of the N-type MOS transistor is connected to the output of the low-voltage level conversion circuit; The positive high-voltage HVP transmission path includes two P-type MOS transistors, where the drain of one P-type MOS transistor is connected to the source of the other P-type MOS transistor, the gate is connected to the output of the positive high-voltage level conversion circuit, and the gate of the other P-type MOS transistor is grounded; The negative high-voltage HVN transmission path includes two N-type MOS transistors, where the drain of one N-type MOS transistor is connected to the source of the other N-type MOS transistor, the gate is connected to the output of the negative high-voltage level conversion circuit, and the gate of the other N-type MOS transistor is grounded; The outputs of the low-voltage LV transmission path, the positive high-voltage HVP transmission path, and the negative high-voltage HVN transmission path are commonly connected to the output VO of the core drive circuit.

3. The circuit according to claim 2, characterized in that, The digital signals input to the logic circuit include: SWITCH<1>, PULSE_TO_MUX, SWITCH<0>, and SWITCH<2>.

4. The circuit according to claim 3, wherein In the positive high-voltage level conversion circuit: The enable signal of the positive high-voltage level conversion circuit is generated by performing an AND operation on SWITCH<1> and PULSE_TO_MUX once, the input signal of the positive high-voltage level conversion circuit is the inverted signal of the enable signal; the output signal of the positive high-voltage level conversion circuit is VHH; The enable signal of the low-voltage level conversion circuit is generated by performing an OR operation on the result of performing an AND operation on the result of inverting SWITCH<1> and PULSE_TO_MUX once and SWITCH<0> once, the input signal of the low-voltage level conversion circuit is the inverted signal of the enable signal; the output signal of the low-voltage level conversion circuit is EN_LV; The enable signal of the negative high-voltage level conversion circuit is SWITCH<2>, the input signal of the negative high-voltage level conversion circuit is the inverted signal of the enable signal; the output signal of the negative high-voltage level conversion circuit is VLL.

5. The circuit according to claim 4, wherein The logic circuit includes several inverters, AND gates, and OR gates.

6. A driving method for a composite dielectric gate photosensitive detector, characterized in that, The method is implemented based on the circuit according to any one of claims 1-5 above.

7. The method according to claim 6, wherein The method is: the logic circuit performs a logic operation on the input digital signal to generate an enable signal for controlling the operation of the level conversion circuit; the level conversion circuit outputs a signal for controlling the core drive circuit according to the enable signal generated by the logic circuit; the core drive circuit is controlled by the level conversion circuit to output positive / negative high voltage or low voltage.

8. The method according to claim 7, wherein In the level conversion circuit: When the enable signal of the positive high-voltage level conversion circuit is at a high level and the input signal of the positive high-voltage level conversion circuit is at a low level, the output voltage of the positive high-voltage level conversion circuit is the input positive high-voltage signal; when the enable signal of the positive high-voltage level conversion circuit is at a low level and the input signal of the positive high-voltage level conversion circuit is at a high level, the output voltage of the positive high-voltage level conversion circuit is the ground signal; When the enable signal of the negative high-voltage level conversion circuit is at a high level and the input signal of the negative high-voltage level conversion circuit is at a low level, the output voltage of the negative high-voltage level conversion circuit is the negative high-voltage signal; when the enable signal of the negative high-voltage level conversion circuit is at a low level and the input signal of the negative high-voltage level conversion circuit is at a high level, the output voltage of the negative high-voltage level conversion circuit is the ground signal; When the enable signal of the low-voltage level conversion circuit is at a high level and the input signal of the low-voltage level conversion circuit is at a low level, the output voltage of the low-voltage level conversion circuit is the low-voltage signal; when the enable signal of the low-voltage level conversion circuit is at a low level and the input signal of the low-voltage level conversion circuit is at a high level, the output voltage of the low-voltage level conversion circuit is the ground signal.

9. The method according to claim 8, characterized in that In the core drive circuit: When the P-type MOS transistor enabled by the positive high-voltage level conversion circuit in the positive high-voltage HVP transmission path and the N-type MOS transistor enabled by the negative high-voltage level conversion circuit in the negative high-voltage HVN transmission path are turned off, and the N-type MOS transistor in the low-voltage LV transmission path is turned on, the low-voltage LV transmission path is conducting, and the output voltage VO of the core drive circuit = LV; When the N-type MOS transistor in the low-voltage LV transmission path and the N-type MOS transistor enabled by the negative high-voltage level conversion circuit in the negative high-voltage HVN transmission path are turned off, and the two P-type MOS transistors in the positive high-voltage HVP transmission path are turned on, the positive high-voltage HVP transmission path is conducting, and the output voltage VO of the core drive circuit = HVP; When the N-type MOS transistor in the low-voltage LV transmission path and the P-type MOS transistor enabled by the positive high-voltage level conversion circuit in the positive high-voltage HVP transmission path are turned off, and the two N-type MOS transistors in the negative high-voltage HVN transmission path are turned on, the negative high-voltage HVN transmission path is conducting, and the output voltage VO of the core drive circuit = HVN.

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