A programmable frequency divider for JESD204B / C

Abstract

This invention relates to a programmable frequency divider for JESD204B / C standards. The divider comprises a prescaler that implements dynamic 1 / 2 / 4 frequency division via a closed-loop feedback structure; a 12-bit main divider with an 11-stage asynchronous CML divide-by-two chain and a separate DFF0 module to control the odd-even frequency division duty cycle. The divider ratio N = DIV_N<11:0> + 2, with the odd-numbered frequency division duty cycle automatically adjusted to (N+1) / 2N; cascaded noise optimization with retiming flip-flops (RetimeDFF1 / 2) that resample the input clock fin; a pulse generator with a four-stage counter that outputs a decimal value of the pulse count K = Pulse_count<3:0>; and an output mode circuit that supports three-mode pass-through. This programmable frequency divider utilizes HBT CML cells and emitter-follower buffering, meeting the high-precision clock synchronization requirements of JESD204B / C systems such as 5G base stations and millimeter-wave radars.

Description

Technical Field

[0001] The present invention relates to the technical field of frequency divider circuit design, and in particular to a programmable frequency divider applied to JESD204B / C. Background Art

[0002] As analog-to-digital converter (ADC) sampling rates exceed Gbps, traditional parallel interfaces based on low-voltage differential signaling (LVDS) are no longer able to meet high-speed data transmission requirements. Consequently, the issue of synchronous high-speed data transmission between multi-channel ADCs and FPGAs has become increasingly prominent. Against this backdrop, the JESD204B interface protocol, proposed by the Solid State Technology Association, provides an innovative solution to this technical bottleneck.

[0003] SYSREF is a global reference signal used for system-level synchronization in the JESD204B / C standard. Its frequency usually needs to be an integer division relationship with the system master clock (Device Clock) and must meet the subclass requirements specified in the JESD204B / C protocol (for example, Subclass 1 / 2 requires periodic SYSREF). When multiple devices share the same clock source, they need to generate phase-consistent SYSREF[3] in their respective chips to avoid synchronization deviations caused by transmission delays. Therefore, a frequency divider is required to convert the high-frequency system clock (Device Clock) to a SYSREF frequency that complies with the protocol specification, and the programmable division ratio characteristics of the frequency divider need to be ensured to support precise control of the trigger interval of the SYSREF pulse. Its design directly affects the synchronization accuracy and reliability of the JESD204B / C system, which is particularly critical in high-speed, multi-channel scenarios.

[0004] Therefore, it is necessary to propose a programmable frequency divider with multiple output modes and high speed and wide bandwidth suitable for use in JESD204B / C systems to overcome the above technical problems. Summary of the Invention

[0005] To solve the above technical problems, the present invention provides a programmable frequency divider for JESD204B / C, comprising cascaded:

[0006] Prescaler: A closed-loop feedback loop is formed by two D flip-flops and two data selectors (MUX1 and MUX2). The input clock fin is connected to the CLK terminal of the first D flip-flop and the input terminal of MUX1. The output of MUX1 drives the D terminal of the second D flip-flop. The output buffer is fed back to MUX2. The output of MUX2 is fed back to the D terminal of the first D flip-flop and outputs fpre_div.

[0007] 12-bit programmable frequency divider: 11-stage asynchronous CML divide-by-two modules (DFF1-DFF11) are cascaded: fpre_div drives the CLK terminal of DFF1, and the Q output of the i-th stage (2≤i≤10) divide-by-two circuit DFFi is connected to the clock input of the i+1-th stage divide-by-two circuit TFFi+1 and one of the inputs of the i-th stage AND gate ANDi. Separate DFF0 module: The lowest bit S0 of the set signal is connected to the set S terminal of the set-number divide-by-two module DFF0, and its Q terminal and the Q terminal of DFF1 drive the reset logic chain through the exclusive OR gate XOR. The reset logic chain includes multiple AND gates and retiming D flip-flops, among which AND gates AND1-AND10 are cascaded for detection. The other input of the i-th stage (1≤i≤9) AND gate ANDi is connected to the output of the i+1-th stage AND gate ANDi+1. The output of AND1 is connected to the data input D terminal of the retiming D flip-flop Retime DFF1, and the output is connected to the retiming flip-flop Retime. After synchronization, DFF1 generates a global set signal CD. Output channel: The output Q of Retime DFF1 is connected to the clock input CLK of the divide-by-two circuit Div_2 DFF. After the divide-by-two signal, it is output from the output Q of Div_2 DFF. The output Q of Div_2 DFF is connected to the data input D of the retimed D flip-flop Retime DFF2. The clock input CLK of Retime DFF2 is connected to the initial input clock fin. The output Q of Retime DFF2 outputs the divided signal fdiv.

[0008] Pulse generator: 4-stage CML divide-by-two frequency modules are cascaded, fdiv drives the first-stage CLK terminal, and the output of the final-stage AND gate chain (AND1~AND3) controls the TFF module to generate pulses;

[0009] Output mode selection circuit: Through MUX1~MUX4 and AND gate combination, select direct fdiv, pulse signal or fSYSREFQ output.

[0010] In one embodiment of the present invention, the closed-loop feedback of the prescaler realizes dynamic frequency division: MUX1 selects fin or the first D flip-flop Q output; MUX2 selects the second D flip-flop Q or the output buffer feedback signal.

[0011] In one embodiment of the present invention, the 12-bit programmable frequency divider satisfies: the frequency division ratio N = (DIV_N<11:0>) + 2; when N is an odd number, the duty cycle fdiv ≠ 50%.

[0012] In one embodiment of the present invention, in the reset logic chain: the second input terminal of ANDi (i=1-9) is connected to the output terminal of ANDi+1; and the CLK terminal of Retime DFF1 / 2 is directly connected to the initial clock fin.

[0013] In one embodiment of the present invention, the CML divide-by-two frequency module also includes: a set-to-digital differential conversion circuit (inverter chain I1-I2 driving MOS transistors M1-M2); a master-slave latch (sampling transistors Q3-Q4 / Q9-Q10 + cross-coupled transistors Q5-Q6 / Q11-Q12); and an emitter follower output buffer (Q1-Q2).

[0014] In one embodiment of the present invention, the logic in the output mode selection circuit includes the following three modes:

[0015] Mode 1: MUX1 selects high level → AND4 passes fdiv → MUX3 selects Retime DFF output;

[0016] Mode 2: MUX1 selects TFF Q → AND4 generates N pulses → MUX3 selects high level;

[0017] Mode 3: MUX4 passes through fSYSREFQ.

[0018] In one embodiment of the present invention, the tail current source of the CML two-way frequency division module is composed of bias transistors Q21-Q26, and the bias voltage uniformly drives the base.

[0019] In one embodiment of the present invention, the pulse number K of the pulse generator is equal to the decimal value of Pulse_count<3:0> (range 1 to 16, note: no pulse is output when all 0s are present), as follows Figure 7 As shown in the figure, the hardware implementation logic is AND1 output falling edge number = Pulse_count decimal value, and each falling edge triggers TFF to generate a pulse.

[0020] In one embodiment of the present invention, the overall frequency division range covers 2 to 16380 (pre-frequency division×main frequency division), and the duty cycle accuracy is ±1%.

[0021] In one embodiment of the present invention, the duty cycle is (N+1) / 2N when the frequency division is odd.

[0022] The above-mentioned technical solution of the present invention has the following advantages over the existing technology: The programmable frequency divider described in the present invention is based on a CML two-way frequency divider with a set position. By cascading and multiplexing it, a 12-bit programmable frequency divider and a pulse generator are realized. Then, a pre-divider and an output mode selection circuit are combined to form a programmable frequency divider with multiple output modes that can realize signal generator, pulse generator, and repeater modes. This expands the frequency division ratio range and output mode of the frequency divider composed of traditional pulse counters. At the same time, it can meet the requirements of different duty cycles for odd and even frequency division of the 12-bit programmable frequency divider. When the frequency is divided at an odd number, the duty cycle of the signal after division is not equal to 50%. In order to increase the maximum operating frequency of the frequency divider, a high cutoff frequency and low phase noise HBT process is adopted, and the traditional two-way frequency divider circuit is improved. An output buffer circuit is introduced to reduce the output load of the node and further increase the operating frequency. Therefore, this programmable frequency divider has a high maximum operating frequency, a wide frequency division range, and selectable output modes, and is suitable for JESD204B / C systems. Furthermore, it is irreplaceable in actual high-speed data conversion systems, high-end test and measurement instruments, medical imaging equipment, optical communication systems, aerospace and avionics, and other scenarios with system clocks greater than 10GHz, especially meeting the stringent synchronization requirements of JESD204B / C Subclass 1 for periodic SYSREF. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0024] Figure 1 1 is a schematic diagram of the structure of a programmable frequency divider applied to JESD204B / C according to the present invention;

[0025] Figure 2 1 is a schematic structural diagram of the pre-divider of the present invention;

[0026] Figure 3 It is a structural diagram of the 12-bit programmable frequency divider of the present invention;

[0027] Figure 4 1 is a schematic structural diagram of a CML two-way frequency division circuit with a set bit according to the present invention;

[0028] Figure 5 It is a structural schematic diagram of the pulse generator and output mode selection circuit of the present invention;

[0029] Figure 6 This is a timing diagram illustrating the implementation principle of the present invention when the frequency division ratio N=3 and the duty cycle is (N+1) / 2N = 66.6%;

[0030] Figure 7is a corresponding diagram of the number of pulses K and the decimal value of Pulse_count<3:0> of the pulse generator of the present invention;

[0031] Figure 8 This is a diagram corresponding to the implementation mode selection logic of the output mode selection circuit in the present invention. DETAILED DESCRIPTION

[0032] like Figure 1 As shown, this embodiment provides a programmable frequency divider applied to JESD204B / C, which internally includes a cascaded pre-divider, a 12-bit programmable frequency divider, a pulse generator, and an output mode selection circuit.

[0033] It can realize the functions of signal generator, pulse generator and repeater, output multi-mode signals for application in JESD204B / C system, and achieve high speed, wide frequency division range and flexible and controllable frequency division ratio.

[0034] The prescaler circuit structure is as follows Figure 2 As shown, it contains two CML D flip-flops and two 2-to-1 data selectors. It is used to prescale the input signal, select the prescale value based on the input signal frequency, and select the data selector output signal through the PRE_DIV<1:0> signal, which can choose to divide the input signal by 1, 2, or 4. The input signal fin is input to the clock CLK terminal of the two CML structure D flip-flops and the signal input terminal of the first 2-to-1 data selector MUX1; the output Q terminal of the first D flip-flop is connected to the other signal input terminal of the first 2-to-1 data selector MUX1; the signal output terminal of the first 2-to-1 data selector MUX1 is connected to the data D terminal of the second D flip-flop and the input terminal of the output buffer Buffer; the output Q terminal of the second D flip-flop is connected to the signal input terminal of the second 2-to-1 data selector MUX2; the output terminal of the output buffer Buffer outputs the pre-divided signal fpre_div, and at the same time, it is connected to the other signal input terminal of the second 2-to-1 data selector MUX2; the signal output terminal of the second 2-to-1 data selector MUX2 is connected to the data D terminal of the first D flip-flop, forming a feedback path to realize the frequency division of the input signal.

[0035] Specifically, the frequency division logic is:

[0036] 00: MUX1 selects fin → direct output (divide by 1)

[0037] 01: MUX1 selects the Q output of DFF1 → DFF2 divides the frequency by 2 → outputs the divided-by-2 signal

[0038] 10: MUX2 selects fpre_div feedback signal → DFF1 and DFF2 are cascaded to achieve 4-frequency division

[0039] The circuit structure of the 12-bit programmable frequency divider is as follows: Figure 3As shown, it includes a 12-bit pulse counter and a reset logic detection circuit. The 12-bit pulse counter includes 11 asynchronous logic cascaded divide-by-two modules with set numbers and realizes the control of the odd and even number of the division ratio by separating the lowest bit. Each level of divide-by-two circuit DFF includes a CLK input terminal (i.e., clock input terminal), an S input terminal (i.e., set number terminal), a CD input terminal (i.e., set number control terminal), and a Q output terminal. The clock input terminal of the first-level divide-by-two circuit DFF1 is connected to the clock signal fpre_div generated after the pre-divider divides the frequency. The Q output terminal of the i-th level (2≤i≤10) divide-by-two circuit DFFi is connected to the clock input terminal of the i+1-th level divide-by-two circuit TFFi+1 and one of the input terminals of the i-th level AND gate ANDi. The Q output terminal of the last level divide-by-two circuit DFF11 is connected to the clock input terminal of the i+1-th level divide-by-two circuit TFFi+1 and one of the input terminals of the i-th level AND gate ANDi. The Q output terminal is only connected to one of the input terminals of the 10th-level AND gate AND10, the set number S terminal of the i-th level (1≤i≤11) divide-by-two frequency circuit DFFi is respectively connected to the set number signal Si, the output Q terminal of the first-level divide-by-two frequency circuit DFF1 is connected to one of the input terminals of the exclusive OR gate XOR, the lowest bit S0 of the set number signal is separated out, and it is connected to the set number S terminal of the divide-by-two frequency module DFF0 with set number, the output Q terminal of DFF0 is connected to the other input terminal of the exclusive OR gate XOR, and the output terminal of XOR is connected to one of the input terminals of the first-level AND gate AND1. The reset logic detection circuit consists of multiple AND gates and retimed D flip-flops. It controls the set control signal CD by detecting the output signals of each divide-by-two module. Because each divider stage is not directly driven by the input clock, phase noise generated by the cascade will accumulate. Therefore, a retimed D flip-flop is used to retime the output clock so that the phase noise is determined solely by it. The other input of the i-th level (1≤i≤9) AND gate ANDi is connected to the output of the i+1-th level AND gate ANDi+1. The output of the first-level AND gate AND1 is connected to the data input D of the retimed D flip-flop Retime DFF1. The clock input CLK of Retime DFF1 is connected to the initial input clock fin. The output Q of Retime DFF1 is connected to the input of inverter INV and the clock input CLK of the divide-by-two module DFF0 with a set number. The output of INV is connected to the set control CD of the i-th level (1≤i≤11) divide-by-two circuit DFFi, controlling the input of the set number signal and, therefore, the operating state of the divide-by-two circuit.After passing through the retimed D flip-flop, the output signal passes through a separate first-level divide-by-two circuit, and the final output signal achieves 12-bit programmable frequency division. The output Q end of RetimeDFF1 is connected to the clock input CLK end of the divide-by-two circuit Div_2 DFF. After frequency division, it is output from the output Q end of Div_2 DFF. The output Q end of Div_2 DFF is connected to the data input D end of the retimed D flip-flop Retime DFF2. The clock input CLK end of Retime DFF2 is connected to the initial input clock fin. The output Q end of Retime DFF2 outputs the divided signal fdiv.

[0040] The 11-stage asynchronous frequency division chain achieves cumulative phase noise > -120dBc / Hz at 1MHz offset. Using RetimeDFF1 / 2 to resample the divided signal with a clean fin, the output phase noise фout = фfin, independent of the cascaded chain. The result is optimized phase noise to -152dBc / Hz (5GHz input, 0.13μm HBT process).

[0041] In this example, due to the separation of the least significant bit in the 12-bit pulse counter, the 12-bit pulse counter is actually set to bits 1 to 11. The signal passes through the logic detection circuit and is then divided by two to obtain the output signal after 12-bit frequency division. Therefore, when considering the counting cycle of the pulse counter, a complete counting cycle should be the reset signal undergoing two cycles of changing from a low level to a high level. It can be understood that the divide-by-two circuit DFF is a settable CML divide-by-two circuit. After receiving a set signal that satisfies a set condition, the divide-by-two circuit DFF of each stage is assigned a set value based on a preset divide-by-two value. The initial output value of the Q output terminal of each stage of the divide-by-two circuit DFF is the set value. Under the influence of the clock signal received at the clock input terminal of each stage of the divide-by-two circuit DFF, the Q output terminal of each stage of the divide-by-two circuit DFF will be adjusted accordingly. It can be understood that the clock signal received at the clock input terminal of the first-stage divide-by-two circuit DFF1 is the signal output by the clock source, and the clock signal received at the clock input terminals of other divide-by-two circuits, such as the second-stage divide-by-two circuit DFF2 to the eleventh-stage divide-by-two circuit DFF11, is the signal output by the Q output terminal of the previous stage of the divide-by-two circuit DFF, corresponding to the actual output value. For example, if the frequency division ratio is an even number, the lowest bit S0 is set to 0, and the pulse counter works as follows: first, the 11-bit pin input is set to (S11S10...S2S1)B. When counting starts, the counting state will be consistent with the state when the reset signal is high, that is, all initial values ​​will be inverted. Then the pulse counter starts to add 1, and counts until there are a total of (S11S10...S2S1)B counting states. Then, after a clock cycle delay through the retiming D flip-flop, the final pulse count value S is (S11S10...S2S1)B+1. The above process is repeated in the second reset cycle. Therefore, the total division ratio is (S11S10…S2S1S0)B+2. If the division ratio is odd, the lowest position is S01. The first reset cycle counts to a total of (S11S10…S2S1)B+1 count states. After a delay of one clock cycle through the retiming D flip-flop, the final pulse count value s is (S11S10…S2S1)B+2. The second reset cycle counts, consistent with the even division ratio, with the pulse count value S being (S11S10…S2S1)B+1. Therefore, the total division ratio is (S11S10…S2S1S0)B+2. In summary, if the 12-position pin value is set to (S11S10…S2S1S0)B, the final division ratio is (S11S10…S2S1S0)B+2. Note that when this is an odd number, the duty cycle of the divided signal is not equal to 50%.

[0042] Specifically, the division ratio is calculated as follows: programmed value DIV_N<11:0> = S11 S10 ... S1 S0 (binary); actual division ratio N = (S11~S0)2+ 2;

[0043] Duty cycle control: When N is an even number (S0=0), the output duty cycle is 50%; DFF0 forces the output to be high → the XOR gate is equivalent to a buffer → the reset signal is aligned with the rising edge of the clock;

[0044] When N is an odd number (S0=1), the output duty cycle is (N+1) / 2N (for example, when N=5, the duty cycle is 60%). Specifically, DFF0 introduces a half-cycle delay → the duty cycle is automatically adjusted to (N+1) / 2N.

[0045] For example, the timing example (N=3) (duty cycle 66.6%) is as follows Figure 6 As shown;

[0046] The CML two-way frequency division circuit structure with setting is as follows Figure 4As shown, the circuit includes a set circuit, a master-slave latch, a set control circuit, and an output buffer circuit. Its main structure is a CML D flip-flop, consisting of two cascaded CML latches. The input differential signals CLK+ and CLK- are connected to the bases of Q16, Q18, and Q15, Q19, respectively. The bias voltage Bias is connected to the bases of Q21, Q22, Q23, Q24, Q25, and Q26 to ensure the generation of a stable tail current source. The set number signal S is connected to the input end of the inverter I1. The output end of the inverter I1 outputs the signal SN, which is connected to the input end of the inverter I2 and the gate of the amplifier tube M2. The output end of the inverter I2 is connected to the gate of the amplifier tube M1. The sources of M1 and M2 are grounded, and the drains are connected to one end of the resistors R7 and R8 respectively. The other end of the resistors is connected to the emitters of the bias tubes Q21 and Q22. The collectors of the bias tubes Q21 and Q22 are connected to one end of the pull-up resistors R1 and R2 respectively. The other end of R1 and R2 is connected to the power supply voltage VDD, thereby realizing the differential input of the set number signal. The set control signal CD is connected to the bases of Q17 and Q20, and the emitters of Q17 and Q20 are connected to the collectors of tail current tubes Q23 and Q24 respectively. The set control signal controls the input of the set circuit signal through a differential pair. The emitters of the differential pair Q7 and Q8 are connected to the collector of Q17, and the bases of Q7 and Q8 are connected to the collectors of bias tubes Q21 and Q22 respectively. The collectors of Q7 and Q8 are connected to the collectors of Q3 and Q4 respectively. The emitters of the differential pair Q13 and Q14 are connected to the collector of Q20, and the bases of Q13 and Q14 are connected to the collectors of bias tubes Q21 and Q22 respectively. The collectors of Q13 and Q14 are connected to the collectors of Q9 and Q10 respectively, forming a signal path for the transmission of the set signal. When the CD terminal is high, the divider stops operating, and the signal at the S terminal is level-converted to the output terminal through the setting circuit and output buffer circuit, completing the setting step. When the CD terminal is low, the master-slave latch operates normally, and the circuit enters the divide-by-two state. A CML-structured D flip-flop is composed of two cascaded CML-structured latches. The CML latch circuit is a combination of a sampling circuit and a cross-coupling circuit. The signal is differentially input through the bases of the sampling transistors and differentially output through the collectors. The bases of the sampling transistors Q3 and Q4 are connected to the collectors of the sampling transistors Q9 and Q10, respectively. The emitters of Q3 and Q4 are connected to the collector of Q15. The bases of the sampling transistors Q9 and Q10 are connected to the collectors of the sampling transistors Q3 and Q4, respectively. The emitters of Q9 and Q10 are connected to the collector of Q18.The sampling tube is connected to the latch tube of the cross-coupling structure, which will lock the signal collected at the previous moment and send the collected signal to the next level when the clock signal arrives at the next moment. The base of Q5 is connected to the collector of Q6, and the base of Q6 is connected to the collector of Q5 to form a cross-coupled pair of tubes. The collectors of the cross-coupled pair of tubes Q5 and Q6 are connected to the collectors of Q3 and Q4 respectively, and the emitters of Q5 and Q6 are connected to the collector of Q16; the base of Q11 is connected to the collector of Q12, and the base of Q12 is connected to the collector of Q11 to form a cross-coupled pair of tubes. The collectors of the cross-coupled pair of tubes Q11 and Q12 are connected to the collectors of Q9 and Q10 respectively, and the emitters of Q11 and Q12 are connected to the collector of Q19. The voltage drop generated by the pull-up resistors limits the circuit's output swing, and the loop's self-resonance is also verified by examining the current flowing through the resistors. Pull-up resistors R3 and R4 have one end connected to the collectors of Q3 and Q4, respectively, and the other end connected to the power supply voltage VDD. Pull-up resistors R5 and R6 have one end connected to the collectors of Q9 and Q10, respectively, and the other end connected to the power supply voltage VDD. The clock input transistor is connected to the tail current transistor, which is externally biased to provide a stable operating current for the circuit. The collector of tail current transistor Q23 is connected to the emitters of the clock input pair of transistors Q15 and Q16 and the emitter of the set control transistor Q17. The emitter of Q23 is connected to one end of resistor R9, the other end of which is grounded. The collector of tail current transistor Q24 is connected to the emitters of the clock input pair of transistors Q18 and Q19 and the emitter of the set control transistor Q20. The emitter of Q24 is connected to one end of resistor R10, the other end of which is grounded. Adding an output buffer circuit at the output reduces the node's output load and adjusts the output voltage level, further increasing the operating frequency. The buffer circuit is actually an emitter-follower circuit. The bases of common-collector amplifiers Q1 and Q2 are connected to the collectors of sampling transistors Q9 and Q10, forming the output signal transmission path. The collectors of Q1 and Q2 are connected to the power supply voltage VDD. The emitters of Q1 and Q2 are connected to the output signal terminals Q- and Q+, respectively, and to the collectors of Q25 and Q26, respectively. The emitters of Q25 and Q26 are connected to one end of resistors R11 and R12, respectively. The other ends of R11 and R12 are grounded. The divide-by-two circuit is actually a simple sequential state machine with only two states (Q = 0, Q = 1). The QN output of the D flip-flop is fed back to the D input. The circuit's output state inverts with the rising (or falling) edge of the clock signal, cycling between the two states, thus achieving the divide-by-two function.

[0047] Specifically, the implementation speed advantages of the CML two-way frequency division unit module are: the emitter follower reduces the output capacitance (50fF→5fF); the cross-coupling structure accelerates the flip (delay <5ps).

[0048] The pulse generator and output mode selection circuit structure are as follows Figure 5 As shown, the main structure of the pulse generator is a 4-bit pulse counter, which realizes pulse counting through a combination of four 2-divide modules and AND gates. The output mode selection circuit selects the output mode through a combination of multiple 2-to-1 data selectors and AND gates. The 4-bit pulse counter circuit includes a multi-stage CML 2-divide circuit DFF with set bits. Each stage of the 2-divide circuit DFF includes a CLK input terminal (i.e., clock input terminal), an S input terminal (i.e., set number terminal), a CD input terminal (i.e., set number control terminal), and a Q output terminal. The clock input terminal of the first-stage 2-divide circuit DFF1 is connected to the clock signal fdiv generated after the 12-bit programmable divider divides the frequency. The Q output terminal of the i-th stage (i≥2) 2-divide circuit DFFi is connected to the clock input terminal of the i+1-th stage 2-divide circuit TFFi+1 and one of the input terminals of the i-th stage AND gate ANDi. The Q output terminal of the last-stage divide-by-two frequency circuit DFF is only connected to one of the input terminals of the third-stage AND gate AND3, the output terminal of the third-stage AND gate AND3 is connected to the other input terminal of the second-stage AND gate AND2, the output terminal of the second-stage AND gate AND2 is connected to the other input terminal of the first-stage AND gate AND1, the output terminal of the first-stage AND gate AND1 is connected to the output terminal of the output buffer Buffer, and the output terminal is connected to the CLK terminal of the divide-by-two frequency module TFF. The output waveform of the output terminal Q of TFF determines the output waveform width, and further determines the number of output pulses in the pulse generator mode. The output mode selection circuit includes multiple 2-to-1 data selectors and AND gates. The high-level signal High level is connected to one of the input terminals of the data selectors MUX1 and MUX2. The other input terminals of MUX1 and MUX2 are connected to the output Q terminal of TFF, transmitting the output signal of the pulse generator to the subsequent circuit; the output terminal of the data selector MUX1 is connected to one of the input terminals of the AND gate AND4, and the other input terminal of AND4 is connected to the output signal fdiv of the frequency divider. The output terminal of AND4 is respectively connected to one of the input terminals of the AND gate AND5 and the data input D terminal of the retimed D flip-flop Retime DFF. The clock CLK terminal of the Retime DFF is connected to the initial input signal fin. The output Q end of DFF is connected to one of the input ends of the data selector MUX3, the other input end of MUX3 is connected to the output end of the data selector MUX2, and the output end of MUX3 is connected to one of the input ends of the AND gate AND5; the other input end of AND5 is connected to the output end of the AND gate AND5, and the output end of AND5 is connected to one of the input ends of the data selector MUX4, and the other input end of MUX4 is connected to the initially provided SYSREFQ signal fSYSREFQ, and the output end of MUX4 outputs the final output signal fOUT.

[0049] like Figure 5As shown, the programmable divider circuit has three output modes, which are controlled by the output mode selection circuit. Specifically, the mode<1:0> signal controls the 2-to-1 data selector in the output mode selection circuit to select and process the previous input signal to output different mode waveforms. Mode 1 is the signal generator mode. In this mode, the data selector MUX1 selects to output the high-level signal High level. This signal and the divider output signal fdiv are logically ANDed by the AND gate AND4. After the signal is consistent with fdiv, it remains consistent with fdiv after the retiming D flip-flop Retime DFF. The data selector MUX2 selects to output the pulse generator transmission signal, and the data selector MUX3 selects to output the retiming D flip-flop Retime DFF outputs the signal at the D end, and the output signal of MUX3 is logically ANDed with the output signal of AND4, and the output signal is consistent with fdiv. MUX4 selects to output the output signal of AND5, so that the final output signal directly outputs the output signal of the divider, and the output waveform is a continuous pulse; Mode 2 is the pulse generator mode. In this mode, the data selector MUX1 selects to output the output signal of the pulse generator, which is actually a pulse signal. The pulse width is the selected number of pulses N and the period of the fdiv output signal. After the signal and the divider output signal fdiv are logically ANDed by the AND gate AND4, the signal is the pulse signal of the selected number. The pulse duration and frequency are equal to the duty cycle and frequency of the divider output respectively. After the retiming D flip-flop Retime The signal after DFF is consistent with the output signal of AND4, the data selector MUX2 chooses to output the high-level signal Highlevel, the data selector MUX3 chooses to output the high-level signal, the data selector MUX4 chooses to output the AND5 output signal, and the output signal of MUX3 is consistent with the AND4 output signal after the logic AND is performed, so that the final output signal is a 4-bit optional number of pulses; Mode three is the repeater mode, the prescaler and divider do not work, the data selector MUX4 chooses to output the SYSREFREQ signal, so that the circuit directly outputs the SYSREFREQ signal.

[0050] The input clock signal is input to the prescaler input, and the prescaler division ratio is controlled by the PRE_DIV<1:0> signal. The prescaler predivides the input clock and inputs it to the 12-bit programmable divider, and the division ratio of the 12-bit programmable divider is controlled by the DIV_N<11:0> signal. The signal divided by the 12-bit programmable divider is simultaneously input to the pulse generator module and the output mode selection module. The pulse generator gates the divider and outputs a 4-bit selectable number of pulses. The pulse duration and frequency are equal to the duty cycle and frequency output by the divider, respectively. The number of output pulses is controlled by the Pulse_count<3:0> signal. The signal passing through the pulse generator, the signal passing through the 12-bit programmable divider, and the SYSREFREQ signal are input to the output mode selection circuit together, and the output signal is controlled by the Mode_select<1:0> signal.

[0051] Specifically, Figure 5 The pulse generator on the left implements the pulse control logic: the Q output of DFF1 to DFF4 → the input of the AND gate chain (AND1 to AND3);

[0052] The output of AND1 → buffer → CLK terminal of the TFF module.

[0053] Another timing synchronization mechanism: TFF's CLK is triggered by the falling edge of AND1 output; each falling edge → TFF outputs a complete pulse cycle; the counter is reset on the rising edge of fdiv to ensure that the pulse group is strictly aligned with the clock.

[0054] and Figure 5 The output mode selection circuit on the right implements the mode selection logic as follows Figure 8 As shown;

[0055] Another anti-glitch design is that the Mode_select signal is buffered by the fin synchronization register, where mode switching only occurs on the falling edge of the clock.

[0056] In summary, the frequency divider of this embodiment is a digital circuit module that divides the input signal frequency into different output signals according to a specific integer ratio. Its core function is to achieve precise frequency division by adjusting the cascade structure of triggers. It is commonly used in scenarios such as clock synchronization, frequency synthesis, and signal modulation and demodulation. Frequency dividers can be divided into three typical categories based on their circuit structure: current mode logic (CML), injection locked (IL), and true single-phase clock (TSPC). These categories show significant differences in key indicators such as power consumption, speed, design complexity, and robustness.

[0057] In the present invention, due to the high bit number, it is necessary to ensure that each two-division frequency module has a small delay to ensure the correctness of the overall frequency division function. Therefore, the programmable frequency divider is designed using a CML structure with high-speed characteristics.

[0058] To further illustrate, the frequency divider workflow described in this embodiment is an example scenario in which a 5G base station generates a 125 MHz SYSREF signal (system clock fin = 5 GHz):

[0059] Prescaler: PRE_DIV=10 (divide by 4) → fpre_div=1.25GHz

[0060] Main frequency division:

[0061] Target division ratio: 5000MHz / 125MHz=40 → DIV_N=38 (binary 0010 0110)

[0062] S0=0 (even number) → duty cycle 50%

[0063] Pulse mode: Pulse_count=0011 (K=3 pulses)

[0064] Output mode: Mode_select = 01 (pulse generator mode) → Outputs three 125MHz pulses.

[0065] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A programmable frequency divider for JESD204B / C, characterized in that: Including cascaded: Prescaler: A closed-loop feedback is formed by two D flip-flops and two data selectors. The input clock fin is connected to the CLK terminal of the first D flip-flop and the input terminal of MUX1. The output of MUX1 drives the D terminal of the second D flip-flop. The output buffer is fed back to MUX2. The output of MUX2 is fed back to the D terminal of the first D flip-flop and outputs fpre_div. 12-bit programmable frequency divider: 11-stage asynchronous CML divide-by-two module cascade: fpre_div drives the CLK terminal of DFF1, and the Q output of the i-th stage (2≤i≤10) divide-by-two circuit DFFi is connected to the clock input of the i+1-th stage divide-by-two circuit TFFi+1 and one of the inputs of the i-th stage AND gate ANDi; separate DFF0 module: The lowest bit S0 of the set signal is connected to the set S terminal of the set-number divide-by-two module DFF0, and its Q terminal and the Q terminal of DFF1 drive the reset logic chain through the exclusive OR gate XOR; the reset logic chain: includes multiple AND gates and retimed D flip-flops, among which AND gates AND1~AND10 are cascaded for detection. The other input of the i-th stage (1≤i≤9) AND gate ANDi is connected to the output of the i+1-th stage AND gate ANDi+1. The output of AND1 is connected to the data input D terminal of the retimed D flip-flop RetimeDFF1. The output is synchronized with the retimed flip-flop Retime DFF1 to generate the global set signal CD; output channel: Retime The output Q of DFF1 is connected to the clock input CLK of the divide-by-two circuit Div_2 DFF. After the frequency is divided by two, it is output from the output Q of Div_2 DFF. The output Q of Div_2 DFF is connected to the data input D of the retimed D flip-flop Retime DFF2. The clock input CLK of Retime DFF2 is connected to the initial input clock fin. The output Q of Retime DFF2 outputs the divided signal fdiv. Pulse generator: 4-stage CML divide-by-two frequency modules are cascaded, fdiv drives the first-stage CLK terminal, and the final-stage AND gate chain output controls the TFF module to generate pulses; Output mode selection circuit: Through MUX1~MUX4 and AND gate combination, select direct fdiv, pulse signal or fSYSREFQ output.

2. The programmable frequency divider according to claim 1, wherein: The closed-loop feedback of the pre-divider realizes dynamic frequency division: MUX1 selects fin or the first D flip-flop Q output; MUX2 selects the second D flip-flop Q or the output buffer feedback signal.

3. The programmable frequency divider according to claim 1, wherein: The 12-bit programmable frequency divider satisfies the following conditions: the frequency division ratio N = (DIV_N<11:0>) + 2; when N is an odd number, the fdiv duty cycle ≠ 50%.

4. The programmable frequency divider according to claim 1, wherein: In the reset logic chain: the second input terminal of ANDi (i=1-9) is connected to the output terminal of ANDi+1; the CLK terminal of Retime DFF1 / 2 is directly connected to the initial clock fin.

5. The programmable frequency divider according to claim 1, wherein: Meanwhile, the CML two-frequency dividing module comprises: a set-digit differential conversion circuit; a master-slave latch; and an emitter follower output buffer.

6. The programmable frequency divider according to claim 1, wherein: The logic in the output mode selection circuit includes the following three modes: Mode 1: MUX1 selects high level → AND4 passes fdiv → MUX3 selects Retime DFF output; Mode 2: MUX1 selects TFF Q → AND4 generates N pulses → MUX3 selects high level; Mode 3: MUX4 passes through fSYSREFQ.

7. The programmable frequency divider according to claim 5, wherein: The tail current source of the CML two-way frequency division module is composed of bias tubes Q21-Q26, and the bias voltage uniformly drives the base.

8. The programmable frequency divider according to claim 1, wherein: The pulse number K of the pulse generator is equal to the decimal value of Pulse_count<3:0>.

9. The programmable frequency divider according to claim 1, wherein: The overall frequency division range covers 2~16380.

10. The programmable frequency divider according to claim 3, wherein: The duty cycle for odd frequency division is (N+1) / 2N.

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