Integer order differential analog-to-digital conversion device for intracranial nerve field potential acquisition

Abstract

The invention provides an integer order differential analog-to-digital conversion device for intracranial neural field potential acquisition. Firstly, an integer order difference operator is designed to calculate any integer order increment code, the intracranial nerve field potential sparsity can be more effectively utilized, the intracranial nerve field potential compression ratio is remarkably improved, meanwhile, higher flexibility is achieved, the difference order is adjustable, and the method can adapt to more intracranial nerve field potential collection application scenes. Secondly, a multi-stage buffer matrix module is designed, and any integer order increment coding value can be generated in a simple and efficient mode. Finally, a serialization bit stream generator is designed, integer order incremental data collected by a plurality of parallel channels can be subjected to serialization packaging, high expandability is achieved, reliable butt joint with a follow-up synchronous clock wireless transmission system can be achieved, overhead and delay of synchronous-asynchronous interface coordination are avoided, and the system performance is improved. And the signal acquisition efficiency is further improved.

Description

Technical Field

[0001] The present invention belongs to the field of brain-computer interfaces, and in particular relates to an integer-order difference analog-to-digital conversion device for intracranial neural field potential acquisition. Background Art

[0002] As a disruptive technology in the interdisciplinary field of neuroscience and engineering, invasive brain-computer interfaces directly capture cortical electrical activities through implantable electrode arrays, and are reshaping the paradigms of rehabilitation for paralyzed patients and the treatment of neurological diseases. This technology can not only parse motor intention signals to help spinal cord injury patients control robotic arms to complete grasping actions, but also intervene in abnormal brain rhythms through closed-loop electrical stimulation to provide precise treatment plans for Parkinson's disease tremor control. Its signal decoding ability with high spatio-temporal resolution enables researchers to explore the neural circuit mechanisms of cognitive functions with single-neuron precision, accelerating the deep integration of brain-computer fusion theory and clinical translational research.

[0003] In invasive systems, intracranial neural field potentials, as the core bioelectrical signals reflecting the synchronous firing of neuron clusters, their acquisition quality directly determines the performance boundary of brain-computer interfaces. Such signals are formed by the superposition of postsynaptic potentials of cortical pyramidal cells, and have the characteristics of microvolt-level amplitude and kilohertz-level dynamic range. To accurately capture their millisecond-level transient fluctuations, implantable electrodes need to penetrate the pia mater to contact the cortical surface, and eliminate electromyogram artifact interference through low-noise amplifiers and high-precision filtering circuits. However, this invasive acquisition method poses multiple engineering challenges to biocompatibility, long-term electrode stability, and signal fidelity. The introduction of any tiny noise may distort the spatio-temporal characteristics of neural coding.

[0004] Traditional acquisition architectures generally use Nyquist analog-to-digital converters (ADCs) to uniformly sample intracranial neural field potentials across the full frequency band. This design has a serious energy efficiency bottleneck when dealing with multi-channel large-scale parallel acquisition. Since the energy of neural electrical signals is mainly concentrated in the frequency band below 300 Hz, and there is a strong correlation between adjacent sampling points, the mandatory high-frequency sampling strategy results in more than 70% of the data being redundant information. This not only causes ineffective occupation of wireless transmission bandwidth, but also makes the power consumption density of implant devices increase sharply. When the number of channels exceeds 128, the static power consumption of the system may exceed the 10-milliwatt threshold, causing local tissue temperature rise and accelerating the aging of electrode packaging materials, seriously threatening the long-term implant safety of the device.

[0005] In order to break through the energy efficiency barrier, event-driven incremental coding analog-to-digital conversion technology (such as Delta-ADC) came into being. This solution innovatively introduces a dynamic threshold comparison mechanism, which triggers the quantization operation only when the signal change amplitude exceeds the preset threshold. This adaptive sampling strategy makes full use of the sparse characteristics of neural signals in the time dimension, and intelligently distinguishes the spike waves during epileptic seizures from the background noise, so that in scenarios such as Parkinson's disease monitoring and rhythm acquisition, the data throughput can be reduced by more than 82%. By constructing a multi-level differential coding tree, the system can simultaneously extract the amplitude mutation and slope change information of the signal, significantly reducing the power consumption of a single channel while maintaining the details of the action potential waveform, thereby extending the battery life of the implanted device.

[0006] However, although Delta-ADC can significantly improve acquisition efficiency in theory, existing implementations still face several key problems. First, the incremental encoding method used by Delta-ADC is not always better than the traditional analog-to-digital converter based on Nyquist sampling. In some application scenarios, especially when the signal changes frequently or is complex, the performance of Delta-ADC may be worse than that of the traditional successive approximation analog-to-digital converter. In addition, existing Delta-ADCs generally use first-order differential calculations to generate first-order incremental encoding. However, first-order incremental encoding does not fully utilize the sparsity of intracranial neural field potentials, resulting in limited compression effect and the acquisition efficiency cannot be fully improved. Finally, most existing Delta-ADC systems use asynchronous sampling mode, while wireless brain-computer interface systems usually use synchronous digital processing. This leads to large overhead and delay in the coordination between system interfaces, further affecting the overall performance and energy efficiency.

[0007] It can be seen that in order to meet the needs of modern brain-computer interfaces for efficient acquisition, low-energy transmission, and high-quality signal recovery, it is crucial to design a new analog-to-digital converter that can effectively compress intracranial neural field potential signals, improve acquisition efficiency, and adapt to wireless transmission requirements. This design not only needs to fully exploit the sparse characteristics of intracranial neural field potentials, but also consider the system's power consumption, sampling efficiency, and compatibility with subsequent processing modules. Summary of the invention

[0008] To overcome the problem of low efficiency in collecting intracranial nerve field potentials in the prior art, the present invention provides an integer order difference analog-to-digital converter (IOD-ADC) for collecting intracranial nerve field potentials, which comprehensively improves the signal collection efficiency while maintaining the simplicity of the circuit topology. First, an integer order difference operator is designed to calculate arbitrary integer order delta encodings. Compared with the existing first-order delta encoding, it can not only make more effective use of the sparsity of intracranial nerve field potentials, significantly improve the compression ratio of intracranial nerve field potentials, but also has higher flexibility. The difference order is adjustable, which can adapt to more application scenarios of intracranial nerve field potential collection. Second, a multi-stage buffer matrix module is designed, which can generate arbitrary integer order delta encoding values in a simple and efficient manner. Finally, a serialized bitstream generator is designed, which can serialize and package the integer order delta data collected by multiple parallel channels. It not only has high scalability and can be applied to multi-channel collection, but also can be reliably docked with the subsequent synchronous clock wireless transmission system, avoiding the overhead and delay of synchronous-asynchronous interface coordination, and further improving the signal collection efficiency.

[0009] The integer order difference analog-to-digital converter for collecting intracranial nerve field potentials involved in the present invention is composed of a multiplexer, a multi-stage buffer matrix module, a DAC controller, a DAC, a comparator, an increment counter, and a serialized bitstream generator. Among them, the multiplexer is controlled by the global clock CLK of the IOD-ADC ADC to switch the acquisition channel in each clock cycle and stabilize the current acquisition signal to support multi-channel parallel acquisition.

[0010] Furthermore, the multi-stage buffer matrix module is controlled by the global clock CLK of the IOD-ADC ADC and is responsible for storing and outputting the previous acquisition value of each channel to support the calculation of arbitrary integer order delta encodings.

[0011] Even further, the DAC controller is used to read the previous acquisition value of the multi-stage buffer matrix module and generate a DAC control code in combination with the output of the increment counter.

[0012] Even further, the DAC reads the DAC control code output by the DAC controller, converts it into a signal to be compared. After multiple comparisons, the final DAC output is stored as the current acquisition value of the current channel in the multi-stage buffer matrix module.

[0013] Even further, the comparator is used to compare the signal to be acquired output by the multiplexer and the signal to be compared output by the DAC, and input the comparison result into the increment counter for increment counting.

[0014] Furthermore, the increment counter is controlled by the global clock CLK of the IOD-ADC. ADC In each clock cycle, the output result of the comparator is read in, the integer-order increment of the current acquired signal and the previous acquired value is calculated, and the increment is transmitted to the DAC controller and the serialized bitstream generator.

[0015] Furthermore, the serialized bitstream generator is controlled by the global clock CLK of the IOD-ADC. ADC In each clock cycle, the signal increment output by the increment counter is stored and converted into a bitstream, realizing data compression, and then serialized and packed to ensure the synchronization of data transmission, generating the final bitstream output by the IOD-ADC.

[0016] The present invention first designs an integer-order difference operator to calculate arbitrary integer-order differential coding. Compared with the existing first-order differential coding, it can not only make more effective use of the sparsity of intracranial nerve field potentials, significantly improve the compression rate of intracranial nerve field potentials, but also has higher flexibility with adjustable differential orders, and can adapt to more application scenarios of intracranial nerve field potential acquisition. Secondly, a multi-level buffer matrix module is designed to generate arbitrary integer-order differential coding values in a simple and efficient manner. Finally, a serialized bitstream generator is designed to serialize and pack the integer-order differential data collected from multiple parallel channels. It not only has high scalability and can be applied to multi-channel acquisition, but also can be reliably docked with the subsequent synchronous clock wireless transmission system, avoiding the overhead and delay of synchronous-asynchronous interface coordination, and further improving the signal acquisition efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 It is the overall architecture of the integer-order differential analog-to-digital conversion device for intracranial nerve field potential acquisition proposed by the present invention;

[0019] Figure 2 It is a schematic diagram of the multi-level buffer matrix module;

[0020] Figure 3 It is a process diagram of the multi-level buffer matrix module;

[0021] Figure 4 It is a schematic diagram of the working principle of the DAC controller;

[0022] Figure 5 It is the structural diagram of the DAC;

[0023] Figure 6 It is the structural diagram of the comparator;

[0024] Figure 7 It is the working principle diagram of the increment counter;

[0025] Figure 8 It is the example timing diagram of the increment counter;

[0026] Figure 9 It is the working principle diagram of the serialization bit stream generator;

[0027] Figure 10 They are the data results collected by two types of ADCs;

[0028] Figure 11 They are the results of normalizing the data collected by two types of ADCs;

[0029] Figure 12 They are the results of converting the data collected by two types of ADCs into bit streams;

[0030] Figure 13 It is to count the number of 0s and 1s in the bit stream and the total number of binary values. Detailed implementation manners

[0031] In the following description, for the purpose of illustration rather than limitation, specific details such as specific system structures and technologies are presented to thoroughly understand the embodiments of the present invention. However, those skilled in the art should clearly understand that the present invention can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present invention.

[0032] For an N-point time series signal X = [x1, x2, …, x N T , its r-order difference operator is defined as:

[0033]

[0034] where x i is the i-th element in the signal X, r is a positive integer, represents the combination number of choosing j from r, and Y is the increment after the signal X undergoes r-order difference calculation. D r is the r-order difference operator and can be expressed in matrix form as follows:

[0035]

[0036] ​As can be seen from the above formula, when calculating the r-th order increment of the currently acquired data point, the values of the previous r acquired data points need to be obtained.

[0037] Taking the second-order difference operator as an example, its matrix form is:

[0038]

[0039] When calculating the second-order difference increment value of the currently acquired data point, first, the values of the previous 2 acquired data points need to be obtained. After calculation, the second-order minuend y i =(2x i-1 -x i-2 ), and then the currently acquired data point x i is used to subtract y i to obtain the second-order difference increment value z i =x i -y i =x i -(2x i-1 -x i-2 ).

[0040] Taking the third-order difference operator as an example, its matrix form is:

[0041]

[0042] When calculating the third-order difference increment value of the currently acquired data point, first, the values of the previous 3 acquired data points need to be obtained. After calculation, the third-order minuend y i =(-3x i-1 +3x i-2 -x i-3 ), and then the currently acquired data point x i is used to subtract y i to obtain the third-order difference increment value z i =x i -y i =x i -(-3x i-1 +3x i-2 -x i-3 ).

[0043] To achieve r-th order increment acquisition, the present invention proposes an integer-order difference analog-to-digital conversion device for intracranial nerve field potential acquisition, and the overall architecture is as Figure 1 shown. This device consists of a multiplexer, a multi-stage buffer matrix module, a DAC controller, a DAC, a comparator, an increment counter, and a serialized bitstream generator.

[0044] The multiplexer is driven by the global clock CLK of the IOD-ADC ADCControl, switch the acquisition channel every clock cycle, and stabilize the current acquisition signal after the channel switch, so as to support multi-channel parallel acquisition. The multiplexer in this circuit adopts a standard time-division multiplexing structure, allowing the signals of L channels to share a physical channel for transmission, and occupying this channel in turn within different CLK ADC cycles to achieve efficient data acquisition.

[0045] In the present invention, the time-division multiplexing structure is implemented through a multiplexer circuit, and the switch position is switched once every clock cycle to select different acquisition channels. After the multiplexer, the signal enters the sample-and-hold circuit, where a switched-capacitor circuit is used to physically hold the signal to ensure the stability of the signal during the acquisition process and guarantee the accuracy and reliability of subsequent acquisitions.

[0046] As Figure 2 shown, the multi-stage buffer matrix module is controlled by the global clock CLK of the IOD-ADC ADC and is responsible for storing and outputting the values of the previous r acquisition data points of each channel to support the calculation of the rth-order minuend, while avoiding the complexity of the traditional first-in-first-out buffer structure.

[0047] Specifically, this module includes a storage matrix and a calculation matrix. The storage matrix includes r rows and L columns. In each clock cycle, the data input from the DAC is input to the left side of the rth row, and the data on the rightmost side of each row is shifted out of the storage matrix and input to the calculation matrix for calculation. At the same time, the data in the storage matrix moves in a circular manner, that is, the data shifted out from the lower row is simultaneously moved into the left side of the upper row. Except for the rth row that can input data from the DAC, the data of other rows can only be moved in from the corresponding lower row and cannot receive input data from outside the module. It can be seen that this storage matrix forms a 1-input r-output structure. The design of this structure is intended to cooperate with the calculation matrix to read data in a fixed form, thereby avoiding increasing the circuit complexity and power consumption due to frequent switching of the readout ports.

[0048] The calculation matrix is composed of a series of calculation units, including a shift unit, an addition unit, and an inversion unit. The shift unit can shift the input data left or right by bits to implement multiplication or division operations. The addition unit is used to perform addition operations on the input data. The inversion unit is used to invert the sign bit of the input data to obtain the inverted value of the input data. By combining the above calculation units, the calculation of the rth-order minuend can be achieved, and the differential increment value is output to the DAC controller to complete the task of the multi-stage buffer matrix module.

[0049] The multi-stage buffer matrix module is controlled by the global clock CLK of the IOD-ADC ADCControl, receives one piece of data, performs one memory matrix read, and performs one calculation per cycle. Taking a 3rd-order IOD-ADC as an example, assuming the current is the i-th cycle and the first channel is to be sampled, the sampled value is obtained At this time, the 3rd-order differential increment value is Then the execution process is as Figure 3 shown, specifically as follows:

[0050] Assume that the data stored in the current memory matrix is:

[0051]

[0052] First step: Take the first 3 sampled values of the first channel from the 3 output terminals of the memory matrix and Input these three sampled values into the calculation matrix for calculation operations respectively.

[0053] Second step: Activate a negation unit in the calculation matrix, input into the negation unit in the calculation matrix, and obtain

[0054] Third step, activate a shift unit and an addition unit in the calculation matrix, input into the shift unit for a left shift by 1 bit, and obtain Then input the result into the addition unit and add them together to obtain

[0055] Fourth step, activate a shift unit, an addition unit, and a negation unit in the calculation matrix, input into the shift unit for a left shift by 1 bit, and obtain Then input the result into the addition unit and add them together to obtain Finally, input the result into the negation unit to obtain

[0056] Fifth step, activate an addition unit in the calculation matrix, input the three results obtained from the second step to the fourth step into the addition unit, and obtain which is the output 3rd-order minuend.

[0057] As Figure 4 shown, the DAC controller is used to read the r-th order minuend output by the multi-level buffer matrix module and generate a DAC control code in combination with the output of the increment counter.

[0058] Specifically, under the global clock CLK ADCFor the control, the IOD-ADC will sequentially collect data from L channels, with one channel's data collected per clock cycle. Assume that currently the first channel is to be collected, and the collected value is obtained. Then the working process of the DAC controller is as follows:

[0059] In the first step, the r-order minuend y is calculated through the multi-stage buffer matrix module. i .

[0060] In the second step: The increment counter inputs the increment value kΔ, and adds it to the r-order minuend y i to obtain the value to be compared y i + kΔ, where Δ is the minimum quantization unit of the IOD-ADC. The initial value of the increment value is 0Δ.

[0061] In the third step: The value to be compared y i + kΔ is used as the DAC control code and input into the DAC to be converted into the corresponding signal to be compared.

[0062] In the fourth step: The signal to be compared is input into the comparator and compared with the signal to be collected. If the signal to be collected is greater than the signal to be compared, the increment counter is incremented by 1Δ, and the increment value becomes (k + 1)Δ; otherwise, it is decremented by 1Δ, and the increment value becomes (k - 1)Δ.

[0063] In the fifth step: The second to fourth steps are looped until the difference between the signal to be collected and the signal to be compared is less than 1Δ. At this time, the loop stops, and the output of the DAC at this time is used as the collected value.

[0064] In the sixth step: It is stored back into the multi-stage buffer matrix module to update the values of each row in the multi-stage buffer matrix module.

[0065] Subsequently, according to the above process, the collection of the 2nd to Lth channels can be continued. After collecting the Lth channel, the collection of the first channel is then resumed.

[0066] As Figure 5 shown, the DAC reads the DAC control code output by the DAC controller, converts it into the signal to be compared, and after multiple comparisons, the final DAC output is used as the collected value of the current channel for this collection and stored in the multi-stage buffer matrix module.

[0067] Specifically, the DAC adopts an 8-bit capacitive voltage division structure, consisting of an array of 8 weighted capacitors. The sizes of the 8 capacitors are C, 2C, 4C, 8C, C, 2C, 4C, and 8C respectively. Before starting the conversion, the Reset switch is closed, and the upper plates of all capacitors are grounded to discharge the capacitor array. During the conversion phase, the Reset switch is opened, and the lower plates of the 8 binary weighted capacitors are connected to V according to the control code.ref Alternatively, a 1.067C attenuation capacitor is connected to divide the capacitor array into two parts, thereby reducing the types of capacitors. The rightmost part of the DAC forms a voltage follower structure through an operational amplifier with negative feedback connected, isolating the capacitor array from the DAC output to reduce the output impedance and enhance the load driving ability.

[0068] As Figure 6 shown, the comparator is used to compare the signal to be acquired output by the multiplexer with the signal to be compared output by the DAC, and input the comparison result into the increment counter for increment counting. To reduce power consumption, a dynamic comparator is adopted in the IOD-ADC. The signal to be acquired is input from the Vi np terminal, the signal to be compared is input from the V inn terminal, and the comparison result is output from the V out terminal.

[0069] As Figure 7 shown, the increment counter is controlled by the global clock CLK ADC of the IOD-ADC. In each clock cycle, it reads the output result of the comparator, calculates the integer-order increment of the current acquired signal and the previous acquired value, and transmits the increment to the DAC controller and the serialized bitstream generator.

[0070] Specifically, the increment counter contains two modules. Among them, the sign register is composed of a 1-bit register circuit and is used to store the sign of the increment value. The 8-bit binary counter is composed of 8 D flip-flops and is used to store the magnitude of the increment value.

[0071] The working mode of the increment counter is as follows: The initial value of the increment value is 0Δ. When the output of the comparator is positive, it is judged that the signal to be acquired is greater than the signal to be compared, then the increment counter is incremented by 1Δ, the sign register is a positive sign, and the increment value becomes (0 + 1)Δ. When the output of the comparator is negative, it is judged that the signal to be acquired is less than the signal to be compared, then the increment counter is decremented by 1Δ, the sign register is a negative sign, and the increment value becomes (0 - 1)Δ. After each judgment, the increment value is output to the DAC controller to generate the DAC control code. The above judgment steps are cycled until the difference between the signal to be acquired and the signal to be compared is less than 1Δ. At this time, the loop stops, and the sign in the sign register and the value in the 8-bit binary counter are concatenated to obtain the final integer-order increment value.

[0072] As Figure 8 shown, it is an example timing diagram of the increment counter. In each period of the global clock CLK ADC , one channel is acquired respectively. In each clock cycle, the output of the multiplexer remains stable for the increment counter to perform analog-to-digital conversion.

[0073] In the first cycle, the incremental counter performs analog-to-digital conversion on the CH1 channel. During the low level of CLK ADC , both the signal to be acquired and the DAC output signal remain stable. At this time, the DAC output signal is the signal to be compared for the CH1 channel. During the high level of CLK ADC , the incremental counter starts analog-to-digital conversion. The first comparison reveals that the signal to be compared is less than the signal to be acquired. Therefore, after incrementing by 1Δ, the comparison continues. After 6 increments of 1Δ, the difference between the signal to be compared and the signal to be acquired is less than 1Δ, and the conversion is completed at this time. At the start of the next CLK ADC cycle, the incremental counter outputs the incremental value of the CH1 channel, which is +6Δ.

[0074] In the second cycle, the incremental counter performs analog-to-digital conversion on the CH2 channel. During the low level of CLK ADC , both the signal to be acquired and the DAC output signal remain stable. At this time, the DAC output signal is the signal to be compared for the CH2 channel. During the high level of CLK ADC , the incremental counter starts analog-to-digital conversion. The first comparison shows that the difference between the signal to be compared and the signal to be acquired is less than 1Δ, and the conversion is completed at this time. At the start of the next CLK ADC cycle, the incremental counter outputs the incremental value of the CH2 channel, which is 0Δ. At this time, it is considered that there is no increment between this acquisition and the previous acquisition of the CH2 channel.

[0075] In the third cycle, the incremental counter performs analog-to-digital conversion on the CH3 channel. During the low level of CLK ADC , both the signal to be acquired and the DAC output signal remain stable. At this time, the DAC output signal is the signal to be compared for the CH3 channel. During the high level of CLK ADC , the incremental counter starts analog-to-digital conversion. The first comparison shows that the signal to be compared is greater than the signal to be acquired. Therefore, after decrementing by 1Δ, the comparison continues. After 4 decrements of 1Δ, the difference between the signal to be compared and the signal to be acquired is less than 1Δ, and the conversion is completed at this time. At the start of the next CLK ADC cycle, the incremental counter outputs the incremental value of the CH3 channel, which is -4Δ.

[0076] Other channels perform analog-to-digital conversion cycle by cycle according to the above conversion rules.

[0077] As Figure 9 shown, the serialized bitstream generator is controlled by the global clock CLK ADC of the IOD-ADC. In each clock cycle, it stores and converts the signal increment output by the incremental counter into a bitstream, realizes data compression, and performs serialization and packaging to ensure the synchronization of data transmission and generate the final bitstream output by the IOD-ADC.

[0078] Specifically, at each global clock CLK ADC At the rising edge of , the event judge reads the increment value from the increment counter and determines whether the increment value forms an integer increment event. When the increment value is not 0Δ, it indicates that the current acquisition signal is different from the signal to be compared, and it can be determined as an integer increment event. At this time, the increment value is stored in the event register.

[0079] Each integer-order incremental event requires 9+log2L bits of storage space, of which log2L bits are used for the number of L channels, 1 bit is used for the incremental value sign, and 8 bits are used to store the incremental value amplitude. In addition, the system is also equipped with a 9+log2L-bit replica memory for parallel data caching and processing to improve data throughput efficiency.

[0080] After all L channels have completed one acquisition, a complete data acquisition frame is formed. After each acquisition frame is completed, the finite state machine generates an enable signal ENA and inputs it to the bit stream clock generator. The clock generator has a built-in ring oscillator and is dedicated to providing the clock CLK for bit stream packaging. BIT .

[0081] Subsequently, the finite state machine scans the data in the event register and based on CLK BIT The clock is used to pack the bit stream and finally generate the IOD-ADC data bit stream.

[0082] The IOD-ADC proposed in the present invention is compared with the most advanced Nyquist ADC currently available. The experimental setting is as follows: the test animal is anesthetized and stationary in an animal cage, and electrodes are implanted in the head to lead out two electrode channels. The same neural field potential exists on each electrode channel, where channel 1 is collected using the Nyquist ADC and channel 2 is collected using the IOD-ADC. The differential order of the IOD-ADC is selected as 1, 2, and 3 respectively for comprehensive comparison. The collected data is transmitted to a computer via wired mode for analysis.

[0083] The data collected by the two ADCs are as follows: Figure 10 As shown, it can be seen that the data collected by Nyquist ADC has a large volatility and a large amplitude, while the data collected by IOD-ADC has a small volatility. Most of the collected values are very close to 0, and only a few collected values are relatively large, showing a high sparsity.

[0084] The data collected by the two ADCs are arranged in descending order and normalized. Figure 11 As shown in Figure 2, it can be seen that the data collected by IOD-ADC is significantly sparser than the data collected by Nyquist ADC.

[0085] Convert the data collected by the two ADCs into bitstreams, as Figure 12 shown. It can be seen that the bitstream of the IOD-ADC is sparser than that of the Nyquist ADC.

[0086] Convert the data collected by the two ADCs into bitstreams, and count the number of 0s and 1s in the bitstream as well as the total number of binary values, as Figure 13 shown. It can be concluded that the data volume of the 1st-order IOD-ADC bitstream is 47.3% of that of the Nyquist ADC bitstream, the data volume of the 2nd-order IOD-ADC bitstream is 43.2% of that of the Nyquist ADC bitstream, and the data volume of the 3rd-order IOD-ADC bitstream is 41.4% of that of the Nyquist ADC bitstream.

[0087] The above shows that the data volume required to be transmitted by the IOD-ADC is significantly lower than that required to be transmitted by the Nyquist ADC, thus having higher energy efficiency.

[0088] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

[0089] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above division of each functional unit and module is used as an example for illustration. In practical applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiments can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit. In addition, the specific names of each functional unit and module are only for the convenience of mutual distinction and do not limit the protection scope of the present application. The specific working processes of the units and modules in the above system can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0090] In the above embodiments, the descriptions of each embodiment have their own emphases. For the parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0091] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0092] In the embodiments provided by the present invention, it should be understood that the disclosed device / terminal device and method can be implemented in other ways. For example, the device / terminal device embodiments described above are merely illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces. The indirect coupling or communication connection of the device or unit can be in an electrical, mechanical or other form.

[0093] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place, or can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0094] In addition, the functional units in each embodiment of the present invention can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated units can be implemented in the form of hardware or in the form of software functional units.

[0095] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, to implement all or part of the processes in the above-described embodiment methods of the present invention, it can also be completed by a computer program instructing relevant hardware. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above-described various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file, or some intermediate form, etc. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disc, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the content included in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice within the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.

[0096] The above-described embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or perform equivalent replacements for some of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention and should all be included within the protection scope of the present invention.

Claims

1. An Integer Order Difference Analog-to-Digital Converter (IOD-ADC) for intracranial nerve field potential acquisition. The device consists of a multiplexer, a multi-stage buffer matrix module, a DAC controller, a DAC, a comparator, an increment counter, and a serialized bitstream generator, and is used to acquire intracranial nerve field potential signals; The multiplexer, multi-stage buffer matrix module, increment counter, and serialized bitstream generator are all under the control of the global clock CLK of the IOD-ADC ADC control; The multiplexer switches the acquisition channels in each clock cycle and stabilizes the current acquisition signal to support multi-channel parallel acquisition; The multi-stage buffer matrix module is responsible for storing and outputting the previous acquisition value of each channel to support the calculation of any integer-order delta encoding; The DAC controller is used to read the previous acquisition value of the multi-stage buffer matrix module and generate a DAC control code in combination with the output of the increment counter; The DAC reads the DAC control code output by the DAC controller, converts it into a signal to be compared. After multiple comparisons, the final DAC output is stored as the current acquisition value of the current channel in the multi-stage buffer matrix module; The comparator is used to compare the signal to be acquired output by the multiplexer with the signal to be compared output by the DAC, and input the comparison result into the increment counter for increment counting; The increment counter reads the output result of the comparator in each clock cycle, calculates the integer-order increment of the current acquisition signal and the previous acquisition value, and transmits the increment to the DAC controller and the serialized bitstream generator; The serialized bitstream generator stores and converts the signal increment output by the increment counter into a bitstream in each clock cycle, and generates the final bitstream output by the IOD-ADC.

2. An integer order difference analog-to-digital converter according to claim 1, wherein the multiplexer adopts a standard time-division multiplexing structure, and the time-division multiplexing structure is implemented by a multiplexer circuit. The switch position is switched once in each clock cycle to select different acquisition channels.

3. An integer order difference analog-to-digital converter according to claim 1, wherein the multi-stage buffer matrix module includes a storage matrix and a calculation matrix; The storage matrix includes r rows and L columns, and reads data in a fixed form; The calculation matrix consists of a shift unit, an addition unit, and an inversion unit. The shift unit shifts the input data left or right by bit to implement multiplication or division operations. The addition unit is used to perform addition operations on the input data. The inversion unit is used to invert the sign bit of the input data to obtain the inverted value of the input data. By combining the above calculation units, the r-order minuend calculation can be realized, and the differential increment value is output to the DAC controller to complete the task of the multi-stage buffer matrix module.

4. An integer-order differential analog-to-digital conversion device according to claim 3, wherein in each clock cycle, the data input from the DAC is input to the left side of the r-th row of the storage matrix, and the data on the rightmost side of each row is shifted out of the storage matrix and input to the calculation matrix for calculation; at the same time, the data in the storage matrix is circularly shifted, that is, the data shifted out of the lower row is simultaneously shifted into the left side of the upper row; except that the r-th row can input data from the DAC, the data of other rows can only be shifted in from the corresponding lower row and cannot receive input data from outside the module.

5. An integer-order differential analog-to-digital conversion device according to claim 1, wherein the DAC controller is used to read the r-th order minuend output by the multi-level buffer matrix module and generate a DAC control code in combination with the output of the increment counter.

6. An integer-order differential analog-to-digital conversion device according to claim 1, and the working process of the DAC controller is as follows: First, calculate the minuend y of order r through the multi-level buffer matrix module i ; Step 2: The increment counter inputs an increment value kΔ, and the r-th minuend y i is added to obtain a value y to be compared i +kΔ, where Δ is the minimum quantization unit of the IOD-ADC, and the initial value of the increment value is 0Δ; Step 3: Use the value y to be compared i +kΔ as the DAC control code, input it into the DAC, and convert it into the corresponding signal to be compared; The fourth step: Input the signal to be compared into the comparator to compare with the signal to be collected; if the signal to be collected is greater than the signal to be compared, the increment counter is incremented by 1Δ, and the increment value becomes (k + 1)Δ, otherwise it is decremented by 1Δ, and the increment value becomes (k - 1)Δ; Step 5: Loop through Step 2 to Step 4 until the difference between the signal to be collected and the signal to be compared is less than 1Δ. At this point, stop the loop and use the output of the DAC at this time as the collected value Step 6: Store back into the multi-level buffer matrix module and update the values of each row in the multi-level buffer matrix module.

7. An integer-order differential analog-to-digital conversion device according to claim 1, wherein the DAC is implemented by an 8-bit capacitive voltage division structure; the comparator uses a dynamic comparator.

8. An integer-order differential analog-to-digital conversion device according to claim 1, wherein the increment counter includes a sign register and an 8-bit binary counter. The sign register is composed of a 1-bit register circuit and is used to store the sign of the increment value. The 8-bit binary counter is composed of 8 D flip-flops and is used to store the amplitude of the increment value.

9. An integer-order differential analog-to-digital conversion device according to claim 8, and the working process of the increment counter is: the initial value of the increment value is 0Δ; when the output of the comparator is positive, it is judged that the signal to be collected is greater than the signal to be compared, then the increment counter is incremented by 1Δ, the sign register is a positive sign, and the increment value becomes (0 + 1)Δ; when the output of the comparator is negative, it is judged that the signal to be collected is less than the signal to be compared, then the increment counter is decremented by 1Δ, the sign register is a negative sign, and the increment value becomes (0 - 1)Δ; after each judgment, the increment value is output to the DAC controller to generate a DAC control code; the above judgment steps are cycled until the difference between the signal to be collected and the signal to be compared is less than 1Δ, at which time the loop is stopped, and the sign in the sign register and the value in the 8-bit binary counter are spliced to obtain the final integer-order increment value.

10. An integer-order differential analog-to-digital conversion device according to claim 1, wherein the serialized bitstream generator is composed of an event judge, an event register, a finite state machine, a bitstream clock generator, and a bitstream packer.

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