Data compression method and module, electronic equipment and debugging system
By combining the sequential instruction filtering, differential compression and Hafman coding of tracking instructions, the problems of large amount of data and large storage space requirements in the prior art are solved, and data volume reduction and communication efficiency improvement are achieved.
Patent Information
- Application Number
- CN202510524014.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-24
- Publication Date
- 2025-07-25
AI Technical Summary
The existing tracking instruction data compression scheme is difficult to meet the requirements of reduced data volume, improved communication efficiency and small storage space requirements at the same time. The Deflate compression algorithm is complex, and the static Huffman encoding compression algorithm based on the dual hash structure requires additional storage space.
The combination of filtering and filtering, differential compression, leading zero compression and binary tree compression encoding of sequential instruction classes is adopted to perform multi-layer compression of tracking instructions, including filtering out sequential instruction classes, differential compression instruction address information, compressing leading zero characters and Huffman encoding.
It effectively reduces the amount of data transmitted and tracking instructions in the chip, improves data communication efficiency, and reduces the hardware storage space requirements.
Smart Images
Figure CN120377932A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of data encoding and compression processing, and particularly relates to a data compression method, module, electronic device and debugging system. Background Art
[0002] In modern chip designs, to meet the growing computing demands, multiple processor cores are usually set up to simultaneously run different tasks or threads through a multi-core architecture, so as to improve computing efficiency and performance. With the increasing complexity of chip designs, the amount of data of trace instructions generated during chip operation has increased significantly. These trace instructions are characterized by large data volume and high data repeatability. Therefore, data compression for trace instructions is particularly important.
[0003] For data compression of trace instructions, the Deflate compression algorithm and the static Huffman coding compression algorithm based on a double hash structure are currently commonly used. However, the Deflate compression algorithm has high complexity and time-consuming calculations, which affect the overall operation performance of the chip; the static Huffman coding compression algorithm based on a double hash structure requires additional storage space to store Huffman tree information, resulting in a large storage space requirement. That is to say, the existing data compression solutions for trace instructions in the market are difficult to simultaneously meet the requirements of reducing data volume, improving communication efficiency, and having a small storage space requirement. Summary of the Invention
[0004] The purpose of this application is to provide a data compression method, module, electronic device and debugging system for the characteristics of large data volume and high data repeatability of the read data of trace instructions, which can reduce the amount of data used to transmit trace instructions in the chip, improve data communication efficiency, and reduce the hardware storage cost.
[0005] According to the first aspect of the embodiments of this application, a data compression method is provided, including: Reading the program blocks generated by a processing module to obtain an original instruction set, where the original instruction set has at least one instruction information; Filtering out the instruction information determined to be sequential instruction types in the original instruction set according to a preset rule to obtain a first instruction set; Differentially compressing the instruction address information of the instruction information in the first instruction set to obtain a second instruction set; Compressing the leading zero characters of the instruction information in the second instruction set to obtain a third instruction set; Compressing the third instruction set into a fourth data set through binary tree compression coding; Storing the fourth data set as the compression result of the program block into a storage module.
[0006] According to the above technical solution, based on program blocks, the instruction information in the same program block is successively filtered and screened for sequential instruction types, the address information is differentially compressed, leading zero compression and binary tree compression encoding are performed, and the instruction information is compressed through multiple layers to obtain a fourth data set, so that the data volume of the fourth data set used to transmit trace instructions in the chip decreases, improving data communication efficiency. And since the data volume of the compressed fourth data set is smaller than that of the program block, the hardware storage space occupied during transmission also becomes smaller.
[0007] In one implementation, filtering out the instruction information determined to be of sequential instruction types in the original instruction set according to a preset rule to obtain a first instruction set includes: Dividing the instruction information in the original instruction set into reserved instructions and instructions to be divided, where the reserved instructions are the instruction information at the head in the original instruction set; Performing character recognition on the instructions to be divided according to a preset vocabulary, and dividing the instructions to be divided into sequential instruction types or non-sequential instruction types; Deleting all the instructions to be divided of sequential instruction types from the original instruction set to obtain a first instruction set.
[0008] According to the above technical solution, performing character recognition on the other instruction information in the original instruction set except the instruction information at the head, and screening out the recognized instruction information of sequential instruction types to obtain a first instruction set. Since sequential instructions are not the key information in the program, filtering out the instruction information of sequential instruction types will not cause the loss of key information. This solution compresses the data volume of the instruction information in the original instruction set and also ensures the retention of key information.
[0009] In one implementation, the instructions to be divided of non-sequential instruction types include jump instructions, return instructions, subroutine call instructions, control instructions, I / O instructions, and processing instructions, and the processing instructions are applied to strings and memory blocks.
[0010] In one implementation, differentially compressing the instruction address information of the instruction information in the first instruction set to obtain a second instruction set includes: Reading the instruction address information of all instruction information in the first instruction set; Calculating the difference between the instruction address information of the next instruction information and the instruction address information of the previous instruction information to obtain the address difference corresponding to the next instruction information until the instruction address information of the next instruction is the instruction address information of the instruction information at the end in the first instruction set; According to the instruction information, replacing the instruction address information in the first instruction set with the corresponding address difference to obtain a second instruction set.
[0011] According to the above technical solution, differential compression is performed on each instruction information in the first instruction set with respect to the instruction address information. While ensuring that the receiving end can decode smoothly, this differential compression further reduces the data volume of the second instruction set.
[0012] In one implementation, among the instructions in the second instruction set, the first instruction information has instruction address information, and other instruction information has address differences.
[0013] In one implementation, the leading zero characters of the instruction information in the second instruction set are compressed to obtain a third instruction set, including: Recording the numerical value of the number of consecutive zero values at the front end of the address difference in the second instruction set; Deleting the consecutive zero values at the front end of the address difference and filling in the numerical value to obtain the third instruction set.
[0014] According to the above technical solution, leading zero compression is performed on the address differences in the second instruction set. Without changing the amount of information, the data volume of each instruction information with an address difference in the second instruction set is reduced, realizing further data compression.
[0015] In one implementation, the third instruction set is compressed into a fourth data set by binary tree compression encoding, including: Extracting the operation code and operation number of each instruction information in the third instruction set; Updating the Huffman tree according to the operation code and the operation number to obtain an optimal tree structure; Compressing the instruction information into a conflict-free prefix code according to the optimal tree structure to obtain a fourth data set, where the fourth data set includes the conflict-free prefix code and the optimal tree structure.
[0016] According to the above technical solution, dynamic Huffman coding is performed on the operation code and operation number of the instruction. Dynamic Huffman coding generates a conflict-free prefix code by updating the operation code frequency in real time and reconstructing the optimal tree structure, and at the same time saves the tree structure information to achieve efficient compressed transmission.
[0017] According to the second aspect of the embodiments of the present application, a data compression module is provided, including: A reading unit for reading the program block generated by the processing module to obtain an original instruction set, where the original instruction set has at least one instruction information; An instruction compression unit connected to the reading unit for filtering out the instruction information determined to be sequential instruction types in the original instruction set according to a preset rule to obtain a first instruction set; An address compression unit connected to the instruction compression unit for differentially compressing the instruction address information of the instruction information in the first instruction set to obtain a second instruction set; A character compression unit, connected to the address compression unit, is configured to compress leading zero characters of instruction information in the second instruction set to obtain a third instruction set; An encoding compression unit, connected to the character compression unit, is configured to compress the third instruction set into a fourth data set through binary tree compression encoding; A compression output unit, connected to the encoding compression unit, is configured to store the fourth data set as a compression result of the program block in a storage module.
[0018] According to the above technical solution, the instruction information in the same original instruction set undergoes filtering and screening, differential compression of address information, leading zero compression, and Huffman encoding compression in sequence. The instruction information is compressed through multiple layers to obtain a fourth data set, reducing the data volume of the fourth data set for transmitting trace instructions in the chip, improving data communication efficiency, and since the data volume of the compressed fourth data set is smaller than that of the program block, the hardware storage space occupied during transmission also becomes smaller.
[0019] According to a third aspect of the embodiments of the present application, an electronic device is provided, including a memory and a processor. The memory is configured to store a computer program executable by the processor; the processor is configured to execute the computer program in the memory to implement the above method.
[0020] According to a fourth aspect of the embodiments of the present application, a debugging system is provided, including a processing module, the above data compression module, a storage module, and a trace debugging module; the processing module is configured to generate a program block; the data compression module is connected to the processing module and the storage module, and is configured to perform the above data compression method on the program block to obtain a fourth data set and store it in the storage module; the trace debugging module is connected to the storage module and is configured to read the fourth data set, locate the program block corresponding to the fourth data set, and perform debugging. Description of the Drawings
[0021] Figure 1 is a flowchart of a data compression method shown according to an exemplary embodiment.
[0022] Figure 2 is Figure 1 a flowchart of step 102 in
[0023] Figure 3 is Figure 1 a flowchart of step 103 in
[0024] Figure 4 is Figure 1 a flowchart of step 104 in
[0025] Figure 5 isFigure 1 Flowchart of step 105 in
[0026] Figure 6 Schematic diagram of a data compression module shown according to another exemplary embodiment.
[0027] Figure 7 Block diagram of an electronic device shown according to an exemplary embodiment.
[0028] Figure 8 Schematic diagram of a debugging system shown according to another exemplary embodiment. Detailed implementation manners
[0029] Unless otherwise defined, the technical terms or scientific terms used in this specification and the claims should have the ordinary meanings understood by those of ordinary skill in the technical field to which the present invention belongs. The following will describe the specific implementation manners of the present invention with reference to the accompanying drawings. It should be noted that in the specific description of these implementation manners, for the sake of concise description, this specification may not describe all features of the actual implementation manners in detail. Without departing from the spirit and scope of the present invention, those skilled in the art can modify and replace the implementation manners of the present invention, and the obtained implementation manners are also within the protection scope of the present invention.
[0030] An embodiment of the present application provides a data compression method. This data compression method can be applied to electronic devices such as data compressors and display chips. Please refer to Figure 1 , this data compression method may include the following steps 101 to step 103: Step 101: Read the program blocks generated by the processing module to obtain the original instruction set.
[0031] Specifically, in the debugging system, each processor (CPU) generates a large amount of instruction information during operation. The program block represents a segment of instruction information generated by the processing module. Reading these program blocks obtains the original instruction set, and the original instruction set has at least one instruction information. Usually, there are multiple instruction information in an original instruction set, and the program blocks generated by the processing module can be read multiple times to generate multiple original instruction sets.
[0032] Step 102: Filter out the instruction information determined to be sequential instruction types in the original instruction set according to the preset rules to obtain the first instruction set.
[0033] Specifically, sequential instructions refer to a sequence of instructions that are executed in the order of the instructions in the program. The execution of each instruction depends on the completion of the previous instruction, and the execution order of the instructions is exactly the same as the order in the program code. In a program, logic and function are the key information, rather than the instruction execution order. Sequential instructions are only a means to implement these functions, rather than the core of the program logic. Therefore, sequential instructions are not the key information in the program.
[0034] In one example, referring to Figure 2 as shown, the implementation of step 102 includes: Step 2-1, divide the instruction information in the original instruction set into reserved instructions and instructions to be divided. The reserved instructions are the instruction information at the top of the original instruction set.
[0035] Step 2-2, perform character recognition on the instructions to be divided according to a preset word library, and divide the instructions to be divided into sequential instruction classes or non-sequential instruction classes.
[0036] Step 2-3, delete all the instructions to be divided in the sequential instruction class from the original instruction set to obtain a first instruction set.
[0037] In this example, in the original instruction set, the instruction at the top is used as the reserved instruction, and other instruction information is used as the instructions to be divided. The word library is set by the staff, and there is at least one character for identifying sequential instruction classes or at least one character for identifying non-sequential instruction classes in the word library. Among them, the word library can be set manually or imported in batches. In the first case, the word library is set with characters for identifying sequential instructions. Through the character recognition in step 2-2, the instruction information in the sequential instruction class can be identified from the instructions to be divided, and other instruction information is set as the non-sequential instruction class; in the second case, the word library is set with characters for identifying non-sequential instructions. Through the character recognition in step 2-2, the instruction information in the non-sequential instruction class is identified from the instructions to be divided, and other instruction information is set as the sequential instruction class; in the third case, the word library is set with characters for identifying sequential instructions and characters for identifying non-sequential instructions. The instruction information in the sequential instruction class can be identified from the instructions to be divided, and the instruction information in the non-sequential instruction class can be identified from the instructions to be divided. By deleting the instruction information determined to be in the sequential instruction class from the original instruction set through step 2-3, a first instruction set containing only the instruction information in the non-sequential instruction class is obtained. Since sequential instructions are not the key information in the program, filtering out the instruction information in the sequential instruction class will not cause the loss of key information in the program. This solution compresses the data volume of the instruction information in the program and also ensures the retention of key information.
[0038] It should be noted that the instructions to be classified in the non-sequential instruction category include jump instructions, return instructions, subroutine call instructions, control instructions, I / O instructions, and processing instructions. The processing instructions are applied to strings and memory blocks. The instruction information of these instructions determined to be in the non-sequential instruction category represents the logic and functions in the program and is the key information of the program. Through the character recognition in step 2-2 above, the instruction information of these non-sequential instruction category instructions can be saved and aggregated into the first instruction set.
[0039] Step 103, perform differential compression on the instruction address information of the instruction information in the first instruction set to obtain the second instruction set.
[0040] Specifically, the instruction information in the first instruction set is the instruction information of the non-sequential instruction information category obtained in step 102 above. In this step 103, further compression is performed on the instruction address information of these instruction information to obtain the second instruction set. Differential compression is performed on the instruction address information of each instruction information in the first instruction set. While ensuring that the receiving end can decode smoothly, this differential compression further reduces the data volume of the second instruction set.
[0041] In an example, refer to the appendix Figure 3 As shown, the implementation of step 103 includes: Step 3-1, read the instruction address information of all instruction information in the first instruction set.
[0042] Step 3-2, calculate the difference between the instruction address information of the subsequent instruction information and the instruction address information of the previous instruction information to obtain the address difference corresponding to the subsequent instruction information until the instruction address information of the subsequent instruction is the instruction address information of the instruction information at the end in the first instruction set.
[0043] Step 3-3, use the address difference of the instruction information to update the instruction address information of the corresponding instruction information in the first instruction set to obtain the second instruction set.
[0044] In this example, in step 3-1, the instruction address information of each instruction information in the first instruction set obtained after going through step 102 is read. The instruction address information of the first instruction information is D1, the instruction address information of the second instruction information is D2,..., and the instruction address information of the nth instruction information is Dn.
[0045] In step 3-2, the instruction address information D1 of the first instruction information; the instruction address information D2 of the second instruction information is subtracted from the instruction address information D1 of the first instruction information to obtain the address difference △D2 of the second instruction information, △D2 = D2 - D1; the instruction address information D3 of the third instruction information is subtracted from the instruction address information D2 of the second instruction information to obtain the address difference △D3 of the second instruction information, △D3 = D3 - D2;... the instruction address information Dn of the nth instruction information is subtracted from the instruction address information D(n-1) of the (n-1)th instruction information to obtain the address difference △Dn of the second instruction information, △Dn = Dn - D(n-1). The last instruction information is the nth instruction information, and the instruction address information of the last instruction information is Dn. That is to say, step 3-2 performs differential calculation on the instruction information to obtain the address differences {△D2, △D3,..., △Dn} from the second instruction information to the last instruction information (i.e., the nth instruction information).
[0046] In step 3-3, the instruction address information of the corresponding instruction information in the first instruction set is updated using the address differences of the instruction information, and the instruction address information {D2, D3,..., Dn} of the corresponding instruction information is updated using the address differences {△D2, △D3,..., △Dn}, thereby obtaining the second instruction set. In this second instruction set, the instruction address information D1 of the first instruction information, the address difference △D2 of the second instruction information,..., and the address difference △Dn of the nth instruction information represent the address at the same time.
[0047] It should be noted that in the second instruction set obtained in this example, the first instruction information has instruction address information, and the other instruction information has address differences.
[0048] Since the instruction information (i.e., the trace instruction data) has the characteristics of a large amount of data and high data repeatability, and the instruction address information between the instruction information is very likely to be adjacent, the amount of data of the address difference is very likely to be smaller than the original instruction address information. In this example, the instruction address information is further compressed.
[0049] Step 104, compress the leading zero characters of the instruction information in the second instruction set to obtain the third instruction set.
[0050] Specifically, after step 103 is implemented, there are leading zero characters in the address differences of the instruction information in the second instruction set. In this case, these leading zero characters are compressed to obtain the third instruction set with the same amount of information and a smaller amount of data.
[0051] In one example, as shown in the attached Figure 4 figure, the implementation of step 104 includes: Step 4-1, record the quantity value of the leading consecutive zeros of the address difference in the second instruction set.
[0052] Step 4-2, delete the leading consecutive zeros of the address difference and fill in the quantity value to obtain the third instruction set.
[0053] In this example, since the difference between the instruction addresses of adjacent instruction information of non-sequential instruction classes is not large, the address difference obtained after step 103 has leading consecutive zeros. Subsequently, in this step 4-1, record the quantity value of the leading consecutive zeros in each address difference, and in step 4-2, use the quantity value to replace the leading zeros. For example, if the quantity value corresponding to the leading consecutive zeros "00000" of the address difference is "5", then subsequently use this quantity value to replace the leading consecutive zeros, achieving the effect of reducing the data volume while keeping the information content unchanged, and further compressing the second instruction set to obtain the third instruction set as the compression result.
[0054] Step 105, compress the third instruction set into the fourth data set through binary tree compression encoding.
[0055] Specifically, binary tree compression encoding is a data compression method based on a binary tree structure, usually used for lossless data compression. By constructing a binary tree to assign variable-length codes to the symbols in the data, the optimal prefix code is generated to achieve data compression. The preferred binary tree is set as a Huffman tree, and the binary tree compression encoding is set as Huffman Coding. The third instruction set is losslessly compressed through Huffman coding to obtain the fourth data set. This case also supports using other binary tree compression encodings to compress the third instruction set, such as binary arithmetic coding and binary tree dictionary coding.
[0056] In one example, refer to Figure 5 as shown, the implementation of step 105 includes: Step 5-1, extract the operation code and operands of each instruction information in the third instruction set.
[0057] Step 5-2, update the Huffman tree according to the operation code and operands to obtain the optimal tree structure, and generate non-conflicting prefix codes corresponding to each instruction information.
[0058] Step 5-3, compress the instruction information into non-conflicting prefix codes according to the optimal tree structure to obtain the fourth data set.
[0059] In this example, the opcode is the field in the instruction information that indicates the operation type, and the operand is the field in the instruction information that specifies the operation object. After the opcode and operand of each instruction information are extracted in step 5-1, the Huffman tree is updated in step 5-2: if the opcode has not appeared in the Huffman tree, insert it as a new node and update the tree structure; if the opcode already exists, increase its frequency and adjust the tree structure to maintain optimality; if the operand has not appeared in the Huffman tree, insert it as a new node and update the tree structure; if the operand already exists, increase its frequency and adjust the tree structure to maintain optimality. Finally, the optimal Huffman tree structure (optimal tree structure) is obtained, and based on this optimal tree structure, the opcode and operand of each instruction information are encoded to obtain a conflict-free prefix code. In step 5-3, the fourth data set includes the conflict-free prefix code and the optimal tree structure, and each instruction information corresponds to a conflict-free prefix code. This fourth data set is the result of compressing the third instruction set of this time through Huffman coding.
[0060] Step 106, store the fourth data set as the compression result of the program block in the storage module.
[0061] Specifically, output the fourth data set obtained in step 105. This fourth data set is the original instruction set that has been compressed multiple times in terms of data volume after going through step 102 of sequential instruction filtering, step 103 of differential compression of instruction address information, step 104 of leading zero compression, and step 104 of Huffman coding compression.
[0062] In summary, the technical solution provided by this application has the following advantages: Since sequential instructions are not the key information of the program, they can be directly removed. In this case, sequential instructions are filtered out, reducing the data volume of the second instruction set. Moreover, differential compression and leading zero character compression are performed on the instruction addresses in the instruction information, further reducing the overall data volume. Finally, Huffman coding is used for another compression. The instruction information in the original instruction set is compressed in multiple rounds of data compression, and the data volume of the fourth data set as the compression result is as small as possible. The execution method is simple, the hardware is easy to implement, and the reduction in data volume also makes the storage space occupied by transmitting the fourth data set in this case smaller compared to directly transmitting the program block.
[0063] Another exemplary embodiment of this application further provides a data compression module 60. As Figure 6 shown, in this embodiment, the data compression module includes: A reading unit 601, configured to read the program block generated by the processing module 81 to obtain an original instruction set, where the original instruction set has at least one instruction information; The instruction compression unit 602, connected to the reading unit 601, is configured to filter out the instruction information determined to be sequential instruction classes in the original instruction set according to a preset rule, and obtain a first instruction set; The address compression unit 603, connected to the instruction compression unit 602, is configured to differentially compress the instruction address information of the instruction information in the first instruction set to obtain a second instruction set; The character compression unit 604, connected to the address compression unit 603, is configured to compress the leading zero characters of the instruction information in the second instruction set to obtain a third instruction set; The encoding compression unit 605, connected to the character compression unit 604, is configured to compress the third instruction set into a fourth data set through binary tree compression encoding; The compression output unit 606, connected to the encoding compression unit 605, is configured to store the fourth data set as the compression result of the program block in the storage module 82.
[0064] In this example, based on the program block, the instruction information in the original instruction set obtained by reading the program block undergoes filtering and screening, differential compression of the address information, leading zero compression, and Huffman encoding compression in sequence. The instruction information is compressed through multiple layers to obtain a fourth data set, which reduces the amount of data for transmitting trace instructions in the chip, improves the data communication efficiency, and the fourth data set also occupies less hardware storage space compared to the program block during transmission.
[0065] An embodiment of the present application also proposes an electronic device, including a processor and a memory; the memory is used to store a computer program executable by the processor; the processor is used to execute the computer program in the memory to implement the data compression method described in any of the above embodiments.
[0066] Figure 7 is a block diagram of an electronic device shown according to an exemplary embodiment. For example, the electronic device 700 may be provided as a server. Referring to Figure 7 , the device 700 includes a processing component 722, which further includes one or more processors and memory resources represented by the memory 732 for storing instructions executable by the processing component 722, such as application programs. The application programs stored in the memory 732 may include one or more modules each corresponding to a set of instructions. In addition, the processing component 722 is configured to execute instructions to perform the above data compression method.
[0067] Device 700 may also include a power supply component 726 configured to perform power management of device 700, a wired or wireless network interface 750 configured to connect device 700 to a network, and an input / output (I / O) interface 758. Device 700 may operate based on an operating system stored in memory 732, such as Windows ServerTM, MacOS XTM, UnixTM, LinuxTM, FreeBSDTM or the like.
[0068] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as memory 732 including instructions, and the above instructions can be executed by processing component 722 of device 700 to complete the above method. For example, the non-transitory computer-readable storage medium may be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.
[0069] Another exemplary embodiment of the present application also proposes a debugging system, as shown in Figure 8 FIG. The debugging system 80 includes a processing module 81, the above data compression module 60, a storage module 82, and a trace debugging module 83.
[0070] The processing module 81 is used to generate program blocks and is usually set as at least one processor CPU; The data compression module 60 is connected to the processing module 81 and the storage module 82, and is used to perform the above data compression method on the program blocks to obtain a fourth data set and store it in the storage module 82; The trace debugging module 83 is connected to the storage module 82, and is used to read the fourth data set, locate the program block corresponding to the fourth data set, and perform debugging.
[0071] In the debugging system 80 in this example, the data compression module 60 performs extreme data compression on the instruction information in the program blocks generated by the processing module 81, and stores the fourth data set obtained by data compression in the storage module 82 for the trace debugging module 83 to read the compressed fourth data set, directly locate the program block corresponding to this compressed instruction, and then perform debugging.
[0072] In the present invention, the terms "first", "second", "third" and "fourth" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. The term "plurality" means two or more, unless otherwise clearly defined.
[0073] The above description of the embodiments is to enable those of ordinary skill in the art to understand and apply the present application. It is obvious that those skilled in the art can easily make various modifications to these embodiments and apply the general principles described herein to other embodiments without creative efforts. Therefore, the present application is not limited to the embodiments herein, and the improvements and modifications made by those skilled in the art based on the content disclosed in the present application without departing from the scope and spirit of the present application are within the scope of the present application.
Claims
1. A data compression method, characterized in that, including: generating a program block generated by a read processing module to obtain an original instruction set, the original instruction set having at least one instruction information; filtering out instruction information determined to be sequential instruction types in the original instruction set according to a preset rule to obtain a first instruction set; differentially compressing instruction address information of instruction information in the first instruction set to obtain a second instruction set; compressing leading zero characters of instruction information in the second instruction set to obtain a third instruction set; compressing the third instruction set into a fourth data set by binary tree compression encoding; storing the fourth data set as a compression result of the program block in a storage module.
2. The data compression method according to claim 1, wherein The filtering out instruction information determined to be sequential instruction types in the original instruction set according to a preset rule to obtain a first instruction set includes: dividing instruction information in the original instruction set into reserved instructions and instructions to be divided, the reserved instructions being the instruction information at the head in the original instruction set; performing character recognition on the instructions to be divided according to a preset vocabulary, and dividing the instructions to be divided into sequential instruction types or non-sequential instruction types; deleting all the instructions to be divided of sequential instruction types from the original instruction set to obtain the first instruction set.
3. The data compression method according to claim 2, wherein The instructions to be divided of non-sequential instruction types include jump instructions, return instructions, subroutine call instructions, control instructions, I / O instructions, and processing instructions, and the processing instructions are applied to strings and memory blocks.
4. The data compression method according to claim 1, wherein The differentially compressing instruction address information of instruction information in the first instruction set to obtain a second instruction set includes: reading instruction address information of all instruction information in the first instruction set; calculating a difference between the instruction address information of a subsequent instruction information and the instruction address information of a previous instruction information to obtain an address difference corresponding to the subsequent instruction information until the instruction address information of the subsequent instruction address information is the instruction address information of the instruction information at the end in the first instruction set; replacing the instruction address information in the first instruction set with the corresponding address difference according to the instruction information to obtain a second instruction set.
5. The data compression method according to claim 4, wherein In the second instruction set, the instruction information at the head has instruction address information, and other instruction information has address differences.
6. The data compression method according to claim 4, wherein The compressing leading zero characters of instruction information in the second instruction set to obtain a third instruction set includes: recording a quantity value of consecutive zero values at the front end of the address difference in the second instruction set; deleting the consecutive zero values at the front end of the address difference and supplementing the quantity value to obtain the third instruction set.
7. The data compression method according to claim 1, wherein The compressing the third instruction set into a fourth data set by binary tree compression encoding includes: extracting an operation code and an operand of each instruction information in the third instruction set; updating a Huffman tree according to the operation code and the operand to obtain an optimal tree structure; compressing the instruction information into a conflict-free prefix code according to the optimal tree structure to obtain a fourth data set, the fourth data set including the conflict-free prefix code and the optimal tree structure.
8. A data compression module, characterized in that, including: a reading unit for reading a program block generated by a processing module to obtain an original instruction set, the original instruction set having at least one instruction information; An instruction compression unit, connected to the reading unit, is configured to filter out the instruction information determined to be sequential instruction types in the original instruction set according to a preset rule to obtain a first instruction set; An address compression unit, connected to the instruction compression unit, is configured to differentially compress the instruction address information of the instruction information in the first instruction set to obtain a second instruction set; A character compression unit, connected to the address compression unit, is configured to compress the leading zero characters of the instruction information in the second instruction set to obtain a third instruction set; An encoding compression unit, connected to the character compression unit, is configured to compress the third instruction set into a fourth data set through binary tree compression encoding; A compression output unit, connected to the encoding compression unit, is configured to store the fourth data set as the compression result of the program block into a storage module.
9. An electronic device, characterized in that, It includes a memory and a processor. The memory is used to store a computer program executable by the processor; the processor is used to execute the computer program in the memory to implement the method according to any one of claims 1 to 7.
10. A debugging system, characterized in that, It includes a processing module, the data compression module according to claim 8, a storage module, and a trace debugging module; The processing module is used to generate a program block; The data compression module is connected to the processing module and the storage module, and is configured to perform the data compression method according to any one of claims 1 to 7 on the program block, obtain a fourth data set, and store it in the storage module; The trace debugging module is connected to the storage module, and is configured to read the fourth data set, locate the program block corresponding to the fourth data set, and perform debugging.