Variable node switching method, switching module, LDPC decoding method and decoder
By judging and exchanging variable node indexes in multiple LDPC codes, the memory access conflict problem is solved, the throughput and performance of the decoder is improved, and the defects of conventional methods are avoided.
Patent Information
- Application Number
- CN202510425435.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-07
- Publication Date
- 2025-07-25
AI Technical Summary
In the prior art, memory access conflicts are prone to occur when the variable nodes of multivariate LDPC code are updated, resulting in a decrease in the decoder throughput, and conventional solutions will affect the decoding performance.
By receiving the variable node index of the check matrix, we can judge whether it is consistent, and exchange variable nodes when it is consistent, changing the write order of each layer address, avoiding memory access conflicts, and using variable node exchange module and exchange method to improve the update process of variable nodes.
It improves the throughput of the decoder, avoids memory access conflicts, improves the decoding performance, and overcomes the defect of reducing throughput in conventional methods due to waiting for the upper-level information to be updated.
Smart Images
Figure CN120377935A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of communication technologies, and particularly to a variable node exchange method, an exchange module, an LDPC decoding method, and a decoder. Background Art
[0002] Low Density Parity Check (LDPC) codes are a class of linear block codes with sparse parity-check matrices proposed by Gallager. Multiple LDPC was first studied by Davey and MacKay in 1998. Compared with binary LDPC codes, multiple LDPC with medium and short code lengths has better decoding performance, has better effects in aspects such as high-order modulation and burst error correction, and is widely used in fields such as mobile communication and storage.
[0003] However, the information update between layers of a typical block parallel structure decoder is dependent. After the check node information update of the upper layer is completed, the lower layer can start to update the variable node information. If a certain variable node participates in two adjacent consecutive layers, an additional clock needs to be delayed to wait for the information update of the upper layer to be completed, which also brings a great burden to the control unit of the decoder. On the other hand, it will also reduce the throughput rate of the decoder. However, if in the parity-check matrix of the multiple LDPC code, any two adjacent layers are strictly orthogonal, that is, there is no '1' at the same position in the two adjacent layers, this phenomenon will not occur; but some multiple LDPC codes are not strictly orthogonal, so the problem of avoiding memory access conflicts needs to be considered.
[0004] At the same time, inserting an additional clock and waiting for the information update of the upper layer to be completed before processing the variable node information of the lower layer is a method to solve the memory access conflict, or abandoning the information updated in the i-th layer and still using the old information when the (i + 1)-th layer is updated. This way of solving the memory access conflict will reduce the bit error rate performance of the decoder because the information updated in the upper layer cannot be utilized in time when the lower layer is updated, reducing the frequency of information iteration.
[0005] Therefore, the present invention aims to provide a variable node exchange method, an exchange module, an LDPC decoding method, and a decoder to solve the above-mentioned related problems. Summary of the Invention
[0006] The technical problem to be solved by the present invention is the technical problem that memory access conflicts are likely to occur during the update of variable nodes in the prior art. The purpose is to provide a variable node swapping method, a swapping module, an LDPC decoding method and a decoder. When updating variable nodes but there is a memory access conflict, through the variable node swapping method provided by the present invention and the execution of the variable node swapping module, by receiving the variable node indexes used in the nth layer and the (n + 1)th layer of the parity-check matrix at the tth access moment, it is judged whether the two variable node indexes are the same; and according to the judgment result, the variable node used in the (n + 1)th layer at the tth access moment is swapped with the variable node used in the (n + 1)th layer at the (t + 1)th access moment, so as to improve the update process of variable nodes; adding the node swapping module provided in this embodiment to the LPDC decoder to change the writing order of each layer address, thereby avoiding the problem of needing to read before the information is updated, and at the same time directly avoiding the problem of generating memory access conflicts; it can improve the throughput rate of the decoder, overcoming the defect that the throughput rate is reduced by the conventional method of inserting an extra clock to wait for the upper-layer information to be updated before processing the variable node information of the next layer.
[0007] The present invention is realized through the following technical solutions:
[0008] A variable node swapping method, which is used when there is a memory access conflict during the decoding process. The method includes:
[0009] Receiving the variable node indexes used in the nth layer and the (n + 1)th layer of the parity-check matrix at the tth access moment;
[0010] If the two variable node indexes are the same, then swap the variable node used in the (n + 1)th layer at the tth access moment with the variable node used in the (n + 1)th layer at the (t + 1)th access moment.
[0011] The present invention also provides a variable node swapping module, which is used for the variable node swapping method described above. The variable node swapping module includes:
[0012] A judgment unit, which is used to receive the variable node indexes used in the nth layer and the (n + 1)th layer of the parity-check matrix at the tth access moment and judge whether the two variable node indexes are the same;
[0013] A selection unit, which is used to receive the judgment result output by the judgment unit. If the judgment result is that the two variable node indexes are the same, then swap the variable node used in the (n + 1)th layer at the tth access moment with the variable node used in the (n + 1)th layer at the (t + 1)th access moment.
[0014] Further, the judgment unit adopts an exclusive-OR logic gate.
[0015] Further, the selection unit adopts a two-way data selector.
[0016] The present invention also provides an LDPC decoding method, which includes the variable node transformation method described above. Specifically:
[0017] According to the non-zero elements at the corresponding positions of the variable nodes in the parity-check matrix, permute the message vector output by the variable nodes to obtain a permuted variable node message vector;
[0018] Based on the permuted variable node message vector, update the parity-check node message vector to obtain an updated parity-check node message vector;
[0019] Perform an inverse permutation on the updated parity-check node message vector; and after performing the inverse permutation on the updated parity-check node message vector, use the variable node transformation method to exchange the variable nodes used in the (n + 1)-th layer at the t-th access time and the variable nodes used in the (n + 1)-th layer at the (t + 1)-th access time, and output the exchanged variable nodes;
[0020] Based on the inverse permuted parity-check node message vector, update the variable node message vector of the exchanged variable nodes to obtain an updated variable node message vector;
[0021] According to the updated variable node message vector and parity-check node message vector, obtain an updated parity-check matrix;
[0022] Check the decoding sequence according to the updated parity-check matrix; if the checksum is an all-zero vector, the decoding is successful and the decoding result is output; otherwise, perform the next round of information transfer and update of the variable nodes and parity-check nodes until the maximum number of iterations is reached or the decoding is successful.
[0023] Further, before permuting the message vector output by the variable nodes according to the non-zero elements at the corresponding positions of the variable nodes in the parity-check matrix to obtain a permuted variable node message vector, the method further includes:
[0024] Map the received binary bit stream to finite field symbols according to the channel received sequence, and convert the reliability information of the received finite field symbols into an initial message vector of the variable nodes according to the channel noise.
[0025] The present invention also provides an LDPC decoder, which includes the variable node exchange module described in any one of the above. The system further includes:
[0026] A permutation module, configured to permute the message vector output by the variable nodes according to the non-zero elements at the corresponding positions of the variable nodes in the parity-check matrix to obtain a permuted variable node message vector;
[0027] A check node update module, configured to update a check node message vector based on the permuted variable node message vector to obtain an updated check node message vector;
[0028] An inverse permutation module, configured to perform an inverse permutation on the updated check node message vector;
[0029] A variable node exchange module, configured to, after performing an inverse permutation on the updated check node message vector, exchange the variable nodes used in the (n + 1)-th layer at the t-th access time with the variable nodes used in the (n + 1)-th layer at the (t + 1)-th access time by using a variable node transformation method, and output the exchanged variable nodes;
[0030] A variable node update module, configured to update the variable node message vector of the exchanged variable nodes based on the inversely permuted check node message vector to obtain an updated variable node message vector;
[0031] A decision decoding module, configured to obtain an updated parity check matrix according to the updated variable node message vector and check node message vector; check the decoding sequence according to the updated parity check matrix; if the checksum is an all-zero vector, the decoding is successful and the decoding result is output; otherwise, perform the information transfer and update of the variable nodes and check nodes in the next round until the maximum number of iterations is reached or the decoding is successful.
[0032] The present invention further provides a computer device, including a system memory and a processor, where the system memory stores a computer program, and when the processor executes the computer program, the steps of the above-mentioned variable node exchange method are implemented; when the processor executes the computer program, the steps of the decoding method described in any one of the above are also implemented.
[0033] The present invention further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned variable node exchange method are implemented; when the computer program is executed by a processor, the steps of the decoding method described in any one of the above are also implemented.
[0034] The present invention further provides a computer program product including instructions, and when the instructions are run by a computer device cluster, the computer device cluster is enabled to execute the above-mentioned variable node exchange method and execute the decoding method described in any one of the above.
[0035] Compared with the prior art, the present invention has the following advantages and beneficial effects:
[0036] In the present invention, when updating a variable node and a memory access conflict occurs, through the variable node swapping method provided by the present invention and the variable node swapping module that executes the method, by receiving the variable node indexes used in the n-th layer and the (n + 1)-th layer of the parity-check matrix at the t-th access moment, it is determined whether the two variable node indexes are the same; and according to the determination result, the variable node used in the (n + 1)-th layer at the t-th access moment is swapped with the variable node used in the (n + 1)-th layer at the (t + 1)-th access moment, so as to improve the variable node update process; by adding the node swapping module provided in this embodiment to the LPDC decoder, the writing order of each layer address is changed, thereby avoiding the problem of needing to read when the information has not been updated, and directly avoiding the problem of memory access conflict; it can improve the throughput rate of the decoder, and overcome the defect that the throughput rate is reduced by the conventional method of inserting an extra clock to wait for the upper layer information to be updated before processing the variable node information of the next layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following will briefly introduce the drawings required in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings. In the drawings:
[0038] Figure 1 is a schematic structural diagram of a variable node swapping module in this embodiment;
[0039] Figure 2 is a schematic flowchart of a variable node change method in this embodiment;
[0040] Figure 3 is a schematic diagram of the parity-check matrix when a memory access conflict occurs in the row-layered decoding algorithm exemplified in this embodiment;
[0041] Figure 4 is a swapping schematic diagram of the variable node swapping order in the parity-check matrix exemplified in this embodiment;
[0042] Figure 5 is an example diagram of node swapping applied to block-parallel variable nodes in this embodiment;
[0043] Figure 6 is a flowchart of a method of an LDPC decoding method in this embodiment;
[0044] Figure 7 is a schematic diagram of the module connection of an LDPC decoder in this embodiment;
[0045] Figure 8This is a schematic structural diagram of a computer device in this embodiment. Detailed implementation manners
[0046] The following describes exemplary embodiments of the present disclosure with reference to the accompanying drawings. Various details of the embodiments of the present disclosure are included to assist in understanding, and they should be considered merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of the present disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.
[0047] In the present disclosure, unless otherwise specified, the terms "first", "second", etc. are used to describe various elements and are not intended to limit the positional relationship, temporal relationship, or importance relationship of these elements. Such terms are only used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of the element, and in certain cases, based on the context description, they may also refer to different instances.
[0048] In the description of various examples in the present disclosure, the terms used are only for the purpose of describing specific examples and are not intended to be limiting. Unless the context clearly indicates otherwise, if the number of elements is not specifically limited, the element may be one or more. In addition, the term "and / or" used in the present disclosure covers any one of the listed items and all possible combinations.
[0049] To facilitate understanding of the embodiments of the present invention, first, some terms related to the present invention are explained.
[0050] In a check matrix (H matrix) with a dimension of m×n, each row corresponds to a check node (CN), representing a check equation; each column corresponds to a variable node (VN), representing a bit in the codeword, and is used to store soft information received by the channel (such as LLR, log-likelihood ratio); non-zero elements (usually 1) indicate that the variable node participates in the constraint of the check node.
[0051] Embodiment
[0052] This embodiment provides a variable node exchange module. Refer to Figure 1 , Figure 1 shows a schematic structural diagram of a variable node exchange module. Among them, the variable node exchange module includes:
[0053] A judgment unit is configured to receive the variable node indices used in the n-th layer and the (n + 1)-th layer of the check matrix at the t-th access moment, and determine whether the two variable node indices are the same; after the judgment unit finishes determining whether the two variable node indices are the same, a judgment result is obtained; A selection unit is configured to receive the judgment result output by the judgment unit. If the judgment result is that the two variable node indices are the same, the variable node used in the (n + 1)-th layer at the t-th access moment is exchanged with the variable node used in the (n + 1)-th layer at the (t + 1)-th access moment.
[0054] It should be noted that in this embodiment, the n-th layer refers to the current layer of the check matrix accessed at the current moment, and the specific layer number depends on the actual access, while the (n + 1)-th layer refers to the next layer of the n-th layer; the t-th access moment refers to the n-th moment of accessing the memory according to a specific clock edge; at the same time, in this embodiment, the judgment unit adopts an exclusive-OR logic gate; the selection unit adopts a two-way data selector; the first input terminal (read1) of the exclusive-OR logic gate is used to input the variable node index used in the n-th layer, and the second input terminal (read2) of the exclusive-OR logic gate is used to input the variable node index used in the (n + 1)-th layer; the output terminal of the exclusive-OR logic gate is connected to the control terminal of the two-way data selector, and is used to output a judgment result signal to the two-way data selector. The first input terminal of the two-way data selector is used to input the variable node (VN n ) used in the (n + 1)-th layer at the t-th access moment, and the second input terminal of the two-way data selector is used to input the variable node (VN n+1 ) used in the (n + 1)-th layer at the (t + 1)-th access moment. The output terminal of the two-way data selector is used to output the variable node selected based on the node judgment result.
[0055] This embodiment also provides a variable node exchange method. Refer to Figure 2 , Figure 2 which shows a schematic flowchart of a variable node change method. This method is used in the variable node exchange module described above. The method includes:
[0056] S1: Receive the variable node indices used in the n-th layer and the (n + 1)-th layer of the check matrix at the t-th access moment;
[0057] S2: If the two variable node indices are the same, exchange the variable node used in the (n + 1)-th layer at the t-th access moment with the variable node used in the (n + 1)-th layer at the (t + 1)-th access moment.
[0058] It should be noted that in this embodiment, the variable node index refers to a unique number or position identifier used to identify and locate the variable nodes that need to be processed in a specific layer; the variable node index used in the nth layer refers to the variable node index of the variable nodes used by the nth check node, and the variable node index used in the (n + 1)th layer refers to the variable node index of the variable nodes used by the (n + 1)th check node.
[0059] Specifically, in this embodiment, the variable node index used in the nth layer is input to the first input terminal (read1) of the exclusive-OR logic gate, and the variable node index used in the (n + 1)th layer is input to the second input terminal (read2) of the exclusive-OR logic gate, and then it is judged whether they are the same through the exclusive-OR logic gate; and the node judgment result is input to the two-way data selector. If they are the same, the variable nodes used in the (n + 1)th layer at the tth access time are exchanged with the variable nodes used in the (n + 1)th layer at the (t + 1)th access time; if they are different, the variable node exchange is not performed.
[0060] Exemplarily, in this embodiment, the situation when a memory access conflict occurs in the row-layered decoding algorithm is given. Refer to Figure 3 , when it reaches the 3rd clock cycle, it is necessary to read the information of the 13th variable node in the 1st layer and the 2nd layer at the same time. At this time, the information of the 13th variable node in the 1st layer has not been updated yet, which will cause a memory access conflict error in the read data; then it is necessary to rearrange the order of reading variable nodes in the 2nd layer; exchange the order of the conflicting position in the 2nd layer with the variable node to be read at the next clock, and the conflict can be avoided, as Figure 4 shown.
[0061] This embodiment also provides an example of node exchange applied to block-parallel variable nodes. Refer to Figure 5 shown. Specifically, in 100 check nodes of degree 4, each check node has exactly one connection with a variable node in every 50 columns. Therefore, the entire check matrix can be divided into 4 variable matrix blocks, and each block has 50 variable nodes of degree 4. In this configuration, each block receives 200 input bits from adjacent blocks and outputs 200 bits to each adjacent block. In order to form a parity check equation, each variable node in the block exchanges its output bits with the input bits received from adjacent blocks and passes them to the next adjacent block.
[0062] Specifically, in this embodiment, when updating variable nodes and there is a memory access conflict, through the variable node swapping method provided by the present invention and the variable node swapping module that executes it, by receiving the variable node indices used in the nth layer and the (n + 1)th layer of the parity-check matrix at the t-th access moment, it is determined whether the two variable node indices are the same; and according to the judgment result, the variable node used in the (n + 1)th layer at the t-th access moment is swapped with the variable node used in the (n + 1)th layer at the (t + 1)-th access moment, so as to improve the update process of variable nodes; adding the node swapping module provided in this embodiment to the LPDC decoder to change the writing order of each layer address, thereby avoiding the problem of reading when the information has not been updated, and at the same time directly avoiding the problem of memory access conflict; it can improve the throughput rate of the decoder and overcome the defect of reducing the throughput rate by conventionally inserting an extra clock to wait for the upper layer information to be updated before processing the variable node information of the next layer.
[0063] This embodiment also provides an LDPC decoding method. Refer to Figure 6 , Figure 6 which shows a method flow chart of an LDPC decoding method. This method includes the variable node transformation method described above. Specifically:
[0064] S10: Map the received binary bit stream into finite field symbols according to the channel received sequence, and convert the reliability information of the received finite field symbols into the initial message vector of the variable nodes according to the channel noise; according to the non-zero elements at the corresponding positions of the variable nodes in the parity-check matrix, permute the message vector output by the variable nodes to obtain the permuted variable node message vector;
[0065] Specifically, in this embodiment, according to the non-zero elements at the corresponding positions of the variable nodes in the parity-check matrix, the message vector output by the variable nodes is permuted. In this process, the message vector output by the variable nodes is multiplied by the corresponding finite field elements in the finite field. The permutation process is a conventional technical means and will not be elaborated here too much.
[0066] S20: Update the parity-check node message vector based on the permuted variable node message vector to obtain the updated parity-check node message vector;
[0067] Specifically, in this embodiment, the parity-check node message vector is updated by the following formula. Specifically: Wherein, represents the probability value when there is a correlation between the parity-check node m and the variable node n, c m represents the parity-check result related to the parity-check node m, x n represents the probability value of the variable node n, a represents the value size, h mn′ represents the element in the parity-check matrix, Denote the message vector related to variable node n' and value a passed from other nodes during message passing, Denote the variable nodes n' connected to the check node m other than n Perform a continuous multiplication. V represents the set of all symbol sequences that satisfy the m-th check relation.
[0068] S30: Perform an inverse permutation on the updated check node message vector; and after performing the inverse permutation on the updated check node message vector, use the variable node transformation method to exchange the variable nodes used in the (n + 1)-th layer at the t-th access time with the variable nodes used in the (n + 1)-th layer at the (t + 1)-th access time, and output the exchanged variable nodes;
[0069] Specifically, in this embodiment, performing an inverse permutation on the updated check node message vector is the inverse operation of finite field multiplication in the check equation, and the finite field symbols corresponding to the check node message vector are permuted to: Among them, Denote the finite field symbol corresponding to the output message of the check node, Denote the finite field symbol after the inverse operation. Through a single finite field division operation, the posterior probability is corresponded to the original symbol;
[0070] Then, based on the node exchange method proposed in this embodiment, judge the variable node indexes used in the current layer and the variable node indexes used in the next layer, and output the judged variable nodes to re-plan and schedule the update of the variable nodes.
[0071] S40: Based on the inverse permuted check node message vector, update the variable node message vector of the exchanged variable nodes to obtain the updated variable node message vector;
[0072] Specifically, in this embodiment, the variable node message vector is updated by the following formula, specifically: Among them, Denote the probability that the variable node n takes the value a given the check information {c k} k∈M(n)\m related to the check node m and the received information. Derive the above formula through Bayes' formula: The first step: First, through The conditional probability is split and transformed. P(x n =a|y n ) is the probability that the variable node n takes the value a given the received information y n , and ({c k} k∈M(n)\m |y n ) is the probability of the check information other than that related to node m given the received information y nThe probability P({c k} k∈M(n)\m ∣x n =a,y n ) is the probability of the parity-check information except for that related to node m given that the variable node n takes the value a and the received message is y n . Second step: Then, through transform the probability term P({c k} k∈M(n)\m ∣x n =a,y n ) obtained in the first step into a product form of the conditional probabilities of all the parity-check nodes k connected to node n (except node m); Third step: Obtain where α mn is the normalization factor, f n a is a function or intermediate variable related to the variable node n taking the value a, is the probability value of the value a from the parity-check node to the variable node involved in the parity-check node update process.
[0073] The posterior probability of the symbol probability determined by the message vector under the condition that the currently received message sequence satisfies other parity-check nodes except the current parity-check node. The posterior probability after correction after introducing correlation by the parity-check matrix, where the current parity-check equation is excluded to prevent the decoding from not converging due to the recycling of information.
[0074] S50: Obtain the updated parity-check matrix according to the updated variable node message vector and parity-check node message vector;
[0075] S60: Check the decoded sequence according to the updated parity-check matrix; if the checksum is an all-zero vector, the decoding is successful and the decoding result is output; otherwise, perform the next round of information passing and update of the variable node and parity-check node until the maximum number of iterations is reached or the decoding is successful.
[0076] Specifically, in this embodiment, each element of the finite field GF(q) used for the current LDPC code is determined by the following formula, specifically: where P(x n =a∣y n ,{c k} k∈M(n) ) represents the probability that the variable node n takes the value a given the received message y n and the set of parity-check nodes {c k} k∈M(n) connected to the variable node n; z′ n is the normalization factor used to ensure that the sum of the probabilities is 1, It is a certain message or probability value regarding the value a passed from the check node m to the variable node n during the update process of the check node. It is a certain message or probability value regarding the value passed from the check node m to the variable node n during the update process of the variable node; after making a decision on each element of the finite field GF(q) used by the current LDPC code, the decision decoding sequence can be obtained. If the checksum is an all-zero vector, it indicates successful decoding, the iteration ends, and the decoding sequence is returned; otherwise, the information transfer between the variable node and the check node is carried out in the next round until the maximum number of iterations is reached or the decoding is successful. If the decoding sequence still does not converge (i.e., it is not 0) when the iteration reaches the preset maximum number of iterations, the decoding fails, the iteration stops, and the current decoding sequence is output.
[0077] This embodiment also provides an LDPC decoder. Refer to Figure 7 , Figure 7 FIG. shows a schematic diagram of the module connection of an LDPC decoder. The system includes the variable node exchange module described in any one of the above. The system further includes:
[0078] The permutation module 100 is used to permute the message vector output by the variable node according to the non-zero elements at the corresponding positions of the variable nodes in the parity-check matrix to obtain the permuted variable node message vector.
[0079] The check node update module 200 is used to update the check node message vector based on the permuted variable node message vector to obtain the updated check node message vector.
[0080] The inverse permutation module 300 is used to perform an inverse permutation on the updated check node message vector.
[0081] The variable node exchange module 400 is used to, after performing an inverse permutation on the updated check node message vector, use the variable node transformation method to judge the variable node index used in the current layer and the variable node index used in the next layer, and output the judged variable node.
[0082] The variable node update module 500 is used to update the variable node message vector of the judged variable node based on the inversely permuted check node message vector to obtain the updated variable node message vector.
[0083] The decision decoding module 600 is used to obtain the updated parity-check matrix according to the updated variable node message vector and the check node message vector; check the decoding sequence according to the updated parity-check matrix; if the checksum is an all-zero vector, the decoding is successful and the decoding result is output; otherwise, the information transfer and update between the variable node and the check node are carried out in the next round until the maximum number of iterations is reached or the decoding is successful.
[0084] It should be noted that the modules in the system of this embodiment correspond to the steps in the method of this embodiment. The steps in the method of this embodiment have been elaborated in detail, and the content of the modules in the system will not be elaborated in detail here.
[0085] This embodiment also provides a computer device. Refer to Figure 8 , Figure 8 which shows a schematic structural diagram of a computer device, including a system memory 1005 and a processor 1001. The system memory 1005 stores a computer program, and when the processor 1001 executes the computer program, it implements the steps of the method in any one of the above.
[0086] It should be noted that the processor 1001 is used to execute the steps in the above method embodiment according to the instructions in the program code. Alternatively, when the processor 1001 executes the computer program, it implements the functions of each module / unit in each of the above system / device embodiments.
[0087] Specifically, in this embodiment, the computer program can be divided into one or more modules / units. One or more modules / units are stored in the system memory 1005 and are executed by the processor 1001 to complete this application. One or more modules / units can be a series of computer program instruction segments that can complete specific functions, and these instruction segments are used to describe the execution process of the computer program in the terminal device.
[0088] The terminal device can be a computing device such as a desktop computer, a notebook, a palm computer, and a cloud server. The terminal device may include, but is not limited to, a processor 1001 and a system memory 1005. Those skilled in the art can understand that it does not constitute a limitation on the terminal device, and it may include more or fewer components than shown in the figure, or combine certain components, or different components. For example, the terminal device may also include an input / output device 1003, a network access device 1002, a bus 1006, etc.
[0089] The processor 1001 may be a central processing unit (CPU), or may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.
[0090] The system memory 1005 can be an internal storage unit of the terminal device, such as the hard disk or memory of the terminal device. The system memory 1005 can also be the storage device 1004 of the terminal device, such as a plug-in hard disk, a SmartMedia Card (SMC), a Secure Digital (SD) card, a FlashCard, etc. equipped on the terminal device. Further, the system memory 1005 can also include both the internal storage unit of the terminal device and the storage device 1004. The system memory 1005 is used to store computer programs and other programs and data required by the terminal device. The system memory 1005 can also be used to temporarily store data that has been output or will be output.
[0091] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the above-described systems, systems, and units can refer to the corresponding processes in the foregoing method embodiments, and will not be described herein again.
[0092] This embodiment provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method in any one of the above are implemented.
[0093] Among them, the computer-readable storage medium can be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems, or devices, or any combination of the above. More specific examples (non-exhaustive list) of the computer-readable storage medium include: an electrical connection with one or more wires, a portable computer disk, a hard disk. Random Access Memory (RAM), Read-Only Memory (ROM), Erasable Programmable Read Only Memory (EPROM), registers, hard disks, optical fibers, portable compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above, or any other form of computer-readable storage medium known in the art.
[0094] An exemplary storage medium is coupled to a processor, enabling the processor to read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an Application Specific Integrated Circuit (ASIC). In an embodiment of the present invention, the computer-readable storage medium can be any tangible medium that contains or stores a program, and the program can be used by or in conjunction with an instruction execution system, system, or device.
[0095] This embodiment also provides a computer program product containing instructions. When the instructions are run by a computer device cluster, the computer device cluster is caused to execute the method described in Embodiment 1.
[0096] The specific embodiments described above further elaborate on the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only the specific embodiments of the present invention and is not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A variable node swapping method, characterized in that, This method is used in the case of memory access conflict during the decoding process. The method includes: Receiving the variable node indices used in the n-th layer and the (n + 1)-th layer of the parity-check matrix at the t-th access moment; If the two variable node indices are the same, then swap the variable node used in the (n + 1)-th layer at the t-th access moment with the variable node used in the (n + 1)-th layer at the (t + 1)-th access moment.
2. A variable node swapping module, characterized in that This variable node swapping module is used to execute the variable node swapping method described in claim 1. The variable node swapping module includes: A judgment unit, configured to receive the variable node indices used in the n-th layer and the (n + 1)-th layer of the parity-check matrix at the t-th access moment, and judge whether the two variable node indices are the same; A selection unit, configured to receive the judgment result output by the judgment unit. If the judgment result is that the two variable node indices are the same, then swap the variable node used in the (n + 1)-th layer at the t-th access moment with the variable node used in the (n + 1)-th layer at the (t + 1)-th access moment.
3. The variable node exchange module according to claim 2, wherein, The judgment unit adopts an exclusive-OR logic gate.
4. The variable node swapping module according to claim 2, characterized in that The selection unit adopts a two-way data selector.
5. An LDPC decoding method, characterized in that This method includes the variable node transformation method described in claim 1. Specifically: According to the non-zero elements at the corresponding positions of the variable nodes in the parity-check matrix, permute the message vector output by the variable nodes to obtain a permuted variable node message vector; Based on the permuted variable node message vector, update the parity-check node message vector to obtain an updated parity-check node message vector; Perform an inverse permutation on the updated parity-check node message vector; and after performing the inverse permutation on the updated parity-check node message vector, use the variable node transformation method to swap the variable node used in the (n + 1)-th layer at the t-th access moment with the variable node used in the (n + 1)-th layer at the (t + 1)-th access moment, and output the swapped variable nodes; Based on the inversely permuted parity-check node message vector, update the variable node message vector of the swapped variable nodes to obtain an updated variable node message vector; According to the updated variable node message vector and the parity-check node message vector, obtain an updated parity-check matrix; Check the decoding sequence according to the updated parity-check matrix; If the checksum is an all-zero vector, the decoding is successful and the decoding result is output; Otherwise, perform the next round of information passing and updating of the variable nodes and the parity-check nodes until the maximum number of iterations is reached or the decoding is successful.
6. The LDPC decoding method according to claim 5, wherein Before permuting the message vector output by the variable nodes according to the non-zero elements at the corresponding positions of the variable nodes in the parity-check matrix to obtain a permuted variable node message vector, the method further includes: Mapping the received binary bit stream to finite field symbols according to the channel received sequence, and converting the reliability information of the received finite field symbols into an initial message vector of the variable nodes according to the channel noise.
7. An LDPC decoder, characterized in that, This decoder includes the variable node swapping module described in any one of claims 2-4. The decoder further includes: A permutation module, configured to permute the message vector output by the variable nodes according to the non-zero elements at the corresponding positions of the variable nodes in the parity-check matrix to obtain a permuted variable node message vector; A check node update module, configured to update a check node message vector based on a permuted variable node message vector to obtain an updated check node message vector; An inverse permutation module, configured to perform an inverse permutation on the updated check node message vector; A variable node swapping module, configured to, after performing an inverse permutation on the updated check node message vector, swap a variable node used at the (t + 1)-th access time for the (n + 1)-th layer with a variable node used at the t-th access time for the (n + 1)-th layer by using a variable node transformation method, and output the swapped variable nodes; A variable node update module, configured to update a variable node message vector of the swapped variable nodes based on the inversely permuted check node message vector to obtain an updated variable node message vector; A decision decoding module, configured to obtain an updated parity check matrix according to the updated variable node message vector and check node message vector; check a decoded sequence according to the updated parity check matrix; if the checksum is an all-zero vector, the decoding is successful and the decoding result is output; otherwise, information passing updates of variable nodes and check nodes are performed in the next round until the maximum number of iterations is reached or the decoding is successful.
8. A computer device, including a system memory and a processor, the system memory storing a computer program, characterized in that, When the processor executes the computer program, it implements the variable node swapping method described in claim 1; when the processor executes the computer program, it also implements the decoding method described in any one of claims 5 to 6.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the variable node swapping method described in claim 1; when the computer program is executed by the processor, it also implements the decoding method described in any one of claims 5 to 6.
10. A computer program product comprising instructions, characterized in that, When the instruction is run by a computer device cluster, the computer device cluster is caused to execute the variable node swapping method described in claim 1, and execute the decoding method described in any one of claims 5 to 6.